ddr: fip:c1 conflict between retraining and normal cpu reading [3/3]
PD#SWPL-25565
Problem:
LPDDR4 board booting timeout issue due to ddr-windowing test hang,
conflict between retraining and normal cpu reading;
Solution:
as long as the CPU has the operation controller to read and write
the PHY register,it will first shut down the retraining of phy,
and then restore the retraining state after the CPU operation is completed;
Verify:
test pass at c1
Change-Id: Ibf187c9a1e45f3068801c1e8668744774c6bd00f
Signed-off-by: zhiguang.ouyang <zhiguang.ouyang@amlogic.com>
1 file changed