| commit | 6fd2ee0e792865c48cec9b3c8776db4bccf5615a | [log] [tgz] |
|---|---|---|
| author | xiaobo gu <xiaobo.gu@amlogic.com> | Sun May 26 17:43:05 2019 +0800 |
| committer | xiaobo gu <xiaobo.gu@amlogic.com> | Thu Jun 27 18:03:49 2019 +0800 |
| tree | 7882e652ec45399a781443e2eb1228ce3b22c338 | |
| parent | de7c295069c5c40b41c0e4396d4029ab4c4959b1 [diff] |
a1: sync ddr fw since uart port changed [1/1] PD#SWPL-7723 Problem: ddr init flow have no log Solution: need update ddr fw since uart port changed Verify: test pass on ad409 Change-Id: I74d81b99322d8d7c060c3924b99062a62f72f8a2 Signed-off-by: xiaobo gu <xiaobo.gu@amlogic.com>