typo check: fix bl30/src_ao typo issue [1/1]
PD#SWPL-102807
Problem:
typo issue
Solution:
fix the typo issue
Verify:
local check
local build
sc2,t5w,a5
Change-Id: I69fa2278321a537724e7dd5a68e299de56d20c6f
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
diff --git a/demos/amlogic/driver/glb_timer/glb_timer.c b/demos/amlogic/driver/glb_timer/glb_timer.c
index 324f8b7..e506632 100644
--- a/demos/amlogic/driver/glb_timer/glb_timer.c
+++ b/demos/amlogic/driver/glb_timer/glb_timer.c
@@ -194,7 +194,7 @@
* lib/third_party/amlogic/include/drivers/global_timer.h note that this
* number and GPIO
* line number should keep mapping 0-31 <--> GLBT_GPIO0_IRQ -- GLBT_GPIO31_IRQ
- * @retruns:the global timer 64 bit snapshot value
+ * @returns:the global timer 64 bit snapshot value
*/
uint64_t ullGlobalTimerInputGPIOGetSnapshot(uint8_t ucSrc)
{
@@ -285,7 +285,7 @@
* @uInterval: pulse interval in global timer cycles
* @ucInitval: decides the initial value of the gpio state and the pulse
* would be inverse of that init value
- * @retruns: 0 on success and error code on failure
+ * @returns: 0 on success and error code on failure
*/
int uGlobalTimerOutputGPIOSetup(uint8_t ucSrc, uint8_t ucOneshot,
uint32_t uPulseWith, uint32_t uInterval,
diff --git a/demos/amlogic/n200/include/a5/p_register.h b/demos/amlogic/n200/include/a5/p_register.h
index 2fbe570..62f5ea0 100644
--- a/demos/amlogic/n200/include/a5/p_register.h
+++ b/demos/amlogic/n200/include/a5/p_register.h
@@ -200,14 +200,14 @@
//bit 10 force to disable the clock of dfi command generation
//bit 9 force to disable the clock of dram controller
//bit 8 force to disable the clock of dfi data path.
-//bit 7. force to disalbe the clock of write rsp generation.
-//bit 6. force to disalbe the clock of read rsp generation.
-//bit 5. force to disalbe the clock of command filter.
-//bit 4. force to disalbe the clock of write reorder buffer.
-//bit 3. force to disalbe the clock of write data buffer.
-//bit 2. force to disalbe the clock of read reorder buffer.
-//bit 1. force to disalbe the clock of read canvas.
-//bit 0. force to disalbe the clock of write canvas.
+//bit 7. force to disable the clock of write rsp generation.
+//bit 6. force to disable the clock of read rsp generation.
+//bit 5. force to disable the clock of command filter.
+//bit 4. force to disable the clock of write reorder buffer.
+//bit 3. force to disable the clock of write data buffer.
+//bit 2. force to disable the clock of read reorder buffer.
+//bit 1. force to disable the clock of read canvas.
+//bit 0. force to disable the clock of write canvas.
#define P_DMC_MON_CTRL0 (volatile uint32_t *)0xfe036080
//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
@@ -228,7 +228,7 @@
#define P_DMC_MON_ALL16_BW (volatile uint32_t *)0xfe036090
// at the test period, the whole MMC granted data cycles which goes to 16bits ddr. unit:64bits
#define P_DMC_MON0_CTRL (volatile uint32_t *)0xfe036094
-//BW MONTIOR 0 address range control. start addrss <= AXI address[31:16] <= end address
+//BW MONITOR 0 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define P_DMC_MON0_CTRL1 (volatile uint32_t *)0xfe036098
@@ -239,7 +239,7 @@
#define P_DMC_MON0_BW (volatile uint32_t *)0xfe0360a0
// at the test period, this range granted data cycles for the selected channel and ports.
#define P_DMC_MON1_CTRL (volatile uint32_t *)0xfe0360a4
-//BW monitor 1 address range control. start addrss <= AXI address[31:16] <= end address
+//BW monitor 1 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define P_DMC_MON1_CTRL1 (volatile uint32_t *)0xfe0360a8
@@ -250,7 +250,7 @@
#define P_DMC_MON1_BW (volatile uint32_t *)0xfe0360b0
// at the test period, this range granted data cycles for the selected channel and ports.
#define P_DMC_MON2_CTRL (volatile uint32_t *)0xfe0360b4
-//BW monitor 2 address range control. start addrss <= AXI address[31:16] <= end address
+//BW monitor 2 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define P_DMC_MON2_CTRL1 (volatile uint32_t *)0xfe0360b8
@@ -261,7 +261,7 @@
#define P_DMC_MON2_BW (volatile uint32_t *)0xfe0360c0
// at the test period, this range granted data cycles for the selected channel and ports.
#define P_DMC_MON3_CTRL (volatile uint32_t *)0xfe0360c4
-//BW monitor 3 address range control. start addrss <= AXI address[31:16] <= end address
+//BW monitor 3 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define P_DMC_MON3_CTRL1 (volatile uint32_t *)0xfe0360c8
@@ -272,7 +272,7 @@
#define P_DMC_MON3_BW (volatile uint32_t *)0xfe0360d0
// at the test period, this range granted data cycles for the selected channel and ports.
#define P_DMC_MON4_CTRL (volatile uint32_t *)0xfe0360d4
-//BW monitor 4 address range control. start addrss <= AXI address[31:16] <= end address
+//BW monitor 4 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define P_DMC_MON4_CTRL1 (volatile uint32_t *)0xfe0360d8
@@ -283,7 +283,7 @@
#define P_DMC_MON4_BW (volatile uint32_t *)0xfe0360e0
// at the test period, this range granted data cycles for the selected channel and ports.
#define P_DMC_MON5_CTRL (volatile uint32_t *)0xfe0360e4
-//BW monitor 5 address range control. start addrss <= AXI address[31:16] <= end address
+//BW monitor 5 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define P_DMC_MON5_CTRL1 (volatile uint32_t *)0xfe0360e8
@@ -294,7 +294,7 @@
#define P_DMC_MON5_BW (volatile uint32_t *)0xfe0360f0
// at the test period, this range granted data cycles for the selected channel and ports.
#define P_DMC_MON6_CTRL (volatile uint32_t *)0xfe0360f4
-//BW monitor 6 address range control. start addrss <= AXI address[31:16] <= end address
+//BW monitor 6 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define P_DMC_MON6_CTRL1 (volatile uint32_t *)0xfe0360f8
@@ -305,7 +305,7 @@
#define P_DMC_MON6_BW (volatile uint32_t *)0xfe036100
// at the test period, this range granted data cycles for the selected channel and ports.
#define P_DMC_MON7_CTRL (volatile uint32_t *)0xfe036104
-//BW monitor 7 address range control. start addrss <= AXI address[31:16] <= end address
+//BW monitor 7 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define P_DMC_MON7_CTRL1 (volatile uint32_t *)0xfe036108
@@ -347,7 +347,7 @@
//bit 15:8. write urgent 1 request pending hold num.
//bit 7:0. write urgent 0 request pending hold num.
#define P_DMC_CMD_FILTER_CTRL7 (volatile uint32_t *)0xfe036158
-//bit 31:24. aw_req_pedning singal assertion after wbuf full.
+//bit 31:24. aw_req_pending singal assertion after wbuf full.
//bit 23:16 aw_req_pending singal hold how long if wbuf not full.
//bit 15:8 write to read waiting cycles if there write hit request.
//bit 7:0 read to write waiting cycles if there write hit request.
@@ -531,7 +531,7 @@
#define P_DMC_CHAN_STS (volatile uint32_t *)0xfe036338
//AXI0 is first CPU and Mali combined channel from CCI-400 directly. The first 2Gbyte address will go through this channel.
//AXI10 is the second CPU, Mali channel combined with NNA from NIC-400. The upper 2Gbyte address will go through this channel.
-// read only regsiter.
+// read only register.
// the second mali and NNA channel IDLE.
// the second CPU channel IDLE.
// the first mali channel IDLE.
@@ -552,7 +552,7 @@
//bit 31:16 : range end address.
//bit 15:0 : range start address
#define P_DMC_PROT0_CTRL (volatile uint32_t *)0xfe036344
-//bit 23:16. each bit to eanble one of the 8 ambus channal for the protection function.
+//bit 23:16. each bit to enable one of the 8 ambus channal for the protection function.
//bit 15:0 each bit to enable one of the 15 channel input for the protection function.
#define P_DMC_PROT0_CTRL1 (volatile uint32_t *)0xfe036348
//bit 26. protection 0 read access protection enable.
@@ -564,7 +564,7 @@
//bit 31:16 : range end address.
//bit 15:0 : range start address
#define P_DMC_PROT1_CTRL (volatile uint32_t *)0xfe036350
-//bit 23:16. each bit to eanble one of the 8 ambus channal for the protection function.
+//bit 23:16. each bit to enable one of the 8 ambus channal for the protection function.
//bit 15:0 each bit to enable one of the 15 channel input for the protection function.
#define P_DMC_PROT1_CTRL1 (volatile uint32_t *)0xfe036354
//bit 26. protection range 1 read access protection enable bit.
@@ -645,37 +645,37 @@
//bit 31:16. the Forth cycle.
//bit 15:0. the third cycle.
#define P_DMC_TEST_WD0 (volatile uint32_t *)0xfe037840
-// write data 0 for write command. also for read back data comparision.
+// write data 0 for write command. also for read back data comparison.
#define P_DMC_TEST_WD1 (volatile uint32_t *)0xfe037844
-// write data 1 for write command. also for read back data comparision.
+// write data 1 for write command. also for read back data comparison.
#define P_DMC_TEST_WD2 (volatile uint32_t *)0xfe037848
-// write data 2 for write command. also for read back data comparision.
+// write data 2 for write command. also for read back data comparison.
#define P_DMC_TEST_WD3 (volatile uint32_t *)0xfe03784c
-// write data 3 for write command. also for read back data comparision.
+// write data 3 for write command. also for read back data comparison.
#define P_DMC_TEST_WD4 (volatile uint32_t *)0xfe037850
-// write data 4 for write command. also for read back data comparision.
+// write data 4 for write command. also for read back data comparison.
#define P_DMC_TEST_WD5 (volatile uint32_t *)0xfe037854
-// write data 5 for write command. also for read back data comparision.
+// write data 5 for write command. also for read back data comparison.
#define P_DMC_TEST_WD6 (volatile uint32_t *)0xfe037858
-// write data 6 for write command. also for read back data comparision.
+// write data 6 for write command. also for read back data comparison.
#define P_DMC_TEST_WD7 (volatile uint32_t *)0xfe03785c
-// write data 7 for write command. also for read back data comparision.
+// write data 7 for write command. also for read back data comparison.
#define P_DMC_TEST_WD8 (volatile uint32_t *)0xfe037860
-// write data 8 for write command. also for read back data comparision.
+// write data 8 for write command. also for read back data comparison.
#define P_DMC_TEST_WD9 (volatile uint32_t *)0xfe037864
-// write data 9 for write command. also for read back data comparision.
+// write data 9 for write command. also for read back data comparison.
#define P_DMC_TEST_WD10 (volatile uint32_t *)0xfe037868
-// write data 10 for write command. also for read back data comparision.
+// write data 10 for write command. also for read back data comparison.
#define P_DMC_TEST_WD11 (volatile uint32_t *)0xfe03786c
-// write data 11 for write command. also for read back data comparision.
+// write data 11 for write command. also for read back data comparison.
#define P_DMC_TEST_WD12 (volatile uint32_t *)0xfe037870
-// write data 12 for write command. also for read back data comparision.
+// write data 12 for write command. also for read back data comparison.
#define P_DMC_TEST_WD13 (volatile uint32_t *)0xfe037874
-// write data 13 for write command. also for read back data comparision.
+// write data 13 for write command. also for read back data comparison.
#define P_DMC_TEST_WD14 (volatile uint32_t *)0xfe037878
-// write data 14 for write command. also for read back data comparision.
+// write data 14 for write command. also for read back data comparison.
#define P_DMC_TEST_WD15 (volatile uint32_t *)0xfe03787c
-// write data 15 for write command. also for read back data comparision.
+// write data 15 for write command. also for read back data comparison.
#define P_DMC_TEST_RD0 (volatile uint32_t *)0xfe037880
// the read back data 0. if error happens, it would capture the first error data.
#define P_DMC_TEST_RD1 (volatile uint32_t *)0xfe037884
@@ -814,7 +814,7 @@
#define P_DMC_DRAM_TDPD (volatile uint32_t *)0xfe036474
//not support.
#define P_DMC_DRAM_DFITCTRLDELAY (volatile uint32_t *)0xfe036478
-//bit 3:0. DFI_t_ctrldealy
+//bit 3:0. DFI_t_ctrldelay
#define P_DMC_DRAM_DFITPHYWRDATA (volatile uint32_t *)0xfe03647c
//bit 5:0. dfi_t_phy_wrdata.
#define P_DMC_DRAM_DFITPHYWRLAT (volatile uint32_t *)0xfe036480
@@ -824,7 +824,7 @@
#define P_DMC_DRAM_DFITPHYRDLAT (volatile uint32_t *)0xfe036488
//bit 5:0. dfi_t_rdlat.
#define P_DMC_DRAM_DFITCTRLUPDMIN (volatile uint32_t *)0xfe03648c
-//bit 7:0. CTRLUPD_MIN minimux clock cycle to maintain CTRLUPD_REQ.
+//bit 7:0. CTRLUPD_MIN minimum clock cycle to maintain CTRLUPD_REQ.
#define P_DMC_DRAM_DFITCTRLUPDMAX (volatile uint32_t *)0xfe036490
//bit 7:0 CTRLUPD_MAX. maxmum clock cycle to maintain CTRLUPD_REQ if no CTRLUPD_ACK response.
#define P_DMC_DRAM_DFITREFMSKI (volatile uint32_t *)0xfe036498
@@ -900,7 +900,7 @@
//23:16. when to send PHY ZQ UPDATE command.
//15:8. when to send ZQCS/ZQCAL to rank1 DDR SDRAM.
//7:0. when to senc ZQCS/ZQCAL to rank0 DDR SDRAM.
-//timing paramter for frequency set 1.
+//timing parameter for frequency set 1.
#define P_DMC_NFQ_TMRD (volatile uint32_t *)0xfe036500
#define P_DMC_NFQ_TRFC (volatile uint32_t *)0xfe036504
#define P_DMC_NFQ_TRP (volatile uint32_t *)0xfe036508
@@ -986,7 +986,7 @@
//bit 10 1: enable staggered chip select for 2 ranks DRAM.
//bit 9 1: enable send auto refresh command to DDR SDRAM when PCTL is in CFG/STOP state.
//bit 8 send auto refr cmd before enter register triggered self refresh
-//bit 7 send auto refr cmd after exit regsiter triggered self refresh mode.
+//bit 7 send auto refr cmd after exit register triggered self refresh mode.
//bit 6 disable dram clock after enter register triggered self refresh.
//bit 5 send DFI_LP_REQ to PHY after enter register triggered elf refresh mode.
//bit 4 send DRAM to power down mode after enter self refresh. ONLY for LPDDR4.
@@ -1070,7 +1070,7 @@
//bit 31 . write 1 to change freqency read 0: finished.
//bit 30. waiting for software to send some manual command. 1 : waiting. 0 : not ready yet.
//bit 29:23. not used.
-//bit 22. after freqchenge send refresh command.
+//bit 22. after freqchange send refresh command.
//bit 21 after Freqchange send PHY ZQ update.
//bit 20 send CTRLUPD_REQ to PHY after freq_change finished.
//bit 19:16. how many cycles to send PLL change req after init_complete signal to low.
@@ -1078,7 +1078,7 @@
//bit 14. freq post config_en. After freq enter stop state let DMC configure DDR SDRAM.
//bit 13. send zqcl after freq change in DDR3/4 mode.
//bit 12. send zqcs after freq change. 1: enable. 0 not send.
-//bit 11. in AUTO MRW fucntion: the data format. 1: use USR_CMD format. 0: MRW format.
+//bit 11. in AUTO MRW function: the data format. 1: use USR_CMD format. 0: MRW format.
//bit 10. AUTO MRW function: 1 use hardware auto MRW function. 0: don't do auto MRW.
//bit 9. 1 : FREQ MRW done. let FREQ change machine continue.
//bit 8 FREQ WAIT. 1 when freq change finishes, state machine stop at self refresh state in case there's something need to handle.
@@ -1156,7 +1156,7 @@
//bit 25:24 : retraining dfi_freq[4:3], the [2:0] bit still use the dfi_freq bits to keep the frequency.
//bit 23:0: retraining period unit : 100ns.
#define P_DMC_DFI_ERR_STAT (volatile uint32_t *)0xfe036660
-//LPDDR4 PHY DFI error infomation.
+//LPDDR4 PHY DFI error information.
//bit 31:20. not used.
//bit 9. ddr0_dfi_error
//bit 8:5 ddr0_dfi_error_info.
@@ -1661,7 +1661,7 @@
//DMC use 15bits ID to identify the input ports and ID.
// bit 14:10.
// AXI bus ID number from 0 ~15. 2, 8~10, 12~15 Not used the others defined as bellow.
-// 0 : CPU and MALI. Mali and cpu will be seperated to 2 channel. CPU traffic will be assigned to ID = 0. Mali traffic will assigned to ID =1.
+// 0 : CPU and MALI. Mali and cpu will be separated to 2 channel. CPU traffic will be assigned to ID = 0. Mali traffic will assigned to ID =1.
// 1 : Mali
// 3 : HDMI.
// 4 : HEVC. //HEVC_F/B combined to one
@@ -2044,37 +2044,37 @@
//bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
//bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
#define P_DDR_APB_SEC_CTRL2 (volatile uint32_t *)0xfe0373c8
-// APB access control for DMC PLL clock frequency control regsiter.
+// APB access control for DMC PLL clock frequency control register.
//default : 0x005
//bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
//bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
#define P_DDR_APB_SEC_CTRL3 (volatile uint32_t *)0xfe0373cc
-// APB access control for DMC sticky control regsiter.
+// APB access control for DMC sticky control register.
//default : 0x005
//bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
//bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
#define P_DDR_APB_SEC_CTRL4 (volatile uint32_t *)0xfe0373d0
-// APB access control for DMC test control regsiter.
+// APB access control for DMC test control register.
//default : 0x005
//bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
//bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
#define P_DDR_APB_SEC_CTRL5 (volatile uint32_t *)0xfe0373d4
-// APB access control for DMC clk reset control regsiter.
+// APB access control for DMC clk reset control register.
//default : 0x005
//bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
//bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
#define P_DDR_APB_SEC_CTRL6 (volatile uint32_t *)0xfe0373d8
-// APB access control for DMC protection regsiter.
+// APB access control for DMC protection register.
//default : 0x005
//bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
//bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
#define P_DDR_APB_SEC_CTRL7 (volatile uint32_t *)0xfe0373dc
-// APB access control for DMC normal regsiter.
+// APB access control for DMC normal register.
//default : 0x0ff
//bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
//bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
#define P_DDR_APB_SEC_CTRL8 (volatile uint32_t *)0xfe0373e0
-// APB access control for DDR PHY group regsiters.
+// APB access control for DDR PHY group registers.
//default : 0x50005
//bit 23:16. APB access enable for DDR PHY group 1 register.
//bit 10 PHY IMEM control 1: force PHY IMEM output 0. 0: normal working mode.
@@ -2082,7 +2082,7 @@
//bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
//bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
#define P_DDR_APB_SEC_CTRL9 (volatile uint32_t *)0xfe0373e4
-// APB access control for DMC canvas regsiter.
+// APB access control for DMC canvas register.
//default : 0x005
//bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
//bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
@@ -2342,7 +2342,7 @@
#define P_DMC_DDR_CTRL1 (volatile uint32_t *)0xfe0374c0
//bit 1. 1: only allow DMA/DEMUX write data level == region security level. 0: DMA/DEMUX write data level <= region sec level.
//bit 0. DMC_DDR_LOCK. 1: LOCK DMC_DDR_CTRL, DMC_DDR_CTRL1, DMC_AXI2DDRx, DDR0/1_ADDRMAP_x registers. those register can't modified any more.
-// 0: all these regsiters can be read/write by secure APB access.
+// 0: all these registers can be read/write by secure APB access.
//
// Closing file: ../mmc_lp4/dmc/rtl/dmc_reg.vh
//
@@ -2377,7 +2377,7 @@
//bit 5. LPDT data endian. 1 = transfer the high bit first. 0 : transfer the low bit first.
//bit 4. HS data endian.
//bit 3. force data byte lane in stop mode.
-//bit 2. force data byte lane 0 in reciever mode.
+//bit 2. force data byte lane 0 in receiver mode.
//bit 1. write 1 to sync the txclkesc input. the internal logic have to use txclkesc to decide Txvalid and Txready.
//bit 0. enalbe the MIPI DSI PHY TxDDRClk.
#define P_MIPI_DSI_CHAN_CTRL (volatile uint32_t *)0xfe01c004
@@ -2436,8 +2436,8 @@
#define P_MIPI_DSI_WAKEUP_TIM (volatile uint32_t *)0xfe01c020
//TWAKEUP.
#define P_MIPI_DSI_LPOK_TIM (volatile uint32_t *)0xfe01c024
-//bit 31:0 when in RxULPS state, RX reciever is in sleep mode.
-//every MIPI_DSI_ULPS_CHECK period, the reciever would be enabled once, and waiting this timer period to get the stable input.
+//bit 31:0 when in RxULPS state, RX receiver is in sleep mode.
+//every MIPI_DSI_ULPS_CHECK period, the receiver would be enabled once, and waiting this timer period to get the stable input.
#define P_MIPI_DSI_LP_WCHDOG (volatile uint32_t *)0xfe01c028
//bit 31:0 watch dog timer for MIPI DSI LP receive state.
#define P_MIPI_DSI_ANA_CTRL (volatile uint32_t *)0xfe01c02c
@@ -2448,7 +2448,7 @@
#define P_MIPI_DSI_TURN_WCHDOG (volatile uint32_t *)0xfe01c034
//bit 31:0 watch dog timer for lane 0 LP turn around waiting time.
#define P_MIPI_DSI_ULPS_CHECK (volatile uint32_t *)0xfe01c038
-//bit 31:0 when Lane0 in LP recieve state, if the another side sent Low power command, using this timer to enable Tcheck the another size wakeup nor not.
+//bit 31:0 when Lane0 in LP receive state, if the another side sent Low power command, using this timer to enable Tcheck the another size wakeup nor not.
#define P_MIPI_DSI_TEST_CTRL0 (volatile uint32_t *)0xfe01c03c
#define P_MIPI_DSI_TEST_CTRL1 (volatile uint32_t *)0xfe01c040
//========================================================================
@@ -4946,7 +4946,7 @@
#define BT_CLK27_SEL_BIT 7 // 1 : external xclk27 0 : internal clk27.
#define BT_CLK27_PHASE_BIT 6 // 1 : no inverted 0 : inverted.
#define BT_ACE_MODE_BIT 5 // 1 : auto cover error by hardware.
-#define BT_SLICE_MODE_BIT 4 // 1 : no ancillay flag 0 : with ancillay flag.
+#define BT_SLICE_MODE_BIT 4 // 1 : no ancillary flag 0 : with ancillary flag.
#define BT_FMT_MODE_BIT 3 // 1 : ntsc 0 : pal.
#define BT_REF_MODE_BIT 2 // 1 : from bit stream. 0 : from ports.
#define BT_MODE_BIT 1 // 1 : BT656 model 0 : SAA7118 mode.
@@ -6671,16 +6671,16 @@
//Bit 6:4, reg_frddr_type ,default = 0
//Bit 3:0, reserved
#define P_EARCTX_SPDIFOUT_PREAMB (volatile uint32_t *)0xfe333418
-//Bit 31, reg_premable_Z_set ,default = 0,user 8'b11101000 1 user 7:0
-//Bit 30, reg_premable_Y_set ,default = 0,user 8'b11100100 1 user 15:8
-//Bit 29, reg_premable_X_set ,default = 0,user 8'b11100010 1 user 23:16
+//Bit 31, reg_preamble_Z_set ,default = 0,user 8'b11101000 1 user 7:0
+//Bit 30, reg_preamble_Y_set ,default = 0,user 8'b11100100 1 user 15:8
+//Bit 29, reg_preamble_X_set ,default = 0,user 8'b11100010 1 user 23:16
//Bit 28:24, reserved
-//Bit 23:16, reg_premable_X_value ,default = 0
-//Bit 15:8, reg_premable_Y_value ,default = 0
-//Bit 7:0, reg_premable_Z_value ,default = 0
+//Bit 23:16, reg_preamble_X_value ,default = 0
+//Bit 15:8, reg_preamble_Y_value ,default = 0
+//Bit 7:0, reg_preamble_Z_value ,default = 0
#define P_EARCTX_SPDIFOUT_SWAP (volatile uint32_t *)0xfe33341c
//Bit 31:16, reg_hold_cnt ,default = 0,hold start cnt ,valid when reg_hold_for_tdm set 1
-//Bit 15, reg_init_send_en ,default = 0,send 01 sequence some times after intial done from frddr set
+//Bit 15, reg_init_send_en ,default = 0,send 01 sequence some times after initial done from frddr set
//Bit 14:0, reg_init_send_cnt ,default = 0,send 01 sequence time ,valid when reg_init_send_en set 1
#define P_EARCTX_ERR_CORRT_CTRL0 (volatile uint32_t *)0xfe333420
//Bit 31:24, reserved
@@ -6725,7 +6725,7 @@
//Bit 21, reg_data_sel ,default = 0,//data sel: 0 data 1 reg_mute_data_value
//Bit 20:19, reg_ubit_sel ,default = 0,//userBit sel: 0 data 1 reg_value 2 fifo data
//Bit 18, reg_vbit_sel ,default = 0,//validBit sel: 0 data 1 reg_value
-//Bit 17, reg_chst_sel ,default = 0,//chanel status sel: 0 data 1 reg_value
+//Bit 17, reg_chst_sel ,default = 0,//channel status sel: 0 data 1 reg_value
//Bit 16, reg_ubit_fifo_less_irq_en ,default = 0,fifo_less_thd irq enable
//Bit 15:8, reg_ubit_fifo_start_thd ,default = 0,start transmit iu after fifo level greater than this value
//Bit 7:0, reg_ubit_fifo_less_thd ,default = 0,generate irq,when fifo level less than this value
@@ -7076,22 +7076,22 @@
#define P_EARC_RX_CMDC_STATUS5 (volatile uint32_t *)0xfe3338b0
//Bit 31:0, ro_cmdc_status5 unsigned, RO, default = 0,
#define P_EARC_RX_CMDC_STATUS6 (volatile uint32_t *)0xfe3338b4
-//Bit 31, ro_idle2_int unsigned, RO, dfault =0
-//Bit 30, ro_idle1_int unsigned, RO, dfault =0
-//Bit 29, ro_disc2_int unsigned, RO, dfault =0
-//Bit 28, ro_disc1_int unsigned, RO, dfault =0
-//Bit 27, ro_earc_int unsigned, RO, dfault =0
-//Bit 26, ro_hb_status_int unsigned, RO, dfault =0
-//Bit 25, ro_losthb_int unsigned, RO, dfault =0
-//Bit 24, ro_timeout_int unsigned, RO, dfault =0
-//Bit 23, ro_status_ch_int unsigned, RO, dfault =0
-//Bit 22, ro_int_rec_invalid_id unsigned, RO, dfault =0
-//Bit 21, ro_int_rec_invalid_offset unsigned, RO, dfault =0
-//Bit 20, ro_int_rec_unexp unsigned, RO, dfault =0
-//Bit 19, ro_int_rec_ecc_err unsigned, RO, dfault =0
-//Bit 18, ro_int_rec_parity_err unsigned, RO, dfault =0
-//Bit 17, ro_int_recv_packet unsigned, RO, dfault =0
-//Bit 16, ro_int_rec_time_out unsigned, RO, dfault =0
+//Bit 31, ro_idle2_int unsigned, RO, default =0
+//Bit 30, ro_idle1_int unsigned, RO, default =0
+//Bit 29, ro_disc2_int unsigned, RO, default =0
+//Bit 28, ro_disc1_int unsigned, RO, default =0
+//Bit 27, ro_earc_int unsigned, RO, default =0
+//Bit 26, ro_hb_status_int unsigned, RO, default =0
+//Bit 25, ro_losthb_int unsigned, RO, default =0
+//Bit 24, ro_timeout_int unsigned, RO, default =0
+//Bit 23, ro_status_ch_int unsigned, RO, default =0
+//Bit 22, ro_int_rec_invalid_id unsigned, RO, default =0
+//Bit 21, ro_int_rec_invalid_offset unsigned, RO, default =0
+//Bit 20, ro_int_rec_unexp unsigned, RO, default =0
+//Bit 19, ro_int_rec_ecc_err unsigned, RO, default =0
+//Bit 18, ro_int_rec_parity_err unsigned, RO, default =0
+//Bit 17, ro_int_recv_packet unsigned, RO, default =0
+//Bit 16, ro_int_rec_time_out unsigned, RO, default =0
//Bit 15:0, reserved
//
// Closing file: earc_rx_cmdc.h
@@ -7233,10 +7233,10 @@
//Bit 31, reg_work_enable unsigned, default = 0, dmac user bit decode enable
//Bit 30:24, reg_iu_sync unsigned, default = 0, iu sync value
//Bit 23:16, reg_fifo_thd unsigned, default = 0, generate irq when fifo level pass some threshold
-//Bit 15, reg_max_dist_en unsigned, default = 0, max distance bewteen IUs to set lost
+//Bit 15, reg_max_dist_en unsigned, default = 0, max distance between IUs to set lost
//Bit 14, reg_iu_sync_en unsigned, default = 0, iu sync code enable 0 : all iu to fifo 1 only sync iu packet to fifo
//Bit 13:12, reg_user_lr unsigned, default = 0, 00 off 01 use l channel userbit 10 use r channel userbit 11 user lr channel userbit
-//Bit 11:8, reg_max_dist unsigned, default = 0, max distance bewteen IUs value
+//Bit 11:8, reg_max_dist unsigned, default = 0, max distance between IUs value
//Bit 7, reg_fifo_thd_en unsigned, default = 0, fifo_thd irq enable
//Bit 6, reg_fifo_lost_init_en unsigned, default = 0, when lost,initial fifo
//Bit 5, reg_fifo_init unsigned, default = 0, fifo initial
diff --git a/demos/amlogic/n200/include/a5/register.h b/demos/amlogic/n200/include/a5/register.h
index 112f999..3892843 100644
--- a/demos/amlogic/n200/include/a5/register.h
+++ b/demos/amlogic/n200/include/a5/register.h
@@ -216,14 +216,14 @@
//bit 10 force to disable the clock of dfi command generation
//bit 9 force to disable the clock of dram controller
//bit 8 force to disable the clock of dfi data path.
- //bit 7. force to disalbe the clock of write rsp generation.
- //bit 6. force to disalbe the clock of read rsp generation.
- //bit 5. force to disalbe the clock of command filter.
- //bit 4. force to disalbe the clock of write reorder buffer.
- //bit 3. force to disalbe the clock of write data buffer.
- //bit 2. force to disalbe the clock of read reorder buffer.
- //bit 1. force to disalbe the clock of read canvas.
- //bit 0. force to disalbe the clock of write canvas.
+ //bit 7. force to disable the clock of write rsp generation.
+ //bit 6. force to disable the clock of read rsp generation.
+ //bit 5. force to disable the clock of command filter.
+ //bit 4. force to disable the clock of write reorder buffer.
+ //bit 3. force to disable the clock of write data buffer.
+ //bit 2. force to disable the clock of read reorder buffer.
+ //bit 1. force to disable the clock of read canvas.
+ //bit 0. force to disable the clock of write canvas.
#define DMC_MON_CTRL0 ((0x0020 << 2) + 0xfe036000)
//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
@@ -244,7 +244,7 @@
#define DMC_MON_ALL16_BW ((0x0024 << 2) + 0xfe036000)
// at the test period, the whole MMC granted data cycles which goes to 16bits ddr. unit:64bits
#define DMC_MON0_CTRL ((0x0025 << 2) + 0xfe036000)
- //BW MONTIOR 0 address range control. start addrss <= AXI address[31:16] <= end address
+ //BW MONITOR 0 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define DMC_MON0_CTRL1 ((0x0026 << 2) + 0xfe036000)
@@ -255,7 +255,7 @@
#define DMC_MON0_BW ((0x0028 << 2) + 0xfe036000)
// at the test period, this range granted data cycles for the selected channel and ports.
#define DMC_MON1_CTRL ((0x0029 << 2) + 0xfe036000)
- //BW monitor 1 address range control. start addrss <= AXI address[31:16] <= end address
+ //BW monitor 1 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define DMC_MON1_CTRL1 ((0x002a << 2) + 0xfe036000)
@@ -266,7 +266,7 @@
#define DMC_MON1_BW ((0x002c << 2) + 0xfe036000)
// at the test period, this range granted data cycles for the selected channel and ports.
#define DMC_MON2_CTRL ((0x002d << 2) + 0xfe036000)
- //BW monitor 2 address range control. start addrss <= AXI address[31:16] <= end address
+ //BW monitor 2 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define DMC_MON2_CTRL1 ((0x002e << 2) + 0xfe036000)
@@ -277,7 +277,7 @@
#define DMC_MON2_BW ((0x0030 << 2) + 0xfe036000)
// at the test period, this range granted data cycles for the selected channel and ports.
#define DMC_MON3_CTRL ((0x0031 << 2) + 0xfe036000)
- //BW monitor 3 address range control. start addrss <= AXI address[31:16] <= end address
+ //BW monitor 3 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define DMC_MON3_CTRL1 ((0x0032 << 2) + 0xfe036000)
@@ -288,7 +288,7 @@
#define DMC_MON3_BW ((0x0034 << 2) + 0xfe036000)
// at the test period, this range granted data cycles for the selected channel and ports.
#define DMC_MON4_CTRL ((0x0035 << 2) + 0xfe036000)
- //BW monitor 4 address range control. start addrss <= AXI address[31:16] <= end address
+ //BW monitor 4 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define DMC_MON4_CTRL1 ((0x0036 << 2) + 0xfe036000)
@@ -299,7 +299,7 @@
#define DMC_MON4_BW ((0x0038 << 2) + 0xfe036000)
// at the test period, this range granted data cycles for the selected channel and ports.
#define DMC_MON5_CTRL ((0x0039 << 2) + 0xfe036000)
- //BW monitor 5 address range control. start addrss <= AXI address[31:16] <= end address
+ //BW monitor 5 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define DMC_MON5_CTRL1 ((0x003a << 2) + 0xfe036000)
@@ -310,7 +310,7 @@
#define DMC_MON5_BW ((0x003c << 2) + 0xfe036000)
// at the test period, this range granted data cycles for the selected channel and ports.
#define DMC_MON6_CTRL ((0x003d << 2) + 0xfe036000)
- //BW monitor 6 address range control. start addrss <= AXI address[31:16] <= end address
+ //BW monitor 6 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define DMC_MON6_CTRL1 ((0x003e << 2) + 0xfe036000)
@@ -321,7 +321,7 @@
#define DMC_MON6_BW ((0x0040 << 2) + 0xfe036000)
// at the test period, this range granted data cycles for the selected channel and ports.
#define DMC_MON7_CTRL ((0x0041 << 2) + 0xfe036000)
- //BW monitor 7 address range control. start addrss <= AXI address[31:16] <= end address
+ //BW monitor 7 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define DMC_MON7_CTRL1 ((0x0042 << 2) + 0xfe036000)
@@ -363,7 +363,7 @@
//bit 15:8. write urgent 1 request pending hold num.
//bit 7:0. write urgent 0 request pending hold num.
#define DMC_CMD_FILTER_CTRL7 ((0x0056 << 2) + 0xfe036000)
- //bit 31:24. aw_req_pedning singal assertion after wbuf full.
+ //bit 31:24. aw_req_pending singal assertion after wbuf full.
//bit 23:16 aw_req_pending singal hold how long if wbuf not full.
//bit 15:8 write to read waiting cycles if there write hit request.
//bit 7:0 read to write waiting cycles if there write hit request.
@@ -547,7 +547,7 @@
#define DMC_CHAN_STS ((0x00ce << 2) + 0xfe036000)
//AXI0 is first CPU and Mali combined channel from CCI-400 directly. The first 2Gbyte address will go through this channel.
//AXI10 is the second CPU, Mali channel combined with NNA from NIC-400. The upper 2Gbyte address will go through this channel.
- // read only regsiter.
+ // read only register.
// the second mali and NNA channel IDLE.
// the second CPU channel IDLE.
// the first mali channel IDLE.
@@ -568,7 +568,7 @@
//bit 31:16 : range end address.
//bit 15:0 : range start address
#define DMC_PROT0_CTRL ((0x00d1 << 2) + 0xfe036000)
- //bit 23:16. each bit to eanble one of the 8 ambus channal for the protection function.
+ //bit 23:16. each bit to enable one of the 8 ambus channal for the protection function.
//bit 15:0 each bit to enable one of the 15 channel input for the protection function.
#define DMC_PROT0_CTRL1 ((0x00d2 << 2) + 0xfe036000)
//bit 26. protection 0 read access protection enable.
@@ -580,7 +580,7 @@
//bit 31:16 : range end address.
//bit 15:0 : range start address
#define DMC_PROT1_CTRL ((0x00d4 << 2) + 0xfe036000)
- //bit 23:16. each bit to eanble one of the 8 ambus channal for the protection function.
+ //bit 23:16. each bit to enable one of the 8 ambus channal for the protection function.
//bit 15:0 each bit to enable one of the 15 channel input for the protection function.
#define DMC_PROT1_CTRL1 ((0x00d5 << 2) + 0xfe036000)
//bit 26. protection range 1 read access protection enable bit.
@@ -661,37 +661,37 @@
//bit 31:16. the Forth cycle.
//bit 15:0. the third cycle.
#define DMC_TEST_WD0 ((0x0010 << 2) + 0xfe037800)
- // write data 0 for write command. also for read back data comparision.
+ // write data 0 for write command. also for read back data comparison.
#define DMC_TEST_WD1 ((0x0011 << 2) + 0xfe037800)
- // write data 1 for write command. also for read back data comparision.
+ // write data 1 for write command. also for read back data comparison.
#define DMC_TEST_WD2 ((0x0012 << 2) + 0xfe037800)
- // write data 2 for write command. also for read back data comparision.
+ // write data 2 for write command. also for read back data comparison.
#define DMC_TEST_WD3 ((0x0013 << 2) + 0xfe037800)
- // write data 3 for write command. also for read back data comparision.
+ // write data 3 for write command. also for read back data comparison.
#define DMC_TEST_WD4 ((0x0014 << 2) + 0xfe037800)
- // write data 4 for write command. also for read back data comparision.
+ // write data 4 for write command. also for read back data comparison.
#define DMC_TEST_WD5 ((0x0015 << 2) + 0xfe037800)
- // write data 5 for write command. also for read back data comparision.
+ // write data 5 for write command. also for read back data comparison.
#define DMC_TEST_WD6 ((0x0016 << 2) + 0xfe037800)
- // write data 6 for write command. also for read back data comparision.
+ // write data 6 for write command. also for read back data comparison.
#define DMC_TEST_WD7 ((0x0017 << 2) + 0xfe037800)
- // write data 7 for write command. also for read back data comparision.
+ // write data 7 for write command. also for read back data comparison.
#define DMC_TEST_WD8 ((0x0018 << 2) + 0xfe037800)
- // write data 8 for write command. also for read back data comparision.
+ // write data 8 for write command. also for read back data comparison.
#define DMC_TEST_WD9 ((0x0019 << 2) + 0xfe037800)
- // write data 9 for write command. also for read back data comparision.
+ // write data 9 for write command. also for read back data comparison.
#define DMC_TEST_WD10 ((0x001a << 2) + 0xfe037800)
- // write data 10 for write command. also for read back data comparision.
+ // write data 10 for write command. also for read back data comparison.
#define DMC_TEST_WD11 ((0x001b << 2) + 0xfe037800)
- // write data 11 for write command. also for read back data comparision.
+ // write data 11 for write command. also for read back data comparison.
#define DMC_TEST_WD12 ((0x001c << 2) + 0xfe037800)
- // write data 12 for write command. also for read back data comparision.
+ // write data 12 for write command. also for read back data comparison.
#define DMC_TEST_WD13 ((0x001d << 2) + 0xfe037800)
- // write data 13 for write command. also for read back data comparision.
+ // write data 13 for write command. also for read back data comparison.
#define DMC_TEST_WD14 ((0x001e << 2) + 0xfe037800)
- // write data 14 for write command. also for read back data comparision.
+ // write data 14 for write command. also for read back data comparison.
#define DMC_TEST_WD15 ((0x001f << 2) + 0xfe037800)
- // write data 15 for write command. also for read back data comparision.
+ // write data 15 for write command. also for read back data comparison.
#define DMC_TEST_RD0 ((0x0020 << 2) + 0xfe037800)
// the read back data 0. if error happens, it would capture the first error data.
#define DMC_TEST_RD1 ((0x0021 << 2) + 0xfe037800)
@@ -830,7 +830,7 @@
#define DMC_DRAM_TDPD ((0x001d << 2) + 0xfe036400)
//not support.
#define DMC_DRAM_DFITCTRLDELAY ((0x001e << 2) + 0xfe036400)
- //bit 3:0. DFI_t_ctrldealy
+ //bit 3:0. DFI_t_ctrldelay
#define DMC_DRAM_DFITPHYWRDATA ((0x001f << 2) + 0xfe036400)
//bit 5:0. dfi_t_phy_wrdata.
#define DMC_DRAM_DFITPHYWRLAT ((0x0020 << 2) + 0xfe036400)
@@ -840,7 +840,7 @@
#define DMC_DRAM_DFITPHYRDLAT ((0x0022 << 2) + 0xfe036400)
//bit 5:0. dfi_t_rdlat.
#define DMC_DRAM_DFITCTRLUPDMIN ((0x0023 << 2) + 0xfe036400)
- //bit 7:0. CTRLUPD_MIN minimux clock cycle to maintain CTRLUPD_REQ.
+ //bit 7:0. CTRLUPD_MIN minimum clock cycle to maintain CTRLUPD_REQ.
#define DMC_DRAM_DFITCTRLUPDMAX ((0x0024 << 2) + 0xfe036400)
//bit 7:0 CTRLUPD_MAX. maxmum clock cycle to maintain CTRLUPD_REQ if no CTRLUPD_ACK response.
#define DMC_DRAM_DFITREFMSKI ((0x0026 << 2) + 0xfe036400)
@@ -916,7 +916,7 @@
//23:16. when to send PHY ZQ UPDATE command.
//15:8. when to send ZQCS/ZQCAL to rank1 DDR SDRAM.
//7:0. when to senc ZQCS/ZQCAL to rank0 DDR SDRAM.
-//timing paramter for frequency set 1.
+//timing parameter for frequency set 1.
#define DMC_NFQ_TMRD ((0x0040 << 2) + 0xfe036400)
#define DMC_NFQ_TRFC ((0x0041 << 2) + 0xfe036400)
#define DMC_NFQ_TRP ((0x0042 << 2) + 0xfe036400)
@@ -1002,7 +1002,7 @@
//bit 10 1: enable staggered chip select for 2 ranks DRAM.
//bit 9 1: enable send auto refresh command to DDR SDRAM when PCTL is in CFG/STOP state.
//bit 8 send auto refr cmd before enter register triggered self refresh
- //bit 7 send auto refr cmd after exit regsiter triggered self refresh mode.
+ //bit 7 send auto refr cmd after exit register triggered self refresh mode.
//bit 6 disable dram clock after enter register triggered self refresh.
//bit 5 send DFI_LP_REQ to PHY after enter register triggered elf refresh mode.
//bit 4 send DRAM to power down mode after enter self refresh. ONLY for LPDDR4.
@@ -1086,7 +1086,7 @@
//bit 31 . write 1 to change freqency read 0: finished.
//bit 30. waiting for software to send some manual command. 1 : waiting. 0 : not ready yet.
//bit 29:23. not used.
-//bit 22. after freqchenge send refresh command.
+//bit 22. after freqchange send refresh command.
//bit 21 after Freqchange send PHY ZQ update.
//bit 20 send CTRLUPD_REQ to PHY after freq_change finished.
//bit 19:16. how many cycles to send PLL change req after init_complete signal to low.
@@ -1094,7 +1094,7 @@
//bit 14. freq post config_en. After freq enter stop state let DMC configure DDR SDRAM.
//bit 13. send zqcl after freq change in DDR3/4 mode.
//bit 12. send zqcs after freq change. 1: enable. 0 not send.
-//bit 11. in AUTO MRW fucntion: the data format. 1: use USR_CMD format. 0: MRW format.
+//bit 11. in AUTO MRW function: the data format. 1: use USR_CMD format. 0: MRW format.
//bit 10. AUTO MRW function: 1 use hardware auto MRW function. 0: don't do auto MRW.
//bit 9. 1 : FREQ MRW done. let FREQ change machine continue.
//bit 8 FREQ WAIT. 1 when freq change finishes, state machine stop at self refresh state in case there's something need to handle.
@@ -1172,7 +1172,7 @@
//bit 25:24 : retraining dfi_freq[4:3], the [2:0] bit still use the dfi_freq bits to keep the frequency.
//bit 23:0: retraining period unit : 100ns.
#define DMC_DFI_ERR_STAT ((0x0098 << 2) + 0xfe036400)
- //LPDDR4 PHY DFI error infomation.
+ //LPDDR4 PHY DFI error information.
//bit 31:20. not used.
//bit 9. ddr0_dfi_error
//bit 8:5 ddr0_dfi_error_info.
@@ -1677,7 +1677,7 @@
//DMC use 15bits ID to identify the input ports and ID.
// bit 14:10.
// AXI bus ID number from 0 ~15. 2, 8~10, 12~15 Not used the others defined as bellow.
-// 0 : CPU and MALI. Mali and cpu will be seperated to 2 channel. CPU traffic will be assigned to ID = 0. Mali traffic will assigned to ID =1.
+// 0 : CPU and MALI. Mali and cpu will be separated to 2 channel. CPU traffic will be assigned to ID = 0. Mali traffic will assigned to ID =1.
// 1 : Mali
// 3 : HDMI.
// 4 : HEVC. //HEVC_F/B combined to one
@@ -2060,37 +2060,37 @@
//bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
//bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
#define DDR_APB_SEC_CTRL2 ((0x00f2 << 2) + 0xfe037000)
- // APB access control for DMC PLL clock frequency control regsiter.
+ // APB access control for DMC PLL clock frequency control register.
//default : 0x005
//bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
//bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
#define DDR_APB_SEC_CTRL3 ((0x00f3 << 2) + 0xfe037000)
- // APB access control for DMC sticky control regsiter.
+ // APB access control for DMC sticky control register.
//default : 0x005
//bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
//bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
#define DDR_APB_SEC_CTRL4 ((0x00f4 << 2) + 0xfe037000)
- // APB access control for DMC test control regsiter.
+ // APB access control for DMC test control register.
//default : 0x005
//bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
//bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
#define DDR_APB_SEC_CTRL5 ((0x00f5 << 2) + 0xfe037000)
- // APB access control for DMC clk reset control regsiter.
+ // APB access control for DMC clk reset control register.
//default : 0x005
//bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
//bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
#define DDR_APB_SEC_CTRL6 ((0x00f6 << 2) + 0xfe037000)
- // APB access control for DMC protection regsiter.
+ // APB access control for DMC protection register.
//default : 0x005
//bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
//bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
#define DDR_APB_SEC_CTRL7 ((0x00f7 << 2) + 0xfe037000)
- // APB access control for DMC normal regsiter.
+ // APB access control for DMC normal register.
//default : 0x0ff
//bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
//bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
#define DDR_APB_SEC_CTRL8 ((0x00f8 << 2) + 0xfe037000)
- // APB access control for DDR PHY group regsiters.
+ // APB access control for DDR PHY group registers.
//default : 0x50005
//bit 23:16. APB access enable for DDR PHY group 1 register.
//bit 10 PHY IMEM control 1: force PHY IMEM output 0. 0: normal working mode.
@@ -2098,7 +2098,7 @@
//bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
//bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
#define DDR_APB_SEC_CTRL9 ((0x00f9 << 2) + 0xfe037000)
- // APB access control for DMC canvas regsiter.
+ // APB access control for DMC canvas register.
//default : 0x005
//bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
//bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
@@ -2358,7 +2358,7 @@
#define DMC_DDR_CTRL1 ((0x0130 << 2) + 0xfe037000)
//bit 1. 1: only allow DMA/DEMUX write data level == region security level. 0: DMA/DEMUX write data level <= region sec level.
//bit 0. DMC_DDR_LOCK. 1: LOCK DMC_DDR_CTRL, DMC_DDR_CTRL1, DMC_AXI2DDRx, DDR0/1_ADDRMAP_x registers. those register can't modified any more.
- // 0: all these regsiters can be read/write by secure APB access.
+ // 0: all these registers can be read/write by secure APB access.
//
// Closing file: ../mmc_lp4/dmc/rtl/dmc_reg.vh
//
@@ -2393,7 +2393,7 @@
//bit 5. LPDT data endian. 1 = transfer the high bit first. 0 : transfer the low bit first.
//bit 4. HS data endian.
//bit 3. force data byte lane in stop mode.
- //bit 2. force data byte lane 0 in reciever mode.
+ //bit 2. force data byte lane 0 in receiver mode.
//bit 1. write 1 to sync the txclkesc input. the internal logic have to use txclkesc to decide Txvalid and Txready.
//bit 0. enalbe the MIPI DSI PHY TxDDRClk.
#define MIPI_DSI_CHAN_CTRL ((0x0001 << 2) + 0xfe01c000)
@@ -2452,8 +2452,8 @@
#define MIPI_DSI_WAKEUP_TIM ((0x0008 << 2) + 0xfe01c000)
//TWAKEUP.
#define MIPI_DSI_LPOK_TIM ((0x0009 << 2) + 0xfe01c000)
- //bit 31:0 when in RxULPS state, RX reciever is in sleep mode.
- //every MIPI_DSI_ULPS_CHECK period, the reciever would be enabled once, and waiting this timer period to get the stable input.
+ //bit 31:0 when in RxULPS state, RX receiver is in sleep mode.
+ //every MIPI_DSI_ULPS_CHECK period, the receiver would be enabled once, and waiting this timer period to get the stable input.
#define MIPI_DSI_LP_WCHDOG ((0x000a << 2) + 0xfe01c000)
//bit 31:0 watch dog timer for MIPI DSI LP receive state.
#define MIPI_DSI_ANA_CTRL ((0x000b << 2) + 0xfe01c000)
@@ -2464,7 +2464,7 @@
#define MIPI_DSI_TURN_WCHDOG ((0x000d << 2) + 0xfe01c000)
//bit 31:0 watch dog timer for lane 0 LP turn around waiting time.
#define MIPI_DSI_ULPS_CHECK ((0x000e << 2) + 0xfe01c000)
- //bit 31:0 when Lane0 in LP recieve state, if the another side sent Low power command, using this timer to enable Tcheck the another size wakeup nor not.
+ //bit 31:0 when Lane0 in LP receive state, if the another side sent Low power command, using this timer to enable Tcheck the another size wakeup nor not.
#define MIPI_DSI_TEST_CTRL0 ((0x000f << 2) + 0xfe01c000)
#define MIPI_DSI_TEST_CTRL1 ((0x0010 << 2) + 0xfe01c000)
//========================================================================
@@ -4961,7 +4961,7 @@
#define BT_CLK27_SEL_BIT 7 // 1 : external xclk27 0 : internal clk27.
#define BT_CLK27_PHASE_BIT 6 // 1 : no inverted 0 : inverted.
#define BT_ACE_MODE_BIT 5 // 1 : auto cover error by hardware.
- #define BT_SLICE_MODE_BIT 4 // 1 : no ancillay flag 0 : with ancillay flag.
+ #define BT_SLICE_MODE_BIT 4 // 1 : no ancillary flag 0 : with ancillary flag.
#define BT_FMT_MODE_BIT 3 // 1 : ntsc 0 : pal.
#define BT_REF_MODE_BIT 2 // 1 : from bit stream. 0 : from ports.
#define BT_MODE_BIT 1 // 1 : BT656 model 0 : SAA7118 mode.
@@ -6686,16 +6686,16 @@
//Bit 6:4, reg_frddr_type ,default = 0
//Bit 3:0, reserved
#define EARCTX_SPDIFOUT_PREAMB ((0x0006 << 2) + 0xfe333400)
-//Bit 31, reg_premable_Z_set ,default = 0,user 8'b11101000 1 user 7:0
-//Bit 30, reg_premable_Y_set ,default = 0,user 8'b11100100 1 user 15:8
-//Bit 29, reg_premable_X_set ,default = 0,user 8'b11100010 1 user 23:16
+//Bit 31, reg_preamble_Z_set ,default = 0,user 8'b11101000 1 user 7:0
+//Bit 30, reg_preamble_Y_set ,default = 0,user 8'b11100100 1 user 15:8
+//Bit 29, reg_preamble_X_set ,default = 0,user 8'b11100010 1 user 23:16
//Bit 28:24, reserved
-//Bit 23:16, reg_premable_X_value ,default = 0
-//Bit 15:8, reg_premable_Y_value ,default = 0
-//Bit 7:0, reg_premable_Z_value ,default = 0
+//Bit 23:16, reg_preamble_X_value ,default = 0
+//Bit 15:8, reg_preamble_Y_value ,default = 0
+//Bit 7:0, reg_preamble_Z_value ,default = 0
#define EARCTX_SPDIFOUT_SWAP ((0x0007 << 2) + 0xfe333400)
//Bit 31:16, reg_hold_cnt ,default = 0,hold start cnt ,valid when reg_hold_for_tdm set 1
-//Bit 15, reg_init_send_en ,default = 0,send 01 sequence some times after intial done from frddr set
+//Bit 15, reg_init_send_en ,default = 0,send 01 sequence some times after initial done from frddr set
//Bit 14:0, reg_init_send_cnt ,default = 0,send 01 sequence time ,valid when reg_init_send_en set 1
#define EARCTX_ERR_CORRT_CTRL0 ((0x0008 << 2) + 0xfe333400)
//Bit 31:24, reserved
@@ -6740,7 +6740,7 @@
//Bit 21, reg_data_sel ,default = 0,//data sel: 0 data 1 reg_mute_data_value
//Bit 20:19, reg_ubit_sel ,default = 0,//userBit sel: 0 data 1 reg_value 2 fifo data
//Bit 18, reg_vbit_sel ,default = 0,//validBit sel: 0 data 1 reg_value
-//Bit 17, reg_chst_sel ,default = 0,//chanel status sel: 0 data 1 reg_value
+//Bit 17, reg_chst_sel ,default = 0,//channel status sel: 0 data 1 reg_value
//Bit 16, reg_ubit_fifo_less_irq_en ,default = 0,fifo_less_thd irq enable
//Bit 15:8, reg_ubit_fifo_start_thd ,default = 0,start transmit iu after fifo level greater than this value
//Bit 7:0, reg_ubit_fifo_less_thd ,default = 0,generate irq,when fifo level less than this value
@@ -7091,22 +7091,22 @@
#define EARC_RX_CMDC_STATUS5 ((0x002c << 2) + 0xfe333800)
//Bit 31:0, ro_cmdc_status5 unsigned, RO, default = 0,
#define EARC_RX_CMDC_STATUS6 ((0x002d << 2) + 0xfe333800)
-//Bit 31, ro_idle2_int unsigned, RO, dfault =0
-//Bit 30, ro_idle1_int unsigned, RO, dfault =0
-//Bit 29, ro_disc2_int unsigned, RO, dfault =0
-//Bit 28, ro_disc1_int unsigned, RO, dfault =0
-//Bit 27, ro_earc_int unsigned, RO, dfault =0
-//Bit 26, ro_hb_status_int unsigned, RO, dfault =0
-//Bit 25, ro_losthb_int unsigned, RO, dfault =0
-//Bit 24, ro_timeout_int unsigned, RO, dfault =0
-//Bit 23, ro_status_ch_int unsigned, RO, dfault =0
-//Bit 22, ro_int_rec_invalid_id unsigned, RO, dfault =0
-//Bit 21, ro_int_rec_invalid_offset unsigned, RO, dfault =0
-//Bit 20, ro_int_rec_unexp unsigned, RO, dfault =0
-//Bit 19, ro_int_rec_ecc_err unsigned, RO, dfault =0
-//Bit 18, ro_int_rec_parity_err unsigned, RO, dfault =0
-//Bit 17, ro_int_recv_packet unsigned, RO, dfault =0
-//Bit 16, ro_int_rec_time_out unsigned, RO, dfault =0
+//Bit 31, ro_idle2_int unsigned, RO, default =0
+//Bit 30, ro_idle1_int unsigned, RO, default =0
+//Bit 29, ro_disc2_int unsigned, RO, default =0
+//Bit 28, ro_disc1_int unsigned, RO, default =0
+//Bit 27, ro_earc_int unsigned, RO, default =0
+//Bit 26, ro_hb_status_int unsigned, RO, default =0
+//Bit 25, ro_losthb_int unsigned, RO, default =0
+//Bit 24, ro_timeout_int unsigned, RO, default =0
+//Bit 23, ro_status_ch_int unsigned, RO, default =0
+//Bit 22, ro_int_rec_invalid_id unsigned, RO, default =0
+//Bit 21, ro_int_rec_invalid_offset unsigned, RO, default =0
+//Bit 20, ro_int_rec_unexp unsigned, RO, default =0
+//Bit 19, ro_int_rec_ecc_err unsigned, RO, default =0
+//Bit 18, ro_int_rec_parity_err unsigned, RO, default =0
+//Bit 17, ro_int_recv_packet unsigned, RO, default =0
+//Bit 16, ro_int_rec_time_out unsigned, RO, default =0
//Bit 15:0, reserved
//
// Closing file: earc_rx_cmdc.h
@@ -7248,10 +7248,10 @@
//Bit 31, reg_work_enable unsigned, default = 0, dmac user bit decode enable
//Bit 30:24, reg_iu_sync unsigned, default = 0, iu sync value
//Bit 23:16, reg_fifo_thd unsigned, default = 0, generate irq when fifo level pass some threshold
-//Bit 15, reg_max_dist_en unsigned, default = 0, max distance bewteen IUs to set lost
+//Bit 15, reg_max_dist_en unsigned, default = 0, max distance between IUs to set lost
//Bit 14, reg_iu_sync_en unsigned, default = 0, iu sync code enable 0 : all iu to fifo 1 only sync iu packet to fifo
//Bit 13:12, reg_user_lr unsigned, default = 0, 00 off 01 use l channel userbit 10 use r channel userbit 11 user lr channel userbit
-//Bit 11:8, reg_max_dist unsigned, default = 0, max distance bewteen IUs value
+//Bit 11:8, reg_max_dist unsigned, default = 0, max distance between IUs value
//Bit 7, reg_fifo_thd_en unsigned, default = 0, fifo_thd irq enable
//Bit 6, reg_fifo_lost_init_en unsigned, default = 0, when lost,initial fifo
//Bit 5, reg_fifo_init unsigned, default = 0, fifo initial
diff --git a/demos/amlogic/n200/include/p1/register.h b/demos/amlogic/n200/include/p1/register.h
index 50baa85..da9d4db 100755
--- a/demos/amlogic/n200/include/p1/register.h
+++ b/demos/amlogic/n200/include/p1/register.h
@@ -5618,16 +5618,16 @@
//Bit 6:4, reg_frddr_type ,default = 0
//Bit 3:0, reserved
#define EARCTX_SPDIFOUT_PREAMB ((0x0006 << 2) + 0xfe333400)
-//Bit 31, reg_premable_Z_set ,default = 0,user 8'b11101000 1 user 7:0
-//Bit 30, reg_premable_Y_set ,default = 0,user 8'b11100100 1 user 15:8
-//Bit 29, reg_premable_X_set ,default = 0,user 8'b11100010 1 user 23:16
+//Bit 31, reg_preamble_Z_set ,default = 0,user 8'b11101000 1 user 7:0
+//Bit 30, reg_preamble_Y_set ,default = 0,user 8'b11100100 1 user 15:8
+//Bit 29, reg_preamble_X_set ,default = 0,user 8'b11100010 1 user 23:16
//Bit 28:24, reserved
-//Bit 23:16, reg_premable_X_value ,default = 0
-//Bit 15:8, reg_premable_Y_value ,default = 0
-//Bit 7:0, reg_premable_Z_value ,default = 0
+//Bit 23:16, reg_preamble_X_value ,default = 0
+//Bit 15:8, reg_preamble_Y_value ,default = 0
+//Bit 7:0, reg_preamble_Z_value ,default = 0
#define EARCTX_SPDIFOUT_SWAP ((0x0007 << 2) + 0xfe333400)
//Bit 31:16, reg_hold_cnt ,default = 0,hold start cnt ,valid when reg_hold_for_tdm set 1
-//Bit 15, reg_init_send_en ,default = 0,send 01 sequence some times after intial done from frddr set
+//Bit 15, reg_init_send_en ,default = 0,send 01 sequence some times after initial done from frddr set
//Bit 14:0, reg_init_send_cnt ,default = 0,send 01 sequence time ,valid when reg_init_send_en set 1
#define EARCTX_ERR_CORRT_CTRL0 ((0x0008 << 2) + 0xfe333400)
//Bit 31:24, reserved
@@ -5672,7 +5672,7 @@
//Bit 21, reg_data_sel ,default = 0,//data sel: 0 data 1 reg_mute_data_value
//Bit 20:19, reg_ubit_sel ,default = 0,//userBit sel: 0 data 1 reg_value 2 fifo data
//Bit 18, reg_vbit_sel ,default = 0,//validBit sel: 0 data 1 reg_value
-//Bit 17, reg_chst_sel ,default = 0,//chanel status sel: 0 data 1 reg_value
+//Bit 17, reg_chst_sel ,default = 0,//channel status sel: 0 data 1 reg_value
//Bit 16, reg_ubit_fifo_less_irq_en ,default = 0,fifo_less_thd irq enable
//Bit 15:8, reg_ubit_fifo_start_thd ,default = 0,start transmit iu after fifo level greater than this value
//Bit 7:0, reg_ubit_fifo_less_thd ,default = 0,generate irq,when fifo level less than this value
@@ -6023,22 +6023,22 @@
#define EARC_RX_CMDC_STATUS5 ((0x002c << 2) + 0xfe333800)
//Bit 31:0, ro_cmdc_status5 unsigned, RO, default = 0,
#define EARC_RX_CMDC_STATUS6 ((0x002d << 2) + 0xfe333800)
-//Bit 31, ro_idle2_int unsigned, RO, dfault =0
-//Bit 30, ro_idle1_int unsigned, RO, dfault =0
-//Bit 29, ro_disc2_int unsigned, RO, dfault =0
-//Bit 28, ro_disc1_int unsigned, RO, dfault =0
-//Bit 27, ro_earc_int unsigned, RO, dfault =0
-//Bit 26, ro_hb_status_int unsigned, RO, dfault =0
-//Bit 25, ro_losthb_int unsigned, RO, dfault =0
-//Bit 24, ro_timeout_int unsigned, RO, dfault =0
-//Bit 23, ro_status_ch_int unsigned, RO, dfault =0
-//Bit 22, ro_int_rec_invalid_id unsigned, RO, dfault =0
-//Bit 21, ro_int_rec_invalid_offset unsigned, RO, dfault =0
-//Bit 20, ro_int_rec_unexp unsigned, RO, dfault =0
-//Bit 19, ro_int_rec_ecc_err unsigned, RO, dfault =0
-//Bit 18, ro_int_rec_parity_err unsigned, RO, dfault =0
-//Bit 17, ro_int_recv_packet unsigned, RO, dfault =0
-//Bit 16, ro_int_rec_time_out unsigned, RO, dfault =0
+//Bit 31, ro_idle2_int unsigned, RO, default =0
+//Bit 30, ro_idle1_int unsigned, RO, default =0
+//Bit 29, ro_disc2_int unsigned, RO, default =0
+//Bit 28, ro_disc1_int unsigned, RO, default =0
+//Bit 27, ro_earc_int unsigned, RO, default =0
+//Bit 26, ro_hb_status_int unsigned, RO, default =0
+//Bit 25, ro_losthb_int unsigned, RO, default =0
+//Bit 24, ro_timeout_int unsigned, RO, default =0
+//Bit 23, ro_status_ch_int unsigned, RO, default =0
+//Bit 22, ro_int_rec_invalid_id unsigned, RO, default =0
+//Bit 21, ro_int_rec_invalid_offset unsigned, RO, default =0
+//Bit 20, ro_int_rec_unexp unsigned, RO, default =0
+//Bit 19, ro_int_rec_ecc_err unsigned, RO, default =0
+//Bit 18, ro_int_rec_parity_err unsigned, RO, default =0
+//Bit 17, ro_int_recv_packet unsigned, RO, default =0
+//Bit 16, ro_int_rec_time_out unsigned, RO, default =0
//Bit 15:0, reserved
//
// Closing file: ./earc_rx_cmdc.h
@@ -6181,10 +6181,10 @@
//Bit 31, reg_work_enable unsigned, default = 0, dmac user bit decode enable
//Bit 30:24, reg_iu_sync unsigned, default = 0, iu sync value
//Bit 23:16, reg_fifo_thd unsigned, default = 0, generate irq when fifo level pass some threshold
-//Bit 15, reg_max_dist_en unsigned, default = 0, max distance bewteen IUs to set lost
+//Bit 15, reg_max_dist_en unsigned, default = 0, max distance between IUs to set lost
//Bit 14, reg_iu_sync_en unsigned, default = 0, iu sync code enable 0 : all iu to fifo 1 only sync iu packet to fifo
//Bit 13:12, reg_user_lr unsigned, default = 0, 00 off 01 use l channel userbit 10 use r channel userbit 11 user lr channel userbit
-//Bit 11:8, reg_max_dist unsigned, default = 0, max distance bewteen IUs value
+//Bit 11:8, reg_max_dist unsigned, default = 0, max distance between IUs value
//Bit 7, reg_fifo_thd_en unsigned, default = 0, fifo_thd irq enable
//Bit 6, reg_fifo_lost_init_en unsigned, default = 0, when lost,initial fifo
//Bit 5, reg_fifo_init unsigned, default = 0, fifo initial
@@ -8791,7 +8791,7 @@
// Bit 19:14 -- des_2 ts pl state -- Read Only
// Bit 13:8 -- des ts pl state -- Read Only
// Bit 3:0 PID index to 8 PID to get key-set
-// auto increse after TS_PL_PID_DATA read/write
+// auto increase after TS_PL_PID_DATA read/write
#define TS_PL_PID_INDEX ((0x00f3 << 2) + 0xfe040000)
// Bit 13 -- PID match disble
// Bit 12:0 -- PID
@@ -8819,7 +8819,7 @@
// [3] General enable for the ciplus module
// [2] AES CBC disable (default should be 0 to enable AES CBC)
// [1] AES Enable
-// [0] DES Eanble
+// [0] DES Enable
#define CIPLUS_CONFIG ((0x00fd << 2) + 0xfe040000)
// bit[31:28] AES IV endian
// bit[27:24] AES message out endian
@@ -11530,7 +11530,7 @@
// 1=ABH read request burst size 24;
// 2=ABH read request burst size 32;
// 3=ABH read request burst size 48.
-// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logics except register.
+// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logic except register.
// Bit 0 RW ctrl_free_clk_enable. 0=Default, Enable clock gating. 1=No clock gating, enable free clock.
#define RDMA_CTRL ((0x1114 << 2) + 0xff000000)
// Read only.
@@ -11627,7 +11627,7 @@
//Bit 7:6, component0 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in
//Bit 5, input window selection function enable
//Bit 4, enable VDIN common data input, otherwise there will be no video data input
-//Bit 3:0 vdin selection, 1: mpeg_in from dram, 2: bt656 input, 3: component input, 4: tvdecoder input, 5: hdmi rx input, 6: digtial video input, 7: loopback from Viu1, 8: MIPI.
+//Bit 3:0 vdin selection, 1: mpeg_in from dram, 2: bt656 input, 3: component input, 4: tvdecoder input, 5: hdmi rx input, 6: digital video input, 7: loopback from Viu1, 8: MIPI.
#define VDIN_COM_CTRL0 ((0x1202 << 2) + 0xff000000)
//Bit 28:16 active_max_pix_cnt, readonly
//Bit 12:0 active_max_pix_cnt_shadow, readonly
@@ -13272,7 +13272,7 @@
//Bit 0 reg_ldc_gain_lut_wr // unsigned , RW, default = 0 1:software write 0:software read.
#define LDC_GAIN_LUT_CTRL1 ((0x1475 << 2) + 0xff000000)
//Bit 31: 1 reserved
-//Bit 0 reg_ldc_gain_lut_str // unsigned , RW, default = 0 0->1:one software write/read start,postive edge valid.
+//Bit 0 reg_ldc_gain_lut_str // unsigned , RW, default = 0 0->1:one software write/read start,positive edge valid.
#define LDC_ADJ_VS_CTRL ((0x1476 << 2) + 0xff000000)
//Bit 31:16 reserved
//Bit 15:0 reg_ldc_blk_intsty_calc_intvl // unsigned , RW, default = 200 delay for one block intensity calculation period
@@ -13287,7 +13287,7 @@
//Bit 26 reg_ldc_prt_func_en //unsigned , RW, default = 0 1: enable LDC output protect function 0:disable LDC output protect function
//Bit 25 reg_ldc_bl_input_sft_ctr_en //unsigned , RW, default = 0 1: software control backlight info write index enable
//Bit 24:23 reg_ldc_bl_input_sft_wr_idx //unsigned , RW, default = 0 backlight info write index, for debug only
-//Bit 22 reg_ldc_vsync_get_bl_info_en //unsigned , RW, default = 1 0:get backlight info every block line (no vsync interrupt) 1:get backlight info accroding to vsync
+//Bit 22 reg_ldc_vsync_get_bl_info_en //unsigned , RW, default = 1 0:get backlight info every block line (no vsync interrupt) 1:get backlight info according to vsync
//Bit 21:20 reg_ldc_hist_burst_len //unsigned , RW, default = 0 0:2 times 128bit 1:4 times 128bit 2,3:6 times 128bit
//Bit 19:18 reg_ldc_blk_intsty_burst_len //unsigned , RW, default = 0 0:2 times 128bit 1:4 times 128bit 2:6 times 128bit 3:8 times 128bit
//Bit 17 reg_ldc_vs_edge_sel //unsigned , RW, default = 1 1:posedge vs sync 0:negedge vs sync
@@ -13776,7 +13776,7 @@
//bit 15: 8, mtn_minth
//bit 7: 0, mtn_maxth
#define DI_MTN_1_CTRL5 ((0x1744 << 2) + 0xff000000)
-//bit 31:28, mtn_m1b_extnd
+//bit 31:28, mtn_m1b_extend
//bit 27:24, mtn_m1b_errod
//bit 21:20, mtn_mot_txt_mode
//bit 19:18, mtn_replace_cbyy
@@ -14622,7 +14622,7 @@
//bit 15:8, reg_ei_int_drtdelay2_notver_sadth
//bit 7:0, reg_ei_int_drtdelay2_vlddrt_sadth
#define DI_MTN_1_CTRL6 ((0x17a9 << 2) + 0xff000000)
-//bit 31:24, mtn_m1b_extnd
+//bit 31:24, mtn_m1b_extend
//bit 23:16, mtn_m1b_errod
//bit 15: 8, mtn_core_ykinter
//bit 7: 0, mtn_core_ckinter
@@ -15578,9 +15578,9 @@
// Bit 15:13 v0_gofld_sel, 000: display go_field, 001: DI pre_frame_rst, 010: vdin0 go_field, 011: vdin1 go_field, otherwise: force go_field by
// reg_v0_go_field(bit19)
// Bit 12:6 hole_lines for d2d3 depth read interface
-// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 fomart output), 2'b10: scale output, otherwise nothing as v1
+// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 format output), 2'b10: scale output, otherwise nothing as v1
// Bit 3 use_vdin_eol, if true, use vdin eol as the v0_eol, otherwise using length to get the v0_eol
-// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 fomart output), 101: vpp scale output
+// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 format output), 101: vpp scale output
//
// `define D2D3_INTF_CTRL0 8'h09
#define VD1_AFBCD0_MISC_CTRL ((0x1a0a << 2) + 0xff000000)
@@ -15593,7 +15593,7 @@
// OSD1 registers 0x10-0x2f
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -15720,7 +15720,7 @@
// OSD2 registers 0x30-0x4f 0x64 -0x67
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -17440,9 +17440,9 @@
// Bit 0 SMOKE1 preblend enable only when preblend osd1 is not enable
#define VPP_SMOKE_CTRL ((0x1d29 << 2) + 0xff000000)
//smoke can be used only when that blending is disable and then be used as smoke function
-//smoke1 for OSD1 chanel
-//smoke2 for OSD2 chanel
-//smoke3 for VD2 chanel
+//smoke1 for OSD1 channel
+//smoke2 for OSD2 channel
+//smoke3 for VD2 channel
//31:24 Y
//23:16 Cb
//15:8 Cr
@@ -19081,7 +19081,7 @@
//`define DI_IF0_GEN_REG3 8'h42
//bit 31:1, reversed
//bit 0, cntl_64bit_rev
-// di arbtration :
+// di arbitration :
// the segment is 8'h50-8'h5f
//
// Reading file: ./di_arb_axi_regs.h
@@ -19289,13 +19289,13 @@
//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
//Bit 19 reserved
-//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
//Bit 11 reserved
//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
@@ -19707,13 +19707,13 @@
//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
//Bit 19 reserved
-//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
//Bit 11 reserved
//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
@@ -21620,7 +21620,7 @@
#define VPU_VENC_RGN_CTRL ((0x2789 << 2) + 0xff000000)
#define VPU_VENC_RGN_RSIZE ((0x278a << 2) + 0xff000000)
#define VPU_DISP_WRAP_CTRL ((0x278b << 2) + 0xff000000)
-// vpu arbtration :
+// vpu arbitration :
// the segment is 8'h90-8'hc8
//
// Reading file: ./vpu_arb_axi_regs.h
@@ -21854,8 +21854,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE1 ((0x27a6 << 2) + 0xff000000)
@@ -21867,8 +21867,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE2 ((0x27a7 << 2) + 0xff000000)
@@ -21880,8 +21880,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE3 ((0x27a8 << 2) + 0xff000000)
@@ -21893,8 +21893,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE4 ((0x27a9 << 2) + 0xff000000)
@@ -21906,8 +21906,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_WR_MODE0 ((0x27aa << 2) + 0xff000000)
@@ -21919,8 +21919,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_WR_MODE1 ((0x27ab << 2) + 0xff000000)
@@ -21932,8 +21932,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_WR_MODE2 ((0x27ac << 2) + 0xff000000)
@@ -21945,8 +21945,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_STAT ((0x27ad << 2) + 0xff000000)
@@ -24076,7 +24076,7 @@
// 0: unable; 1: enable, use neighboring mvs in refinement, default = 1
//Bit 11, reserved
//Bit 10, reg_mcdi_referrfrqchken
-// 0: unable; 1: enable, enable mv frquency check while finding min err in ref, default = 1
+// 0: unable; 1: enable, enable mv frequency check while finding min err in ref, default = 1
//Bit 9, reg_mcdi_refen
// 0: unable; 1: enable, enable mv refinement, default = 1
//Bit 8, reg_mcdi_horlineen
@@ -24160,7 +24160,7 @@
//Bit 19:16, reg_mcdi_chkedgedifthd0. thd0 for edge dif check (>=), default = 15
//Bit :15, reserved.
//Bit 14:10, reg_mcdi_chkedgechklen. total check length for edge check, 1~24 (>0), default = 24
-//Bit 9: 8, reg_mcdi_chkedgeedgesel. final edge select mode, 0: original start edge, 1: lpf start edge, 2: orignal start+end edge, 3: lpf start+end edge, default = 1
+//Bit 9: 8, reg_mcdi_chkedgeedgesel. final edge select mode, 0: original start edge, 1: lpf start edge, 2: original start+end edge, 3: lpf start+end edge, default = 1
//Bit 7: 3, reg_mcdi_chkedgesaddstgain. distance gain for sad calc while getting edges, default = 4
//Bit 2, reg_mcdi_chkedgechkmode. edge used in check mode, 0: original edge, 1: lpf edge, default = 1
//Bit 1, reg_mcdi_chkedgestartedge. edge mode for start edge, 0: original edge, 1: lpf edge, default = 0
@@ -24170,7 +24170,7 @@
//Bit 14:12, reg_mcdi_lmvvalidmode valid mode for lmv calc., 100b: use char det, 010b: use flt, 001b: use hori flg
//Bit 11:10, reg_mcdi_lmvgainmvmode four modes of mv selection for lmv weight calculation, default = 1
// 0: cur(x-3), lst(x-1,x,x+1); 1: cur(x-4,x-3), lst(x,x+1); 2: cur(x-5,x-4,x-3), lst(x-1,x,x+1,x+2,x+3); 3: cur(x-6,x-5,x-4,x-3), lst(x-1,x,x+1,x+2);
-//Bit 9, reg_mcdi_lmvinitmode initial lmvs at first row of input field, 0: intial value = 0; 1: inital = 32 (invalid), default = 0
+//Bit 9, reg_mcdi_lmvinitmode initial lmvs at first row of input field, 0: initial value = 0; 1: inital = 32 (invalid), default = 0
//Bit 8, reserved
//Bit 7: 4, reg_mcdi_lmvrt0 ratio of max mv, default = 5
//Bit 3: 0, reg_mcdi_lmvrt1 ratio of second max mv, default = 5
@@ -24283,15 +24283,15 @@
//Bit 3: 0, reg_mcdi_referrgmvgain. (locked) gmv gain for err calc. in ref, normalized to 8 as '1', default = 0
#define MCDI_REF_ERR_FRQ_CHK ((0x2f1d << 2) + 0xff000000)
//Bit 31:28, reserved
-//Bit 27:24, reg_mcdi_referrfrqgain. gain for mv frquency, normalized to 4 as '1', default = 10
+//Bit 27:24, reg_mcdi_referrfrqgain. gain for mv frequency, normalized to 4 as '1', default = 10
//Bit 23:21, reserved
-//Bit 20:16, reg_mcdi_referrfrqmax. max gain for mv frquency check, default = 31
+//Bit 20:16, reg_mcdi_referrfrqmax. max gain for mv frequency check, default = 31
//Bit 15, reserved
-//Bit 14:12, reg_mcdi_ref_errfrqmvdifthd2. mv dif threshold 2 (<) for mv frquency check, default = 3
+//Bit 14:12, reg_mcdi_ref_errfrqmvdifthd2. mv dif threshold 2 (<) for mv frequency check, default = 3
//Bit 11, reserved
-//Bit 10: 8, reg_mcdi_ref_errfrqmvdifthd1. mv dif threshold 1 (<) for mv frquency check, default = 2
+//Bit 10: 8, reg_mcdi_ref_errfrqmvdifthd1. mv dif threshold 1 (<) for mv frequency check, default = 2
//Bit 7, reserved
-//Bit 6: 4, reg_mcdi_ref_errfrqmvdifthd0. mv dif threshold 0 (<) for mv frquency check, default = 1
+//Bit 6: 4, reg_mcdi_ref_errfrqmvdifthd0. mv dif threshold 0 (<) for mv frequency check, default = 1
//Bit 3: 0, reserved
#define MCDI_QME_LPF_MSK ((0x2f1e << 2) + 0xff000000)
//Bit 31:28, reserved
@@ -27035,7 +27035,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 1 debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 1 debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -28998,13 +28998,13 @@
//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
//Bit 19 reserved
-//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
//Bit 11 reserved
//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
@@ -29304,7 +29304,7 @@
//bit[30] R-RW 0~1 0 reg_id_check : check the id of data path and req path
//bit[29] R-RW 0~1 0 reg_clear_fifo : manually reset bit
//bit[28] R-RW 0~1 0 reg_vsync_rst : soft_rst auto reset enable
-//bit[27] R-RW 0~1 0 reg_update_addr : manually udpate start addr
+//bit[27] R-RW 0~1 0 reg_update_addr : manually update start addr
//bit[26] R-RW 0~1 0 reg_addr_auto : auto update start addr enable
//bit[25] R-RW 0~1 0 reg_keep_receive : data path keep receive
//bit[24:19] R-RW 0~63 0 reg_req_th : fifo_room > req_th, then send the request
@@ -29812,7 +29812,7 @@
//Bit 3: 2, reg_nr_cti_blend_mode : blend mode of nr and lti result: 0: nr; 1:cti; 2: (nr+cti)/2; 3:cti + dlt_nr . unsigned , default = 1
//Bit 1: 0, reg_nr_lti_blend_mode : blend mode of nr and lti result: 0: nr; 1:lti; 2: (nr+lti)/2; 3:lti + dlt_nr . unsigned , default = 2
////////////////////////////////////////////////////////////////////////////////
-// new ti regsters from here
+// new ti registers from here
////////////////////////////////////////////////////////////////////////////////
#define LTI_DIR_CORE_ALPHA ((0x502a << 2) + 0xff000000)
//Bit 31:30, reserved
@@ -30113,7 +30113,7 @@
//Bit 23:16, reg_sr3_pk_hp_hvcon_replace8lv_gain //u8: gain to local variant before calculating the hv gain for peaking, normalized to 32 as "1" default = 32;
//Bit 15:8, reg_sr3_pk_bp_hvcon_replace8lv_gain //u8: gain to local variant before calculating the hv gain for peaking, normalized to 32 as "1" default = 32;
//Bit 7, reg_sr3_sad_intlev_mode //u1: interleave detection xerr mode: 0 max; 1:sum default=1
-//Bit 6, reg_sr3_sad_intlev_mode1 //u1: mode 1 of using diagonal protection: 0: no digonal protection; 1: with diagonal protection default=1
+//Bit 6, reg_sr3_sad_intlev_mode1 //u1: mode 1 of using diagonal protection: 0: no diagonal protection; 1: with diagonal protection default=1
//Bit 5:0, reg_sr3_sad_intlev_gain //u6: interleave detection for sad gain applied, normalized to 8 as 1 default=12
#define SHARP_DEJ_CTRL ((0x5064 << 2) + 0xff000000)
//Bit 31:4 reserved
@@ -30192,7 +30192,7 @@
#define SHARP_SR3_DERING_LUMA2PKGAIN_4TO6 ((0x506d << 2) + 0xff000000)
//Bit 31:24 reserved
//Bit 23:16 reg_sr3_dering_luma2pkgain6 // u8: rate1 (for bpcon>th1) of curve for dering pkgain based on LPF luma level. default =24
-//Bit 15:8 reg_sr3_dering_luma2pkgain5 // u8: rate0 (for bpcon<th0) of curve for dering pkgain based on LPF luma level. dfault =50
+//Bit 15:8 reg_sr3_dering_luma2pkgain5 // u8: rate0 (for bpcon<th0) of curve for dering pkgain based on LPF luma level. default =50
//Bit 7:0 reg_sr3_dering_luma2pkgain4 // u8: level limit(for bpcon>th1) of curve for dering pkgain based on LPF luma level. default =255
#define SHARP_SR3_DERING_LUMA2PKOS_0TO3 ((0x506e << 2) + 0xff000000)
//Bit 31:24 reg_sr3_dering_luma2pkos3 // u8: level limit(for th0<bpcon<th1) of curve for dering pkOS based on LPF luma level. default=255
@@ -30202,7 +30202,7 @@
#define SHARP_SR3_DERING_LUMA2PKOS_4TO6 ((0x506f << 2) + 0xff000000)
//Bit 31:24 reserved
//Bit 23:16 reg_sr3_dering_luma2pkos6 // u8: rate1 (for bpcon>th1) of curve for dering pkOS based on LPF luma level. default =24
-//Bit 15:8 reg_sr3_dering_luma2pkos5 // u8: rate0 (for bpcon<th0) of curve for dering pkOS based on LPF luma level. dfault =50
+//Bit 15:8 reg_sr3_dering_luma2pkos5 // u8: rate0 (for bpcon<th0) of curve for dering pkOS based on LPF luma level. default =50
//Bit 7:0 reg_sr3_dering_luma2pkos4 // u8: level limit(for bpcon>th1) of curve for dering pkOS based on LPF luma level. default =255
#define SHARP_SR3_DERING_GAINVS_MADSAD ((0x5070 << 2) + 0xff000000)
//Bit 31:28 reg_sr3_dering_gainvs_maxsad7 //u4: pkgain vs maxsad value, 8 node interpolations, default = 0
@@ -30249,7 +30249,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 1 debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 1 debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -30752,8 +30752,8 @@
//Bit 31:12 reserved
//Bit 11:10 reg_fmeter_vwin_mm //u2, vertical window size, 0:1 cloumn, 1:3cloumn, 2or3: 5cloumn .unsigned , default = 0
//Bit 9 : 8 reg_fmeter_hwin_mm //u2, horizontal window size, 0:1x7, 1:1x9, 2or3: 1x11 .unsigned , default = 0
-//Bit 7 reg_fmeter_d2_mode //u1, selectino filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
-//Bit 6 reg_fmeter_v2_mode //u1, selectino filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 7 reg_fmeter_d2_mode //u1, selection filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 6 reg_fmeter_v2_mode //u1, selection filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
//Bit 5: 4 reg_fmeter_h2_mode //u2, selection filter H2, 0: [0 0 0 -2 0 0 2 0 0], 1: [-2 0 0 0 2], 2or3: [0-2 0 0 0 0 0 2 0] .unsigned , default = 0
//Bit 3: 1 reserved
//Bit 0 reg_freq_meter_en //u1, freq meter enable .unsigned , default = 0
@@ -33817,7 +33817,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -33986,7 +33986,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -34155,7 +34155,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -34324,7 +34324,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -34976,22 +34976,22 @@
//Bit 0 reg_chn_ystride_0 // unsigned , RW, default = 0 0: ystride=2 (jump 1 pixel), 1: ystride=4 (jump 3 pixel), strides for raw channel 0
#define ISP_TOP_EXPO_TIME_L0 ((0x0104 << 2) + 0xff900000)
//Bit 31:20 reserved
-//Bit 19: 0 reg_expo_time_0 // unsigned , RW, default = 70 exposure time, following the sensor paramters
+//Bit 19: 0 reg_expo_time_0 // unsigned , RW, default = 70 exposure time, following the sensor parameters
#define ISP_TOP_EXPO_TIME_S1 ((0x0105 << 2) + 0xff900000)
//Bit 31:20 reserved
-//Bit 19: 0 reg_expo_time_1 // unsigned , RW, default = 8 exposure time, following the sensor paramters
+//Bit 19: 0 reg_expo_time_1 // unsigned , RW, default = 8 exposure time, following the sensor parameters
#define ISP_TOP_EXPO_TIME_S2 ((0x0106 << 2) + 0xff900000)
//Bit 31:20 reserved
-//Bit 19: 0 reg_expo_time_2 // unsigned , RW, default = 0 exposure time, following the sensor paramters
+//Bit 19: 0 reg_expo_time_2 // unsigned , RW, default = 0 exposure time, following the sensor parameters
#define ISP_TOP_EXPO_TIME_S3 ((0x0107 << 2) + 0xff900000)
//Bit 31:20 reserved
-//Bit 19: 0 reg_expo_time_3 // unsigned , RW, default = 0 exposure time, following the sensor paramters
+//Bit 19: 0 reg_expo_time_3 // unsigned , RW, default = 0 exposure time, following the sensor parameters
#define ISP_TOP_EXPO_RATIO_0 ((0x0108 << 2) + 0xff900000)
//Bit 31:16 reserved
-//Bit 15: 0 reg_expo_ratio_0 // unsigned , RW, default = 8 u8.8 relative exposures ratios, following the sensor paramters
+//Bit 15: 0 reg_expo_ratio_0 // unsigned , RW, default = 8 u8.8 relative exposures ratios, following the sensor parameters
#define ISP_TOP_EXPO_RATIO_12 ((0x0109 << 2) + 0xff900000)
-//Bit 31:16 reg_expo_ratio_2 // unsigned , RW, default = 0 u8.8 relative exposures ratios, following the sensor paramters
-//Bit 15: 0 reg_expo_ratio_1 // unsigned , RW, default = 0 u8.8 relative exposures ratios, following the sensor paramters
+//Bit 31:16 reg_expo_ratio_2 // unsigned , RW, default = 0 u8.8 relative exposures ratios, following the sensor parameters
+//Bit 15: 0 reg_expo_ratio_1 // unsigned , RW, default = 0 u8.8 relative exposures ratios, following the sensor parameters
#define ISP_TOP_FEO_CTRL0 ((0x010a << 2) + 0xff900000)
//Bit 31:13 reserved
//Bit 12 reg_crop_en // unsigned , RW, default = 0 enable crop mode
@@ -35068,7 +35068,7 @@
//Bit 6 reg_dnlp_en // unsigned , RW, default = 0 enable dnlp contrast
//Bit 5 reg_pk_en // unsigned , RW, default = 0 enable peaking for sharpness
//Bit 4 reg_nr_en // unsigned , RW, default = 0 enable noise reduction for sharpness
-//Bit 3 reg_fmeter_en // unsigned , RW, default = 1 enable fmeter fucntion
+//Bit 3 reg_fmeter_en // unsigned , RW, default = 1 enable fmeter function
//Bit 2 reg_grph_en // unsigned , RW, default = 1 enable graphic statistic
//Bit 1: 0 reg_yhs_sta_en // unsigned , RW, default = 1
#define ISP_TOP_3A_STAT_CRTL ((0x0110 << 2) + 0xff900000)
@@ -35478,7 +35478,7 @@
//Bit 11:10 reserved
//Bit 9: 8 reg_dpc_xphs_ofst // unsigned , RW, default = 1
//Bit 7: 5 reserved
-//Bit 4 reg_dpc_det_en // unsigned , RW, default = 1 1 = enable defect pixel detection, 0 = diable
+//Bit 4 reg_dpc_det_en // unsigned , RW, default = 1 1 = enable defect pixel detection, 0 = disable
//Bit 3: 1 reserved
//Bit 0 reg_dpc_cor_en // unsigned , RW, default = 1 1 = enable defect pixel correction, 0 = disable
#define ISP_DPC0_AVG_GAIN0 ((0x0261 << 2) + 0xff900000)
@@ -35515,7 +35515,7 @@
#define ISP_DPC0_AVG_MOD ((0x0267 << 2) + 0xff900000)
//Bit 31:18 reserved
//Bit 17:16 reg_dpc_avg_mode // unsigned , RW, default = 3 0 = auto selection average value between avg6 and avg4,1 = avg6, 2 = avg4, 3 = avg8
-//Bit 15: 8 reg_dpc_avg_bias_thd // unsigned , RW, default = 40 it is used to set theshold for selecting the average value
+//Bit 15: 8 reg_dpc_avg_bias_thd // unsigned , RW, default = 40 it is used to set threshold for selecting the average value
//Bit 7: 2 reserved
//Bit 1: 0 reg_dpc_med_mode // unsigned , RW, default = 2 it is used to select the median value from 8 data,0 = auto, 1= data[3], 2 =data[4], 3 = (data[3]+data[4])/2
#define ISP_DPC0_AVG_DEV ((0x0268 << 2) + 0xff900000)
@@ -35557,7 +35557,7 @@
//Bit 15 reserved
//Bit 14:12 reg_dpc_vote_thd // unsigned , RW, default = 3 it is used to set the vote threshold.
//Bit 11 reserved
-//Bit 10: 8 reg_dpc_ud_mode // unsigned , RW, default = 4 it is used to set the mode for un-diretioanal estimation.0= auto,1=median,2= avg6, 3=avg4,4=avg8,
+//Bit 10: 8 reg_dpc_ud_mode // unsigned , RW, default = 4 it is used to set the mode for un-directional estimation.0= auto,1=median,2= avg6, 3=avg4,4=avg8,
//Bit 7: 5 reserved
//Bit 4 reg_dpc_highlight_en // unsigned , RW, default = 0 it is used to enable highlighting the defect pixels. 1= enbale, 0=disable
//Bit 3: 2 reserved
@@ -35673,7 +35673,7 @@
//Bit 11:10 reserved
//Bit 9: 8 reg_dpc_xphs_ofst // unsigned , RW, default = 1
//Bit 7: 5 reserved
-//Bit 4 reg_dpc_det_en // unsigned , RW, default = 1 1 = enable defect pixel detection, 0 = diable
+//Bit 4 reg_dpc_det_en // unsigned , RW, default = 1 1 = enable defect pixel detection, 0 = disable
//Bit 3: 1 reserved
//Bit 0 reg_dpc_cor_en // unsigned , RW, default = 1 1 = enable defect pixel correction, 0 = disable
#define ISP_DPC1_AVG_GAIN0 ((0x02e1 << 2) + 0xff900000)
@@ -35710,7 +35710,7 @@
#define ISP_DPC1_AVG_MOD ((0x02e7 << 2) + 0xff900000)
//Bit 31:18 reserved
//Bit 17:16 reg_dpc_avg_mode // unsigned , RW, default = 3 0 = auto selection average value between avg6 and avg4,1 = avg6, 2 = avg4, 3 = avg8
-//Bit 15: 8 reg_dpc_avg_bias_thd // unsigned , RW, default = 40 it is used to set theshold for selecting the average value
+//Bit 15: 8 reg_dpc_avg_bias_thd // unsigned , RW, default = 40 it is used to set threshold for selecting the average value
//Bit 7: 2 reserved
//Bit 1: 0 reg_dpc_med_mode // unsigned , RW, default = 2 it is used to select the median value from 8 data,0 = auto, 1= data[3], 2 =data[4], 3 = (data[3]+data[4])/2
#define ISP_DPC1_AVG_DEV ((0x02e8 << 2) + 0xff900000)
@@ -35752,7 +35752,7 @@
//Bit 15 reserved
//Bit 14:12 reg_dpc_vote_thd // unsigned , RW, default = 3 it is used to set the vote threshold.
//Bit 11 reserved
-//Bit 10: 8 reg_dpc_ud_mode // unsigned , RW, default = 4 it is used to set the mode for un-diretioanal estimation.0= auto,1=median,2= avg6, 3=avg4,4=avg8,
+//Bit 10: 8 reg_dpc_ud_mode // unsigned , RW, default = 4 it is used to set the mode for un-directional estimation.0= auto,1=median,2= avg6, 3=avg4,4=avg8,
//Bit 7: 5 reserved
//Bit 4 reg_dpc_highlight_en // unsigned , RW, default = 0 it is used to enable highlighting the defect pixels. 1= enbale, 0=disable
//Bit 3: 2 reserved
@@ -35843,7 +35843,7 @@
//Bit 31:18 reserved
//Bit 17:16 reg_inp_fmt_chn // unsigned , RW, default = 1 the data channels after input formatter, support (1+inp_fmt_chn) as 1/2/3/4
//Bit 15:13 reserved
-//Bit 12 reg_inp_fmt_diag_mux // unsigned , RW, default = 0 0: select 0 or (0,1), 1: select 1 or (1,0), ouput mux for diagonal split
+//Bit 12 reg_inp_fmt_diag_mux // unsigned , RW, default = 0 0: select 0 or (0,1), 1: select 1 or (1,0), output mux for diagonal split
//Bit 11: 8 reg_inp_fmt_split_sbit // unsigned , RW, default = 4 short exp bits split for combined split
//Bit 7: 6 reserved
//Bit 5: 4 reg_inp_fmt_split_mode // unsigned , RW, default = 0 0: bypass, 1: long/short split, 2or3: diag sum split for quadra, channel0 split mode for input formatter
@@ -36290,8 +36290,8 @@
//Bit 15: 0 reg_pdpc_hoti_thr // unsigned , RW, default = 65535 hot pixel threshold, maximum valid pixel range
#define ISP_LCGE_CTRL ((0x0927 << 2) + 0xff900000)
//Bit 31:24 reserved
-//Bit 23:16 reg_lcge_dif02_ndrt // unsigned , RW, default = 20 threshold to |Gr-Gb|deside if this is no direction (x<<1)
-//Bit 15: 8 reg_lcge_dif01_thrd // unsigned , RW, default = 30 threshold to |Gr-Gb|deside if this is GE range or picture texture (x<<4)
+//Bit 23:16 reg_lcge_dif02_ndrt // unsigned , RW, default = 20 threshold to |Gr-Gb|decide if this is no direction (x<<1)
+//Bit 15: 8 reg_lcge_dif01_thrd // unsigned , RW, default = 30 threshold to |Gr-Gb|decide if this is GE range or picture texture (x<<4)
//Bit 7: 0 reg_lcge_dif02_thrd // unsigned , RW, default = 40 threshold Gr/Gb nearby pixels, if this is Ge range or picture texture (x<<4)
#define ISP_LCGE_FLAT ((0x0928 << 2) + 0xff900000)
//Bit 31:11 reserved
@@ -36322,7 +36322,7 @@
//Bit 7: 4 reg_lcge_luma_scal_1 // unsigned , RW, default = 8 gain to the thrd base on the avg_G, avg_G is the Gr and Gb average, norm to 8 as 1.0
//Bit 3: 0 reg_lcge_luma_scal_0 // unsigned , RW, default = 8 gain to the thrd base on the avg_G, avg_G is the Gr and Gb average, norm to 8 as 1.0
#define ISP_LCGESTA_SETTING ((0x092c << 2) + 0xff900000)
-//Bit 31:24 reg_lcgesta_dif01_thrd // unsigned , RW, default = 18 threshold lto |Gr-Gb|deside if this is GE range or picture texture (x<<4)
+//Bit 31:24 reg_lcgesta_dif01_thrd // unsigned , RW, default = 18 threshold lto |Gr-Gb|decide if this is GE range or picture texture (x<<4)
//Bit 23:16 reg_lcgesta_dif02_thrd // unsigned , RW, default = 28 threshold Gr/Gb nearby pixels, if this is Ge range or picture texture (x<<4)
//Bit 15:14 reserved
//Bit 13: 8 reg_lcgesta_ratio_0 // unsigned , RW, default = 16 if (dif02>thrd)||(dif01>thrd)) hist[2]++; else {if ((dif01<(dif02*ratio[0]/16)), hist[0]++; elseif (dif01>(dif02*ratio[1]>>4)) hist[1]++;} default = [16, 20]
@@ -37238,8 +37238,8 @@
#define ISP_DMS_CT_PARAM0 ((0x1413 << 2) + 0xff900000)
//Bit 31:16 reserved
//Bit 15: 8 reg_ctran_coring // unsigned , RW, default = 30 coring to the color transition_level, ignore small color transition
-//Bit 7: 6 reg_ctran_h_dial_win // unsigned , RW, default = 2 horizontal dialation window size for ctran_h, 0: no dialation else (x+1)
-//Bit 5: 4 reg_ctran_v_dial_win // unsigned , RW, default = 2 horizontal dialation window size for ctran_v, 0: no dialation, else (x+1)
+//Bit 7: 6 reg_ctran_h_dial_win // unsigned , RW, default = 2 horizontal dilation window size for ctran_h, 0: no dilation else (x+1)
+//Bit 5: 4 reg_ctran_v_dial_win // unsigned , RW, default = 2 horizontal dilation window size for ctran_v, 0: no dilation, else (x+1)
//Bit 3 reg_ctran_powersaving // unsigned , RW, default = 0 enable bit gate the ctran clock for power saving, just output cdf_l
//Bit 2 reg_ctrs_csat_max_en // unsigned , RW, default = 1 enable bit to do ctrs and csat max to get ctrans, default = 1
//Bit 1 reg_ctran_h_lpf_en // unsigned , RW, default = 1 enable bit to do horizontal [12221] lpf for lbuf_ctran_h_lpf, default = 1
@@ -37289,7 +37289,7 @@
//Bit 23:16 reg_drt_grad_calp // unsigned , RW, default = 40 color error alpha for final error blend, normalized to 32 as 1.0
//Bit 15: 4 reg_drt_hfrq_coring // unsigned , RW, default = 16 coring threshold for high frequency count in drt
//Bit 3: 1 reserved
-//Bit 0 reg_drt_grad_err_mode // unsigned , RW, default = 0 0: orginal error, 1: blended error, error mode for final error ouput
+//Bit 0 reg_drt_grad_err_mode // unsigned , RW, default = 0 0: original error, 1: blended error, error mode for final error output
#define ISP_DMS_DRT_HFRQ0 ((0x141b << 2) + 0xff900000)
//Bit 31:28 reserved
//Bit 27:16 reg_drt_hfrq_dif_thd_1 // unsigned , RW, default = 256 dif threshold1 for dif to gain calc. for high frequency count in drt
@@ -37418,21 +37418,21 @@
//Bit 27:20 reg_cbd7_dif1_thrd // unsigned , RW, default = 60 (diff1_abssum< 4*thr) as cb7 detected condition, (u12 precision)
//Bit 19:18 reserved
//Bit 17:12 reg_cbd7_dif21_rat // unsigned , RW, default = 16 (dif2_abssum< dif1_abssum*rat/32) as cb7 detected condition, default = 24
-//Bit 11:10 reg_cbdlev_dia_win // unsigned , RW, default = 2 window half size to do horizontal dialation
+//Bit 11:10 reg_cbdlev_dia_win // unsigned , RW, default = 2 window half size to do horizontal dilation
//Bit 9: 8 reg_cbdlev_lpf_mod // unsigned , RW, default = 1 lpf mode for alpha, 0: no lpf, 1: [1 2 1], 2/3, [1 2 2 2 1]
//Bit 7: 6 reserved
//Bit 5: 0 reg_cbdlev_gain // unsigned , RW, default = 16 gain to cbdlev(alpha) before clipping, normalized to 16 as 1.0
#define ISP_DMS_PP_CBLEV_ALP_LIMT ((0x1483 << 2) + 0xff900000)
//Bit 31:30 reserved
-//Bit 29:24 reg_cbdlev_min_1 // unsigned , RW, default = 32 4x is low limit for cbdlev(alpha), to ctrl nyquist frequecy strenght, [0] for luma, [1] for chroma
+//Bit 29:24 reg_cbdlev_min_1 // unsigned , RW, default = 32 4x is low limit for cbdlev(alpha), to ctrl nyquist frequecy strength, [0] for luma, [1] for chroma
//Bit 23:22 reserved
-//Bit 21:16 reg_cbdlev_max_1 // unsigned , RW, default = 63 4x is high limit for cbdlev(alpha), to ctrl nyquist frequecy strenght, [0] for luma, [1] for chroma
+//Bit 21:16 reg_cbdlev_max_1 // unsigned , RW, default = 63 4x is high limit for cbdlev(alpha), to ctrl nyquist frequecy strength, [0] for luma, [1] for chroma
//Bit 15:14 reserved
-//Bit 13: 8 reg_cbdlev_min_0 // unsigned , RW, default = 32 4x is low limit for cbdlev(alpha), to ctrl nyquist frequecy strenght, [0] for luma, [1] for chroma
+//Bit 13: 8 reg_cbdlev_min_0 // unsigned , RW, default = 32 4x is low limit for cbdlev(alpha), to ctrl nyquist frequecy strength, [0] for luma, [1] for chroma
//Bit 7: 6 reserved
-//Bit 5: 0 reg_cbdlev_max_0 // unsigned , RW, default = 63 4x is high limit for cbdlev(alpha), to ctrl nyquist frequecy strenght, [0] for luma, [1] for chroma
+//Bit 5: 0 reg_cbdlev_max_0 // unsigned , RW, default = 63 4x is high limit for cbdlev(alpha), to ctrl nyquist frequecy strength, [0] for luma, [1] for chroma
#define ISP_DMS_PP_CBLEV_MXERRTH ((0x1484 << 2) + 0xff900000)
-//Bit 31:24 reg_cbdlev_mxerrth_0 // unsigned , RW, default = 40 4x threshold to maxerr of drt4 to [0] avoid dialation, [1] horizontal fir-lpf and [2] vertical iir-lpf, default = 40
+//Bit 31:24 reg_cbdlev_mxerrth_0 // unsigned , RW, default = 40 4x threshold to maxerr of drt4 to [0] avoid dilation, [1] horizontal fir-lpf and [2] vertical iir-lpf, default = 40
//Bit 23:16 reg_cbdlev_mxerrth_1 // unsigned , RW, default = 40
//Bit 15: 8 reg_cbdlev_mxerrth_2 // unsigned , RW, default = 60
//Bit 7: 4 reserved
@@ -37486,7 +37486,7 @@
//Bit 7: 0 reg_cbp_sigma_1 // unsigned , RW, default = 60 sigma for Y or Cb/Cr for avoiding including that pixel to cbf if ABS|pix-cur|> sigma, [0] for luma, [1] for U/V, x16 for u12 precision
#define ISP_DMS_PP_CBALP_RO ((0x148b << 2) + 0xff900000)
//Bit 31 reserved
-//Bit 30: 0 ro_cbd_alpsum_frm // unsigned , RO, default = 0 read-only sum of pixels chessboard level alpha. reset to 0 begining of each frame (FW), for FW algorithm base
+//Bit 30: 0 ro_cbd_alpsum_frm // unsigned , RO, default = 0 read-only sum of pixels chessboard level alpha. reset to 0 beginning of each frame (FW), for FW algorithm base
#define ISP_DMS_PP_DRT_ALP_LUT ((0x148c << 2) + 0xff900000)
//Bit 31:28 reg_drtlpd_alp_lut_7 // unsigned , RW, default = 2 for min_err/max_err ratio decision for blender alpha base, 16 as 1.0, the larger final alpha, the more drtlpf applied
//Bit 27:24 reg_drtlpd_alp_lut_6 // unsigned , RW, default = 4 for min_err/max_err ratio decision for blender alpha base, 16 as 1.0, the larger final alpha, the more drtlpf applied
@@ -37516,7 +37516,7 @@
//Bit 3: 0 reg_drtlpd_lam_lut_8 // unsigned , RW, default = 15 for edge strength decision for blender alpha , 16 as 1.0, normally apply larger alpha for stronger edge
#define ISP_DMS_PP_DRT_ALP ((0x148f << 2) + 0xff900000)
//Bit 31:24 reg_drtlpd_ambi_thr // unsigned , RW, default = 60 threshold to min2_err for ambiguity detection. only for both min_err and min2_err pretty small and crossed.
-//Bit 23:22 reg_drtlpd_hdia_win // unsigned , RW, default = 2 horizontal dialation for the drtlpf_alpha
+//Bit 23:22 reg_drtlpd_hdia_win // unsigned , RW, default = 2 horizontal dilation for the drtlpf_alpha
//Bit 21:16 reg_drtlpd_alp_gain // unsigned , RW, default = 18 gain to alp before clipping, normalized to 16 as 1.0
//Bit 15:14 reserved
//Bit 13: 8 reg_drtlpd_alp_min // unsigned , RW, default = 0 low limit for drtlpf_alpha
@@ -37559,13 +37559,13 @@
//Bit 7: 0 reg_pk_con2gain_bp_4 // unsigned , RW, default = 100 curve parm for con2gain, x=con(maxerr), y-gain, [0:6]={th0, th1, lev0, lv1, lv2, rat0, rat1}, rate normalized to 32 as 1.0
#define ISP_DMS_PP_PK_CIR_FILT_LIMT ((0x1497 << 2) + 0xff900000)
//Bit 31:22 reserved
-//Bit 21:20 reg_pk_con2gain_dia_win // unsigned , RW, default = 1 dialation window half size for stable gain, default= 1
+//Bit 21:20 reg_pk_con2gain_dia_win // unsigned , RW, default = 1 dilation window half size for stable gain, default= 1
//Bit 19 reserved
//Bit 18 reg_pk_con2gain_hlpf // unsigned , RW, default = 1 horizontal [1 2 1] filter for the hp_gain and bp_gain, default = 1
//Bit 17 reg_pk_gama_cirvsdrt_ambi // unsigned , RW, default = 1 set to 63 for gama_cirvsdrt if ambiguity detected, default = 1
//Bit 16 reg_pk_gama_cirvsdrt_hlpf // unsigned , RW, default = 1 horizontal [1 2 1] filter for the gama_cirvsdrt, default = 1
//Bit 15:14 reserved
-//Bit 13: 8 reg_pk_gama_cirvsdrt_min // unsigned , RW, default = 0 mimimum limit to gamma for cir filter result percentage, default=0
+//Bit 13: 8 reg_pk_gama_cirvsdrt_min // unsigned , RW, default = 0 minimum limit to gamma for cir filter result percentage, default=0
//Bit 7: 6 reserved
//Bit 5: 0 reg_pk_gama_cirvsdrt_max // unsigned , RW, default = 48 maximum limit to gamma for cir filter result percentage, default=63
#define ISP_DMS_PP_PK_CIR_BLD_LUT_0 ((0x1498 << 2) + 0xff900000)
@@ -39721,10 +39721,10 @@
//Bit 7 reg_ae_input_2ln // unsigned , RW, default = 1 input buffer 2 lines together, reg_ae_stat_switch=0, set 1, otherwise set to 0
//Bit 6 reserved
//Bit 5 reg_ae_histo_useweight // unsigned , RW, default = 1 hist1024 use regional weight, default=1
-//Bit 4 reg_ae_glbal_useweight // unsigned , RW, default = 1 global use regional weight, default=1
+//Bit 4 reg_ae_global_useweight // unsigned , RW, default = 1 global use regional weight, default=1
//Bit 3: 2 reg_ae_stat_local_mode // unsigned , RW, default = 0 AE statisic local sta mode: 0: BIN0/1/3/4 in pack0 and pack1; 1: Gr/R/B/Gb/Ir_avg in pack0 and pack1; 2o3: mean/max/min/sat/unsat etc packed. default=0
//Bit 1 reg_ae_stat_hist_sel // unsigned , RW, default = 0 0: global win, 1: roi window, histogram from global window or roi window for ae stats
-//Bit 0 reg_ae_stat_glbal_mode // unsigned , RW, default = 0 AE statisic global sta mode: 0: BIN0/1/3/4 in pack0 and pack1; 1: Gr/R/B/Gb/Ir_avg in pack0 and pack1; default=0
+//Bit 0 reg_ae_stat_global_mode // unsigned , RW, default = 0 AE statisic global sta mode: 0: BIN0/1/3/4 in pack0 and pack1; 1: Gr/R/B/Gb/Ir_avg in pack0 and pack1; default=0
#define ISP_AE_CRTL2_0 ((0x2919 << 2) + 0xff900000)
//Bit 31:25 reserved
//Bit 24 reg_ae_luma_coef_0 // unsigned , RW, default = 1 luma estimate coef for AE, 0: not included in lumat estimate, 1: included; default=[1 1 1 1 1];
@@ -39893,10 +39893,10 @@
//Bit 8 reg_awb_stat_input_format // unsigned , RW, default = 0 input frame buffer format: 0: raw; 1: RGB; default = 0;
//Bit 7 reserved
//Bit 6 reg_awb_grn_use_avg // unsigned , RW, default = 0 enable of Gb=Gr=(Gb+Gr+1)/2, 0: no average, 1: average
-//Bit 5 reg_awb_glbal_useweight // unsigned , RW, default = 1 global use regional weight, default=1
+//Bit 5 reg_awb_global_useweight // unsigned , RW, default = 1 global use regional weight, default=1
//Bit 4: 3 reg_awb_stat_luma_div_mode // unsigned , RW, default = 0 AWB separate STATS on Luma (x+1) ranges, Total STATS RAM same size, needs to reduce hblk_num/vblk_num if x>0. 0: no division; 1: div to 2 range; ...3: div to 4 ranges
//Bit 2 reg_awb_stat_local_mode // unsigned , RW, default = 0 AWB statisic local sta mode: 0: ratio_bg/rg in pack0 and cnt in pack1; 1: (AVG_G<<16)+ AVG_R in pack0 and (Nrm_cnt<<16)+ avg_B in pack1; default=0
-//Bit 1 reg_awb_stat_glbal_mode // unsigned , RW, default = 0 AWB statisic global sta mode: 0: ratio_bg/rg in pack0 and cnt in pack1; 1: (AVG_G<<16)+ AVG_R in pack0 and (Nrm_cnt<<16)+ avg_B in pack1; default=0
+//Bit 1 reg_awb_stat_global_mode // unsigned , RW, default = 0 AWB statisic global sta mode: 0: ratio_bg/rg in pack0 and cnt in pack1; 1: (AVG_G<<16)+ AVG_R in pack0 and (Nrm_cnt<<16)+ avg_B in pack1; default=0
//Bit 0 reg_awb_stat_satur_vald // unsigned , RW, default = 0 AWB statistic over saturation control
#define ISP_AWB_STAT_BLC20_0 ((0x2a17 << 2) + 0xff900000)
//Bit 31:20 reserved
@@ -41332,7 +41332,7 @@
#define PFIFO_WR_PTR ((0x3866 << 2) + 0xfdf00000)
// bit 9:0 -- point to byte address
#define PFIFO_RD_PTR ((0x3867 << 2) + 0xfdf00000)
-// bit 31:0 -- 8/16/24/32 bits data acording to pfifo_data_width
+// bit 31:0 -- 8/16/24/32 bits data according to pfifo_data_width
#define PFIFO_DATA ((0x3868 << 2) + 0xfdf00000)
// bit 31:0 -- parser search pattern
#define PARSER_SEARCH_PATTERN ((0x3869 << 2) + 0xfdf00000)
@@ -41367,7 +41367,7 @@
#define PARSER_PARAMETER ((0x386f << 2) + 0xfdf00000)
// bit 31:0 -- insert data // write only
// write to PARSER_CONTROL will reset the write position
-// continous write to this address can write upto 16 bytes
+// continuous write to this address can write upto 16 bytes
#define PARSER_INSERT_DATA ((0x3870 << 2) + 0xfdf00000)
// Bit 31:24 -- Reserved Stream_ID
// Bit 23:16 -- Sub Stream_ID
@@ -41536,7 +41536,7 @@
#define PARSER_B_PFIFO_WR_PTR ((0x1166 << 2) + 0xfdf00000)
// bit 9:0 -- point to byte address
#define PARSER_B_PFIFO_RD_PTR ((0x1167 << 2) + 0xfdf00000)
-// bit 31:0 -- 8/16/24/32 bits data acording to pfifo_data_width
+// bit 31:0 -- 8/16/24/32 bits data according to pfifo_data_width
#define PARSER_B_PFIFO_DATA ((0x1168 << 2) + 0xfdf00000)
// bit 31:0 -- parser search pattern
#define PARSER_B_PARSER_SEARCH_PATTERN ((0x1169 << 2) + 0xfdf00000)
@@ -41571,7 +41571,7 @@
#define PARSER_B_PARSER_PARAMETER ((0x116f << 2) + 0xfdf00000)
// bit 31:0 -- insert data // write only
// write to PARSER_CONTROL will reset the write position
-// continous write to this address can write upto 16 bytes
+// continuous write to this address can write upto 16 bytes
#define PARSER_B_PARSER_INSERT_DATA ((0x1170 << 2) + 0xfdf00000)
// Bit 31:24 -- Reserved Stream_ID
// Bit 23:16 -- Sub Stream_ID
diff --git a/demos/amlogic/n200/include/s4/register.h b/demos/amlogic/n200/include/s4/register.h
index c95bfd1..8c7a4e9 100644
--- a/demos/amlogic/n200/include/s4/register.h
+++ b/demos/amlogic/n200/include/s4/register.h
@@ -10202,7 +10202,7 @@
// 1=ABH read request burst size 24;
// 2=ABH read request burst size 32;
// 3=ABH read request burst size 48.
-// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logics except register.
+// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logic except register.
// Bit 0 RW ctrl_free_clk_enable. 0=Default, Enable clock gating. 1=No clock gating, enable free clock.
#define RDMA_CTRL ((0x1114 << 2) + 0xff000000)
// Read only.
@@ -13155,7 +13155,7 @@
//bit 15:8, reg_ei_int_drtdelay2_notver_sadth
//bit 7:0, reg_ei_int_drtdelay2_vlddrt_sadth
#define DI_MTN_1_CTRL6 ((0x17a9 << 2) + 0xff000000)
-//bit 31:24, mtn_m1b_extnd
+//bit 31:24, mtn_m1b_extend
//bit 23:16, mtn_m1b_errod
//bit 15: 8, mtn_core_ykinter
//bit 7: 0, mtn_core_ckinter
@@ -13559,9 +13559,9 @@
// Bit 15:13 v0_gofld_sel, 000: display go_field, 001: DI pre_frame_rst, 010: vdin0 go_field, 011: vdin1 go_field, otherwise: force go_field by
// reg_v0_go_field(bit19)
// Bit 12:6 hole_lines for d2d3 depth read interface
-// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 fomart output), 2'b10: scale output, otherwise nothing as v1
+// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 format output), 2'b10: scale output, otherwise nothing as v1
// Bit 3 use_vdin_eol, if true, use vdin eol as the v0_eol, otherwise using length to get the v0_eol
-// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 fomart output), 101: vpp scale output
+// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 format output), 101: vpp scale output
//
// `define D2D3_INTF_CTRL0 8'h09
#define VD1_AFBCD0_MISC_CTRL ((0x1a0a << 2) + 0xff000000)
@@ -13577,7 +13577,7 @@
// OSD1 registers
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -13789,7 +13789,7 @@
// OSD2 registers
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -16687,7 +16687,7 @@
// OSD1 registers
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -18625,8 +18625,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE1 ((0x27a6 << 2) + 0xff000000)
@@ -18638,8 +18638,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE2 ((0x27a7 << 2) + 0xff000000)
@@ -18651,8 +18651,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE3 ((0x27a8 << 2) + 0xff000000)
@@ -18664,8 +18664,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE4 ((0x27a9 << 2) + 0xff000000)
@@ -18677,8 +18677,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_WR_MODE0 ((0x27aa << 2) + 0xff000000)
@@ -18690,8 +18690,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_WR_MODE1 ((0x27ab << 2) + 0xff000000)
@@ -18703,8 +18703,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_WR_MODE2 ((0x27ac << 2) + 0xff000000)
@@ -18716,8 +18716,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_STAT ((0x27ad << 2) + 0xff000000)
@@ -27571,8 +27571,8 @@
//Bit 31:12 reserved
//Bit 11:10 reg_fmeter_vwin_mm //u2, vertical window size, 0:1 cloumn, 1:3cloumn, 2or3: 5cloumn .unsigned , default = 0
//Bit 9 : 8 reg_fmeter_hwin_mm //u2, horizontal window size, 0:1x7, 1:1x9, 2or3: 1x11 .unsigned , default = 0
-//Bit 7 reg_fmeter_d2_mode //u1, selectino filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
-//Bit 6 reg_fmeter_v2_mode //u1, selectino filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 7 reg_fmeter_d2_mode //u1, selection filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 6 reg_fmeter_v2_mode //u1, selection filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
//Bit 5: 4 reg_fmeter_h2_mode //u2, selection filter H2, 0: [0 0 0 -2 0 0 2 0 0], 1: [-2 0 0 0 2], 2or3: [0-2 0 0 0 0 0 2 0] .unsigned , default = 0
//Bit 3: 1 reserved
//Bit 0 reg_freq_meter_en //u1, freq meter enable .unsigned , default = 0
diff --git a/demos/amlogic/n200/include/sc2/register.h b/demos/amlogic/n200/include/sc2/register.h
index 03ce780..13d9f4e 100644
--- a/demos/amlogic/n200/include/sc2/register.h
+++ b/demos/amlogic/n200/include/sc2/register.h
@@ -2020,7 +2020,7 @@
#define DMC_DRAM_DFITPHYRDLAT ((0x0022 << 2) + 0xfe036400)
//bit 5:0. dfi_t_rdlat.
#define DMC_DRAM_DFITCTRLUPDMIN ((0x0023 << 2) + 0xfe036400)
- //bit 7:0. CTRLUPD_MIN minimux clock cycle to maintain CTRLUPD_REQ.
+ //bit 7:0. CTRLUPD_MIN minimum clock cycle to maintain CTRLUPD_REQ.
#define DMC_DRAM_DFITCTRLUPDMAX ((0x0024 << 2) + 0xfe036400)
//bit 7:0 CTRLUPD_MAX. maxmum clock cycle to maintain CTRLUPD_REQ if no CTRLUPD_ACK response.
#define DMC_DRAM_DFITREFMSKI ((0x0026 << 2) + 0xfe036400)
@@ -10159,7 +10159,7 @@
// 1=ABH read request burst size 24;
// 2=ABH read request burst size 32;
// 3=ABH read request burst size 48.
-// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logics except register.
+// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logic except register.
// Bit 0 RW ctrl_free_clk_enable. 0=Default, Enable clock gating. 1=No clock gating, enable free clock.
#define RDMA_CTRL ((0x1114 << 2) + 0xff000000)
// Read only.
@@ -13534,7 +13534,7 @@
// OSD1 registers
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -13746,7 +13746,7 @@
// OSD2 registers
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -16640,7 +16640,7 @@
// OSD1 registers
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -18578,8 +18578,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE1 ((0x27a6 << 2) + 0xff000000)
@@ -18591,8 +18591,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE2 ((0x27a7 << 2) + 0xff000000)
@@ -18604,8 +18604,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE3 ((0x27a8 << 2) + 0xff000000)
@@ -18617,8 +18617,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE4 ((0x27a9 << 2) + 0xff000000)
@@ -18630,8 +18630,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_WR_MODE0 ((0x27aa << 2) + 0xff000000)
@@ -18643,8 +18643,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_WR_MODE1 ((0x27ab << 2) + 0xff000000)
@@ -18656,8 +18656,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_WR_MODE2 ((0x27ac << 2) + 0xff000000)
@@ -18669,8 +18669,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_STAT ((0x27ad << 2) + 0xff000000)
@@ -20896,7 +20896,7 @@
//Bit 19:16, reg_mcdi_chkedgedifthd0. thd0 for edge dif check (>=), default = 15
//Bit :15, reserved.
//Bit 14:10, reg_mcdi_chkedgechklen. total check length for edge check, 1~24 (>0), default = 24
-//Bit 9: 8, reg_mcdi_chkedgeedgesel. final edge select mode, 0: original start edge, 1: lpf start edge, 2: orignal start+end edge, 3: lpf start+end edge, default = 1
+//Bit 9: 8, reg_mcdi_chkedgeedgesel. final edge select mode, 0: original start edge, 1: lpf start edge, 2: original start+end edge, 3: lpf start+end edge, default = 1
//Bit 7: 3, reg_mcdi_chkedgesaddstgain. distance gain for sad calc while getting edges, default = 4
//Bit 2, reg_mcdi_chkedgechkmode. edge used in check mode, 0: original edge, 1: lpf edge, default = 1
//Bit 1, reg_mcdi_chkedgestartedge. edge mode for start edge, 0: original edge, 1: lpf edge, default = 0
@@ -27516,8 +27516,8 @@
//Bit 31:12 reserved
//Bit 11:10 reg_fmeter_vwin_mm //u2, vertical window size, 0:1 cloumn, 1:3cloumn, 2or3: 5cloumn .unsigned , default = 0
//Bit 9 : 8 reg_fmeter_hwin_mm //u2, horizontal window size, 0:1x7, 1:1x9, 2or3: 1x11 .unsigned , default = 0
-//Bit 7 reg_fmeter_d2_mode //u1, selectino filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
-//Bit 6 reg_fmeter_v2_mode //u1, selectino filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 7 reg_fmeter_d2_mode //u1, selection filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 6 reg_fmeter_v2_mode //u1, selection filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
//Bit 5: 4 reg_fmeter_h2_mode //u2, selection filter H2, 0: [0 0 0 -2 0 0 2 0 0], 1: [-2 0 0 0 2], 2or3: [0-2 0 0 0 0 0 2 0] .unsigned , default = 0
//Bit 3: 1 reserved
//Bit 0 reg_freq_meter_en //u1, freq meter enable .unsigned , default = 0
diff --git a/demos/amlogic/n200/include/t3/register.h b/demos/amlogic/n200/include/t3/register.h
index f1823bf..a5ed985 100644
--- a/demos/amlogic/n200/include/t3/register.h
+++ b/demos/amlogic/n200/include/t3/register.h
@@ -301,7 +301,7 @@
//bit 5. LPDT data endian. 1 = transfer the high bit first. 0 : transfer the low bit first.
//bit 4. HS data endian.
//bit 3. force data byte lane in stop mode.
- //bit 2. force data byte lane 0 in reciever mode.
+ //bit 2. force data byte lane 0 in receiver mode.
//bit 1. write 1 to sync the txclkesc input. the internal logic have to use txclkesc to decide Txvalid and Txready.
//bit 0. enalbe the MIPI DSI PHY TxDDRClk.
#define MIPI_DSI_CHAN_CTRL ((0x0001 << 2) + 0xfe014000)
@@ -360,8 +360,8 @@
#define MIPI_DSI_WAKEUP_TIM ((0x0008 << 2) + 0xfe014000)
//TWAKEUP.
#define MIPI_DSI_LPOK_TIM ((0x0009 << 2) + 0xfe014000)
- //bit 31:0 when in RxULPS state, RX reciever is in sleep mode.
- //every MIPI_DSI_ULPS_CHECK period, the reciever would be enabled once, and waiting this timer period to get the stable input.
+ //bit 31:0 when in RxULPS state, RX receiver is in sleep mode.
+ //every MIPI_DSI_ULPS_CHECK period, the receiver would be enabled once, and waiting this timer period to get the stable input.
#define MIPI_DSI_LP_WCHDOG ((0x000a << 2) + 0xfe014000)
//bit 31:0 watch dog timer for MIPI DSI LP receive state.
#define MIPI_DSI_ANA_CTRL ((0x000b << 2) + 0xfe014000)
@@ -372,7 +372,7 @@
#define MIPI_DSI_TURN_WCHDOG ((0x000d << 2) + 0xfe014000)
//bit 31:0 watch dog timer for lane 0 LP turn around waiting time.
#define MIPI_DSI_ULPS_CHECK ((0x000e << 2) + 0xfe014000)
- //bit 31:0 when Lane0 in LP recieve state, if the another side sent Low power command, using this timer to enable Tcheck the another size wakeup nor not.
+ //bit 31:0 when Lane0 in LP receive state, if the another side sent Low power command, using this timer to enable Tcheck the another size wakeup nor not.
#define MIPI_DSI_TEST_CTRL0 ((0x000f << 2) + 0xfe014000)
#define MIPI_DSI_TEST_CTRL1 ((0x0010 << 2) + 0xfe014000)
//========================================================================
@@ -393,7 +393,7 @@
//bit 5. LPDT data endian. 1 = transfer the high bit first. 0 : transfer the low bit first.
//bit 4. HS data endian.
//bit 3. force data byte lane in stop mode.
- //bit 2. force data byte lane 0 in reciever mode.
+ //bit 2. force data byte lane 0 in receiver mode.
//bit 1. write 1 to sync the txclkesc input. the internal logic have to use txclkesc to decide Txvalid and Txready.
//bit 0. enalbe the MIPI DSI PHY TxDDRClk.
#define MIPI_DSI_B_CHAN_CTRL ((0x0001 << 2) + 0xfe016000)
@@ -452,8 +452,8 @@
#define MIPI_DSI_B_WAKEUP_TIM ((0x0008 << 2) + 0xfe016000)
//TWAKEUP.
#define MIPI_DSI_B_LPOK_TIM ((0x0009 << 2) + 0xfe016000)
- //bit 31:0 when in RxULPS state, RX reciever is in sleep mode.
- //every MIPI_DSI_ULPS_CHECK period, the reciever would be enabled once, and waiting this timer period to get the stable input.
+ //bit 31:0 when in RxULPS state, RX receiver is in sleep mode.
+ //every MIPI_DSI_ULPS_CHECK period, the receiver would be enabled once, and waiting this timer period to get the stable input.
#define MIPI_DSI_B_LP_WCHDOG ((0x000a << 2) + 0xfe016000)
//bit 31:0 watch dog timer for MIPI DSI LP receive state.
#define MIPI_DSI_B_ANA_CTRL ((0x000b << 2) + 0xfe016000)
@@ -464,7 +464,7 @@
#define MIPI_DSI_B_TURN_WCHDOG ((0x000d << 2) + 0xfe016000)
//bit 31:0 watch dog timer for lane 0 LP turn around waiting time.
#define MIPI_DSI_B_ULPS_CHECK ((0x000e << 2) + 0xfe016000)
- //bit 31:0 when Lane0 in LP recieve state, if the another side sent Low power command, using this timer to enable Tcheck the another size wakeup nor not.
+ //bit 31:0 when Lane0 in LP receive state, if the another side sent Low power command, using this timer to enable Tcheck the another size wakeup nor not.
#define MIPI_DSI_B_TEST_CTRL0 ((0x000f << 2) + 0xfe016000)
#define MIPI_DSI_B_TEST_CTRL1 ((0x0010 << 2) + 0xfe016000)
//========================================================================
@@ -5403,16 +5403,16 @@
//Bit 6:4, reg_frddr_type ,default = 0
//Bit 3:0, reserved
#define EARCTX_SPDIFOUT_PREAMB ((0x0006 << 2) + 0xfe333400)
-//Bit 31, reg_premable_Z_set ,default = 0,user 8'b11101000 1 user 7:0
-//Bit 30, reg_premable_Y_set ,default = 0,user 8'b11100100 1 user 15:8
-//Bit 29, reg_premable_X_set ,default = 0,user 8'b11100010 1 user 23:16
+//Bit 31, reg_preamble_Z_set ,default = 0,user 8'b11101000 1 user 7:0
+//Bit 30, reg_preamble_Y_set ,default = 0,user 8'b11100100 1 user 15:8
+//Bit 29, reg_preamble_X_set ,default = 0,user 8'b11100010 1 user 23:16
//Bit 28:24, reserved
-//Bit 23:16, reg_premable_X_value ,default = 0
-//Bit 15:8, reg_premable_Y_value ,default = 0
-//Bit 7:0, reg_premable_Z_value ,default = 0
+//Bit 23:16, reg_preamble_X_value ,default = 0
+//Bit 15:8, reg_preamble_Y_value ,default = 0
+//Bit 7:0, reg_preamble_Z_value ,default = 0
#define EARCTX_SPDIFOUT_SWAP ((0x0007 << 2) + 0xfe333400)
//Bit 31:16, reg_hold_cnt ,default = 0,hold start cnt ,valid when reg_hold_for_tdm set 1
-//Bit 15, reg_init_send_en ,default = 0,send 01 sequence some times after intial done from frddr set
+//Bit 15, reg_init_send_en ,default = 0,send 01 sequence some times after initial done from frddr set
//Bit 14:0, reg_init_send_cnt ,default = 0,send 01 sequence time ,valid when reg_init_send_en set 1
#define EARCTX_ERR_CORRT_CTRL0 ((0x0008 << 2) + 0xfe333400)
//Bit 31:24, reserved
@@ -5457,7 +5457,7 @@
//Bit 21, reg_data_sel ,default = 0,//data sel: 0 data 1 reg_mute_data_value
//Bit 20:19, reg_ubit_sel ,default = 0,//userBit sel: 0 data 1 reg_value 2 fifo data
//Bit 18, reg_vbit_sel ,default = 0,//validBit sel: 0 data 1 reg_value
-//Bit 17, reg_chst_sel ,default = 0,//chanel status sel: 0 data 1 reg_value
+//Bit 17, reg_chst_sel ,default = 0,//channel status sel: 0 data 1 reg_value
//Bit 16, reg_ubit_fifo_less_irq_en ,default = 0,fifo_less_thd irq enable
//Bit 15:8, reg_ubit_fifo_start_thd ,default = 0,start transmit iu after fifo level greater than this value
//Bit 7:0, reg_ubit_fifo_less_thd ,default = 0,generate irq,when fifo level less than this value
@@ -5808,22 +5808,22 @@
#define EARC_RX_CMDC_STATUS5 ((0x002c << 2) + 0xfe333800)
//Bit 31:0, ro_cmdc_status5 unsigned, RO, default = 0,
#define EARC_RX_CMDC_STATUS6 ((0x002d << 2) + 0xfe333800)
-//Bit 31, ro_idle2_int unsigned, RO, dfault =0
-//Bit 30, ro_idle1_int unsigned, RO, dfault =0
-//Bit 29, ro_disc2_int unsigned, RO, dfault =0
-//Bit 28, ro_disc1_int unsigned, RO, dfault =0
-//Bit 27, ro_earc_int unsigned, RO, dfault =0
-//Bit 26, ro_hb_status_int unsigned, RO, dfault =0
-//Bit 25, ro_losthb_int unsigned, RO, dfault =0
-//Bit 24, ro_timeout_int unsigned, RO, dfault =0
-//Bit 23, ro_status_ch_int unsigned, RO, dfault =0
-//Bit 22, ro_int_rec_invalid_id unsigned, RO, dfault =0
-//Bit 21, ro_int_rec_invalid_offset unsigned, RO, dfault =0
-//Bit 20, ro_int_rec_unexp unsigned, RO, dfault =0
-//Bit 19, ro_int_rec_ecc_err unsigned, RO, dfault =0
-//Bit 18, ro_int_rec_parity_err unsigned, RO, dfault =0
-//Bit 17, ro_int_recv_packet unsigned, RO, dfault =0
-//Bit 16, ro_int_rec_time_out unsigned, RO, dfault =0
+//Bit 31, ro_idle2_int unsigned, RO, default =0
+//Bit 30, ro_idle1_int unsigned, RO, default =0
+//Bit 29, ro_disc2_int unsigned, RO, default =0
+//Bit 28, ro_disc1_int unsigned, RO, default =0
+//Bit 27, ro_earc_int unsigned, RO, default =0
+//Bit 26, ro_hb_status_int unsigned, RO, default =0
+//Bit 25, ro_losthb_int unsigned, RO, default =0
+//Bit 24, ro_timeout_int unsigned, RO, default =0
+//Bit 23, ro_status_ch_int unsigned, RO, default =0
+//Bit 22, ro_int_rec_invalid_id unsigned, RO, default =0
+//Bit 21, ro_int_rec_invalid_offset unsigned, RO, default =0
+//Bit 20, ro_int_rec_unexp unsigned, RO, default =0
+//Bit 19, ro_int_rec_ecc_err unsigned, RO, default =0
+//Bit 18, ro_int_rec_parity_err unsigned, RO, default =0
+//Bit 17, ro_int_recv_packet unsigned, RO, default =0
+//Bit 16, ro_int_rec_time_out unsigned, RO, default =0
//Bit 15:0, reserved
//
// Closing file: ./earc_rx_cmdc.h
@@ -5966,10 +5966,10 @@
//Bit 31, reg_work_enable unsigned, default = 0, dmac user bit decode enable
//Bit 30:24, reg_iu_sync unsigned, default = 0, iu sync value
//Bit 23:16, reg_fifo_thd unsigned, default = 0, generate irq when fifo level pass some threshold
-//Bit 15, reg_max_dist_en unsigned, default = 0, max distance bewteen IUs to set lost
+//Bit 15, reg_max_dist_en unsigned, default = 0, max distance between IUs to set lost
//Bit 14, reg_iu_sync_en unsigned, default = 0, iu sync code enable 0 : all iu to fifo 1 only sync iu packet to fifo
//Bit 13:12, reg_user_lr unsigned, default = 0, 00 off 01 use l channel userbit 10 use r channel userbit 11 user lr channel userbit
-//Bit 11:8, reg_max_dist unsigned, default = 0, max distance bewteen IUs value
+//Bit 11:8, reg_max_dist unsigned, default = 0, max distance between IUs value
//Bit 7, reg_fifo_thd_en unsigned, default = 0, fifo_thd irq enable
//Bit 6, reg_fifo_lost_init_en unsigned, default = 0, when lost,initial fifo
//Bit 5, reg_fifo_init unsigned, default = 0, fifo initial
@@ -8576,7 +8576,7 @@
// Bit 19:14 -- des_2 ts pl state -- Read Only
// Bit 13:8 -- des ts pl state -- Read Only
// Bit 3:0 PID index to 8 PID to get key-set
-// auto increse after TS_PL_PID_DATA read/write
+// auto increase after TS_PL_PID_DATA read/write
#define TS_PL_PID_INDEX ((0x00f3 << 2) + 0xfe040000)
// Bit 13 -- PID match disble
// Bit 12:0 -- PID
@@ -8604,7 +8604,7 @@
// [3] General enable for the ciplus module
// [2] AES CBC disable (default should be 0 to enable AES CBC)
// [1] AES Enable
-// [0] DES Eanble
+// [0] DES Enable
#define CIPLUS_CONFIG ((0x00fd << 2) + 0xfe040000)
// bit[31:28] AES IV endian
// bit[27:24] AES message out endian
@@ -9137,7 +9137,7 @@
// To measure display slave's frame rate, we can use a reference clock to measure the duration of one of more edpite pulse(s).
// Measurement control is by register MIPI_DSI_TOP_MEAS_CNTL bit[9:0].
// Reference clock comes from clk_rst_tst.cts_dsi_meas_clk, and is defined by HIU register HHI_VDIN_MEAS_CLK_CNTL bit[23:12].
-// Mesurement result is in MIPI_DSI_TOP_MEAS_STAT_TE0 and MIPI_DSI_TOP_MEAS_STAT_TE1, as below:
+// Measurement result is in MIPI_DSI_TOP_MEAS_STAT_TE0 and MIPI_DSI_TOP_MEAS_STAT_TE1, as below:
// edpite_meas_count[47:0]: Number of reference clock cycles counted during one measure period (non-incremental measure), or
// during all measure periods so far (incremental measure).
// edpite_meas_count_n[3:0]:Number of measure periods has been done. Number can wrap over.
@@ -9150,7 +9150,7 @@
// To measure Host's frame rate, we can use a reference clock to measure the duration of one of more Vsync pulse(s).
// Measurement control is by register MIPI_DSI_TOP_MEAS_CNTL bit[19:10].
// Reference clock comes from clk_rst_tst.cts_dsi_meas_clk, and is defined by HIU register HHI_VDIN_MEAS_CLK_CNTL bit[23:12].
-// Mesurement result is in MIPI_DSI_TOP_MEAS_STAT_VS0 and MIPI_DSI_TOP_MEAS_STAT_VS1, as below:
+// Measurement result is in MIPI_DSI_TOP_MEAS_STAT_VS0 and MIPI_DSI_TOP_MEAS_STAT_VS1, as below:
// vsync_meas_count[47:0]: Number of reference clock cycles counted during one measure period (non-incremental measure), or
// during all measure periods so far (incremental measure).
// vsync_meas_count_n[3:0]: Number of measure periods has been done. Number can wrap over.
@@ -9344,7 +9344,7 @@
// To measure display slave's frame rate, we can use a reference clock to measure the duration of one of more edpite pulse(s).
// Measurement control is by register MIPI_DSI_B_TOP_MEAS_CNTL bit[9:0].
// Reference clock comes from clk_rst_tst.cts_dsi_meas_clk, and is defined by HIU register HHI_VDIN_MEAS_CLK_CNTL bit[23:12].
-// Mesurement result is in MIPI_DSI_B_TOP_MEAS_STAT_TE0 and MIPI_DSI_B_TOP_MEAS_STAT_TE1, as below:
+// Measurement result is in MIPI_DSI_B_TOP_MEAS_STAT_TE0 and MIPI_DSI_B_TOP_MEAS_STAT_TE1, as below:
// edpite_meas_count[47:0]: Number of reference clock cycles counted during one measure period (non-incremental measure), or
// during all measure periods so far (incremental measure).
// edpite_meas_count_n[3:0]:Number of measure periods has been done. Number can wrap over.
@@ -9357,7 +9357,7 @@
// To measure Host's frame rate, we can use a reference clock to measure the duration of one of more Vsync pulse(s).
// Measurement control is by register MIPI_DSI_B_TOP_MEAS_CNTL bit[19:10].
// Reference clock comes from clk_rst_tst.cts_dsi_meas_clk, and is defined by HIU register HHI_VDIN_MEAS_CLK_CNTL bit[23:12].
-// Mesurement result is in MIPI_DSI_B_TOP_MEAS_STAT_VS0 and MIPI_DSI_B_TOP_MEAS_STAT_VS1, as below:
+// Measurement result is in MIPI_DSI_B_TOP_MEAS_STAT_VS0 and MIPI_DSI_B_TOP_MEAS_STAT_VS1, as below:
// vsync_meas_count[47:0]: Number of reference clock cycles counted during one measure period (non-incremental measure), or
// during all measure periods so far (incremental measure).
// vsync_meas_count_n[3:0]: Number of measure periods has been done. Number can wrap over.
@@ -11112,7 +11112,7 @@
#define AWSUB0_ISP_LOSS_FRAME_HOLD ((0x0001 << 2) + 0xfe3b4400)
//Bit 31:0 reg_frame_hold_nums // unsigned , RW, default = 16, hold clock number from frame_rst, to wait register ready
#define AWSUB0_ISP_LOSS_GCLK_CTRL ((0x0002 << 2) + 0xfe3b4400)
-//Bit 31: 0 reg_gclk_ctrl // unsigned , RW, default = 0 resevsed for gated-clock control
+//Bit 31: 0 reg_gclk_ctrl // unsigned , RW, default = 0 reserved for gated-clock control
#define AWSUB0_ISP_LOSS_RO_CODEC_STATUS ((0x0003 << 2) + 0xfe3b4400)
//Bit 31: 0 ro_codec_status // unsigned , RW, default = 0, codec status, write 1 to clear
#define AWSUB0_ISP_LOSS_MISC ((0x0004 << 2) + 0xfe3b4400)
@@ -11836,7 +11836,7 @@
#define ARSUB0_ISP_LOSS_FRAME_HOLD ((0x0081 << 2) + 0xfe3b4400)
//Bit 31:0 reg_frame_hold_nums // unsigned , RW, default = 16, hold clock number from frame_rst, to wait register ready
#define ARSUB0_ISP_LOSS_GCLK_CTRL ((0x0082 << 2) + 0xfe3b4400)
-//Bit 31: 0 reg_gclk_ctrl // unsigned , RW, default = 0 resevsed for gated-clock control
+//Bit 31: 0 reg_gclk_ctrl // unsigned , RW, default = 0 reserved for gated-clock control
#define ARSUB0_ISP_LOSS_RO_CODEC_STATUS ((0x0083 << 2) + 0xfe3b4400)
//Bit 31: 0 ro_codec_status // unsigned , RW, default = 0, codec status, write 1 to clear
#define ARSUB0_ISP_LOSS_MISC ((0x0084 << 2) + 0xfe3b4400)
@@ -12912,7 +12912,7 @@
#define TWSUB0_ISP_LOSS_FRAME_HOLD ((0x0001 << 2) + 0xfe3b4c00)
//Bit 31:0 reg_frame_hold_nums // unsigned , RW, default = 16, hold clock number from frame_rst, to wait register ready
#define TWSUB0_ISP_LOSS_GCLK_CTRL ((0x0002 << 2) + 0xfe3b4c00)
-//Bit 31: 0 reg_gclk_ctrl // unsigned , RW, default = 0 resevsed for gated-clock control
+//Bit 31: 0 reg_gclk_ctrl // unsigned , RW, default = 0 reserved for gated-clock control
#define TWSUB0_ISP_LOSS_RO_CODEC_STATUS ((0x0003 << 2) + 0xfe3b4c00)
//Bit 31: 0 ro_codec_status // unsigned , RW, default = 0, codec status, write 1 to clear
#define TWSUB0_ISP_LOSS_MISC ((0x0004 << 2) + 0xfe3b4c00)
@@ -13636,7 +13636,7 @@
#define TRSUB0_ISP_LOSS_FRAME_HOLD ((0x0081 << 2) + 0xfe3b4c00)
//Bit 31:0 reg_frame_hold_nums // unsigned , RW, default = 16, hold clock number from frame_rst, to wait register ready
#define TRSUB0_ISP_LOSS_GCLK_CTRL ((0x0082 << 2) + 0xfe3b4c00)
-//Bit 31: 0 reg_gclk_ctrl // unsigned , RW, default = 0 resevsed for gated-clock control
+//Bit 31: 0 reg_gclk_ctrl // unsigned , RW, default = 0 reserved for gated-clock control
#define TRSUB0_ISP_LOSS_RO_CODEC_STATUS ((0x0083 << 2) + 0xfe3b4c00)
//Bit 31: 0 ro_codec_status // unsigned , RW, default = 0, codec status, write 1 to clear
#define TRSUB0_ISP_LOSS_MISC ((0x0084 << 2) + 0xfe3b4c00)
@@ -14376,7 +14376,7 @@
#define TWSUB1_ISP_LOSS_FRAME_HOLD ((0x0001 << 2) + 0xfe3b5000)
//Bit 31:0 reg_frame_hold_nums // unsigned , RW, default = 16, hold clock number from frame_rst, to wait register ready
#define TWSUB1_ISP_LOSS_GCLK_CTRL ((0x0002 << 2) + 0xfe3b5000)
-//Bit 31: 0 reg_gclk_ctrl // unsigned , RW, default = 0 resevsed for gated-clock control
+//Bit 31: 0 reg_gclk_ctrl // unsigned , RW, default = 0 reserved for gated-clock control
#define TWSUB1_ISP_LOSS_RO_CODEC_STATUS ((0x0003 << 2) + 0xfe3b5000)
//Bit 31: 0 ro_codec_status // unsigned , RW, default = 0, codec status, write 1 to clear
#define TWSUB1_ISP_LOSS_MISC ((0x0004 << 2) + 0xfe3b5000)
@@ -15100,7 +15100,7 @@
#define TRSUB1_ISP_LOSS_FRAME_HOLD ((0x0081 << 2) + 0xfe3b5000)
//Bit 31:0 reg_frame_hold_nums // unsigned , RW, default = 16, hold clock number from frame_rst, to wait register ready
#define TRSUB1_ISP_LOSS_GCLK_CTRL ((0x0082 << 2) + 0xfe3b5000)
-//Bit 31: 0 reg_gclk_ctrl // unsigned , RW, default = 0 resevsed for gated-clock control
+//Bit 31: 0 reg_gclk_ctrl // unsigned , RW, default = 0 reserved for gated-clock control
#define TRSUB1_ISP_LOSS_RO_CODEC_STATUS ((0x0083 << 2) + 0xfe3b5000)
//Bit 31: 0 ro_codec_status // unsigned , RW, default = 0, codec status, write 1 to clear
#define TRSUB1_ISP_LOSS_MISC ((0x0084 << 2) + 0xfe3b5000)
@@ -17166,7 +17166,7 @@
// 1=ABH read request burst size 24;
// 2=ABH read request burst size 32;
// 3=ABH read request burst size 48.
-// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logics except register.
+// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logic except register.
// Bit 0 RW ctrl_free_clk_enable. 0=Default, Enable clock gating. 1=No clock gating, enable free clock.
#define RDMA_CTRL ((0x1114 << 2) + 0xff000000)
// Read only.
@@ -17263,7 +17263,7 @@
//Bit 7:6, component0 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in
//Bit 5, input window selection function enable
//Bit 4, enable VDIN common data input, otherwise there will be no video data input
-//Bit 3:0 vdin selection, 1: mpeg_in from dram, 2: bt656 input, 3: component input, 4: tvdecoder input, 5: hdmi rx input, 6: digtial video input, 7: loopback from Viu1, 8: MIPI.
+//Bit 3:0 vdin selection, 1: mpeg_in from dram, 2: bt656 input, 3: component input, 4: tvdecoder input, 5: hdmi rx input, 6: digital video input, 7: loopback from Viu1, 8: MIPI.
#define VDIN_COM_CTRL0 ((0x1202 << 2) + 0xff000000)
//Bit 28:16 active_max_pix_cnt, readonly
//Bit 12:0 active_max_pix_cnt_shadow, readonly
@@ -18908,7 +18908,7 @@
//Bit 0 reg_ldc_gain_lut_wr // unsigned , RW, default = 0 1:software write 0:software read.
#define LDC_GAIN_LUT_CTRL1 ((0x1475 << 2) + 0xff000000)
//Bit 31: 1 reserved
-//Bit 0 reg_ldc_gain_lut_str // unsigned , RW, default = 0 0->1:one software write/read start,postive edge valid.
+//Bit 0 reg_ldc_gain_lut_str // unsigned , RW, default = 0 0->1:one software write/read start, positive edge valid.
#define LDC_ADJ_VS_CTRL ((0x1476 << 2) + 0xff000000)
//Bit 31:16 reserved
//Bit 15:0 reg_ldc_blk_intsty_calc_intvl // unsigned , RW, default = 200 delay for one block intensity calculation period
@@ -18923,7 +18923,7 @@
//Bit 26 reg_ldc_prt_func_en //unsigned , RW, default = 0 1: enable LDC output protect function 0:disable LDC output protect function
//Bit 25 reg_ldc_bl_input_sft_ctr_en //unsigned , RW, default = 0 1: software control backlight info write index enable
//Bit 24:23 reg_ldc_bl_input_sft_wr_idx //unsigned , RW, default = 0 backlight info write index, for debug only
-//Bit 22 reg_ldc_vsync_get_bl_info_en //unsigned , RW, default = 1 0:get backlight info every block line (no vsync interrupt) 1:get backlight info accroding to vsync
+//Bit 22 reg_ldc_vsync_get_bl_info_en //unsigned , RW, default = 1 0:get backlight info every block line (no vsync interrupt) 1:get backlight info according to vsync
//Bit 21:20 reg_ldc_hist_burst_len //unsigned , RW, default = 0 0:2 times 128bit 1:4 times 128bit 2,3:6 times 128bit
//Bit 19:18 reg_ldc_blk_intsty_burst_len //unsigned , RW, default = 0 0:2 times 128bit 1:4 times 128bit 2:6 times 128bit 3:8 times 128bit
//Bit 17 reg_ldc_vs_edge_sel //unsigned , RW, default = 1 1:posedge vs sync 0:negedge vs sync
@@ -19412,7 +19412,7 @@
//bit 15: 8, mtn_minth
//bit 7: 0, mtn_maxth
#define DI_MTN_1_CTRL5 ((0x1744 << 2) + 0xff000000)
-//bit 31:28, mtn_m1b_extnd
+//bit 31:28, mtn_m1b_extend
//bit 27:24, mtn_m1b_errod
//bit 21:20, mtn_mot_txt_mode
//bit 19:18, mtn_replace_cbyy
@@ -20258,7 +20258,7 @@
//bit 15:8, reg_ei_int_drtdelay2_notver_sadth
//bit 7:0, reg_ei_int_drtdelay2_vlddrt_sadth
#define DI_MTN_1_CTRL6 ((0x17a9 << 2) + 0xff000000)
-//bit 31:24, mtn_m1b_extnd
+//bit 31:24, mtn_m1b_extend
//bit 23:16, mtn_m1b_errod
//bit 15: 8, mtn_core_ykinter
//bit 7: 0, mtn_core_ckinter
@@ -21215,9 +21215,9 @@
// Bit 15:13 v0_gofld_sel, 000: display go_field, 001: DI pre_frame_rst, 010: vdin0 go_field, 011: vdin1 go_field, otherwise: force go_field by
// reg_v0_go_field(bit19)
// Bit 12:6 hole_lines for d2d3 depth read interface
-// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 fomart output), 2'b10: scale output, otherwise nothing as v1
+// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 format output), 2'b10: scale output, otherwise nothing as v1
// Bit 3 use_vdin_eol, if true, use vdin eol as the v0_eol, otherwise using length to get the v0_eol
-// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 fomart output), 101: vpp scale output
+// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 format output), 101: vpp scale output
//
// `define D2D3_INTF_CTRL0 8'h09
#define VD1_AFBCD0_MISC_CTRL ((0x1a0a << 2) + 0xff000000)
@@ -21230,7 +21230,7 @@
// OSD1 registers 0x10-0x2f
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -21357,7 +21357,7 @@
// OSD2 registers 0x30-0x4f 0x64 -0x67
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -23060,9 +23060,9 @@
// Bit 0 SMOKE1 preblend enable only when preblend osd1 is not enable
#define VPP_SMOKE_CTRL ((0x1d29 << 2) + 0xff000000)
//smoke can be used only when that blending is disable and then be used as smoke function
-//smoke1 for OSD1 chanel
-//smoke2 for OSD2 chanel
-//smoke3 for VD2 chanel
+//smoke1 for OSD1 channel
+//smoke2 for OSD2 channel
+//smoke3 for VD2 channel
//31:24 Y
//23:16 Cb
//15:8 Cr
@@ -24895,7 +24895,7 @@
//
// Closing file: ./noise_estimate_reg.h
//
-// di arbtration :
+// di arbitration :
// the segment is 8'h50-8'h5f
//
// Reading file: ./di_arb_axi_regs.h
@@ -25103,13 +25103,13 @@
//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
//Bit 19 reserved
-//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
//Bit 11 reserved
//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
@@ -25521,13 +25521,13 @@
//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
//Bit 19 reserved
-//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
//Bit 11 reserved
//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
@@ -27448,7 +27448,7 @@
//Bit 4 reg_frc_pos_sel // unsigned , RW, default = 0, select singal of frc positon switch,1:before postblend 0:after postblend
//Bit 3:1 reserved
//Bit 0 reg_frc_byp_en // unsigned , RW, default = 1, bypass enable singal of frc,1:bypas frc 0:open frc
-// vpu arbtration :
+// vpu arbitration :
// the segment is 8'h90-8'hc8
//
// Reading file: ./vpu_arb_axi_regs.h
@@ -27702,8 +27702,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE1 ((0x27a6 << 2) + 0xff000000)
@@ -27715,8 +27715,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE2 ((0x27a7 << 2) + 0xff000000)
@@ -27728,8 +27728,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE3 ((0x27a8 << 2) + 0xff000000)
@@ -27741,8 +27741,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE4 ((0x27a9 << 2) + 0xff000000)
@@ -27754,8 +27754,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_WR_MODE0 ((0x27aa << 2) + 0xff000000)
@@ -27767,8 +27767,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_WR_MODE1 ((0x27ab << 2) + 0xff000000)
@@ -27780,8 +27780,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_WR_MODE2 ((0x27ac << 2) + 0xff000000)
@@ -27793,8 +27793,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_STAT ((0x27ad << 2) + 0xff000000)
@@ -30226,7 +30226,7 @@
// 0: unable; 1: enable, use neighboring mvs in refinement, default = 1
//Bit 11, reserved
//Bit 10, reg_mcdi_referrfrqchken
-// 0: unable; 1: enable, enable mv frquency check while finding min err in ref, default = 1
+// 0: unable; 1: enable, enable mv frequency check while finding min err in ref, default = 1
//Bit 9, reg_mcdi_refen
// 0: unable; 1: enable, enable mv refinement, default = 1
//Bit 8, reg_mcdi_horlineen
@@ -30310,7 +30310,7 @@
//Bit 19:16, reg_mcdi_chkedgedifthd0. thd0 for edge dif check (>=), default = 15
//Bit :15, reserved.
//Bit 14:10, reg_mcdi_chkedgechklen. total check length for edge check, 1~24 (>0), default = 24
-//Bit 9: 8, reg_mcdi_chkedgeedgesel. final edge select mode, 0: original start edge, 1: lpf start edge, 2: orignal start+end edge, 3: lpf start+end edge, default = 1
+//Bit 9: 8, reg_mcdi_chkedgeedgesel. final edge select mode, 0: original start edge, 1: lpf start edge, 2: original start+end edge, 3: lpf start+end edge, default = 1
//Bit 7: 3, reg_mcdi_chkedgesaddstgain. distance gain for sad calc while getting edges, default = 4
//Bit 2, reg_mcdi_chkedgechkmode. edge used in check mode, 0: original edge, 1: lpf edge, default = 1
//Bit 1, reg_mcdi_chkedgestartedge. edge mode for start edge, 0: original edge, 1: lpf edge, default = 0
@@ -30320,7 +30320,7 @@
//Bit 14:12, reg_mcdi_lmvvalidmode valid mode for lmv calc., 100b: use char det, 010b: use flt, 001b: use hori flg
//Bit 11:10, reg_mcdi_lmvgainmvmode four modes of mv selection for lmv weight calculation, default = 1
// 0: cur(x-3), lst(x-1,x,x+1); 1: cur(x-4,x-3), lst(x,x+1); 2: cur(x-5,x-4,x-3), lst(x-1,x,x+1,x+2,x+3); 3: cur(x-6,x-5,x-4,x-3), lst(x-1,x,x+1,x+2);
-//Bit 9, reg_mcdi_lmvinitmode initial lmvs at first row of input field, 0: intial value = 0; 1: inital = 32 (invalid), default = 0
+//Bit 9, reg_mcdi_lmvinitmode initial lmvs at first row of input field, 0: initial value = 0; 1: inital = 32 (invalid), default = 0
//Bit 8, reserved
//Bit 7: 4, reg_mcdi_lmvrt0 ratio of max mv, default = 5
//Bit 3: 0, reg_mcdi_lmvrt1 ratio of second max mv, default = 5
@@ -30433,15 +30433,15 @@
//Bit 3: 0, reg_mcdi_referrgmvgain. (locked) gmv gain for err calc. in ref, normalized to 8 as '1', default = 0
#define MCDI_REF_ERR_FRQ_CHK ((0x2f1d << 2) + 0xff000000)
//Bit 31:28, reserved
-//Bit 27:24, reg_mcdi_referrfrqgain. gain for mv frquency, normalized to 4 as '1', default = 10
+//Bit 27:24, reg_mcdi_referrfrqgain. gain for mv frequency, normalized to 4 as '1', default = 10
//Bit 23:21, reserved
-//Bit 20:16, reg_mcdi_referrfrqmax. max gain for mv frquency check, default = 31
+//Bit 20:16, reg_mcdi_referrfrqmax. max gain for mv frequency check, default = 31
//Bit 15, reserved
-//Bit 14:12, reg_mcdi_ref_errfrqmvdifthd2. mv dif threshold 2 (<) for mv frquency check, default = 3
+//Bit 14:12, reg_mcdi_ref_errfrqmvdifthd2. mv dif threshold 2 (<) for mv frequency check, default = 3
//Bit 11, reserved
-//Bit 10: 8, reg_mcdi_ref_errfrqmvdifthd1. mv dif threshold 1 (<) for mv frquency check, default = 2
+//Bit 10: 8, reg_mcdi_ref_errfrqmvdifthd1. mv dif threshold 1 (<) for mv frequency check, default = 2
//Bit 7, reserved
-//Bit 6: 4, reg_mcdi_ref_errfrqmvdifthd0. mv dif threshold 0 (<) for mv frquency check, default = 1
+//Bit 6: 4, reg_mcdi_ref_errfrqmvdifthd0. mv dif threshold 0 (<) for mv frequency check, default = 1
//Bit 3: 0, reserved
#define MCDI_QME_LPF_MSK ((0x2f1e << 2) + 0xff000000)
//Bit 31:28, reserved
@@ -33185,7 +33185,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 1 debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 1 debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -35153,13 +35153,13 @@
//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
//Bit 19 reserved
-//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
//Bit 11 reserved
//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
@@ -35459,7 +35459,7 @@
//bit[30] R-RW 0~1 0 reg_id_check : check the id of data path and req path
//bit[29] R-RW 0~1 0 reg_clear_fifo : manually reset bit
//bit[28] R-RW 0~1 0 reg_vsync_rst : soft_rst auto reset enable
-//bit[27] R-RW 0~1 0 reg_update_addr : manually udpate start addr
+//bit[27] R-RW 0~1 0 reg_update_addr : manually update start addr
//bit[26] R-RW 0~1 0 reg_addr_auto : auto update start addr enable
//bit[25] R-RW 0~1 0 reg_keep_receive : data path keep receive
//bit[24:19] R-RW 0~63 0 reg_req_th : fifo_room > req_th, then send the request
@@ -35954,11 +35954,11 @@
//Bit 1: 0 reg_in_ds_rate_y // unsigned , RW, default = 2 Input down-sample registers, normally AVG. value = [0,1,2], change according to input resolution. real rate is 2^reg_in_ds_rate
#define INTRP_PARAM ((0x4b01 << 2) + 0xff000000)
//Bit 31:26 reserved
-//Bit 25:21 reg_intep_phs_x_rtl // signed , RW, default = 0 Interpolation x phase used, could be negtive num, set by SW
-//Bit 20:16 reg_intep_phs_x_use // signed , RW, default = 0 Interpolation x phase used, could be negtive num, set by SW
+//Bit 25:21 reg_intep_phs_x_rtl // signed , RW, default = 0 Interpolation x phase used, could be negative num, set by SW
+//Bit 20:16 reg_intep_phs_x_use // signed , RW, default = 0 Interpolation x phase used, could be negative num, set by SW
//Bit 15:10 reserved
-//Bit 9: 5 reg_intep_phs_y_rtl // signed , RW, default = 0 Interpolation x phase used, could be negtive num, set by SW
-//Bit 4: 0 reg_intep_phs_y_use // signed , RW, default = 0 Interpolation y phase used, could be negtive num, set by SW
+//Bit 9: 5 reg_intep_phs_y_rtl // signed , RW, default = 0 Interpolation x phase used, could be negative num, set by SW
+//Bit 4: 0 reg_intep_phs_y_use // signed , RW, default = 0 Interpolation y phase used, could be negative num, set by SW
#define DCTR_BGRID_PARAM1 ((0x4b02 << 2) + 0xff000000)
//Bit 31:26 reserved
//Bit 25:16 reg_grd_xnum // unsigned , RW, default = 80 number of grid in horizontal dimension, value = [0-80]
@@ -36831,7 +36831,7 @@
//Bit 3: 2, reg_nr_cti_blend_mode : blend mode of nr and lti result: 0: nr; 1:cti; 2: (nr+cti)/2; 3:cti + dlt_nr . unsigned , default = 1
//Bit 1: 0, reg_nr_lti_blend_mode : blend mode of nr and lti result: 0: nr; 1:lti; 2: (nr+lti)/2; 3:lti + dlt_nr . unsigned , default = 2
////////////////////////////////////////////////////////////////////////////////
-// new ti regsters from here
+// new ti registers from here
////////////////////////////////////////////////////////////////////////////////
#define LTI_DIR_CORE_ALPHA ((0x502a << 2) + 0xff000000)
//Bit 31:30, reserved
@@ -37132,7 +37132,7 @@
//Bit 23:16, reg_sr3_pk_hp_hvcon_replace8lv_gain //u8: gain to local variant before calculating the hv gain for peaking, normalized to 32 as "1" default = 32;
//Bit 15:8, reg_sr3_pk_bp_hvcon_replace8lv_gain //u8: gain to local variant before calculating the hv gain for peaking, normalized to 32 as "1" default = 32;
//Bit 7, reg_sr3_sad_intlev_mode //u1: interleave detection xerr mode: 0 max; 1:sum default=1
-//Bit 6, reg_sr3_sad_intlev_mode1 //u1: mode 1 of using diagonal protection: 0: no digonal protection; 1: with diagonal protection default=1
+//Bit 6, reg_sr3_sad_intlev_mode1 //u1: mode 1 of using diagonal protection: 0: no diagonal protection; 1: with diagonal protection default=1
//Bit 5:0, reg_sr3_sad_intlev_gain //u6: interleave detection for sad gain applied, normalized to 8 as 1 default=12
#define SHARP_DEJ_CTRL ((0x5064 << 2) + 0xff000000)
//Bit 31:4 reserved
@@ -37211,7 +37211,7 @@
#define SHARP_SR3_DERING_LUMA2PKGAIN_4TO6 ((0x506d << 2) + 0xff000000)
//Bit 31:24 reserved
//Bit 23:16 reg_sr3_dering_luma2pkgain6 // u8: rate1 (for bpcon>th1) of curve for dering pkgain based on LPF luma level. default =24
-//Bit 15:8 reg_sr3_dering_luma2pkgain5 // u8: rate0 (for bpcon<th0) of curve for dering pkgain based on LPF luma level. dfault =50
+//Bit 15:8 reg_sr3_dering_luma2pkgain5 // u8: rate0 (for bpcon<th0) of curve for dering pkgain based on LPF luma level. default =50
//Bit 7:0 reg_sr3_dering_luma2pkgain4 // u8: level limit(for bpcon>th1) of curve for dering pkgain based on LPF luma level. default =255
#define SHARP_SR3_DERING_LUMA2PKOS_0TO3 ((0x506e << 2) + 0xff000000)
//Bit 31:24 reg_sr3_dering_luma2pkos3 // u8: level limit(for th0<bpcon<th1) of curve for dering pkOS based on LPF luma level. default=255
@@ -37221,7 +37221,7 @@
#define SHARP_SR3_DERING_LUMA2PKOS_4TO6 ((0x506f << 2) + 0xff000000)
//Bit 31:24 reserved
//Bit 23:16 reg_sr3_dering_luma2pkos6 // u8: rate1 (for bpcon>th1) of curve for dering pkOS based on LPF luma level. default =24
-//Bit 15:8 reg_sr3_dering_luma2pkos5 // u8: rate0 (for bpcon<th0) of curve for dering pkOS based on LPF luma level. dfault =50
+//Bit 15:8 reg_sr3_dering_luma2pkos5 // u8: rate0 (for bpcon<th0) of curve for dering pkOS based on LPF luma level. default =50
//Bit 7:0 reg_sr3_dering_luma2pkos4 // u8: level limit(for bpcon>th1) of curve for dering pkOS based on LPF luma level. default =255
#define SHARP_SR3_DERING_GAINVS_MADSAD ((0x5070 << 2) + 0xff000000)
//Bit 31:28 reg_sr3_dering_gainvs_maxsad7 //u4: pkgain vs maxsad value, 8 node interpolations, default = 0
@@ -37268,7 +37268,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 1 debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 1 debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -37771,8 +37771,8 @@
//Bit 31:12 reserved
//Bit 11:10 reg_fmeter_vwin_mm //u2, vertical window size, 0:1 cloumn, 1:3cloumn, 2or3: 5cloumn .unsigned , default = 0
//Bit 9 : 8 reg_fmeter_hwin_mm //u2, horizontal window size, 0:1x7, 1:1x9, 2or3: 1x11 .unsigned , default = 0
-//Bit 7 reg_fmeter_d2_mode //u1, selectino filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
-//Bit 6 reg_fmeter_v2_mode //u1, selectino filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 7 reg_fmeter_d2_mode //u1, selection filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 6 reg_fmeter_v2_mode //u1, selection filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
//Bit 5: 4 reg_fmeter_h2_mode //u2, selection filter H2, 0: [0 0 0 -2 0 0 2 0 0], 1: [-2 0 0 0 2], 2or3: [0-2 0 0 0 0 0 2 0] .unsigned , default = 0
//Bit 3: 1 reserved
//Bit 0 reg_freq_meter_en //u1, freq meter enable .unsigned , default = 0
@@ -41014,7 +41014,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -41183,7 +41183,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -41352,7 +41352,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -41521,7 +41521,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -42658,7 +42658,7 @@
//Bit 4 reg_vp_debug_type_replace_phs_mv_en // unsigned , RW, default = 0 enable of type replace phs mv
//Bit 3 reg_vp_debug_phs_rp_flg_en // unsigned , RW, default = 0 enable of phs rp flg en
//Bit 2 reg_vp_debug_phs_sobj_flg_en // unsigned , RW, default = 0 enable of phs sobj flg en
-//Bit 1 reg_mv_debug_var_level_en // unsigned , RW, default = 0 eanble of var level debug
+//Bit 1 reg_mv_debug_var_level_en // unsigned , RW, default = 0 enable of var level debug
//Bit 0 reg_mv_debug_var2_level_en // unsigned , RW, default = 0 enable of var2 level debug
#define FRC_REG_MC_DEBUG1 ((0x0141 << 2) + 0xff050000)
//Bit 31:24 reserved
@@ -43647,7 +43647,7 @@
// synopsys translate_on
#define FRC_INP_CSC_CTRL ((0x04e0 << 2) + 0xff050000)
//Bit 31: 10 reserved
-//Bit 9 : 8 reg_glk_ctrl // unsigned , RW, default = 0 csc reg_glk_ctrl enable 2'b00:gatting 2'b01:close 2'b1x:always open
+//Bit 9 : 8 reg_glk_ctrl // unsigned , RW, default = 0 csc reg_glk_ctrl enable 2'b00:gating 2'b01:close 2'b1x:always open
//Bit 7: 5 reserved
//Bit 4 reg_sync_en // unsigned , RW, default = 0 reg_csc_en sync enable
//Bit 3 reg_csc_en // unsigned , RW, default = 1 enable rgb2yuv mtrix for ip pattern generation
@@ -43846,44 +43846,44 @@
//Bit 7: 0 reg_iplogo_edgedir4_corr_form_cnt_coring // unsigned , RW, default = 1 dir4 corr form logo same weight cnt coring
#define FRC_IPLOGO_CORR_FORM_UB_GWEIGHT_0 ((0x0507 << 2) + 0xff050000)
//Bit 31: 8 reserved
-//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_4_0 // unsigned , RW, default = 7 dir4 corr form logo gaussion weight
+//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_4_0 // unsigned , RW, default = 7 dir4 corr form logo gaussian weight
#define FRC_IPLOGO_CORR_FORM_LB_GWEIGHT_0 ((0x0508 << 2) + 0xff050000)
-//Bit 31:24 reg_iplogo_edgedir4_corr_weight_5x5_3_0 // unsigned , RW, default = 9 dir4 corr form logo gaussion weight
-//Bit 23:16 reg_iplogo_edgedir4_corr_weight_5x5_2_0 // unsigned , RW, default = 10 dir4 corr form logo gaussion weight
-//Bit 15: 8 reg_iplogo_edgedir4_corr_weight_5x5_1_0 // unsigned , RW, default = 9 dir4 corr form logo gaussion weight
-//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_0_0 // unsigned , RW, default = 7 dir4 corr form logo gaussion weight
+//Bit 31:24 reg_iplogo_edgedir4_corr_weight_5x5_3_0 // unsigned , RW, default = 9 dir4 corr form logo gaussian weight
+//Bit 23:16 reg_iplogo_edgedir4_corr_weight_5x5_2_0 // unsigned , RW, default = 10 dir4 corr form logo gaussian weight
+//Bit 15: 8 reg_iplogo_edgedir4_corr_weight_5x5_1_0 // unsigned , RW, default = 9 dir4 corr form logo gaussian weight
+//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_0_0 // unsigned , RW, default = 7 dir4 corr form logo gaussian weight
#define FRC_IPLOGO_CORR_FORM_UB_GWEIGHT_1 ((0x0509 << 2) + 0xff050000)
//Bit 31: 8 reserved
-//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_4_1 // unsigned , RW, default = 9 dir4 corr form logo gaussion weight
+//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_4_1 // unsigned , RW, default = 9 dir4 corr form logo gaussian weight
#define FRC_IPLOGO_CORR_FORM_LB_GWEIGHT_1 ((0x050a << 2) + 0xff050000)
-//Bit 31:24 reg_iplogo_edgedir4_corr_weight_5x5_3_1 // unsigned , RW, default = 11 dir4 corr form logo gaussion weight
-//Bit 23:16 reg_iplogo_edgedir4_corr_weight_5x5_2_1 // unsigned , RW, default = 12 dir4 corr form logo gaussion weight
-//Bit 15: 8 reg_iplogo_edgedir4_corr_weight_5x5_1_1 // unsigned , RW, default = 11 dir4 corr form logo gaussion weight
-//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_0_1 // unsigned , RW, default = 9 dir4 corr form logo gaussion weight
+//Bit 31:24 reg_iplogo_edgedir4_corr_weight_5x5_3_1 // unsigned , RW, default = 11 dir4 corr form logo gaussian weight
+//Bit 23:16 reg_iplogo_edgedir4_corr_weight_5x5_2_1 // unsigned , RW, default = 12 dir4 corr form logo gaussian weight
+//Bit 15: 8 reg_iplogo_edgedir4_corr_weight_5x5_1_1 // unsigned , RW, default = 11 dir4 corr form logo gaussian weight
+//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_0_1 // unsigned , RW, default = 9 dir4 corr form logo gaussian weight
#define FRC_IPLOGO_CORR_FORM_UB_GWEIGHT_2 ((0x050b << 2) + 0xff050000)
//Bit 31: 8 reserved
-//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_4_2 // unsigned , RW, default = 10 dir4 corr form logo gaussion weight
+//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_4_2 // unsigned , RW, default = 10 dir4 corr form logo gaussian weight
#define FRC_IPLOGO_CORR_FORM_LB_GWEIGHT_2 ((0x050c << 2) + 0xff050000)
-//Bit 31:24 reg_iplogo_edgedir4_corr_weight_5x5_3_2 // unsigned , RW, default = 12 dir4 corr form logo gaussion weight
-//Bit 23:16 reg_iplogo_edgedir4_corr_weight_5x5_2_2 // unsigned , RW, default = 13 dir4 corr form logo gaussion weight
-//Bit 15: 8 reg_iplogo_edgedir4_corr_weight_5x5_1_2 // unsigned , RW, default = 12 dir4 corr form logo gaussion weight
-//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_0_2 // unsigned , RW, default = 10 dir4 corr form logo gaussion weight
+//Bit 31:24 reg_iplogo_edgedir4_corr_weight_5x5_3_2 // unsigned , RW, default = 12 dir4 corr form logo gaussian weight
+//Bit 23:16 reg_iplogo_edgedir4_corr_weight_5x5_2_2 // unsigned , RW, default = 13 dir4 corr form logo gaussian weight
+//Bit 15: 8 reg_iplogo_edgedir4_corr_weight_5x5_1_2 // unsigned , RW, default = 12 dir4 corr form logo gaussian weight
+//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_0_2 // unsigned , RW, default = 10 dir4 corr form logo gaussian weight
#define FRC_IPLOGO_CORR_FORM_UB_GWEIGHT_3 ((0x050d << 2) + 0xff050000)
//Bit 31: 8 reserved
-//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_4_3 // unsigned , RW, default = 9 dir4 corr form logo gaussion weight
+//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_4_3 // unsigned , RW, default = 9 dir4 corr form logo gaussian weight
#define FRC_IPLOGO_CORR_FORM_LB_GWEIGHT_3 ((0x050e << 2) + 0xff050000)
-//Bit 31:24 reg_iplogo_edgedir4_corr_weight_5x5_3_3 // unsigned , RW, default = 11 dir4 corr form logo gaussion weight
-//Bit 23:16 reg_iplogo_edgedir4_corr_weight_5x5_2_3 // unsigned , RW, default = 12 dir4 corr form logo gaussion weight
-//Bit 15: 8 reg_iplogo_edgedir4_corr_weight_5x5_1_3 // unsigned , RW, default = 11 dir4 corr form logo gaussion weight
-//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_0_3 // unsigned , RW, default = 9 dir4 corr form logo gaussion weight
+//Bit 31:24 reg_iplogo_edgedir4_corr_weight_5x5_3_3 // unsigned , RW, default = 11 dir4 corr form logo gaussian weight
+//Bit 23:16 reg_iplogo_edgedir4_corr_weight_5x5_2_3 // unsigned , RW, default = 12 dir4 corr form logo gaussian weight
+//Bit 15: 8 reg_iplogo_edgedir4_corr_weight_5x5_1_3 // unsigned , RW, default = 11 dir4 corr form logo gaussian weight
+//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_0_3 // unsigned , RW, default = 9 dir4 corr form logo gaussian weight
#define FRC_IPLOGO_CORR_FORM_UB_GWEIGHT_4 ((0x050f << 2) + 0xff050000)
//Bit 31: 8 reserved
-//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_4_4 // unsigned , RW, default = 7 dir4 corr form logo gaussion weight
+//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_4_4 // unsigned , RW, default = 7 dir4 corr form logo gaussian weight
#define FRC_IPLOGO_CORR_FORM_LB_GWEIGHT_4 ((0x0510 << 2) + 0xff050000)
-//Bit 31:24 reg_iplogo_edgedir4_corr_weight_5x5_3_4 // unsigned , RW, default = 9 dir4 corr form logo gaussion weight
-//Bit 23:16 reg_iplogo_edgedir4_corr_weight_5x5_2_4 // unsigned , RW, default = 10 dir4 corr form logo gaussion weight
-//Bit 15: 8 reg_iplogo_edgedir4_corr_weight_5x5_1_4 // unsigned , RW, default = 9 dir4 corr form logo gaussion weight
-//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_0_4 // unsigned , RW, default = 7 dir4 corr form logo gaussion weight
+//Bit 31:24 reg_iplogo_edgedir4_corr_weight_5x5_3_4 // unsigned , RW, default = 9 dir4 corr form logo gaussian weight
+//Bit 23:16 reg_iplogo_edgedir4_corr_weight_5x5_2_4 // unsigned , RW, default = 10 dir4 corr form logo gaussian weight
+//Bit 15: 8 reg_iplogo_edgedir4_corr_weight_5x5_1_4 // unsigned , RW, default = 9 dir4 corr form logo gaussian weight
+//Bit 7: 0 reg_iplogo_edgedir4_corr_weight_5x5_0_4 // unsigned , RW, default = 7 dir4 corr form logo gaussian weight
#define FRC_IPLOGO_SCC_GRAY_TH_0 ((0x0511 << 2) + 0xff050000)
//Bit 31:22 reserved
//Bit 21:16 reg_iplogo_scc_dif_th_0 // unsigned , RW, default = 20 scc gray dif rough threshold
@@ -44779,9 +44779,9 @@
#define FRC_IPLOGO_HW_GCLK_CTRL ((0x05e1 << 2) + 0xff050000)
//Bit 31:26 reserved
//Bit 25:6 reg_gclk_ctrl // unsigned , RW, default = 0 reg_gclk_ctrl
-//Bit 5:4 reg_scc_det_gclk_ctrl // unsigned , RW, default = 0 reg_scc_det_gclk_ctrl 0b00:gatting 0b1x:free run clock
-//Bit 3:2 reg_blk_clr_gclk_ctrl // unsigned , RW, default = 0 reg_blk_clr_gclk_ctrl 0b00:gatting 0b1x:free run clock
-//Bit 1:0 reg_pix_logo_gclk_ctrl // unsigned , RW, default = 0 reg_pix_logo_gclk_ctrl 0b00:gatting 0b1x:free run clock
+//Bit 5:4 reg_scc_det_gclk_ctrl // unsigned , RW, default = 0 reg_scc_det_gclk_ctrl 0b00:gating 0b1x:free run clock
+//Bit 3:2 reg_blk_clr_gclk_ctrl // unsigned , RW, default = 0 reg_blk_clr_gclk_ctrl 0b00:gating 0b1x:free run clock
+//Bit 1:0 reg_pix_logo_gclk_ctrl // unsigned , RW, default = 0 reg_pix_logo_gclk_ctrl 0b00:gating 0b1x:free run clock
#define FRC_IPLOGO_HW_FORCE_CTRL ((0x05e2 << 2) + 0xff050000)
//Bit 31:3 reserved
//Bit 2 reg_force_dila_logo_en // unsigned , RW, default = 0 reg_force_dila_logo_en force output of dila
@@ -45627,7 +45627,7 @@
//Bit 21:16 reg_tnr_alpha_min_0 // unsigned , RW, default = 8 down limit to alpah of luma and chroma
//Bit 15:10 reg_tnr_alpha_max_0 // unsigned , RW, default = 63
//Bit 9: 8 reg_tnr_deghost_mode_0 // unsigned , RW, default = 1 window mode for deghost window: 0: 1x3; 1: 3x3; 2:5x5; 3: 7x7
-//Bit 7: 0 reg_tnr_deghost_os_0 // unsigned , RW, default = 20 deghost overshoot marging
+//Bit 7: 0 reg_tnr_deghost_os_0 // unsigned , RW, default = 20 deghost overshoot margins
#define FRC_NR_SNR_1_0 ((0x0807 << 2) + 0xff050000)
//Bit 31:28 reg_snr_err_hgain_0 // unsigned , RW, default = 1 (1+x/8) to the ssim0
//Bit 27:24 reg_snr_err_vgain_0 // unsigned , RW, default = 1 (1+x/8) to the ssim2
@@ -45691,7 +45691,7 @@
//Bit 21:16 reg_tnr_alpha_min_1 // unsigned , RW, default = 8 down limit to alpah of luma and chroma
//Bit 15:10 reg_tnr_alpha_max_1 // unsigned , RW, default = 63
//Bit 9: 8 reg_tnr_deghost_mode_1 // unsigned , RW, default = 1 window mode for deghost window: 0: 1x3; 1: 3x3; 2:5x5; 3: 7x7
-//Bit 7: 0 reg_tnr_deghost_os_1 // unsigned , RW, default = 20 deghost overshoot marging
+//Bit 7: 0 reg_tnr_deghost_os_1 // unsigned , RW, default = 20 deghost overshoot margins
#define FRC_NR_SNR_1_1 ((0x080f << 2) + 0xff050000)
//Bit 31:28 reg_snr_err_hgain_1 // unsigned , RW, default = 1 (1+x/8) to the ssim0
//Bit 27:24 reg_snr_err_vgain_1 // unsigned , RW, default = 1 (1+x/8) to the ssim2
@@ -45806,9 +45806,9 @@
#define CLOSS_FRAME_HOLD_NUMS 0x1 //
//Bit 31: 0 reg_frame_hold_nums // unsigned , RW, default = 0 frame_hold_nums
#define CLOSS_GCLK_CTRL0 0x2 //
-//Bit 31: 0 reg_gclk_ctrl_0 // unsigned , RW, default = 0 resevsed for gated-clock control0
+//Bit 31: 0 reg_gclk_ctrl_0 // unsigned , RW, default = 0 reserved for gated-clock control0
#define CLOSS_GCLK_CTRL1 0x3 //
-//Bit 31: 0 reg_gclk_ctrl_1 // unsigned , RW, default = 0 resevsed for gated-clock control1
+//Bit 31: 0 reg_gclk_ctrl_1 // unsigned , RW, default = 0 reserved for gated-clock control1
#define CLOSS_PIC_SIZE 0x4 //
//Bit 31:16 reg_pic_ysize // unsigned , RW, default = 512 picture vertical size
//Bit 15: 0 reg_pic_xsize // unsigned , RW, default = 1024 picture horizontal size
@@ -46439,7 +46439,7 @@
//Bit 16 reg_me_rpdb_en_fs // unsigned , RW, default = 1 1: enable fs candidate even if fs_en_flag = 1
//Bit 15 reg_me_rpd0_en_fs // unsigned , RW, default = 0 1: enable fs candidate if rpd_flg = 0
//Bit 14 reg_me_rpd1_en_fs // unsigned , RW, default = 0 1: enable fs candidate even if rpd_flg = 1
-//Bit 13:12 reg_me_phs_rp_flg_mode // unsigned , RW, default = 0 selction mode of phase loop rp flg , 0: none, 1: p and c 2:p or c
+//Bit 13:12 reg_me_phs_rp_flg_mode // unsigned , RW, default = 0 selection mode of phase loop rp flg , 0: none, 1: p and c 2:p or c
//Bit 11 reg_me_rpd_penalty_gmv_en // unsigned , RW, default = 1 1: enable special penalty for gmv at rpd==1 case.
//Bit 10 reg_me_rpd_penalty_st_en // unsigned , RW, default = 1 1: enable special penalty for S and T at rpd==1 case.
//Bit 9 reg_me_fs2vp_sel_0 // unsigned , RW, default = 0 fs_ball signal to vp. 0: use bv flag. 1: use current block flag.
@@ -46586,14 +46586,14 @@
//Bit 18 reg_me_rpd_flg_refine_con_3 // unsigned , RW, default = 0 rpd refine process option
//Bit 17 reg_me_rpd_flg_refine_con_4 // unsigned , RW, default = 0 rpd refine process option
//Bit 16 reg_me_rpd_flg_refine_con_5 // unsigned , RW, default = 0 rpd refine process option
-//Bit 15 reg_me_rpd_flg_dialate_en // unsigned , RW, default = 1 enable repeated pattern flag dialation
+//Bit 15 reg_me_rpd_flg_dialate_en // unsigned , RW, default = 1 enable repeated pattern flag dilation
//Bit 14: 8 reg_me_fs_lwidth_col_chk_max_th // unsigned , RW, default = 8 for type_summary_fs_detect, lwidth_chk comparison threshold. ME_FS_RNG_Y/2;
//Bit 7: 0 reg_me_fs_lwidth_row_chk_max_th // unsigned , RW, default = 10 for type_summary_fs_detect, lwidth_chk comparison threshold. ME_FS_RNG_X/2;
#define FRC_ME_RPD_FS_POST ((0x1128 << 2) + 0xff050000)
//Bit 31:28 reg_me_fs_pit_max_blend_coef // unsigned , RW, default = 0 blend coefficient of pit and max_sad
//Bit 27:24 reg_me_fs_low_sad_th_gain // unsigned , RW, default = 8 gain to low_sad_th
//Bit 23:20 reg_me_fs_ero_cnt_th // unsigned , RW, default = 1 threshold of erosion to fs_en_fine_flag
-//Bit 19:16 reg_me_fs_dil_cnt_th // unsigned , RW, default = 3 threshold of dialtion to fs_en_fine_flag
+//Bit 19:16 reg_me_fs_dil_cnt_th // unsigned , RW, default = 3 threshold of dilation to fs_en_fine_flag
//Bit 15:12 reg_me_fs_refine_ball_cnt_th // unsigned , RW, default = 1 threshold of ball cnt to refine fs_en_raw_flag
//Bit 11 reg_me_fs_refine_en // unsigned , RW, default = 0 enable signal for refine to fs_en_raw_flag
//Bit 10 reg_me_fs_ero_en // unsigned , RW, default = 0 enable signal for erosion to fs_en_fine_flag
@@ -46624,24 +46624,24 @@
//Bit 7: 0 reg_me_rpd_min_peak_th // unsigned , RW, default = 0 min peak threshold for repeated pattern search
#define FRC_ME_RPD_T1_FLAT ((0x112c << 2) + 0xff050000)
//Bit 31:28 reserved
-//Bit 27:16 reg_me_rpd_t1_flat_th0 // unsigned , RW, default = 256 flat threshold0 cleanig false type one detection for repeated pattern search
-//Bit 15: 8 reg_me_rpd_t1_flat_th1 // unsigned , RW, default = 6 flat threshold1 cleanig false type one detection for repeated pattern search
+//Bit 27:16 reg_me_rpd_t1_flat_th0 // unsigned , RW, default = 256 flat threshold0 cleaning false type one detection for repeated pattern search
+//Bit 15: 8 reg_me_rpd_t1_flat_th1 // unsigned , RW, default = 6 flat threshold1 cleaning false type one detection for repeated pattern search
//Bit 7: 0 reg_me_rpd_t1_th // unsigned , RW, default = 64 type one rp threshold for repeated pattern search
#define FRC_ME_RPD_T2_LHL ((0x112d << 2) + 0xff050000)
//Bit 31:24 reg_me_rpd_t2_lhl_th // unsigned , RW, default = 12 type two lhl threshold for repeated pattern search
//Bit 23:16 reg_me_rpd_t2_lhlhl_th // unsigned , RW, default = 4 type two lhlhl threshold for repeated pattern search
//Bit 15: 8 reserved
-//Bit 7: 0 reg_me_rpd_t2_flat_th3 // unsigned , RW, default = 8 flat threshold3 cleanig false type two detection for repeated pattern search
+//Bit 7: 0 reg_me_rpd_t2_flat_th3 // unsigned , RW, default = 8 flat threshold3 cleaning false type two detection for repeated pattern search
#define FRC_ME_RPD_T2_FLAT ((0x112e << 2) + 0xff050000)
-//Bit 31:20 reg_me_rpd_t2_flat_th0 // unsigned , RW, default = 256 flat threshold0 cleanig false type two detection for repeated pattern search
-//Bit 19:12 reg_me_rpd_t2_flat_th1 // unsigned , RW, default = 6 flat threshold1 cleanig false type two detection for repeated pattern search
-//Bit 11: 0 reg_me_rpd_t2_flat_th2 // unsigned , RW, default = 128 flat threshold2 cleanig false type two detection for repeated pattern search
+//Bit 31:20 reg_me_rpd_t2_flat_th0 // unsigned , RW, default = 256 flat threshold0 cleaning false type two detection for repeated pattern search
+//Bit 19:12 reg_me_rpd_t2_flat_th1 // unsigned , RW, default = 6 flat threshold1 cleaning false type two detection for repeated pattern search
+//Bit 11: 0 reg_me_rpd_t2_flat_th2 // unsigned , RW, default = 128 flat threshold2 cleaning false type two detection for repeated pattern search
#define FRC_ME_RPD_T3_FLAT ((0x112f << 2) + 0xff050000)
//Bit 31:30 reserved
//Bit 29:24 reg_me_rpd_t3_th // unsigned , RW, default = 2 type three threshold for repeated pattern search, 8 is normalized as 1
-//Bit 23:16 reg_me_rpd_t3_flat_th1 // unsigned , RW, default = 6 flat threshold1 cleanig false type three detection for repeated pattern search
+//Bit 23:16 reg_me_rpd_t3_flat_th1 // unsigned , RW, default = 6 flat threshold1 cleaning false type three detection for repeated pattern search
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_rpd_t3_flat_th0 // unsigned , RW, default = 256 flat threshold0 cleanig false type three detection for repeated pattern search
+//Bit 11: 0 reg_me_rpd_t3_flat_th0 // unsigned , RW, default = 256 flat threshold0 cleaning false type three detection for repeated pattern search
#define FRC_ME_RPD_AUTO_FLAT ((0x1130 << 2) + 0xff050000)
//Bit 31:28 reserved
//Bit 27:16 reg_me_rpd_auto_flat_th0 // unsigned , RW, default = 256 atuo flat flag threshold0 for repeated pattern search
@@ -47628,7 +47628,7 @@
//Bit 14 reg_me_choosebv_mode_0 // unsigned , RW, default = 0 new mode for phase bv selection
//Bit 13 reg_me_loop_scan0_0 // unsigned , RW, default = 1 enable to run the [0]pre point to cur or cur point to pre, [1]cur point to nex, [2]nex point to cur loop 1st run, 0 do not run, 1 run
//Bit 12 reg_me_loop_scan1_0 // unsigned , RW, default = 1 enable to run the [0]pre point to cur or cur point to pre, [1]cur point to nex, [2]nex point to cur loop 2nd run, 0 do not run, 1 run
-//Bit 11 reg_me_ovrwrite_bv_en_0 // unsigned , RW, default = 0 enable to overwrite the mv with reg_me_ovrwrite_vector, 0: no overwrite, 1: overwrite
+//Bit 11 reg_me_overwrite_bv_en_0 // unsigned , RW, default = 0 enable to overwrite the mv with reg_me_overwrite_vector, 0: no overwrite, 1: overwrite
//Bit 10: 8 reg_obme_mask_mode_max_0 // unsigned , RW, default = 3 max of obme mask mode selection, 0: 4x8 mask, 1: 8x8 mask; 2:12x8 mask, 3: 16x8 mask
//Bit 7 reserved
//Bit 6: 4 reg_obme_mask_mode_min_0 // unsigned , RW, default = 0 min of obme mask mode selection, 0: 4x8 mask, 1: 8x8 mask; 2:12x8 mask, 3: 16x8 mask
@@ -47683,7 +47683,7 @@
//Bit 14 reg_me_choosebv_mode_1 // unsigned , RW, default = 0 new mode for phase bv selection
//Bit 13 reg_me_loop_scan0_1 // unsigned , RW, default = 1 enable to run the [0]pre point to cur or cur point to pre, [1]cur point to nex, [2]nex point to cur loop 1st run, 0 do not run, 1 run
//Bit 12 reg_me_loop_scan1_1 // unsigned , RW, default = 1 enable to run the [0]pre point to cur or cur point to pre, [1]cur point to nex, [2]nex point to cur loop 2nd run, 0 do not run, 1 run
-//Bit 11 reg_me_ovrwrite_bv_en_1 // unsigned , RW, default = 0 enable to overwrite the mv with reg_me_ovrwrite_vector, 0: no overwrite, 1: overwrite
+//Bit 11 reg_me_overwrite_bv_en_1 // unsigned , RW, default = 0 enable to overwrite the mv with reg_me_overwrite_vector, 0: no overwrite, 1: overwrite
//Bit 10: 8 reg_obme_mask_mode_max_1 // unsigned , RW, default = 3 max of obme mask mode selection, 0: 4x8 mask, 1: 8x8 mask; 2:12x8 mask, 3: 16x8 mask
//Bit 7 reserved
//Bit 6: 4 reg_obme_mask_mode_min_1 // unsigned , RW, default = 0 min of obme mask mode selection, 0: 4x8 mask, 1: 8x8 mask; 2:12x8 mask, 3: 16x8 mask
@@ -47738,7 +47738,7 @@
//Bit 14 reg_me_choosebv_mode_2 // unsigned , RW, default = 0 new mode for phase bv selection
//Bit 13 reg_me_loop_scan0_2 // unsigned , RW, default = 1 enable to run the [0]pre point to cur or cur point to pre, [1]cur point to nex, [2]nex point to cur loop 1st run, 0 do not run, 1 run
//Bit 12 reg_me_loop_scan1_2 // unsigned , RW, default = 1 enable to run the [0]pre point to cur or cur point to pre, [1]cur point to nex, [2]nex point to cur loop 2nd run, 0 do not run, 1 run
-//Bit 11 reg_me_ovrwrite_bv_en_2 // unsigned , RW, default = 0 enable to overwrite the mv with reg_me_ovrwrite_vector, 0: no overwrite, 1: overwrite
+//Bit 11 reg_me_overwrite_bv_en_2 // unsigned , RW, default = 0 enable to overwrite the mv with reg_me_overwrite_vector, 0: no overwrite, 1: overwrite
//Bit 10: 8 reg_obme_mask_mode_max_2 // unsigned , RW, default = 3 max of obme mask mode selection, 0: 4x8 mask, 1: 8x8 mask; 2:12x8 mask, 3: 16x8 mask
//Bit 7 reserved
//Bit 6: 4 reg_obme_mask_mode_min_2 // unsigned , RW, default = 0 min of obme mask mode selection, 0: 4x8 mask, 1: 8x8 mask; 2:12x8 mask, 3: 16x8 mask
@@ -47895,7 +47895,7 @@
//Bit 19:18 reg_me_bv_e2e_sad_upd_en // unsigned , RW, default = 0 set to 1, enable updating bv01 e2e based sad for phase loop
//Bit 17 reg_me_bv_e2e_sad_chk_en // unsigned , RW, default = 0 copy bv0 to bv1 after swap them by reg_me_bv_e2e_sad_upd_en.
//Bit 16 reg_me_bv_e2e_mv_chk_en // unsigned , RW, default = 0 set to 0, bypass e2e MV check.
-//Bit 15: 8 reg_me_bv_diff_th // unsigned , RW, default = 16 threshold of mvdiff if bvs are differenent
+//Bit 15: 8 reg_me_bv_diff_th // unsigned , RW, default = 16 threshold of mvdiff if bvs are different
//Bit 7: 0 reg_me_bv_sad_ratio // unsigned , RW, default = 20 apl ration for bvs sad, 8% of apl. set this ratio to 0 and reg_me_p2p_bypass_con*=0 will bypass e2e MV check.
#define FRC_ME_E2E_CHK_TH ((0x1525 << 2) + 0xff050000)
//Bit 31:24 reg_me_bv_p2p_diff_th // unsigned , RW, default = 16 mv diff threshold for bvs p2p check
@@ -47972,7 +47972,7 @@
//Bit 31:18 reserved
//Bit 17:16 reg_me_periodic0_gmv_sel // unsigned , RW, default = 1 gmv selection for periodic0, 0: global gmv, 1: finer gmv, 2: region_gmv, 3: force gmv;
//Bit 15:10 reserved
-//Bit 9: 0 reg_me_periodic0_gmv_dtl_th // unsigned , RW, default = 0 gmv detail thresold for periodic0
+//Bit 9: 0 reg_me_periodic0_gmv_dtl_th // unsigned , RW, default = 0 gmv detail threshold for periodic0
#define FRC_ME_P0_REGION_EN ((0x1530 << 2) + 0xff050000)
//Bit 31 reg_me_region_gmv_like_en // unsigned , RW, default = 0 region gmv like enable
//Bit 30:28 reserved
@@ -48169,14 +48169,14 @@
//Bit 12: 0 reg_me_lmt_vbuf_sad_diff_th // unsigned , RW, default = 2560 sad diff threshold for v-buffer clean in limit proc.
#define FRC_ME_GMV ((0x1548 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_gmv_vector_0 // signed , RW, default = 0 global mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_gmv_vector_0 // signed , RW, default = 0 global mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15 reg_me_gmv_invalid // unsigned , RW, default = 1 when 1, gmv is invalid.
//Bit 14 reg_me_gmv_mux_sel // unsigned , RW, default = 0 1: use HW gmv(ro_me_gmv, ro_me_gmv_invalid); 0: use firmware gmv(reg_me_gmv, reg_me_gmv_invalid).
//Bit 13:12 reserved
//Bit 11: 0 reg_me_gmv_vector_1 // signed , RW, default = 0
#define FRC_ME_GMV_2ND ((0x1549 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_gmv_2nd_vector_0 // signed , RW, default = 0 global mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_gmv_2nd_vector_0 // signed , RW, default = 0 global mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
//Bit 11: 0 reg_me_gmv_2nd_vector_1 // signed , RW, default = 0
#define FRC_ME_GMV_PATCH ((0x154a << 2) + 0xff050000)
@@ -48232,124 +48232,124 @@
//Bit 11: 0 reg_me_pg_col_delta_mv_2_vector_1 // signed , RW, default = 0 me pattern generation delta mvy for col
#define FRC_ME_STAT_GMV_RGN_0 ((0x1554 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_0_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_0_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_0_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_0_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_2ND_0 ((0x1555 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_2nd_0_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_2nd_0_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_2nd_0_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_2nd_0_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_1 ((0x1556 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_1_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_1_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_1_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_1_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_2ND_1 ((0x1557 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_2nd_1_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_2nd_1_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_2nd_1_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_2nd_1_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_2 ((0x1558 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_2_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_2_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_2_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_2_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_2ND_2 ((0x1559 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_2nd_2_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_2nd_2_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_2nd_2_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_2nd_2_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_3 ((0x155a << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_3_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_3_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_3_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_3_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_2ND_3 ((0x155b << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_2nd_3_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_2nd_3_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_2nd_3_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_2nd_3_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_4 ((0x155c << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_4_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_4_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_4_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_4_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_2ND_4 ((0x155d << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_2nd_4_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_2nd_4_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_2nd_4_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_2nd_4_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_5 ((0x155e << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_5_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_5_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_5_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_5_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_2ND_5 ((0x155f << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_2nd_5_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_2nd_5_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_2nd_5_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_2nd_5_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_6 ((0x1560 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_6_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_6_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_6_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_6_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_2ND_6 ((0x1561 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_2nd_6_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_2nd_6_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_2nd_6_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_2nd_6_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_7 ((0x1562 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_7_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_7_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_7_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_7_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_2ND_7 ((0x1563 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_2nd_7_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_2nd_7_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_2nd_7_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_2nd_7_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_8 ((0x1564 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_8_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_8_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_8_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_8_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_2ND_8 ((0x1565 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_2nd_8_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_2nd_8_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_2nd_8_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_2nd_8_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_9 ((0x1566 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_9_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_9_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_9_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_9_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_2ND_9 ((0x1567 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_2nd_9_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_2nd_9_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_2nd_9_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_2nd_9_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_10 ((0x1568 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_10_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_10_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_10_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_10_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_2ND_10 ((0x1569 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_2nd_10_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_2nd_10_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_2nd_10_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_2nd_10_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_11 ((0x156a << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_11_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_11_vector_0 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_11_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_11_vector_1 // signed , RW, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GMV_RGN_2ND_11 ((0x156b << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_me_region_gmv_2nd_11_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_me_region_gmv_2nd_11_vector_0 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 reg_me_region_gmv_2nd_11_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 reg_me_region_gmv_2nd_11_vector_1 // signed , RW, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_STAT_GLB_APL ((0x156c << 2) + 0xff050000)
//Bit 31:24 reg_me_glb_apl_0 // unsigned , RW, default = 0 global apl for each loop
//Bit 23:16 reg_me_glb_apl_1 // unsigned , RW, default = 0 global apl for each loop
@@ -48703,9 +48703,9 @@
//Bit 9: 0 reg_me_region_dtl_coring_th // unsigned , RW, default = 50 detail coring threshold for regional statistic
#define FRC_ME_STAT_RGN_GOOD ((0x172b << 2) + 0xff050000)
//Bit 31:26 reserved
-//Bit 25:16 reg_me_region_good_match_t_consis_th // unsigned , RW, default = 3 good match mv temporal consistance threshold for regional statistic
+//Bit 25:16 reg_me_region_good_match_t_consis_th // unsigned , RW, default = 3 good match mv temporal consistence threshold for regional statistic
//Bit 15:10 reserved
-//Bit 9: 0 reg_me_region_good_match_s_consis_th // unsigned , RW, default = 3 good match mv spatial consistance threshold for regional statistic
+//Bit 9: 0 reg_me_region_good_match_s_consis_th // unsigned , RW, default = 3 good match mv spatial consistence threshold for regional statistic
// synopsys translate_off
// synopsys translate_on
//
@@ -48720,9 +48720,9 @@
// synopsys translate_off
// synopsys translate_on
#define FRC_ME_RO_RGN_T_CONSIS_0 ((0x1800 << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_t_consis_0 // unsigned , RO, default = 0 12 region temporal cnosistences for phase loop
+//Bit 31: 0 ro_me_region_t_consis_0 // unsigned , RO, default = 0 12 region temporal consistency for phase loop
#define FRC_ME_RO_RGN_S_CONSIS_0 ((0x1801 << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_s_consis_0 // unsigned , RO, default = 0 12 region spatial cnosistences for phase loop
+//Bit 31: 0 ro_me_region_s_consis_0 // unsigned , RO, default = 0 12 region spatial consistency for phase loop
#define FRC_ME_RO_RGN_DTL_SUM_0 ((0x1802 << 2) + 0xff050000)
//Bit 31 reserved
//Bit 30: 0 ro_me_region_dtl_sum_0 // unsigned , RO, default = 0 12 region high detail sum for phase loop
@@ -48745,9 +48745,9 @@
//Bit 31 reserved
//Bit 30: 0 ro_me_region_apl_sum_0 // unsigned , RO, default = 0 12 region apl sum for phase loop
#define FRC_ME_RO_RGN_T_CONSIS_1 ((0x1809 << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_t_consis_1 // unsigned , RO, default = 0 12 region temporal cnosistences for phase loop
+//Bit 31: 0 ro_me_region_t_consis_1 // unsigned , RO, default = 0 12 region temporal consistency for phase loop
#define FRC_ME_RO_RGN_S_CONSIS_1 ((0x180a << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_s_consis_1 // unsigned , RO, default = 0 12 region spatial cnosistences for phase loop
+//Bit 31: 0 ro_me_region_s_consis_1 // unsigned , RO, default = 0 12 region spatial consistency for phase loop
#define FRC_ME_RO_RGN_DTL_SUM_1 ((0x180b << 2) + 0xff050000)
//Bit 31 reserved
//Bit 30: 0 ro_me_region_dtl_sum_1 // unsigned , RO, default = 0 12 region high detail sum for phase loop
@@ -48770,9 +48770,9 @@
//Bit 31 reserved
//Bit 30: 0 ro_me_region_apl_sum_1 // unsigned , RO, default = 0 12 region apl sum for phase loop
#define FRC_ME_RO_RGN_T_CONSIS_2 ((0x1812 << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_t_consis_2 // unsigned , RO, default = 0 12 region temporal cnosistences for phase loop
+//Bit 31: 0 ro_me_region_t_consis_2 // unsigned , RO, default = 0 12 region temporal consistency for phase loop
#define FRC_ME_RO_RGN_S_CONSIS_2 ((0x1813 << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_s_consis_2 // unsigned , RO, default = 0 12 region spatial cnosistences for phase loop
+//Bit 31: 0 ro_me_region_s_consis_2 // unsigned , RO, default = 0 12 region spatial consistency for phase loop
#define FRC_ME_RO_RGN_DTL_SUM_2 ((0x1814 << 2) + 0xff050000)
//Bit 31 reserved
//Bit 30: 0 ro_me_region_dtl_sum_2 // unsigned , RO, default = 0 12 region high detail sum for phase loop
@@ -48795,9 +48795,9 @@
//Bit 31 reserved
//Bit 30: 0 ro_me_region_apl_sum_2 // unsigned , RO, default = 0 12 region apl sum for phase loop
#define FRC_ME_RO_RGN_T_CONSIS_3 ((0x181b << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_t_consis_3 // unsigned , RO, default = 0 12 region temporal cnosistences for phase loop
+//Bit 31: 0 ro_me_region_t_consis_3 // unsigned , RO, default = 0 12 region temporal consistency for phase loop
#define FRC_ME_RO_RGN_S_CONSIS_3 ((0x181c << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_s_consis_3 // unsigned , RO, default = 0 12 region spatial cnosistences for phase loop
+//Bit 31: 0 ro_me_region_s_consis_3 // unsigned , RO, default = 0 12 region spatial consistency for phase loop
#define FRC_ME_RO_RGN_DTL_SUM_3 ((0x181d << 2) + 0xff050000)
//Bit 31 reserved
//Bit 30: 0 ro_me_region_dtl_sum_3 // unsigned , RO, default = 0 12 region high detail sum for phase loop
@@ -48820,9 +48820,9 @@
//Bit 31 reserved
//Bit 30: 0 ro_me_region_apl_sum_3 // unsigned , RO, default = 0 12 region apl sum for phase loop
#define FRC_ME_RO_RGN_T_CONSIS_4 ((0x1824 << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_t_consis_4 // unsigned , RO, default = 0 12 region temporal cnosistences for phase loop
+//Bit 31: 0 ro_me_region_t_consis_4 // unsigned , RO, default = 0 12 region temporal consistency for phase loop
#define FRC_ME_RO_RGN_S_CONSIS_4 ((0x1825 << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_s_consis_4 // unsigned , RO, default = 0 12 region spatial cnosistences for phase loop
+//Bit 31: 0 ro_me_region_s_consis_4 // unsigned , RO, default = 0 12 region spatial consistency for phase loop
#define FRC_ME_RO_RGN_DTL_SUM_4 ((0x1826 << 2) + 0xff050000)
//Bit 31 reserved
//Bit 30: 0 ro_me_region_dtl_sum_4 // unsigned , RO, default = 0 12 region high detail sum for phase loop
@@ -48845,9 +48845,9 @@
//Bit 31 reserved
//Bit 30: 0 ro_me_region_apl_sum_4 // unsigned , RO, default = 0 12 region apl sum for phase loop
#define FRC_ME_RO_RGN_T_CONSIS_5 ((0x182d << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_t_consis_5 // unsigned , RO, default = 0 12 region temporal cnosistences for phase loop
+//Bit 31: 0 ro_me_region_t_consis_5 // unsigned , RO, default = 0 12 region temporal consistency for phase loop
#define FRC_ME_RO_RGN_S_CONSIS_5 ((0x182e << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_s_consis_5 // unsigned , RO, default = 0 12 region spatial cnosistences for phase loop
+//Bit 31: 0 ro_me_region_s_consis_5 // unsigned , RO, default = 0 12 region spatial consistency for phase loop
#define FRC_ME_RO_RGN_DTL_SUM_5 ((0x182f << 2) + 0xff050000)
//Bit 31 reserved
//Bit 30: 0 ro_me_region_dtl_sum_5 // unsigned , RO, default = 0 12 region high detail sum for phase loop
@@ -48870,9 +48870,9 @@
//Bit 31 reserved
//Bit 30: 0 ro_me_region_apl_sum_5 // unsigned , RO, default = 0 12 region apl sum for phase loop
#define FRC_ME_RO_RGN_T_CONSIS_6 ((0x1836 << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_t_consis_6 // unsigned , RO, default = 0 12 region temporal cnosistences for phase loop
+//Bit 31: 0 ro_me_region_t_consis_6 // unsigned , RO, default = 0 12 region temporal consistency for phase loop
#define FRC_ME_RO_RGN_S_CONSIS_6 ((0x1837 << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_s_consis_6 // unsigned , RO, default = 0 12 region spatial cnosistences for phase loop
+//Bit 31: 0 ro_me_region_s_consis_6 // unsigned , RO, default = 0 12 region spatial consistency for phase loop
#define FRC_ME_RO_RGN_DTL_SUM_6 ((0x1838 << 2) + 0xff050000)
//Bit 31 reserved
//Bit 30: 0 ro_me_region_dtl_sum_6 // unsigned , RO, default = 0 12 region high detail sum for phase loop
@@ -48895,9 +48895,9 @@
//Bit 31 reserved
//Bit 30: 0 ro_me_region_apl_sum_6 // unsigned , RO, default = 0 12 region apl sum for phase loop
#define FRC_ME_RO_RGN_T_CONSIS_7 ((0x183f << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_t_consis_7 // unsigned , RO, default = 0 12 region temporal cnosistences for phase loop
+//Bit 31: 0 ro_me_region_t_consis_7 // unsigned , RO, default = 0 12 region temporal consistency for phase loop
#define FRC_ME_RO_RGN_S_CONSIS_7 ((0x1840 << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_s_consis_7 // unsigned , RO, default = 0 12 region spatial cnosistences for phase loop
+//Bit 31: 0 ro_me_region_s_consis_7 // unsigned , RO, default = 0 12 region spatial consistency for phase loop
#define FRC_ME_RO_RGN_DTL_SUM_7 ((0x1841 << 2) + 0xff050000)
//Bit 31 reserved
//Bit 30: 0 ro_me_region_dtl_sum_7 // unsigned , RO, default = 0 12 region high detail sum for phase loop
@@ -48920,9 +48920,9 @@
//Bit 31 reserved
//Bit 30: 0 ro_me_region_apl_sum_7 // unsigned , RO, default = 0 12 region apl sum for phase loop
#define FRC_ME_RO_RGN_T_CONSIS_8 ((0x1848 << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_t_consis_8 // unsigned , RO, default = 0 12 region temporal cnosistences for phase loop
+//Bit 31: 0 ro_me_region_t_consis_8 // unsigned , RO, default = 0 12 region temporal consistency for phase loop
#define FRC_ME_RO_RGN_S_CONSIS_8 ((0x1849 << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_s_consis_8 // unsigned , RO, default = 0 12 region spatial cnosistences for phase loop
+//Bit 31: 0 ro_me_region_s_consis_8 // unsigned , RO, default = 0 12 region spatial consistency for phase loop
#define FRC_ME_RO_RGN_DTL_SUM_8 ((0x184a << 2) + 0xff050000)
//Bit 31 reserved
//Bit 30: 0 ro_me_region_dtl_sum_8 // unsigned , RO, default = 0 12 region high detail sum for phase loop
@@ -48945,9 +48945,9 @@
//Bit 31 reserved
//Bit 30: 0 ro_me_region_apl_sum_8 // unsigned , RO, default = 0 12 region apl sum for phase loop
#define FRC_ME_RO_RGN_T_CONSIS_9 ((0x1851 << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_t_consis_9 // unsigned , RO, default = 0 12 region temporal cnosistences for phase loop
+//Bit 31: 0 ro_me_region_t_consis_9 // unsigned , RO, default = 0 12 region temporal consistency for phase loop
#define FRC_ME_RO_RGN_S_CONSIS_9 ((0x1852 << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_s_consis_9 // unsigned , RO, default = 0 12 region spatial cnosistences for phase loop
+//Bit 31: 0 ro_me_region_s_consis_9 // unsigned , RO, default = 0 12 region spatial consistency for phase loop
#define FRC_ME_RO_RGN_DTL_SUM_9 ((0x1853 << 2) + 0xff050000)
//Bit 31 reserved
//Bit 30: 0 ro_me_region_dtl_sum_9 // unsigned , RO, default = 0 12 region high detail sum for phase loop
@@ -48970,9 +48970,9 @@
//Bit 31 reserved
//Bit 30: 0 ro_me_region_apl_sum_9 // unsigned , RO, default = 0 12 region apl sum for phase loop
#define FRC_ME_RO_RGN_T_CONSIS_10 ((0x185a << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_t_consis_10 // unsigned , RO, default = 0 12 region temporal cnosistences for phase loop
+//Bit 31: 0 ro_me_region_t_consis_10 // unsigned , RO, default = 0 12 region temporal consistency for phase loop
#define FRC_ME_RO_RGN_S_CONSIS_10 ((0x185b << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_s_consis_10 // unsigned , RO, default = 0 12 region spatial cnosistences for phase loop
+//Bit 31: 0 ro_me_region_s_consis_10 // unsigned , RO, default = 0 12 region spatial consistency for phase loop
#define FRC_ME_RO_RGN_DTL_SUM_10 ((0x185c << 2) + 0xff050000)
//Bit 31 reserved
//Bit 30: 0 ro_me_region_dtl_sum_10 // unsigned , RO, default = 0 12 region high detail sum for phase loop
@@ -48995,9 +48995,9 @@
//Bit 31 reserved
//Bit 30: 0 ro_me_region_apl_sum_10 // unsigned , RO, default = 0 12 region apl sum for phase loop
#define FRC_ME_RO_RGN_T_CONSIS_11 ((0x1863 << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_t_consis_11 // unsigned , RO, default = 0 12 region temporal cnosistences for phase loop
+//Bit 31: 0 ro_me_region_t_consis_11 // unsigned , RO, default = 0 12 region temporal consistency for phase loop
#define FRC_ME_RO_RGN_S_CONSIS_11 ((0x1864 << 2) + 0xff050000)
-//Bit 31: 0 ro_me_region_s_consis_11 // unsigned , RO, default = 0 12 region spatial cnosistences for phase loop
+//Bit 31: 0 ro_me_region_s_consis_11 // unsigned , RO, default = 0 12 region spatial consistency for phase loop
#define FRC_ME_RO_RGN_DTL_SUM_11 ((0x1865 << 2) + 0xff050000)
//Bit 31 reserved
//Bit 30: 0 ro_me_region_dtl_sum_11 // unsigned , RO, default = 0 12 region high detail sum for phase loop
@@ -49020,9 +49020,9 @@
//Bit 31 reserved
//Bit 30: 0 ro_me_region_apl_sum_11 // unsigned , RO, default = 0 12 region apl sum for phase loop
#define FRC_ME_RO_S_CONSIS_0 ((0x186c << 2) + 0xff050000)
-//Bit 31: 0 ro_me_glb_s_consis_0 // unsigned , RO, default = 0 global spatial cnosistences in each loop
+//Bit 31: 0 ro_me_glb_s_consis_0 // unsigned , RO, default = 0 global spatial consistency in each loop
#define FRC_ME_RO_T_CONSIS_0 ((0x186d << 2) + 0xff050000)
-//Bit 31: 0 ro_me_glb_t_consis_0 // unsigned , RO, default = 0 global temporal cnosistences in each loop
+//Bit 31: 0 ro_me_glb_t_consis_0 // unsigned , RO, default = 0 global temporal consistency in each loop
#define FRC_ME_RO_APL_0 ((0x186e << 2) + 0xff050000)
//Bit 31:24 reserved
//Bit 23: 0 ro_me_glb_apl_sum_0 // unsigned , RO, default = 0 global apl for each loop
@@ -49041,9 +49041,9 @@
#define FRC_ME_RO_FCMV_CNT_0 ((0x1874 << 2) + 0xff050000)
//Bit 31: 0 ro_me_fin_cmv_cnt_0 // unsigned , RO, default = 0 fine/final cmv count
#define FRC_ME_RO_S_CONSIS_1 ((0x1875 << 2) + 0xff050000)
-//Bit 31: 0 ro_me_glb_s_consis_1 // unsigned , RO, default = 0 global spatial cnosistences in each loop
+//Bit 31: 0 ro_me_glb_s_consis_1 // unsigned , RO, default = 0 global spatial consistency in each loop
#define FRC_ME_RO_T_CONSIS_1 ((0x1876 << 2) + 0xff050000)
-//Bit 31: 0 ro_me_glb_t_consis_1 // unsigned , RO, default = 0 global temporal cnosistences in each loop
+//Bit 31: 0 ro_me_glb_t_consis_1 // unsigned , RO, default = 0 global temporal consistency in each loop
#define FRC_ME_RO_APL_1 ((0x1877 << 2) + 0xff050000)
//Bit 31:24 reserved
//Bit 23: 0 ro_me_glb_apl_sum_1 // unsigned , RO, default = 0 global apl for each loop
@@ -49062,9 +49062,9 @@
#define FRC_ME_RO_FCMV_CNT_1 ((0x187d << 2) + 0xff050000)
//Bit 31: 0 ro_me_fin_cmv_cnt_1 // unsigned , RO, default = 0 fine/final cmv count
#define FRC_ME_RO_S_CONSIS_2 ((0x187e << 2) + 0xff050000)
-//Bit 31: 0 ro_me_glb_s_consis_2 // unsigned , RO, default = 0 global spatial cnosistences in each loop
+//Bit 31: 0 ro_me_glb_s_consis_2 // unsigned , RO, default = 0 global spatial consistency in each loop
#define FRC_ME_RO_T_CONSIS_2 ((0x187f << 2) + 0xff050000)
-//Bit 31: 0 ro_me_glb_t_consis_2 // unsigned , RO, default = 0 global temporal cnosistences in each loop
+//Bit 31: 0 ro_me_glb_t_consis_2 // unsigned , RO, default = 0 global temporal consistency in each loop
#define FRC_ME_RO_APL_2 ((0x1880 << 2) + 0xff050000)
//Bit 31:24 reserved
//Bit 23: 0 ro_me_glb_apl_sum_2 // unsigned , RO, default = 0 global apl for each loop
@@ -49087,7 +49087,7 @@
//Bit 17: 0 ro_me_glb_unstable_cnt // unsigned , RO, default = 0 global unstable count
#define FRC_ME_RO_GMV_ROUGH ((0x1888 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_gmv_rough_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_gmv_rough_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:13 reserved
//Bit 12 ro_me_gmv_rough_invalid // unsigned , RO, default = 1 when 1, gmv is invalid.
//Bit 11: 0 ro_me_gmv_rough_vector_1 // signed , RO, default = 0
@@ -49134,13 +49134,13 @@
//Bit 17: 0 ro_me_gmv_rough_cnt_3x3_8 // unsigned , RO, default = 0
#define FRC_ME_RO_GMV ((0x1896 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_gmv_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_gmv_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:13 reserved
//Bit 12 ro_me_gmv_invalid // unsigned , RO, default = 1 when 1, gmv is invalid.
//Bit 11: 0 ro_me_gmv_vector_1 // signed , RO, default = 0
#define FRC_ME_RO_GMV_MUX ((0x1897 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_gmv_mux_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_gmv_mux_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:13 reserved
//Bit 12 ro_me_gmv_mux_invalid // unsigned , RO, default = 1
//Bit 11: 0 ro_me_gmv_mux_vector_1 // signed , RO, default = 0
@@ -49206,14 +49206,14 @@
// synopsys translate_on
#define FRC_ME_RO_GMV_RGN_0 ((0x1900 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_0_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_0_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_0_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_0_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_RGN_2ND_0 ((0x1901 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_2nd_0_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_2nd_0_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_2nd_0_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_2nd_0_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_ROUGH_RGN_0 ((0x1902 << 2) + 0xff050000)
//Bit 31:29 reserved
//Bit 28:16 ro_me_region_gmv_rough_0_vector_0 // signed , RO, default = 0
@@ -49226,14 +49226,14 @@
//Bit 11: 0 ro_me_region_gmv_rough_2nd_0_vector_1 // signed , RO, default = 0
#define FRC_ME_RO_GMV_RGN_1 ((0x1904 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_1_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_1_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_1_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_1_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_RGN_2ND_1 ((0x1905 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_2nd_1_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_2nd_1_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_2nd_1_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_2nd_1_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_ROUGH_RGN_1 ((0x1906 << 2) + 0xff050000)
//Bit 31:29 reserved
//Bit 28:16 ro_me_region_gmv_rough_1_vector_0 // signed , RO, default = 0
@@ -49246,14 +49246,14 @@
//Bit 11: 0 ro_me_region_gmv_rough_2nd_1_vector_1 // signed , RO, default = 0
#define FRC_ME_RO_GMV_RGN_2 ((0x1908 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_2_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_2_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_2_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_2_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_RGN_2ND_2 ((0x1909 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_2nd_2_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_2nd_2_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_2nd_2_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_2nd_2_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_ROUGH_RGN_2 ((0x190a << 2) + 0xff050000)
//Bit 31:29 reserved
//Bit 28:16 ro_me_region_gmv_rough_2_vector_0 // signed , RO, default = 0
@@ -49266,14 +49266,14 @@
//Bit 11: 0 ro_me_region_gmv_rough_2nd_2_vector_1 // signed , RO, default = 0
#define FRC_ME_RO_GMV_RGN_3 ((0x190c << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_3_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_3_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_3_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_3_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_RGN_2ND_3 ((0x190d << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_2nd_3_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_2nd_3_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_2nd_3_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_2nd_3_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_ROUGH_RGN_3 ((0x190e << 2) + 0xff050000)
//Bit 31:29 reserved
//Bit 28:16 ro_me_region_gmv_rough_3_vector_0 // signed , RO, default = 0
@@ -49286,14 +49286,14 @@
//Bit 11: 0 ro_me_region_gmv_rough_2nd_3_vector_1 // signed , RO, default = 0
#define FRC_ME_RO_GMV_RGN_4 ((0x1910 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_4_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_4_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_4_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_4_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_RGN_2ND_4 ((0x1911 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_2nd_4_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_2nd_4_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_2nd_4_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_2nd_4_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_ROUGH_RGN_4 ((0x1912 << 2) + 0xff050000)
//Bit 31:29 reserved
//Bit 28:16 ro_me_region_gmv_rough_4_vector_0 // signed , RO, default = 0
@@ -49306,14 +49306,14 @@
//Bit 11: 0 ro_me_region_gmv_rough_2nd_4_vector_1 // signed , RO, default = 0
#define FRC_ME_RO_GMV_RGN_5 ((0x1914 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_5_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_5_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_5_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_5_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_RGN_2ND_5 ((0x1915 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_2nd_5_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_2nd_5_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_2nd_5_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_2nd_5_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_ROUGH_RGN_5 ((0x1916 << 2) + 0xff050000)
//Bit 31:29 reserved
//Bit 28:16 ro_me_region_gmv_rough_5_vector_0 // signed , RO, default = 0
@@ -49326,14 +49326,14 @@
//Bit 11: 0 ro_me_region_gmv_rough_2nd_5_vector_1 // signed , RO, default = 0
#define FRC_ME_RO_GMV_RGN_6 ((0x1918 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_6_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_6_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_6_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_6_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_RGN_2ND_6 ((0x1919 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_2nd_6_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_2nd_6_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_2nd_6_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_2nd_6_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_ROUGH_RGN_6 ((0x191a << 2) + 0xff050000)
//Bit 31:29 reserved
//Bit 28:16 ro_me_region_gmv_rough_6_vector_0 // signed , RO, default = 0
@@ -49346,14 +49346,14 @@
//Bit 11: 0 ro_me_region_gmv_rough_2nd_6_vector_1 // signed , RO, default = 0
#define FRC_ME_RO_GMV_RGN_7 ((0x191c << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_7_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_7_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_7_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_7_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_RGN_2ND_7 ((0x191d << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_2nd_7_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_2nd_7_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_2nd_7_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_2nd_7_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_ROUGH_RGN_7 ((0x191e << 2) + 0xff050000)
//Bit 31:29 reserved
//Bit 28:16 ro_me_region_gmv_rough_7_vector_0 // signed , RO, default = 0
@@ -49366,14 +49366,14 @@
//Bit 11: 0 ro_me_region_gmv_rough_2nd_7_vector_1 // signed , RO, default = 0
#define FRC_ME_RO_GMV_RGN_8 ((0x1920 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_8_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_8_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_8_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_8_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_RGN_2ND_8 ((0x1921 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_2nd_8_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_2nd_8_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_2nd_8_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_2nd_8_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_ROUGH_RGN_8 ((0x1922 << 2) + 0xff050000)
//Bit 31:29 reserved
//Bit 28:16 ro_me_region_gmv_rough_8_vector_0 // signed , RO, default = 0
@@ -49386,14 +49386,14 @@
//Bit 11: 0 ro_me_region_gmv_rough_2nd_8_vector_1 // signed , RO, default = 0
#define FRC_ME_RO_GMV_RGN_9 ((0x1924 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_9_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_9_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_9_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_9_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_RGN_2ND_9 ((0x1925 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_2nd_9_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_2nd_9_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_2nd_9_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_2nd_9_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_ROUGH_RGN_9 ((0x1926 << 2) + 0xff050000)
//Bit 31:29 reserved
//Bit 28:16 ro_me_region_gmv_rough_9_vector_0 // signed , RO, default = 0
@@ -49406,14 +49406,14 @@
//Bit 11: 0 ro_me_region_gmv_rough_2nd_9_vector_1 // signed , RO, default = 0
#define FRC_ME_RO_GMV_RGN_10 ((0x1928 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_10_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_10_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_10_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_10_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_RGN_2ND_10 ((0x1929 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_2nd_10_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_2nd_10_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_2nd_10_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_2nd_10_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_ROUGH_RGN_10 ((0x192a << 2) + 0xff050000)
//Bit 31:29 reserved
//Bit 28:16 ro_me_region_gmv_rough_10_vector_0 // signed , RO, default = 0
@@ -49426,14 +49426,14 @@
//Bit 11: 0 ro_me_region_gmv_rough_2nd_10_vector_1 // signed , RO, default = 0
#define FRC_ME_RO_GMV_RGN_11 ((0x192c << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_11_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_11_vector_0 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_11_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_11_vector_1 // signed , RO, default = 0 mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_RGN_2ND_11 ((0x192d << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_me_region_gmv_2nd_11_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_me_region_gmv_2nd_11_vector_0 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:12 reserved
-//Bit 11: 0 ro_me_region_gmv_2nd_11_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 11: 0 ro_me_region_gmv_2nd_11_vector_1 // signed , RO, default = 0 2nd regional mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
#define FRC_ME_RO_GMV_ROUGH_RGN_11 ((0x192e << 2) + 0xff050000)
//Bit 31:29 reserved
//Bit 28:16 ro_me_region_gmv_rough_11_vector_0 // signed , RO, default = 0
@@ -50315,7 +50315,7 @@
//Bit 0 reg_vp_en // unsigned , RW, default = 1 vp processing enable, 0:disable, 1:enable
#define FRC_VP_GMV ((0x1e01 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 reg_vp_gmv_vector_0 // signed , RW, default = 0 global mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 reg_vp_gmv_vector_0 // signed , RW, default = 0 global mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:13 reserved
//Bit 12 reg_vp_gmv_invalid // unsigned , RW, default = 0 when 1, gmv is invalid.
//Bit 11: 0 reg_vp_gmv_vector_1 // signed , RW, default = 0
@@ -50344,7 +50344,7 @@
//Bit 3: 0 reg_retimer_vsrch_rng // unsigned , RW, default = 7 vp partI (retimer) vertical search range
#define FRC_VP_GMV_MUX ((0x1e08 << 2) + 0xff050000)
//Bit 31:29 reserved
-//Bit 28:16 ro_vp_gmv_mux_vector_0 // signed , RO, default = 0 global mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_ovrwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
+//Bit 28:16 ro_vp_gmv_mux_vector_0 // signed , RO, default = 0 global mv detected by FW, [mvx, mvy] s9.2, replace the bv if reg_me_overwrite_bv_en=1, otherwise is gmv of each loop, only care about the vector, no care of the sad and so on.
//Bit 15:14 reserved
//Bit 13 ro_vp_gmv_mux_invalid // unsigned , RO, default = 0 when 1, gmv is invalid.
//Bit 12: 1 ro_vp_gmv_mux_vector_1 // signed , RO, default = 0
@@ -50562,9 +50562,9 @@
//Bit 0 reg_cn2ncr_cn2ncrr_oor_enable // unsigned , RW, default = 1 enable to use out of range considerations in dir_type decision
#define FRC_VP_SAD_TH ((0x1e39 << 2) + 0xff050000)
//Bit 31:24 reserved
-//Bit 23:16 reg_vp_sad_chk_s_th // unsigned , RW, default = 80 threshold to sad comparision to do sad check for basic sad rule
-//Bit 15: 8 reg_vp_sad_chk_b_th // unsigned , RW, default = 100 threshold to sad comparision to do sad check for replacement sad rule
-//Bit 7: 0 reg_vp_sad_th_xrule // unsigned , RW, default = 10 threshold to sad comparision to do sad check for replacement xross rule sad comparison
+//Bit 23:16 reg_vp_sad_chk_s_th // unsigned , RW, default = 80 threshold to sad comparison to do sad check for basic sad rule
+//Bit 15: 8 reg_vp_sad_chk_b_th // unsigned , RW, default = 100 threshold to sad comparison to do sad check for replacement sad rule
+//Bit 7: 0 reg_vp_sad_th_xrule // unsigned , RW, default = 10 threshold to sad comparison to do sad check for replacement xross rule sad comparison
#define FRC_VP_RETIMER_ENABLE ((0x1e3a << 2) + 0xff050000)
//Bit 31:24 reserved
//Bit 23:16 reg_vp_gmv_similar_th // unsigned , RW, default = 8 threshold to gmv and CP/CN for replacement gmv similar rule check.
@@ -50573,7 +50573,7 @@
//Bit 7 reg_vp_dont_care_gmv // unsigned , RW, default = 1 enable signal to dont care gmv, 0: care gmv; 1: dont care gmv
//Bit 6 reg_vp_uncov_rule_en // unsigned , RW, default = 1 enable signal to use uncov_final, 0: disable 1: enable
//Bit 5 reg_vp_cover_rule_en // unsigned , RW, default = 1 enable signal to use cover_final, 0: disable 1: enable
-//Bit 4 reg_vp_extnd_rule_en // unsigned , RW, default = 1 enable signal to use replace_cp/cn_extend, 0: disable 1: enable
+//Bit 4 reg_vp_extend_rule_en // unsigned , RW, default = 1 enable signal to use replace_cp/cn_extend, 0: disable 1: enable
//Bit 3 reg_vp_sad_rule_en // unsigned , RW, default = 0 enable signal to use replace_cp/cn_sad, 0: disable 1: enable
//Bit 2 reg_vp_oor_rule_en // unsigned , RW, default = 1 enable signal to use replace_cp/cn_oor, 0: disable 1: enable
//Bit 1 reg_vp_cross_rule_en // unsigned , RW, default = 1 enable signal to use replace_cp/cn_cross, 0: disable 1: enable
@@ -52082,7 +52082,7 @@
// synopsys translate_on
#define FRC_MC_CSC_CTRL ((0x30f0 << 2) + 0xff050000)
//Bit 31: 10 reserved
-//Bit 9 : 8 reg_glk_ctrl // unsigned , RW, default = 0 csc reg_glk_ctrl enable 2'b00:gatting 2'b01:close 2'b1x:always open
+//Bit 9 : 8 reg_glk_ctrl // unsigned , RW, default = 0 csc reg_glk_ctrl enable 2'b00:gating 2'b01:close 2'b1x:always open
//Bit 7: 5 reserved
//Bit 4 reg_sync_en // unsigned , RW, default = 1 reg_csc_en sync enable
//Bit 3 reg_csc_en // unsigned , RW, default = 1 enable rgb2yuv mtrix for ip pattern generation
@@ -53421,7 +53421,7 @@
//Bit 31:15 reserved
//Bit 14 reg_mc_force_deflicker_en // unsigned , RW, default = 0 force deflicker
//Bit 13 reg_mc_flicker0_mode // unsigned , RW, default = 0 do-deflicker == 0 mode 0: use all bilinear(c v h c2 v2 h2); mode 1: c use h8v4, v h c2 h2 v2 use bilinear
-//Bit 12 reg_mc_flicker1_mode // unsigned , RW, default = 0 do-deflicker == 1 mode 0: just c use h8v4 not do obmc; mode 1: c use h8 v4, v h c2 h2 v2 use biliear
+//Bit 12 reg_mc_flicker1_mode // unsigned , RW, default = 0 do-deflicker == 1 mode 0: just c use h8v4 not do obmc; mode 1: c use h8 v4, v h c2 h2 v2 use bilinear
//Bit 11:10 reserved
//Bit 9: 0 reg_mc_diff_mv_thrd // unsigned , RW, default = 0 mv diff th
#define FRC_MC_INVALID_CHECK_MODE ((0x3202 << 2) + 0xff050000)
@@ -53810,7 +53810,7 @@
//Bit 22:20 reg_mc_7_flag4_color8_mode // unsigned , RW, default = 0 flag color mode
//Bit 19:16 reg_mc_7_flag4_num8 // unsigned , RW, default = 0 flag num
//Bit 15:14 reserved
-//Bit 13: 8 reg_mc_7_flag_seg_len // unsigned , RW, default = 16 7 flag seg lenth
+//Bit 13: 8 reg_mc_7_flag_seg_len // unsigned , RW, default = 16 7 flag seg length
//Bit 7: 6 reserved
//Bit 5: 0 reg_mc_7_flag_line_width // unsigned , RW, default = 4 7 flag line width
#define FRC_MC_DBG_EN ((0x3234 << 2) + 0xff050000)
@@ -55190,7 +55190,7 @@
#define PFIFO_WR_PTR ((0x3866 << 2) + 0xfdf00000)
// bit 9:0 -- point to byte address
#define PFIFO_RD_PTR ((0x3867 << 2) + 0xfdf00000)
-// bit 31:0 -- 8/16/24/32 bits data acording to pfifo_data_width
+// bit 31:0 -- 8/16/24/32 bits data according to pfifo_data_width
#define PFIFO_DATA ((0x3868 << 2) + 0xfdf00000)
// bit 31:0 -- parser search pattern
#define PARSER_SEARCH_PATTERN ((0x3869 << 2) + 0xfdf00000)
@@ -55225,7 +55225,7 @@
#define PARSER_PARAMETER ((0x386f << 2) + 0xfdf00000)
// bit 31:0 -- insert data // write only
// write to PARSER_CONTROL will reset the write position
-// continous write to this address can write upto 16 bytes
+// continuous write to this address can write upto 16 bytes
#define PARSER_INSERT_DATA ((0x3870 << 2) + 0xfdf00000)
// Bit 31:24 -- Reserved Stream_ID
// Bit 23:16 -- Sub Stream_ID
@@ -55394,7 +55394,7 @@
#define PARSER_B_PFIFO_WR_PTR ((0x1166 << 2) + 0xfdf00000)
// bit 9:0 -- point to byte address
#define PARSER_B_PFIFO_RD_PTR ((0x1167 << 2) + 0xfdf00000)
-// bit 31:0 -- 8/16/24/32 bits data acording to pfifo_data_width
+// bit 31:0 -- 8/16/24/32 bits data according to pfifo_data_width
#define PARSER_B_PFIFO_DATA ((0x1168 << 2) + 0xfdf00000)
// bit 31:0 -- parser search pattern
#define PARSER_B_PARSER_SEARCH_PATTERN ((0x1169 << 2) + 0xfdf00000)
@@ -55429,7 +55429,7 @@
#define PARSER_B_PARSER_PARAMETER ((0x116f << 2) + 0xfdf00000)
// bit 31:0 -- insert data // write only
// write to PARSER_CONTROL will reset the write position
-// continous write to this address can write upto 16 bytes
+// continuous write to this address can write upto 16 bytes
#define PARSER_B_PARSER_INSERT_DATA ((0x1170 << 2) + 0xfdf00000)
// Bit 31:24 -- Reserved Stream_ID
// Bit 23:16 -- Sub Stream_ID
diff --git a/demos/amlogic/n200/include/t5/dos_register.h b/demos/amlogic/n200/include/t5/dos_register.h
index 6e20658..217dff4 100644
--- a/demos/amlogic/n200/include/t5/dos_register.h
+++ b/demos/amlogic/n200/include/t5/dos_register.h
@@ -4816,7 +4816,7 @@
// [12] -- ipp_cntl_clkgate_disbl
// [13] -- ipp_nsamples_proc_clkgate_disbl
// [14] -- ipp_refroute_clkgate_disbl
-// [15] -- ipp_spred_clkgate_disbl
+// [15] -- ipp_spread_clkgate_disbl
// [16] -- ipp_reg_clkgate_disbl
// [17] -- ipp_recon_clkgate_disbl
// [19:18] -- reserved
@@ -4847,7 +4847,7 @@
// [12] -- ipp_cntl_clkgate
// [13] -- ipp_nsamples_proc_clkgate
// [14] -- ipp_refroute_clkgate
-// [15] -- ipp_spred_clkgate
+// [15] -- ipp_spread_clkgate
// [16] -- ipp_reg_clkgate
// [17] -- ipp_recon_clkgate
// [19:18] -- reserved
diff --git a/demos/amlogic/n200/include/t5d/dos_register.h b/demos/amlogic/n200/include/t5d/dos_register.h
index 69671f4..d7fd097 100644
--- a/demos/amlogic/n200/include/t5d/dos_register.h
+++ b/demos/amlogic/n200/include/t5d/dos_register.h
@@ -4816,7 +4816,7 @@
// [12] -- ipp_cntl_clkgate_disbl
// [13] -- ipp_nsamples_proc_clkgate_disbl
// [14] -- ipp_refroute_clkgate_disbl
-// [15] -- ipp_spred_clkgate_disbl
+// [15] -- ipp_spread_clkgate_disbl
// [16] -- ipp_reg_clkgate_disbl
// [17] -- ipp_recon_clkgate_disbl
// [19:18] -- reserved
@@ -4847,7 +4847,7 @@
// [12] -- ipp_cntl_clkgate
// [13] -- ipp_nsamples_proc_clkgate
// [14] -- ipp_refroute_clkgate
-// [15] -- ipp_spred_clkgate
+// [15] -- ipp_spread_clkgate
// [16] -- ipp_reg_clkgate
// [17] -- ipp_recon_clkgate
// [19:18] -- reserved
diff --git a/demos/amlogic/n200/include/t5d/register.h b/demos/amlogic/n200/include/t5d/register.h
index b5308da..c95c9bd 100644
--- a/demos/amlogic/n200/include/t5d/register.h
+++ b/demos/amlogic/n200/include/t5d/register.h
@@ -2577,7 +2577,7 @@
// 1=ABH read request burst size 24;
// 2=ABH read request burst size 32;
// 3=ABH read request burst size 48.
-// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logics except register.
+// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logic except register.
// Bit 0 RW ctrl_free_clk_enable. 0=Default, Enable clock gating. 1=No clock gating, enable free clock.
#define RDMA_CTRL ((0x1114 << 2) + 0xff900000)
// Read only.
@@ -6223,9 +6223,9 @@
// Bit 15:13 v0_gofld_sel, 000: display go_field, 001: DI pre_frame_rst, 010: vdin0 go_field, 011: vdin1 go_field, otherwise: force go_field by
// reg_v0_go_field(bit19)
// Bit 12:6 hole_lines for d2d3 depth read interface
-// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 fomart output), 2'b10: scale output, otherwise nothing as v1
+// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 format output), 2'b10: scale output, otherwise nothing as v1
// Bit 3 use_vdin_eol, if true, use vdin eol as the v0_eol, otherwise using length to get the v0_eol
-// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 fomart output), 101: vpp scale output
+// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 format output), 101: vpp scale output
//
// `define D2D3_INTF_CTRL0 8'h09
#define VD1_AFBCD0_MISC_CTRL ((0x1a0a << 2) + 0xff900000)
@@ -6238,7 +6238,7 @@
// OSD1 registers
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -6450,7 +6450,7 @@
// OSD2 registers
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -9342,7 +9342,7 @@
// OSD1 registers
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -10857,8 +10857,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE1 ((0x27a6 << 2) + 0xff900000)
@@ -10870,8 +10870,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE2 ((0x27a7 << 2) + 0xff900000)
@@ -10883,8 +10883,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE3 ((0x27a8 << 2) + 0xff900000)
@@ -10896,8 +10896,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE4 ((0x27a9 << 2) + 0xff900000)
@@ -10909,8 +10909,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_WR_MODE0 ((0x27aa << 2) + 0xff900000)
@@ -10922,8 +10922,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_WR_MODE1 ((0x27ab << 2) + 0xff900000)
@@ -10935,8 +10935,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_WR_MODE2 ((0x27ac << 2) + 0xff900000)
@@ -10948,8 +10948,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_STAT ((0x27ad << 2) + 0xff900000)
@@ -18449,7 +18449,7 @@
//bit[30] R-RW 0~1 0 reg_id_check : check the id of data path and req path
//bit[29] R-RW 0~1 0 reg_clear_fifo : manually reset bit
//bit[28] R-RW 0~1 0 reg_vsync_rst : soft_rst auto reset enable
-//bit[27] R-RW 0~1 0 reg_update_addr : manually udpate start addr
+//bit[27] R-RW 0~1 0 reg_update_addr : manually update start addr
//bit[26] R-RW 0~1 0 reg_addr_auto : auto update start addr enable
//bit[25] R-RW 0~1 0 reg_keep_receive : data path keep receive
//bit[24:19] R-RW 0~63 0 reg_req_th : fifo_room > req_th, then send the request
@@ -20447,8 +20447,8 @@
//Bit 31:12 reserved
//Bit 11:10 reg_fmeter_vwin_mm //u2, vertical window size, 0:1 cloumn, 1:3cloumn, 2or3: 5cloumn .unsigned , default = 0
//Bit 9 : 8 reg_fmeter_hwin_mm //u2, horizontal window size, 0:1x7, 1:1x9, 2or3: 1x11 .unsigned , default = 0
-//Bit 7 reg_fmeter_d2_mode //u1, selectino filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
-//Bit 6 reg_fmeter_v2_mode //u1, selectino filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 7 reg_fmeter_d2_mode //u1, selection filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 6 reg_fmeter_v2_mode //u1, selection filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
//Bit 5: 4 reg_fmeter_h2_mode //u2, selection filter H2, 0: [0 0 0 -2 0 0 2 0 0], 1: [-2 0 0 0 2], 2or3: [0-2 0 0 0 0 0 2 0] .unsigned , default = 0
//Bit 3: 1 reserved
//Bit 0 reg_freq_meter_en //u1, freq meter enable .unsigned , default = 0
diff --git a/demos/amlogic/n200/include/t5d/t5d_mmc_reg.h b/demos/amlogic/n200/include/t5d/t5d_mmc_reg.h
index 74a0c80..c163dcf 100644
--- a/demos/amlogic/n200/include/t5d/t5d_mmc_reg.h
+++ b/demos/amlogic/n200/include/t5d/t5d_mmc_reg.h
@@ -226,17 +226,17 @@
//bit 10 force to disable the clock of dfi command generation
//bit 9 force to disable the clock of dram controller
//bit 8 force to disable the clock of dfi data path.
- //bit 7. force to disalbe the clock of write rsp generation.
- //bit 6. force to disalbe the clock of read rsp generation.
- //bit 5. force to disalbe the clock of command filter.
- //bit 4. force to disalbe the clock of write reorder buffer.
- //bit 3. force to disalbe the clock of write data buffer.
- //bit 2. force to disalbe the clock of read reorder buffer.
- //bit 1. force to disalbe the clock of read canvas.
- //bit 0. force to disalbe the clock of write canvas.
+ //bit 7. force to disable the clock of write rsp generation.
+ //bit 6. force to disable the clock of read rsp generation.
+ //bit 5. force to disable the clock of command filter.
+ //bit 4. force to disable the clock of write reorder buffer.
+ //bit 3. force to disable the clock of write data buffer.
+ //bit 2. force to disable the clock of read reorder buffer.
+ //bit 1. force to disable the clock of read canvas.
+ //bit 0. force to disable the clock of write canvas.
-// DMC CANVAS setting domain control regsiters.
+// DMC CANVAS setting domain control registers.
#define DC_CAV_LUT_DATAL ((0x0012 << 2) + 0xff638000)
//low 32 bits of canvas data which need to be configured to canvas memory.
#define DC_CAV_LUT_DATAH ((0x0013 << 2) + 0xff638000)
@@ -304,7 +304,7 @@
// at the test period, the whole MMC granted data cycles which goes to 16bits ddr. unit:64bits
#define DMC_MON0_CTRL ((0x0030 << 2) + 0xff638000)
- //BW MONTIOR 0 address range control. start addrss <= AXI address[31:16] <= end address
+ //BW MONITOR 0 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define DMC_MON0_CTRL1 ((0x0031 << 2) + 0xff638000)
@@ -316,7 +316,7 @@
// at the test period, this range granted data cycles for the selected channel and ports.
#define DMC_MON1_CTRL ((0x0034 << 2) + 0xff638000)
- //BW monitor 1 address range control. start addrss <= AXI address[31:16] <= end address
+ //BW monitor 1 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define DMC_MON1_CTRL1 ((0x0035 << 2) + 0xff638000)
@@ -328,7 +328,7 @@
// at the test period, this range granted data cycles for the selected channel and ports.
#define DMC_MON2_CTRL ((0x0038 << 2) + 0xff638000)
- //BW monitor 2 address range control. start addrss <= AXI address[31:16] <= end address
+ //BW monitor 2 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define DMC_MON2_CTRL1 ((0x0039 << 2) + 0xff638000)
@@ -340,7 +340,7 @@
// at the test period, this range granted data cycles for the selected channel and ports.
#define DMC_MON3_CTRL ((0x003c << 2) + 0xff638000)
- //BW monitor 3 address range control. start addrss <= AXI address[31:16] <= end address
+ //BW monitor 3 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define DMC_MON3_CTRL1 ((0x003d << 2) + 0xff638000)
@@ -352,7 +352,7 @@
// at the test period, this range granted data cycles for the selected channel and ports.
#define DMC_MON4_CTRL ((0x00c0 << 2) + 0xff638000)
- //BW monitor 4 address range control. start addrss <= AXI address[31:16] <= end address
+ //BW monitor 4 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define DMC_MON4_CTRL1 ((0x00c1 << 2) + 0xff638000)
@@ -364,7 +364,7 @@
// at the test period, this range granted data cycles for the selected channel and ports.
#define DMC_MON5_CTRL ((0x00c4 << 2) + 0xff638000)
- //BW monitor 5 address range control. start addrss <= AXI address[31:16] <= end address
+ //BW monitor 5 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define DMC_MON5_CTRL1 ((0x00c5 << 2) + 0xff638000)
@@ -376,7 +376,7 @@
// at the test period, this range granted data cycles for the selected channel and ports.
#define DMC_MON6_CTRL ((0x00c8 << 2) + 0xff638000)
- //BW monitor 6 address range control. start addrss <= AXI address[31:16] <= end address
+ //BW monitor 6 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define DMC_MON6_CTRL1 ((0x00c9 << 2) + 0xff638000)
@@ -389,7 +389,7 @@
#define DMC_MON7_CTRL ((0x00cc << 2) + 0xff638000)
- //BW monitor 7 address range control. start addrss <= AXI address[31:16] <= end address
+ //BW monitor 7 address range control. start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
#define DMC_MON7_CTRL1 ((0x00cd << 2) + 0xff638000)
@@ -442,7 +442,7 @@
//bit 7:0. write urgent 0 request pending hold num.
#define DMC_CMD_FILTER_CTRL7 ((0x0046 << 2) + 0xff638000)
- //bit 31:24. aw_req_pedning singal assertion after wbuf full.
+ //bit 31:24. aw_req_pending singal assertion after wbuf full.
//bit 23:16 aw_req_pending singal hold how long if wbuf not full.
//bit 15:8 write to read waiting cycles if there write hit request.
//bit 7:0 read to write waiting cycles if there write hit request.
@@ -917,7 +917,7 @@
#define DMC_CHAN_STS ((0x00bc << 2) + 0xff638000)
//AXI0 is first CPU and Mali combined channel from CCI-400 directly. The first 2Gbyte address will go through this channel.
//AXI10 is the second CPU, Mali channel combined with NNA from NIC-400. The upper 2Gbyte address will go through this channel.
- // read only regsiter.
+ // read only register.
// the second mali and NNA channel IDLE.
// the second CPU channel IDLE.
// the first mali channel IDLE.
@@ -934,7 +934,7 @@
//bit 31:16 : range end address.
//bit 15:0 : range start address
#define DMC_PROT0_CTRL ((0x00d1 << 2) + 0xff638000)
- //bit 23:16. each bit to eanble one of the 8 ambus channal for the protection function.
+ //bit 23:16. each bit to enable one of the 8 ambus channal for the protection function.
//bit 15:0 each bit to enable one of the 15 channel input for the protection function.
#define DMC_PROT0_CTRL1 ((0x00d2 << 2) + 0xff638000)
//bit 26. protection 0 read access protection enable.
@@ -945,7 +945,7 @@
//bit 31:16 : range end address.
//bit 15:0 : range start address
#define DMC_PROT1_CTRL ((0x00d4 << 2) + 0xff638000)
- //bit 23:16. each bit to eanble one of the 8 ambus channal for the protection function.
+ //bit 23:16. each bit to enable one of the 8 ambus channal for the protection function.
//bit 15:0 each bit to enable one of the 15 channel input for the protection function.
#define DMC_PROT1_CTRL1 ((0x00d5 << 2) + 0xff638000)
//bit 26. protection range 1 read access protection enable bit.
@@ -1038,37 +1038,37 @@
#define DMC_TEST_WD0 ((0x0010 << 2) + 0xff639800)
- // write data 0 for write command. also for read back data comparision.
+ // write data 0 for write command. also for read back data comparison.
#define DMC_TEST_WD1 ((0x0011 << 2) + 0xff639800)
- // write data 1 for write command. also for read back data comparision.
+ // write data 1 for write command. also for read back data comparison.
#define DMC_TEST_WD2 ((0x0012 << 2) + 0xff639800)
- // write data 2 for write command. also for read back data comparision.
+ // write data 2 for write command. also for read back data comparison.
#define DMC_TEST_WD3 ((0x0013 << 2) + 0xff639800)
- // write data 3 for write command. also for read back data comparision.
+ // write data 3 for write command. also for read back data comparison.
#define DMC_TEST_WD4 ((0x0014 << 2) + 0xff639800)
- // write data 4 for write command. also for read back data comparision.
+ // write data 4 for write command. also for read back data comparison.
#define DMC_TEST_WD5 ((0x0015 << 2) + 0xff639800)
- // write data 5 for write command. also for read back data comparision.
+ // write data 5 for write command. also for read back data comparison.
#define DMC_TEST_WD6 ((0x0016 << 2) + 0xff639800)
- // write data 6 for write command. also for read back data comparision.
+ // write data 6 for write command. also for read back data comparison.
#define DMC_TEST_WD7 ((0x0017 << 2) + 0xff639800)
- // write data 7 for write command. also for read back data comparision.
+ // write data 7 for write command. also for read back data comparison.
#define DMC_TEST_WD8 ((0x0018 << 2) + 0xff639800)
- // write data 8 for write command. also for read back data comparision.
+ // write data 8 for write command. also for read back data comparison.
#define DMC_TEST_WD9 ((0x0019 << 2) + 0xff639800)
- // write data 9 for write command. also for read back data comparision.
+ // write data 9 for write command. also for read back data comparison.
#define DMC_TEST_WD10 ((0x001a << 2) + 0xff639800)
- // write data 10 for write command. also for read back data comparision.
+ // write data 10 for write command. also for read back data comparison.
#define DMC_TEST_WD11 ((0x001b << 2) + 0xff639800)
- // write data 11 for write command. also for read back data comparision.
+ // write data 11 for write command. also for read back data comparison.
#define DMC_TEST_WD12 ((0x001c << 2) + 0xff639800)
- // write data 12 for write command. also for read back data comparision.
+ // write data 12 for write command. also for read back data comparison.
#define DMC_TEST_WD13 ((0x001d << 2) + 0xff639800)
- // write data 13 for write command. also for read back data comparision.
+ // write data 13 for write command. also for read back data comparison.
#define DMC_TEST_WD14 ((0x001e << 2) + 0xff639800)
- // write data 14 for write command. also for read back data comparision.
+ // write data 14 for write command. also for read back data comparison.
#define DMC_TEST_WD15 ((0x001f << 2) + 0xff639800)
- // write data 15 for write command. also for read back data comparision.
+ // write data 15 for write command. also for read back data comparison.
#define DMC_TEST_RD0 ((0x0020 << 2) + 0xff639800)
// the read back data 0. if error happens, it would capture the first error data.
@@ -1143,7 +1143,7 @@
//DMC use 15bits ID to identify the input ports and ID.
// bit 14:10.
-// 0 : CPU and MALI. Mali and cpu will be seperated to 2 channel. CPU traffic will be assigned to ID = 0. Mali traffic will assigned to ID =1.
+// 0 : CPU and MALI. Mali and cpu will be separated to 2 channel. CPU traffic will be assigned to ID = 0. Mali traffic will assigned to ID =1.
// 1 : Mali
// 2 : PCIE
// 3 : HDMI.
@@ -1153,7 +1153,7 @@
// 7 : Device.
// 8 : HEVC_B
// 9 : WAVE.
-//10 : CPU, GPU and NNA. CPU will assign to ID = 13. GPU and NNA still in ID = 10. we use the GPU/NNA ID to cotrol the secure control.
+//10 : CPU, GPU and NNA. CPU will assign to ID = 13. GPU and NNA still in ID = 10. we use the GPU/NNA ID to control the secure control.
//11 : GDC.
//12 : ISP.
@@ -1844,7 +1844,7 @@
#define DMC_DDR_CTRL1 ((0x0130 << 2) + 0xff639000)
//bit 0. DMC_DDR_LOCK. 1: LOCK DMC_DDR_CTRL, DMC_DDR_CTRL1, DMC_AXI2DDRx, DDR0/1_ADDRMAP_x registers. those register can't modified any more.
- // 0: all these regsiters can be read/write by secure APB access.
+ // 0: all these registers can be read/write by secure APB access.
//
// Closing file: ../mmc_lp4/dmc/rtl/dmc_sec.vh
@@ -1937,7 +1937,7 @@
#define DMC_DRAM_TDPD ((0x001d << 2) + 0xff638400)
//not support.
#define DMC_DRAM_DFITCTRLDELAY ((0x001e << 2) + 0xff638400)
- //bit 3:0. DFI_t_ctrldealy
+ //bit 3:0. DFI_t_ctrldelay
#define DMC_DRAM_DFITPHYWRDATA ((0x001f << 2) + 0xff638400)
//bit 5:0. dfi_t_phy_wrdata.
#define DMC_DRAM_DFITPHYWRLAT ((0x0020 << 2) + 0xff638400)
@@ -1947,7 +1947,7 @@
#define DMC_DRAM_DFITPHYRDLAT ((0x0022 << 2) + 0xff638400)
//bit 5:0. dfi_t_rdlat.
#define DMC_DRAM_DFITCTRLUPDMIN ((0x0023 << 2) + 0xff638400)
- //bit 7:0. CTRLUPD_MIN minimux clock cycle to maintain CTRLUPD_REQ.
+ //bit 7:0. CTRLUPD_MIN minimum clock cycle to maintain CTRLUPD_REQ.
#define DMC_DRAM_DFITCTRLUPDMAX ((0x0024 << 2) + 0xff638400)
//bit 7:0 CTRLUPD_MAX. maxmum clock cycle to maintain CTRLUPD_REQ if no CTRLUPD_ACK response.
#define DMC_DRAM_DFITREFMSKI ((0x0026 << 2) + 0xff638400)
@@ -2033,7 +2033,7 @@
-//timing paramter for frequency set 1.
+//timing parameter for frequency set 1.
#define DMC_NFQ_TMRD ((0x0040 << 2) + 0xff638400)
#define DMC_NFQ_TRFC ((0x0041 << 2) + 0xff638400)
#define DMC_NFQ_TRP ((0x0042 << 2) + 0xff638400)
@@ -2121,7 +2121,7 @@
//bit 10 1: enable staggered chip select for 2 ranks DRAM.
//bit 9 1: enable send auto refresh command to DDR SDRAM when PCTL is in CFG/STOP state.
//bit 8 send auto refr cmd before enter register triggered self refresh
- //bit 7 send auto refr cmd after exit regsiter triggered self refresh mode.
+ //bit 7 send auto refr cmd after exit register triggered self refresh mode.
//bit 6 disable dram clock after enter register triggered self refresh.
//bit 5 send DFI_LP_REQ to PHY after enter register triggered elf refresh mode.
//bit 4 send DRAM to power down mode after enter self refresh. ONLY for LPDDR4.
@@ -2218,7 +2218,7 @@
//bit 14. freq post config_en. After freq enter stop state let DMC configure DDR SDRAM.
//bit 13. send zqcl after freq change in DDR3/4 mode.
//bit 12. send zqcs after freq change. 1: enable. 0 not send.
-//bit 11. in AUTO MRW fucntion: the data format. 1: use USR_CMD format. 0: MRW format.
+//bit 11. in AUTO MRW function: the data format. 1: use USR_CMD format. 0: MRW format.
//bit 10. AUTO MRW function: 1 use hardware auto MRW function. 0: don't do auto MRW.
//bit 9. 1 : FREQ MRW done. let FREQ change machine continue.
//bit 8 FREQ WAIT. 1 when freq change finishes, state machine stop at self refresh state in case there's something need to handle.
@@ -2304,7 +2304,7 @@
#define DMC_DFI_ERR_STAT ((0x0098 << 2) + 0xff638400)
- //LPDDR4 PHY DFI error infomation.
+ //LPDDR4 PHY DFI error information.
//bit 31:20. not used.
//bit 9. ddr0_dfi_error
//bit 8:5 ddr0_dfi_error_info.
diff --git a/demos/amlogic/n200/include/t5w/dos_register.h b/demos/amlogic/n200/include/t5w/dos_register.h
index 0cb52c9..15f7294 100644
--- a/demos/amlogic/n200/include/t5w/dos_register.h
+++ b/demos/amlogic/n200/include/t5w/dos_register.h
@@ -236,7 +236,7 @@
#define HCODEC_MFDIN_REG6_DCFG ((0x100e << 2) + 0xff620000)
//cfg_soft_cmd = mfdin_reg7_scmd; // Soft Command [28]selfcleared start,[27:14]dmb_x,[13:0]dmb_y
#define HCODEC_MFDIN_REG7_SCMD ((0x100f << 2) + 0xff620000)
-//cfg_pic_xsize = mfdin_reg8_dmbl[23:12]; //pixel (x,y) at the begining of last dmb in the picture, picture x size
+//cfg_pic_xsize = mfdin_reg8_dmbl[23:12]; //pixel (x,y) at the beginning of last dmb in the picture, picture x size
//cfg_pic_ysize = mfdin_reg8_dmbl[11:0]; //picture y size
#define HCODEC_MFDIN_REG8_DMBL ((0x1010 << 2) + 0xff620000)
//cfg_endian = mfdin_reg9_endn; //Endian Control
@@ -1636,7 +1636,7 @@
// bit[8] p_top_left_mix
// bit[7] mv_cal_mixed_type
// bit[6] mc_hcmd_mixed_type
-// bit[5] use_seperate_int_control
+// bit[5] use_separate_int_control
// bit[4] hcmd_intra_use_q_info
// bit[3] hcmd_left_use_prev_info
// bit[2] hcmd_use_q_info
@@ -1648,7 +1648,7 @@
//15:8 - hcmd_mb_y_auto
// 7:0 - hcmd_mb_x_auto
#define VLC_HCMD_MBXY_AUTO ((0x1d26 << 2) + 0xff620000)
-// bit[31:0] vlc_int_control_inter -- will be used when use_seperate_int_control is set
+// bit[31:0] vlc_int_control_inter -- will be used when use_separate_int_control is set
#define VLC_INT_CONTROL_INTER ((0x1d2f << 2) + 0xff620000)
// --------------------------------------------
// Picture VLC
@@ -4029,7 +4029,7 @@
// [7:6] - max_pcm_luma_coding_block_size
// [5:4] - min_pcm_luma_coding_block_size
// [3:2] - bit_depth_luma_minus8
-// [1] - enable_negtive_quant
+// [1] - enable_negative_quant
// [0] - pcm_enabled_flag
#define HEVC_PARSER_HEADER_INFO2 ((0x3125 << 2) + 0xff620000)
// Read Only
@@ -4071,14 +4071,14 @@
// cabac_manual_data // 15:0
//
#define HEVC_PARSER_MANUAL_CMD ((0x312b << 2) + 0xff620000)
-// bit [12:0] - Read adress :
+// bit [12:0] - Read address :
// address 0-255 stream_fifo (128x64)
// address 256-319 context_mem (256x7)
// address 512-639 parser_cmd_mem (256x16)
// address 0x400-0xfff vp9_count_mem(768x96)
// address 0x1000-0x11ff vp9_prob_mem(512x32)
#define HEVC_PARSER_MEM_RD_ADDR ((0x312c << 2) + 0xff620000)
-// bit [9:0] - Write adress :
+// bit [9:0] - Write address :
// address 0-255 stream_fifo (128x64)
// address 512-639 parser_cmd_mem (256x16)
// address 0x400-0xfff vp9_count_mem(768x96)
@@ -4816,7 +4816,7 @@
// [12] -- ipp_cntl_clkgate_disbl
// [13] -- ipp_nsamples_proc_clkgate_disbl
// [14] -- ipp_refroute_clkgate_disbl
-// [15] -- ipp_spred_clkgate_disbl
+// [15] -- ipp_spread_clkgate_disbl
// [16] -- ipp_reg_clkgate_disbl
// [17] -- ipp_recon_clkgate_disbl
// [19:18] -- reserved
@@ -4847,7 +4847,7 @@
// [12] -- ipp_cntl_clkgate
// [13] -- ipp_nsamples_proc_clkgate
// [14] -- ipp_refroute_clkgate
-// [15] -- ipp_spred_clkgate
+// [15] -- ipp_spread_clkgate
// [16] -- ipp_reg_clkgate
// [17] -- ipp_recon_clkgate
// [19:18] -- reserved
@@ -4934,7 +4934,7 @@
#define HEVCD_MPP_DECOMP_CTL2 ((0x34c3 << 2) + 0xff620000)
// [9:0] -- decomp_default_Y
// [19:10] -- decomp_default_Cb
-// [29:20] -- decomp_dafault_Cr
+// [29:20] -- decomp_default_Cr
// [31:30] -- bitdepth_sel 00:8bit 01:9bit 10:10bit
#define HEVCD_MPP_DECOMP_CTL3 ((0x34c4 << 2) + 0xff620000)
// HEVCD_MPP_DECOMP_PERFMON_CTL
@@ -5300,9 +5300,9 @@
#define HEVC_SAO_CTRL9 ((0x362d << 2) + 0xff620000)
//[10] dw_output_sel:0=nv21,1=compress,default=0
//[11] fgs_bypass:0=bypass,1=not bypass,default=0
-//[16] fgs_table_disable:0=enable 1=diable,default=0
-//[17] fgs_dma_disable:0=enable 1=diable,default=0
-//[18] fgs_core_disable:0=enable 1=diable,default=0
+//[16] fgs_table_disable:0=enable 1=disable,default=0
+//[17] fgs_dma_disable:0=enable 1=disable,default=0
+//[18] fgs_core_disable:0=enable 1=disable,default=0
//[23:20] fgs_dma_axi_lendian
#define HEVC_SAO_CTRL10 ((0x362e << 2) + 0xff620000)
#define HEVC_SAO_CTRL11 ((0x362f << 2) + 0xff620000)
@@ -9190,7 +9190,7 @@
// bit[8] p_top_left_mix
// bit[7] mv_cal_mixed_type
// bit[6] mc_hcmd_mixed_type
-// bit[5] use_seperate_int_control
+// bit[5] use_separate_int_control
// bit[4] hcmd_intra_use_q_info
// bit[3] hcmd_left_use_prev_info
// bit[2] hcmd_use_q_info
@@ -9202,7 +9202,7 @@
//15:8 - hcmd_mb_y_auto
// 7:0 - hcmd_mb_x_auto
#define HCODEC_VLC_HCMD_MBXY_AUTO ((0x1d26 << 2) + 0xff620000)
-// bit[31:0] vlc_int_control_inter -- will be used when use_seperate_int_control is set
+// bit[31:0] vlc_int_control_inter -- will be used when use_separate_int_control is set
#define HCODEC_VLC_INT_CONTROL_INTER ((0x1d2f << 2) + 0xff620000)
// --------------------------------------------
// Picture VLC
diff --git a/demos/amlogic/n200/include/t5w/register.h b/demos/amlogic/n200/include/t5w/register.h
index 4b0f2eb..50b9aff 100644
--- a/demos/amlogic/n200/include/t5w/register.h
+++ b/demos/amlogic/n200/include/t5w/register.h
@@ -116,7 +116,7 @@
// Bit 19:14 -- des_2 ts pl state -- Read Only
// Bit 13:8 -- des ts pl state -- Read Only
// Bit 3:0 PID index to 8 PID to get key-set
-// auto increse after TS_PL_PID_DATA read/write
+// auto increase after TS_PL_PID_DATA read/write
#define TS_PL_PID_INDEX ((0x18f3 << 2) + 0xffd00000)
// Bit 13 -- PID match disble
// Bit 12:0 -- PID
@@ -144,7 +144,7 @@
// [3] General enable for the ciplus module
// [2] AES CBC disable (default should be 0 to enable AES CBC)
// [1] AES Enable
-// [0] DES Eanble
+// [0] DES Enable
#define CIPLUS_CONFIG ((0x18fd << 2) + 0xffd00000)
// bit[31:28] AES IV endian
// bit[27:24] AES message out endian
@@ -1633,7 +1633,7 @@
#define PFIFO_WR_PTR ((0x3866 << 2) + 0xffd00000)
// bit 9:0 -- point to byte address
#define PFIFO_RD_PTR ((0x3867 << 2) + 0xffd00000)
-// bit 31:0 -- 8/16/24/32 bits data acording to pfifo_data_width
+// bit 31:0 -- 8/16/24/32 bits data according to pfifo_data_width
#define PFIFO_DATA ((0x3868 << 2) + 0xffd00000)
// bit 31:0 -- parser search pattern
#define PARSER_SEARCH_PATTERN ((0x3869 << 2) + 0xffd00000)
@@ -1668,7 +1668,7 @@
#define PARSER_PARAMETER ((0x386f << 2) + 0xffd00000)
// bit 31:0 -- insert data // write only
// write to PARSER_CONTROL will reset the write position
-// continous write to this address can write upto 16 bytes
+// continuous write to this address can write upto 16 bytes
#define PARSER_INSERT_DATA ((0x3870 << 2) + 0xffd00000)
// Bit 31:24 -- Reserved Stream_ID
// Bit 23:16 -- Sub Stream_ID
@@ -1837,7 +1837,7 @@
#define PARSER_B_PFIFO_WR_PTR ((0x3466 << 2) + 0xffd00000)
// bit 9:0 -- point to byte address
#define PARSER_B_PFIFO_RD_PTR ((0x3467 << 2) + 0xffd00000)
-// bit 31:0 -- 8/16/24/32 bits data acording to pfifo_data_width
+// bit 31:0 -- 8/16/24/32 bits data according to pfifo_data_width
#define PARSER_B_PFIFO_DATA ((0x3468 << 2) + 0xffd00000)
// bit 31:0 -- parser search pattern
#define PARSER_B_PARSER_SEARCH_PATTERN ((0x3469 << 2) + 0xffd00000)
@@ -1872,7 +1872,7 @@
#define PARSER_B_PARSER_PARAMETER ((0x346f << 2) + 0xffd00000)
// bit 31:0 -- insert data // write only
// write to PARSER_CONTROL will reset the write position
-// continous write to this address can write upto 16 bytes
+// continuous write to this address can write upto 16 bytes
#define PARSER_B_PARSER_INSERT_DATA ((0x3470 << 2) + 0xffd00000)
// Bit 31:24 -- Reserved Stream_ID
// Bit 23:16 -- Sub Stream_ID
@@ -2114,7 +2114,7 @@
// Bit 11:5 //aififo word counter number
// Bit 4:0 //how many bits left in the first pop register
#define AIU_AIFIFO_STATUS ((0x1401 << 2) + 0xffd00000)
-// Same fucntion as the AIGBIT of AIFIFO in CDROM module
+// Same function as the AIGBIT of AIFIFO in CDROM module
// write to this register how many bits wanna pop,
// and reading this register gets the corresponding bits data
#define AIU_AIFIFO_GBIT ((0x1402 << 2) + 0xffd00000)
@@ -2407,7 +2407,7 @@
// To measure display slave's frame rate, we can use a reference clock to measure the duration of one of more edpite pulse(s).
// Measurement control is by register MIPI_DSI_TOP_MEAS_CNTL bit[9:0].
// Reference clock comes from clk_rst_tst.cts_dsi_meas_clk, and is defined by HIU register HHI_VDIN_MEAS_CLK_CNTL bit[23:12].
-// Mesurement result is in MIPI_DSI_TOP_MEAS_STAT_TE0 and MIPI_DSI_TOP_MEAS_STAT_TE1, as below:
+// Measurement result is in MIPI_DSI_TOP_MEAS_STAT_TE0 and MIPI_DSI_TOP_MEAS_STAT_TE1, as below:
// edpite_meas_count[47:0]: Number of reference clock cycles counted during one measure period (non-incremental measure), or
// during all measure periods so far (incremental measure).
// edpite_meas_count_n[3:0]:Number of measure periods has been done. Number can wrap over.
@@ -2420,7 +2420,7 @@
// To measure Host's frame rate, we can use a reference clock to measure the duration of one of more Vsync pulse(s).
// Measurement control is by register MIPI_DSI_TOP_MEAS_CNTL bit[19:10].
// Reference clock comes from clk_rst_tst.cts_dsi_meas_clk, and is defined by HIU register HHI_VDIN_MEAS_CLK_CNTL bit[23:12].
-// Mesurement result is in MIPI_DSI_TOP_MEAS_STAT_VS0 and MIPI_DSI_TOP_MEAS_STAT_VS1, as below:
+// Measurement result is in MIPI_DSI_TOP_MEAS_STAT_VS0 and MIPI_DSI_TOP_MEAS_STAT_VS1, as below:
// vsync_meas_count[47:0]: Number of reference clock cycles counted during one measure period (non-incremental measure), or
// during all measure periods so far (incremental measure).
// vsync_meas_count_n[3:0]: Number of measure periods has been done. Number can wrap over.
@@ -2630,7 +2630,7 @@
// 1=ABH read request burst size 24;
// 2=ABH read request burst size 32;
// 3=ABH read request burst size 48.
-// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logics except register.
+// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logic except register.
// Bit 0 RW ctrl_free_clk_enable. 0=Default, Enable clock gating. 1=No clock gating, enable free clock.
#define RDMA_CTRL ((0x1114 << 2) + 0xff900000)
// Read only.
@@ -2728,7 +2728,7 @@
//Bit 7:6, component0 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in
//Bit 5, input window selection function enable
//Bit 4, enable VDIN common data input, otherwise there will be no video data input
-//Bit 3:0 vdin selection, 1: mpeg_in from dram, 2: bt656 input, 3: component input, 4: tvdecoder input, 5: hdmi rx input, 6: digtial video input, 7: loopback from Viu1, 8: MIPI.
+//Bit 3:0 vdin selection, 1: mpeg_in from dram, 2: bt656 input, 3: component input, 4: tvdecoder input, 5: hdmi rx input, 6: digital video input, 7: loopback from Viu1, 8: MIPI.
#define VDIN_COM_CTRL0 ((0x1202 << 2) + 0xff900000)
//Bit 28:16 active_max_pix_cnt, readonly
//Bit 12:0 active_max_pix_cnt_shadow, readonly
@@ -4380,7 +4380,7 @@
//Bit 0 reg_ldc_gain_lut_wr // unsigned , RW, default = 0 1:software write 0:software read.
#define LDC_GAIN_LUT_CTRL1 ((0x1475 << 2) + 0xff900000)
//Bit 31: 1 reserved
-//Bit 0 reg_ldc_gain_lut_str // unsigned , RW, default = 0 0->1:one software write/read start,postive edge valid.
+//Bit 0 reg_ldc_gain_lut_str // unsigned , RW, default = 0 0->1:one software write/read start,positive edge valid.
#define LDC_ADJ_VS_CTRL ((0x1476 << 2) + 0xff900000)
//Bit 31:16 reserved
//Bit 15:0 reg_ldc_blk_intsty_calc_intvl // unsigned , RW, default = 200 delay for one block intensity calculation period
@@ -4395,7 +4395,7 @@
//Bit 26 reg_ldc_prt_func_en //unsigned , RW, default = 0 1: enable LDC output protect function 0:disable LDC output protect function
//Bit 25 reg_ldc_bl_input_sft_ctr_en //unsigned , RW, default = 0 1: software control backlight info write index enable
//Bit 24:23 reg_ldc_bl_input_sft_wr_idx //unsigned , RW, default = 0 backlight info write index, for debug only
-//Bit 22 reg_ldc_vsync_get_bl_info_en //unsigned , RW, default = 1 0:get backlight info every block line (no vsync interrupt) 1:get backlight info accroding to vsync
+//Bit 22 reg_ldc_vsync_get_bl_info_en //unsigned , RW, default = 1 0:get backlight info every block line (no vsync interrupt) 1:get backlight info according to vsync
//Bit 21:20 reg_ldc_hist_burst_len //unsigned , RW, default = 0 0:2 times 128bit 1:4 times 128bit 2,3:6 times 128bit
//Bit 19:18 reg_ldc_blk_intsty_burst_len //unsigned , RW, default = 0 0:2 times 128bit 1:4 times 128bit 2:6 times 128bit 3:8 times 128bit
//Bit 17 reg_ldc_vs_edge_sel //unsigned , RW, default = 1 1:posedge vs sync 0:negedge vs sync
@@ -4891,7 +4891,7 @@
//bit 15: 8, mtn_minth
//bit 7: 0, mtn_maxth
#define DI_MTN_1_CTRL5 ((0x1744 << 2) + 0xff900000)
-//bit 31:28, mtn_m1b_extnd
+//bit 31:28, mtn_m1b_extend
//bit 27:24, mtn_m1b_errod
//bit 21:20, mtn_mot_txt_mode
//bit 19:18, mtn_replace_cbyy
@@ -5737,7 +5737,7 @@
//bit 15:8, reg_ei_int_drtdelay2_notver_sadth
//bit 7:0, reg_ei_int_drtdelay2_vlddrt_sadth
#define DI_MTN_1_CTRL6 ((0x17a9 << 2) + 0xff900000)
-//bit 31:24, mtn_m1b_extnd
+//bit 31:24, mtn_m1b_extend
//bit 23:16, mtn_m1b_errod
//bit 15: 8, mtn_core_ykinter
//bit 7: 0, mtn_core_ckinter
@@ -6696,9 +6696,9 @@
// Bit 15:13 v0_gofld_sel, 000: display go_field, 001: DI pre_frame_rst, 010: vdin0 go_field, 011: vdin1 go_field, otherwise: force go_field by
// reg_v0_go_field(bit19)
// Bit 12:6 hole_lines for d2d3 depth read interface
-// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 fomart output), 2'b10: scale output, otherwise nothing as v1
+// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 format output), 2'b10: scale output, otherwise nothing as v1
// Bit 3 use_vdin_eol, if true, use vdin eol as the v0_eol, otherwise using length to get the v0_eol
-// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 fomart output), 101: vpp scale output
+// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 format output), 101: vpp scale output
//
// `define D2D3_INTF_CTRL0 8'h09
#define VD1_AFBCD0_MISC_CTRL ((0x1a0a << 2) + 0xff900000)
@@ -6711,7 +6711,7 @@
// OSD1 registers 0x10-0x2f
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -6838,7 +6838,7 @@
// OSD2 registers 0x30-0x4f 0x64 -0x67
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -8555,9 +8555,9 @@
// Bit 0 SMOKE1 preblend enable only when preblend osd1 is not enable
#define VPP_SMOKE_CTRL ((0x1d29 << 2) + 0xff900000)
//smoke can be used only when that blending is disable and then be used as smoke function
-//smoke1 for OSD1 chanel
-//smoke2 for OSD2 chanel
-//smoke3 for VD2 chanel
+//smoke1 for OSD1 channel
+//smoke2 for OSD2 channel
+//smoke3 for VD2 channel
//31:24 Y
//23:16 Cb
//15:8 Cr
@@ -10395,7 +10395,7 @@
//
// Closing file: noise_estimate_reg.h
//
-// di arbtration :
+// di arbitration :
// the segment is 8'h50-8'h5f
//
// Reading file: di_arb_axi_regs.h
@@ -10604,13 +10604,13 @@
//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
//Bit 19 reserved
-//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
//Bit 11 reserved
//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
@@ -11016,13 +11016,13 @@
//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
//Bit 19 reserved
-//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
//Bit 11 reserved
//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
@@ -12942,7 +12942,7 @@
//Bit 3:1 reserved
//Bit 0 reg_frc_byp_en // unsigned , RW, default = 1, bypass enable singal of frc,1:bypas frc 0:open frc
#define VPU_VIU_ASYNC_MASK1 ((0x278f << 2) + 0xff900000)
-// vpu arbtration :
+// vpu arbitration :
// the segment is 8'h90-8'hc8
//
// Reading file: vpu_arb_axi_regs.h
@@ -13196,8 +13196,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE1 ((0x27a6 << 2) + 0xff900000)
@@ -13209,8 +13209,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE2 ((0x27a7 << 2) + 0xff900000)
@@ -13222,8 +13222,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE3 ((0x27a8 << 2) + 0xff900000)
@@ -13235,8 +13235,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE4 ((0x27a9 << 2) + 0xff900000)
@@ -13248,8 +13248,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_WR_MODE0 ((0x27aa << 2) + 0xff900000)
@@ -13261,8 +13261,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_WR_MODE1 ((0x27ab << 2) + 0xff900000)
@@ -13274,8 +13274,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_WR_MODE2 ((0x27ac << 2) + 0xff900000)
@@ -13287,8 +13287,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_STAT ((0x27ad << 2) + 0xff900000)
@@ -15721,7 +15721,7 @@
// 0: unable; 1: enable, use neighboring mvs in refinement, default = 1
//Bit 11, reserved
//Bit 10, reg_mcdi_referrfrqchken
-// 0: unable; 1: enable, enable mv frquency check while finding min err in ref, default = 1
+// 0: unable; 1: enable, enable mv frequency check while finding min err in ref, default = 1
//Bit 9, reg_mcdi_refen
// 0: unable; 1: enable, enable mv refinement, default = 1
//Bit 8, reg_mcdi_horlineen
@@ -15805,7 +15805,7 @@
//Bit 19:16, reg_mcdi_chkedgedifthd0. thd0 for edge dif check (>=), default = 15
//Bit :15, reserved.
//Bit 14:10, reg_mcdi_chkedgechklen. total check length for edge check, 1~24 (>0), default = 24
-//Bit 9: 8, reg_mcdi_chkedgeedgesel. final edge select mode, 0: original start edge, 1: lpf start edge, 2: orignal start+end edge, 3: lpf start+end edge, default = 1
+//Bit 9: 8, reg_mcdi_chkedgeedgesel. final edge select mode, 0: original start edge, 1: lpf start edge, 2: original start+end edge, 3: lpf start+end edge, default = 1
//Bit 7: 3, reg_mcdi_chkedgesaddstgain. distance gain for sad calc while getting edges, default = 4
//Bit 2, reg_mcdi_chkedgechkmode. edge used in check mode, 0: original edge, 1: lpf edge, default = 1
//Bit 1, reg_mcdi_chkedgestartedge. edge mode for start edge, 0: original edge, 1: lpf edge, default = 0
@@ -15815,7 +15815,7 @@
//Bit 14:12, reg_mcdi_lmvvalidmode valid mode for lmv calc., 100b: use char det, 010b: use flt, 001b: use hori flg
//Bit 11:10, reg_mcdi_lmvgainmvmode four modes of mv selection for lmv weight calculation, default = 1
// 0: cur(x-3), lst(x-1,x,x+1); 1: cur(x-4,x-3), lst(x,x+1); 2: cur(x-5,x-4,x-3), lst(x-1,x,x+1,x+2,x+3); 3: cur(x-6,x-5,x-4,x-3), lst(x-1,x,x+1,x+2);
-//Bit 9, reg_mcdi_lmvinitmode initial lmvs at first row of input field, 0: intial value = 0; 1: inital = 32 (invalid), default = 0
+//Bit 9, reg_mcdi_lmvinitmode initial lmvs at first row of input field, 0: initial value = 0; 1: inital = 32 (invalid), default = 0
//Bit 8, reserved
//Bit 7: 4, reg_mcdi_lmvrt0 ratio of max mv, default = 5
//Bit 3: 0, reg_mcdi_lmvrt1 ratio of second max mv, default = 5
@@ -15928,15 +15928,15 @@
//Bit 3: 0, reg_mcdi_referrgmvgain. (locked) gmv gain for err calc. in ref, normalized to 8 as '1', default = 0
#define MCDI_REF_ERR_FRQ_CHK ((0x2f1d << 2) + 0xff900000)
//Bit 31:28, reserved
-//Bit 27:24, reg_mcdi_referrfrqgain. gain for mv frquency, normalized to 4 as '1', default = 10
+//Bit 27:24, reg_mcdi_referrfrqgain. gain for mv frequency, normalized to 4 as '1', default = 10
//Bit 23:21, reserved
-//Bit 20:16, reg_mcdi_referrfrqmax. max gain for mv frquency check, default = 31
+//Bit 20:16, reg_mcdi_referrfrqmax. max gain for mv frequency check, default = 31
//Bit 15, reserved
-//Bit 14:12, reg_mcdi_ref_errfrqmvdifthd2. mv dif threshold 2 (<) for mv frquency check, default = 3
+//Bit 14:12, reg_mcdi_ref_errfrqmvdifthd2. mv dif threshold 2 (<) for mv frequency check, default = 3
//Bit 11, reserved
-//Bit 10: 8, reg_mcdi_ref_errfrqmvdifthd1. mv dif threshold 1 (<) for mv frquency check, default = 2
+//Bit 10: 8, reg_mcdi_ref_errfrqmvdifthd1. mv dif threshold 1 (<) for mv frequency check, default = 2
//Bit 7, reserved
-//Bit 6: 4, reg_mcdi_ref_errfrqmvdifthd0. mv dif threshold 0 (<) for mv frquency check, default = 1
+//Bit 6: 4, reg_mcdi_ref_errfrqmvdifthd0. mv dif threshold 0 (<) for mv frequency check, default = 1
//Bit 3: 0, reserved
#define MCDI_QME_LPF_MSK ((0x2f1e << 2) + 0xff900000)
//Bit 31:28, reserved
@@ -18686,7 +18686,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 1 debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 1 debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -20521,13 +20521,13 @@
//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
//Bit 19 reserved
-//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
//Bit 11 reserved
//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
@@ -20821,7 +20821,7 @@
//bit[30] R-RW 0~1 0 reg_id_check : check the id of data path and req path
//bit[29] R-RW 0~1 0 reg_clear_fifo : manually reset bit
//bit[28] R-RW 0~1 0 reg_vsync_rst : soft_rst auto reset enable
-//bit[27] R-RW 0~1 0 reg_update_addr : manually udpate start addr
+//bit[27] R-RW 0~1 0 reg_update_addr : manually update start addr
//bit[26] R-RW 0~1 0 reg_addr_auto : auto update start addr enable
//bit[25] R-RW 0~1 0 reg_keep_receive : data path keep receive
//bit[24:19] R-RW 0~63 0 reg_req_th : fifo_room > req_th, then send the request
@@ -21318,11 +21318,11 @@
//Bit 1: 0 reg_in_ds_rate_y // unsigned , RW, default = 2 Input down-sample registers, normally AVG. value = [0,1,2], change according to input resolution. real rate is 2^reg_in_ds_rate
#define INTRP_PARAM ((0x4b01 << 2) + 0xff900000)
//Bit 31:26 reserved
-//Bit 25:21 reg_intep_phs_x_rtl // signed , RW, default = 0 Interpolation x phase used, could be negtive num, set by SW
-//Bit 20:16 reg_intep_phs_x_use // signed , RW, default = 0 Interpolation x phase used, could be negtive num, set by SW
+//Bit 25:21 reg_intep_phs_x_rtl // signed , RW, default = 0 Interpolation x phase used, could be negative num, set by SW
+//Bit 20:16 reg_intep_phs_x_use // signed , RW, default = 0 Interpolation x phase used, could be negative num, set by SW
//Bit 15:10 reserved
-//Bit 9: 5 reg_intep_phs_y_rtl // signed , RW, default = 0 Interpolation x phase used, could be negtive num, set by SW
-//Bit 4: 0 reg_intep_phs_y_use // signed , RW, default = 0 Interpolation y phase used, could be negtive num, set by SW
+//Bit 9: 5 reg_intep_phs_y_rtl // signed , RW, default = 0 Interpolation x phase used, could be negative num, set by SW
+//Bit 4: 0 reg_intep_phs_y_use // signed , RW, default = 0 Interpolation y phase used, could be negative num, set by SW
#define DCTR_BGRID_PARAM1 ((0x4b02 << 2) + 0xff900000)
//Bit 31:26 reserved
//Bit 25:16 reg_grd_xnum // unsigned , RW, default = 80 number of grid in horizontal dimension, value = [0-80]
@@ -22196,7 +22196,7 @@
//Bit 3: 2, reg_nr_cti_blend_mode : blend mode of nr and lti result: 0: nr; 1:cti; 2: (nr+cti)/2; 3:cti + dlt_nr . unsigned , default = 1
//Bit 1: 0, reg_nr_lti_blend_mode : blend mode of nr and lti result: 0: nr; 1:lti; 2: (nr+lti)/2; 3:lti + dlt_nr . unsigned , default = 2
////////////////////////////////////////////////////////////////////////////////
-// new ti regsters from here
+// new ti registers from here
////////////////////////////////////////////////////////////////////////////////
#define LTI_DIR_CORE_ALPHA ((0x502a << 2) + 0xff900000)
//Bit 31:30, reserved
@@ -22497,7 +22497,7 @@
//Bit 23:16, reg_sr3_pk_hp_hvcon_replace8lv_gain //u8: gain to local variant before calculating the hv gain for peaking, normalized to 32 as "1" default = 32;
//Bit 15:8, reg_sr3_pk_bp_hvcon_replace8lv_gain //u8: gain to local variant before calculating the hv gain for peaking, normalized to 32 as "1" default = 32;
//Bit 7, reg_sr3_sad_intlev_mode //u1: interleave detection xerr mode: 0 max; 1:sum default=1
-//Bit 6, reg_sr3_sad_intlev_mode1 //u1: mode 1 of using diagonal protection: 0: no digonal protection; 1: with diagonal protection default=1
+//Bit 6, reg_sr3_sad_intlev_mode1 //u1: mode 1 of using diagonal protection: 0: no diagonal protection; 1: with diagonal protection default=1
//Bit 5:0, reg_sr3_sad_intlev_gain //u6: interleave detection for sad gain applied, normalized to 8 as 1 default=12
#define SHARP_DEJ_CTRL ((0x5064 << 2) + 0xff900000)
//Bit 31:4 reserved
@@ -22576,7 +22576,7 @@
#define SHARP_SR3_DERING_LUMA2PKGAIN_4TO6 ((0x506d << 2) + 0xff900000)
//Bit 31:24 reserved
//Bit 23:16 reg_sr3_dering_luma2pkgain6 // u8: rate1 (for bpcon>th1) of curve for dering pkgain based on LPF luma level. default =24
-//Bit 15:8 reg_sr3_dering_luma2pkgain5 // u8: rate0 (for bpcon<th0) of curve for dering pkgain based on LPF luma level. dfault =50
+//Bit 15:8 reg_sr3_dering_luma2pkgain5 // u8: rate0 (for bpcon<th0) of curve for dering pkgain based on LPF luma level. default =50
//Bit 7:0 reg_sr3_dering_luma2pkgain4 // u8: level limit(for bpcon>th1) of curve for dering pkgain based on LPF luma level. default =255
#define SHARP_SR3_DERING_LUMA2PKOS_0TO3 ((0x506e << 2) + 0xff900000)
//Bit 31:24 reg_sr3_dering_luma2pkos3 // u8: level limit(for th0<bpcon<th1) of curve for dering pkOS based on LPF luma level. default=255
@@ -22586,7 +22586,7 @@
#define SHARP_SR3_DERING_LUMA2PKOS_4TO6 ((0x506f << 2) + 0xff900000)
//Bit 31:24 reserved
//Bit 23:16 reg_sr3_dering_luma2pkos6 // u8: rate1 (for bpcon>th1) of curve for dering pkOS based on LPF luma level. default =24
-//Bit 15:8 reg_sr3_dering_luma2pkos5 // u8: rate0 (for bpcon<th0) of curve for dering pkOS based on LPF luma level. dfault =50
+//Bit 15:8 reg_sr3_dering_luma2pkos5 // u8: rate0 (for bpcon<th0) of curve for dering pkOS based on LPF luma level. default =50
//Bit 7:0 reg_sr3_dering_luma2pkos4 // u8: level limit(for bpcon>th1) of curve for dering pkOS based on LPF luma level. default =255
#define SHARP_SR3_DERING_GAINVS_MADSAD ((0x5070 << 2) + 0xff900000)
//Bit 31:28 reg_sr3_dering_gainvs_maxsad7 //u4: pkgain vs maxsad value, 8 node interpolations, default = 0
@@ -22633,7 +22633,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 1 debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 1 debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -22903,8 +22903,8 @@
//Bit 31:12 reserved
//Bit 11:10 reg_fmeter_vwin_mm //u2, vertical window size, 0:1 cloumn, 1:3cloumn, 2or3: 5cloumn .unsigned , default = 0
//Bit 9 : 8 reg_fmeter_hwin_mm //u2, horizontal window size, 0:1x7, 1:1x9, 2or3: 1x11 .unsigned , default = 0
-//Bit 7 reg_fmeter_d2_mode //u1, selectino filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
-//Bit 6 reg_fmeter_v2_mode //u1, selectino filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 7 reg_fmeter_d2_mode //u1, selection filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 6 reg_fmeter_v2_mode //u1, selection filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
//Bit 5: 4 reg_fmeter_h2_mode //u2, selection filter H2, 0: [0 0 0 -2 0 0 2 0 0], 1: [-2 0 0 0 2], 2or3: [0-2 0 0 0 0 0 2 0] .unsigned , default = 0
//Bit 3: 1 reserved
//Bit 0 reg_freq_meter_en //u1, freq meter enable .unsigned , default = 0
@@ -26215,7 +26215,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -26383,7 +26383,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -26551,7 +26551,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -26719,7 +26719,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
diff --git a/demos/amlogic/n200/include/t5w/secure_apb.h b/demos/amlogic/n200/include/t5w/secure_apb.h
index 6d4cc8d..7d5ff0c 100644
--- a/demos/amlogic/n200/include/t5w/secure_apb.h
+++ b/demos/amlogic/n200/include/t5w/secure_apb.h
@@ -6800,18 +6800,18 @@
#define EARCTX_SPDIFOUT_PREAMB (0xff603400 + (0x006 << 2))
#define SEC_EARCTX_SPDIFOUT_PREAMB (0xff603400 + (0x006 << 2))
#define P_EARCTX_SPDIFOUT_PREAMB (volatile uint32_t *)(0xff603400 + (0x006 << 2))
-//Bit 31, reg_premable_Z_set ,default = 0,user 8'b11101000 1 user 7:0
-//Bit 30, reg_premable_Y_set ,default = 0,user 8'b11100100 1 user 15:8
-//Bit 29, reg_premable_X_set ,default = 0,user 8'b11100010 1 user 23:16
+//Bit 31, reg_preamble_Z_set ,default = 0,user 8'b11101000 1 user 7:0
+//Bit 30, reg_preamble_Y_set ,default = 0,user 8'b11100100 1 user 15:8
+//Bit 29, reg_preamble_X_set ,default = 0,user 8'b11100010 1 user 23:16
//Bit 28:24, reserved
-//Bit 23:16, reg_premable_X_value ,default = 0
-//Bit 15:8, reg_premable_Y_value ,default = 0
-//Bit 7:0, reg_premable_Z_value ,default = 0
+//Bit 23:16, reg_preamble_X_value ,default = 0
+//Bit 15:8, reg_preamble_Y_value ,default = 0
+//Bit 7:0, reg_preamble_Z_value ,default = 0
#define EARCTX_SPDIFOUT_SWAP (0xff603400 + (0x007 << 2))
#define SEC_EARCTX_SPDIFOUT_SWAP (0xff603400 + (0x007 << 2))
#define P_EARCTX_SPDIFOUT_SWAP (volatile uint32_t *)(0xff603400 + (0x007 << 2))
//Bit 31:16, reg_hold_cnt ,default = 0,hold start cnt ,valid when reg_hold_for_tdm set 1
-//Bit 15, reg_init_send_en ,default = 0,send 01 sequence some times after intial done from frddr set
+//Bit 15, reg_init_send_en ,default = 0,send 01 sequence some times after initial done from frddr set
//Bit 14:0, reg_init_send_cnt ,default = 0,send 01 sequence time ,valid when reg_init_send_en set 1
#define EARCTX_ERR_CORRT_CTRL0 (0xff603400 + (0x008 << 2))
#define SEC_EARCTX_ERR_CORRT_CTRL0 (0xff603400 + (0x008 << 2))
@@ -6866,7 +6866,7 @@
//Bit 21, reg_data_sel ,default = 0,//data sel: 0 data 1 reg_mute_data_value
//Bit 20:19, reg_ubit_sel ,default = 0,//userBit sel: 0 data 1 reg_value 2 fifo data
//Bit 18, reg_vbit_sel ,default = 0,//validBit sel: 0 data 1 reg_value
-//Bit 17, reg_chst_sel ,default = 0,//chanel status sel: 0 data 1 reg_value
+//Bit 17, reg_chst_sel ,default = 0,//channel status sel: 0 data 1 reg_value
//Bit 16, reg_ubit_fifo_less_irq_en ,default = 0,fifo_less_thd irq enable
//Bit 15:8, reg_ubit_fifo_start_thd ,default = 0,start transmit iu after fifo level greater than this value
//Bit 7:0, reg_ubit_fifo_less_thd ,default = 0,generate irq,when fifo level less than this value
@@ -7367,22 +7367,22 @@
#define EARC_RX_CMDC_STATUS6 (0xff603800 + (0x02d << 2))
#define SEC_EARC_RX_CMDC_STATUS6 (0xff603800 + (0x02d << 2))
#define P_EARC_RX_CMDC_STATUS6 (volatile uint32_t *)(0xff603800 + (0x02d << 2))
-//Bit 31, ro_idle2_int unsigned, RO, dfault =0
-//Bit 30, ro_idle1_int unsigned, RO, dfault =0
-//Bit 29, ro_disc2_int unsigned, RO, dfault =0
-//Bit 28, ro_disc1_int unsigned, RO, dfault =0
-//Bit 27, ro_earc_int unsigned, RO, dfault =0
-//Bit 26, ro_hb_status_int unsigned, RO, dfault =0
-//Bit 25, ro_losthb_int unsigned, RO, dfault =0
-//Bit 24, ro_timeout_int unsigned, RO, dfault =0
-//Bit 23, ro_status_ch_int unsigned, RO, dfault =0
-//Bit 22, ro_int_rec_invalid_id unsigned, RO, dfault =0
-//Bit 21, ro_int_rec_invalid_offset unsigned, RO, dfault =0
-//Bit 20, ro_int_rec_unexp unsigned, RO, dfault =0
-//Bit 19, ro_int_rec_ecc_err unsigned, RO, dfault =0
-//Bit 18, ro_int_rec_parity_err unsigned, RO, dfault =0
-//Bit 17, ro_int_recv_packet unsigned, RO, dfault =0
-//Bit 16, ro_int_rec_time_out unsigned, RO, dfault =0
+//Bit 31, ro_idle2_int unsigned, RO, default =0
+//Bit 30, ro_idle1_int unsigned, RO, default =0
+//Bit 29, ro_disc2_int unsigned, RO, default =0
+//Bit 28, ro_disc1_int unsigned, RO, default =0
+//Bit 27, ro_earc_int unsigned, RO, default =0
+//Bit 26, ro_hb_status_int unsigned, RO, default =0
+//Bit 25, ro_losthb_int unsigned, RO, default =0
+//Bit 24, ro_timeout_int unsigned, RO, default =0
+//Bit 23, ro_status_ch_int unsigned, RO, default =0
+//Bit 22, ro_int_rec_invalid_id unsigned, RO, default =0
+//Bit 21, ro_int_rec_invalid_offset unsigned, RO, default =0
+//Bit 20, ro_int_rec_unexp unsigned, RO, default =0
+//Bit 19, ro_int_rec_ecc_err unsigned, RO, default =0
+//Bit 18, ro_int_rec_parity_err unsigned, RO, default =0
+//Bit 17, ro_int_recv_packet unsigned, RO, default =0
+//Bit 16, ro_int_rec_time_out unsigned, RO, default =0
//Bit 15:0, reserved
//
// Closing file: earc_rx_cmdc.h
@@ -7564,10 +7564,10 @@
//Bit 31, reg_work_enable unsigned, default = 0, dmac user bit decode enable
//Bit 30:24, reg_iu_sync unsigned, default = 0, iu sync value
//Bit 23:16, reg_fifo_thd unsigned, default = 0, generate irq when fifo level pass some threshold
-//Bit 15, reg_max_dist_en unsigned, default = 0, max distance bewteen IUs to set lost
+//Bit 15, reg_max_dist_en unsigned, default = 0, max distance between IUs to set lost
//Bit 14, reg_iu_sync_en unsigned, default = 0, iu sync code enable 0 : all iu to fifo 1 only sync iu packet to fifo
//Bit 13:12, reg_user_lr unsigned, default = 0, 00 off 01 use l channel userbit 10 use r channel userbit 11 user lr channel userbit
-//Bit 11:8, reg_max_dist unsigned, default = 0, max distance bewteen IUs value
+//Bit 11:8, reg_max_dist unsigned, default = 0, max distance between IUs value
//Bit 7, reg_fifo_thd_en unsigned, default = 0, fifo_thd irq enable
//Bit 6, reg_fifo_lost_init_en unsigned, default = 0, when lost,initial fifo
//Bit 5, reg_fifo_init unsigned, default = 0, fifo initial
diff --git a/demos/amlogic/n200/include/t5w/t5w_mmc_reg.h b/demos/amlogic/n200/include/t5w/t5w_mmc_reg.h
index 2cd9c5a..a0d47a8 100644
--- a/demos/amlogic/n200/include/t5w/t5w_mmc_reg.h
+++ b/demos/amlogic/n200/include/t5w/t5w_mmc_reg.h
@@ -271,14 +271,14 @@
//bit 10 force to disable the clock of dfi command generation
//bit 9 force to disable the clock of dram controller
//bit 8 force to disable the clock of dfi data path.
- //bit 7. force to disalbe the clock of write rsp generation.
- //bit 6. force to disalbe the clock of read rsp generation.
- //bit 5. force to disalbe the clock of command filter.
- //bit 4. force to disalbe the clock of write reorder buffer.
- //bit 3. force to disalbe the clock of write data buffer.
- //bit 2. force to disalbe the clock of read reorder buffer.
- //bit 1. force to disalbe the clock of read canvas.
- //bit 0. force to disalbe the clock of write canvas.
+ //bit 7. force to disable the clock of write rsp generation.
+ //bit 6. force to disable the clock of read rsp generation.
+ //bit 5. force to disable the clock of command filter.
+ //bit 4. force to disable the clock of write reorder buffer.
+ //bit 3. force to disable the clock of write data buffer.
+ //bit 2. force to disable the clock of read reorder buffer.
+ //bit 1. force to disable the clock of read canvas.
+ //bit 0. force to disable the clock of write canvas.
#define DMC_MON_CTRL0 ((0x0020 << 2) + 0xff638000)
//bit 31. qos_mon_en. write 1 to trigger the enable.
@@ -304,7 +304,7 @@
//which goes to 16bits ddr. unit:64bits
#define DMC_MON0_CTRL ((0x0025 << 2) + 0xff638000)
- //BW MONTIOR 0 address range control.
+ //BW MONITOR 0 address range control.
//start address <= AXI address[31:16] <= end address
//bit 31:16 End address[31:16]
//bit 15:0. start address[31:16]
@@ -1116,7 +1116,7 @@
//bit 31:16 : range end address.
//bit 15:0 : range start address
#define DMC_PROT0_CTRL ((0x00d1 << 2) + 0xff638000)
- //bit 23:16. each bit to eanble one of the 8 ambus channal for the protection function.
+ //bit 23:16. each bit to enable one of the 8 ambus channal for the protection function.
//bit 15:0 each bit to enable one of the 15 channel input for the protection function.
#define DMC_PROT0_CTRL1 ((0x00d2 << 2) + 0xff638000)
//bit 26. protection 0 read access protection enable.
@@ -1131,7 +1131,7 @@
//bit 31:16 : range end address.
//bit 15:0 : range start address
#define DMC_PROT1_CTRL ((0x00d4 << 2) + 0xff638000)
- //bit 23:16. each bit to eanble one of the 8 ambus channal for the protection function.
+ //bit 23:16. each bit to enable one of the 8 ambus channal for the protection function.
//bit 15:0 each bit to enable one of the 15 channel input for the protection function.
#define DMC_PROT1_CTRL1 ((0x00d5 << 2) + 0xff638000)
//bit 26. protection range 1 read access protection enable bit.
@@ -1238,37 +1238,37 @@
//bit 15:0. the third cycle.
#define DMC_TEST_WD0 ((0x0010 << 2) + 0xff639800)
- // write data 0 for write command. also for read back data comparision.
+ // write data 0 for write command. also for read back data comparison.
#define DMC_TEST_WD1 ((0x0011 << 2) + 0xff639800)
- // write data 1 for write command. also for read back data comparision.
+ // write data 1 for write command. also for read back data comparison.
#define DMC_TEST_WD2 ((0x0012 << 2) + 0xff639800)
- // write data 2 for write command. also for read back data comparision.
+ // write data 2 for write command. also for read back data comparison.
#define DMC_TEST_WD3 ((0x0013 << 2) + 0xff639800)
- // write data 3 for write command. also for read back data comparision.
+ // write data 3 for write command. also for read back data comparison.
#define DMC_TEST_WD4 ((0x0014 << 2) + 0xff639800)
- // write data 4 for write command. also for read back data comparision.
+ // write data 4 for write command. also for read back data comparison.
#define DMC_TEST_WD5 ((0x0015 << 2) + 0xff639800)
- // write data 5 for write command. also for read back data comparision.
+ // write data 5 for write command. also for read back data comparison.
#define DMC_TEST_WD6 ((0x0016 << 2) + 0xff639800)
- // write data 6 for write command. also for read back data comparision.
+ // write data 6 for write command. also for read back data comparison.
#define DMC_TEST_WD7 ((0x0017 << 2) + 0xff639800)
- // write data 7 for write command. also for read back data comparision.
+ // write data 7 for write command. also for read back data comparison.
#define DMC_TEST_WD8 ((0x0018 << 2) + 0xff639800)
- // write data 8 for write command. also for read back data comparision.
+ // write data 8 for write command. also for read back data comparison.
#define DMC_TEST_WD9 ((0x0019 << 2) + 0xff639800)
- // write data 9 for write command. also for read back data comparision.
+ // write data 9 for write command. also for read back data comparison.
#define DMC_TEST_WD10 ((0x001a << 2) + 0xff639800)
- // write data 10 for write command. also for read back data comparision.
+ // write data 10 for write command. also for read back data comparison.
#define DMC_TEST_WD11 ((0x001b << 2) + 0xff639800)
- // write data 11 for write command. also for read back data comparision.
+ // write data 11 for write command. also for read back data comparison.
#define DMC_TEST_WD12 ((0x001c << 2) + 0xff639800)
- // write data 12 for write command. also for read back data comparision.
+ // write data 12 for write command. also for read back data comparison.
#define DMC_TEST_WD13 ((0x001d << 2) + 0xff639800)
- // write data 13 for write command. also for read back data comparision.
+ // write data 13 for write command. also for read back data comparison.
#define DMC_TEST_WD14 ((0x001e << 2) + 0xff639800)
- // write data 14 for write command. also for read back data comparision.
+ // write data 14 for write command. also for read back data comparison.
#define DMC_TEST_WD15 ((0x001f << 2) + 0xff639800)
- // write data 15 for write command. also for read back data comparision.
+ // write data 15 for write command. also for read back data comparison.
#define DMC_TEST_RD0 ((0x0020 << 2) + 0xff639800)
// the read back data 0. if error happens, it would capture the first error data.
diff --git a/demos/amlogic/n200/include/t7/register.h b/demos/amlogic/n200/include/t7/register.h
index 87fa10a..e6042e0 100644
--- a/demos/amlogic/n200/include/t7/register.h
+++ b/demos/amlogic/n200/include/t7/register.h
@@ -17018,7 +17018,7 @@
// 1=ABH read request burst size 24;
// 2=ABH read request burst size 32;
// 3=ABH read request burst size 48.
-// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logics except register.
+// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logic except register.
// Bit 0 RW ctrl_free_clk_enable. 0=Default, Enable clock gating. 1=No clock gating, enable free clock.
#define RDMA_CTRL ((0x1114 << 2) + 0xff000000)
// Read only.
@@ -21066,9 +21066,9 @@
// Bit 15:13 v0_gofld_sel, 000: display go_field, 001: DI pre_frame_rst, 010: vdin0 go_field, 011: vdin1 go_field, otherwise: force go_field by
// reg_v0_go_field(bit19)
// Bit 12:6 hole_lines for d2d3 depth read interface
-// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 fomart output), 2'b10: scale output, otherwise nothing as v1
+// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 format output), 2'b10: scale output, otherwise nothing as v1
// Bit 3 use_vdin_eol, if true, use vdin eol as the v0_eol, otherwise using length to get the v0_eol
-// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 fomart output), 101: vpp scale output
+// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 format output), 101: vpp scale output
//
// `define D2D3_INTF_CTRL0 8'h09
#define VD1_AFBCD0_MISC_CTRL ((0x1a0a << 2) + 0xff000000)
@@ -21081,7 +21081,7 @@
// OSD1 registers 0x10-0x2f
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -21208,7 +21208,7 @@
// OSD2 registers 0x30-0x4f 0x64 -0x67
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -21585,7 +21585,7 @@
//Bit 12:0 coef21
#define VIU_OSD1_MATRIX_COEF20_21 ((0x1a94 << 2) + 0xff000000)
//Bit 31:30 mat_clmod
-//Bit 18:16 mat_convers
+//Bit 18:16 mat_conversion
//Bit 12:0 mat_coef42
#define VIU_OSD1_MATRIX_COLMOD_COEF42 ((0x1a95 << 2) + 0xff000000)
//Bit 26:16 offset0
@@ -27342,8 +27342,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE1 ((0x27a6 << 2) + 0xff000000)
@@ -27355,8 +27355,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE2 ((0x27a7 << 2) + 0xff000000)
@@ -27368,8 +27368,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE3 ((0x27a8 << 2) + 0xff000000)
@@ -27381,8 +27381,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE4 ((0x27a9 << 2) + 0xff000000)
@@ -27394,8 +27394,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_WR_MODE0 ((0x27aa << 2) + 0xff000000)
@@ -27407,8 +27407,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_WR_MODE1 ((0x27ab << 2) + 0xff000000)
@@ -27420,8 +27420,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_WR_MODE2 ((0x27ac << 2) + 0xff000000)
@@ -27433,8 +27433,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_STAT ((0x27ad << 2) + 0xff000000)
@@ -36240,8 +36240,8 @@
//Bit 31:12 reserved
//Bit 11:10 reg_fmeter_vwin_mm //u2, vertical window size, 0:1 cloumn, 1:3cloumn, 2or3: 5cloumn .unsigned , default = 0
//Bit 9 : 8 reg_fmeter_hwin_mm //u2, horizontal window size, 0:1x7, 1:1x9, 2or3: 1x11 .unsigned , default = 0
-//Bit 7 reg_fmeter_d2_mode //u1, selectino filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
-//Bit 6 reg_fmeter_v2_mode //u1, selectino filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 7 reg_fmeter_d2_mode //u1, selection filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 6 reg_fmeter_v2_mode //u1, selection filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
//Bit 5: 4 reg_fmeter_h2_mode //u2, selection filter H2, 0: [0 0 0 -2 0 0 2 0 0], 1: [-2 0 0 0 2], 2or3: [0-2 0 0 0 0 0 2 0] .unsigned , default = 0
//Bit 3: 1 reserved
//Bit 0 reg_freq_meter_en //u1, freq meter enable .unsigned , default = 0
diff --git a/demos/amlogic/n200/include/t7/register_revc.h b/demos/amlogic/n200/include/t7/register_revc.h
index c811f57..7e6d39b 100644
--- a/demos/amlogic/n200/include/t7/register_revc.h
+++ b/demos/amlogic/n200/include/t7/register_revc.h
@@ -224,7 +224,7 @@
//bit 5. LPDT data endian. 1 = transfer the high bit first. 0 : transfer the low bit first.
//bit 4. HS data endian.
//bit 3. force data byte lane in stop mode.
- //bit 2. force data byte lane 0 in reciever mode.
+ //bit 2. force data byte lane 0 in receiver mode.
//bit 1. write 1 to sync the txclkesc input. the internal logic have to use txclkesc to decide Txvalid and Txready.
//bit 0. enalbe the MIPI DSI PHY TxDDRClk.
#define MIPI_DSI_CHAN_CTRL ((0x0001 << 2) + 0xfe014000)
@@ -283,8 +283,8 @@
#define MIPI_DSI_WAKEUP_TIM ((0x0008 << 2) + 0xfe014000)
//TWAKEUP.
#define MIPI_DSI_LPOK_TIM ((0x0009 << 2) + 0xfe014000)
- //bit 31:0 when in RxULPS state, RX reciever is in sleep mode.
- //every MIPI_DSI_ULPS_CHECK period, the reciever would be enabled once, and waiting this timer period to get the stable input.
+ //bit 31:0 when in RxULPS state, RX receiver is in sleep mode.
+ //every MIPI_DSI_ULPS_CHECK period, the receiver would be enabled once, and waiting this timer period to get the stable input.
#define MIPI_DSI_LP_WCHDOG ((0x000a << 2) + 0xfe014000)
//bit 31:0 watch dog timer for MIPI DSI LP receive state.
#define MIPI_DSI_ANA_CTRL ((0x000b << 2) + 0xfe014000)
@@ -295,7 +295,7 @@
#define MIPI_DSI_TURN_WCHDOG ((0x000d << 2) + 0xfe014000)
//bit 31:0 watch dog timer for lane 0 LP turn around waiting time.
#define MIPI_DSI_ULPS_CHECK ((0x000e << 2) + 0xfe014000)
- //bit 31:0 when Lane0 in LP recieve state, if the another side sent Low power command, using this timer to enable Tcheck the another size wakeup nor not.
+ //bit 31:0 when Lane0 in LP receive state, if the another side sent Low power command, using this timer to enable Tcheck the another size wakeup nor not.
#define MIPI_DSI_TEST_CTRL0 ((0x000f << 2) + 0xfe014000)
#define MIPI_DSI_TEST_CTRL1 ((0x0010 << 2) + 0xfe014000)
//========================================================================
@@ -316,7 +316,7 @@
//bit 5. LPDT data endian. 1 = transfer the high bit first. 0 : transfer the low bit first.
//bit 4. HS data endian.
//bit 3. force data byte lane in stop mode.
- //bit 2. force data byte lane 0 in reciever mode.
+ //bit 2. force data byte lane 0 in receiver mode.
//bit 1. write 1 to sync the txclkesc input. the internal logic have to use txclkesc to decide Txvalid and Txready.
//bit 0. enalbe the MIPI DSI PHY TxDDRClk.
#define MIPI_DSI_B_CHAN_CTRL ((0x0001 << 2) + 0xfe016000)
@@ -375,8 +375,8 @@
#define MIPI_DSI_B_WAKEUP_TIM ((0x0008 << 2) + 0xfe016000)
//TWAKEUP.
#define MIPI_DSI_B_LPOK_TIM ((0x0009 << 2) + 0xfe016000)
- //bit 31:0 when in RxULPS state, RX reciever is in sleep mode.
- //every MIPI_DSI_ULPS_CHECK period, the reciever would be enabled once, and waiting this timer period to get the stable input.
+ //bit 31:0 when in RxULPS state, RX receiver is in sleep mode.
+ //every MIPI_DSI_ULPS_CHECK period, the receiver would be enabled once, and waiting this timer period to get the stable input.
#define MIPI_DSI_B_LP_WCHDOG ((0x000a << 2) + 0xfe016000)
//bit 31:0 watch dog timer for MIPI DSI LP receive state.
#define MIPI_DSI_B_ANA_CTRL ((0x000b << 2) + 0xfe016000)
@@ -387,7 +387,7 @@
#define MIPI_DSI_B_TURN_WCHDOG ((0x000d << 2) + 0xfe016000)
//bit 31:0 watch dog timer for lane 0 LP turn around waiting time.
#define MIPI_DSI_B_ULPS_CHECK ((0x000e << 2) + 0xfe016000)
- //bit 31:0 when Lane0 in LP recieve state, if the another side sent Low power command, using this timer to enable Tcheck the another size wakeup nor not.
+ //bit 31:0 when Lane0 in LP receive state, if the another side sent Low power command, using this timer to enable Tcheck the another size wakeup nor not.
#define MIPI_DSI_B_TEST_CTRL0 ((0x000f << 2) + 0xfe016000)
#define MIPI_DSI_B_TEST_CTRL1 ((0x0010 << 2) + 0xfe016000)
//========================================================================
@@ -5357,16 +5357,16 @@
//Bit 6:4, reg_frddr_type ,default = 0
//Bit 3:0, reserved
#define EARCTX_SPDIFOUT_PREAMB ((0x0006 << 2) + 0xfe333400)
-//Bit 31, reg_premable_Z_set ,default = 0,user 8'b11101000 1 user 7:0
-//Bit 30, reg_premable_Y_set ,default = 0,user 8'b11100100 1 user 15:8
-//Bit 29, reg_premable_X_set ,default = 0,user 8'b11100010 1 user 23:16
+//Bit 31, reg_preamble_Z_set ,default = 0,user 8'b11101000 1 user 7:0
+//Bit 30, reg_preamble_Y_set ,default = 0,user 8'b11100100 1 user 15:8
+//Bit 29, reg_preamble_X_set ,default = 0,user 8'b11100010 1 user 23:16
//Bit 28:24, reserved
-//Bit 23:16, reg_premable_X_value ,default = 0
-//Bit 15:8, reg_premable_Y_value ,default = 0
-//Bit 7:0, reg_premable_Z_value ,default = 0
+//Bit 23:16, reg_preamble_X_value ,default = 0
+//Bit 15:8, reg_preamble_Y_value ,default = 0
+//Bit 7:0, reg_preamble_Z_value ,default = 0
#define EARCTX_SPDIFOUT_SWAP ((0x0007 << 2) + 0xfe333400)
//Bit 31:16, reg_hold_cnt ,default = 0,hold start cnt ,valid when reg_hold_for_tdm set 1
-//Bit 15, reg_init_send_en ,default = 0,send 01 sequence some times after intial done from frddr set
+//Bit 15, reg_init_send_en ,default = 0,send 01 sequence some times after initial done from frddr set
//Bit 14:0, reg_init_send_cnt ,default = 0,send 01 sequence time ,valid when reg_init_send_en set 1
#define EARCTX_ERR_CORRT_CTRL0 ((0x0008 << 2) + 0xfe333400)
//Bit 31:24, reserved
@@ -5411,7 +5411,7 @@
//Bit 21, reg_data_sel ,default = 0,//data sel: 0 data 1 reg_mute_data_value
//Bit 20:19, reg_ubit_sel ,default = 0,//userBit sel: 0 data 1 reg_value 2 fifo data
//Bit 18, reg_vbit_sel ,default = 0,//validBit sel: 0 data 1 reg_value
-//Bit 17, reg_chst_sel ,default = 0,//chanel status sel: 0 data 1 reg_value
+//Bit 17, reg_chst_sel ,default = 0,//channel status sel: 0 data 1 reg_value
//Bit 16, reg_ubit_fifo_less_irq_en ,default = 0,fifo_less_thd irq enable
//Bit 15:8, reg_ubit_fifo_start_thd ,default = 0,start transmit iu after fifo level greater than this value
//Bit 7:0, reg_ubit_fifo_less_thd ,default = 0,generate irq,when fifo level less than this value
@@ -5762,22 +5762,22 @@
#define EARC_RX_CMDC_STATUS5 ((0x002c << 2) + 0xfe333800)
//Bit 31:0, ro_cmdc_status5 unsigned, RO, default = 0,
#define EARC_RX_CMDC_STATUS6 ((0x002d << 2) + 0xfe333800)
-//Bit 31, ro_idle2_int unsigned, RO, dfault =0
-//Bit 30, ro_idle1_int unsigned, RO, dfault =0
-//Bit 29, ro_disc2_int unsigned, RO, dfault =0
-//Bit 28, ro_disc1_int unsigned, RO, dfault =0
-//Bit 27, ro_earc_int unsigned, RO, dfault =0
-//Bit 26, ro_hb_status_int unsigned, RO, dfault =0
-//Bit 25, ro_losthb_int unsigned, RO, dfault =0
-//Bit 24, ro_timeout_int unsigned, RO, dfault =0
-//Bit 23, ro_status_ch_int unsigned, RO, dfault =0
-//Bit 22, ro_int_rec_invalid_id unsigned, RO, dfault =0
-//Bit 21, ro_int_rec_invalid_offset unsigned, RO, dfault =0
-//Bit 20, ro_int_rec_unexp unsigned, RO, dfault =0
-//Bit 19, ro_int_rec_ecc_err unsigned, RO, dfault =0
-//Bit 18, ro_int_rec_parity_err unsigned, RO, dfault =0
-//Bit 17, ro_int_recv_packet unsigned, RO, dfault =0
-//Bit 16, ro_int_rec_time_out unsigned, RO, dfault =0
+//Bit 31, ro_idle2_int unsigned, RO, default =0
+//Bit 30, ro_idle1_int unsigned, RO, default =0
+//Bit 29, ro_disc2_int unsigned, RO, default =0
+//Bit 28, ro_disc1_int unsigned, RO, default =0
+//Bit 27, ro_earc_int unsigned, RO, default =0
+//Bit 26, ro_hb_status_int unsigned, RO, default =0
+//Bit 25, ro_losthb_int unsigned, RO, default =0
+//Bit 24, ro_timeout_int unsigned, RO, default =0
+//Bit 23, ro_status_ch_int unsigned, RO, default =0
+//Bit 22, ro_int_rec_invalid_id unsigned, RO, default =0
+//Bit 21, ro_int_rec_invalid_offset unsigned, RO, default =0
+//Bit 20, ro_int_rec_unexp unsigned, RO, default =0
+//Bit 19, ro_int_rec_ecc_err unsigned, RO, default =0
+//Bit 18, ro_int_rec_parity_err unsigned, RO, default =0
+//Bit 17, ro_int_recv_packet unsigned, RO, default =0
+//Bit 16, ro_int_rec_time_out unsigned, RO, default =0
//Bit 15:0, reserved
//
// Closing file: ./earc_rx_cmdc.h
@@ -5920,10 +5920,10 @@
//Bit 31, reg_work_enable unsigned, default = 0, dmac user bit decode enable
//Bit 30:24, reg_iu_sync unsigned, default = 0, iu sync value
//Bit 23:16, reg_fifo_thd unsigned, default = 0, generate irq when fifo level pass some threshold
-//Bit 15, reg_max_dist_en unsigned, default = 0, max distance bewteen IUs to set lost
+//Bit 15, reg_max_dist_en unsigned, default = 0, max distance between IUs to set lost
//Bit 14, reg_iu_sync_en unsigned, default = 0, iu sync code enable 0 : all iu to fifo 1 only sync iu packet to fifo
//Bit 13:12, reg_user_lr unsigned, default = 0, 00 off 01 use l channel userbit 10 use r channel userbit 11 user lr channel userbit
-//Bit 11:8, reg_max_dist unsigned, default = 0, max distance bewteen IUs value
+//Bit 11:8, reg_max_dist unsigned, default = 0, max distance between IUs value
//Bit 7, reg_fifo_thd_en unsigned, default = 0, fifo_thd irq enable
//Bit 6, reg_fifo_lost_init_en unsigned, default = 0, when lost,initial fifo
//Bit 5, reg_fifo_init unsigned, default = 0, fifo initial
@@ -8530,7 +8530,7 @@
// Bit 19:14 -- des_2 ts pl state -- Read Only
// Bit 13:8 -- des ts pl state -- Read Only
// Bit 3:0 PID index to 8 PID to get key-set
-// auto increse after TS_PL_PID_DATA read/write
+// auto increase after TS_PL_PID_DATA read/write
#define TS_PL_PID_INDEX ((0x00f3 << 2) + 0xfe040000)
// Bit 13 -- PID match disble
// Bit 12:0 -- PID
@@ -8558,7 +8558,7 @@
// [3] General enable for the ciplus module
// [2] AES CBC disable (default should be 0 to enable AES CBC)
// [1] AES Enable
-// [0] DES Eanble
+// [0] DES Enable
#define CIPLUS_CONFIG ((0x00fd << 2) + 0xfe040000)
// bit[31:28] AES IV endian
// bit[27:24] AES message out endian
@@ -9085,7 +9085,7 @@
// To measure display slave's frame rate, we can use a reference clock to measure the duration of one of more edpite pulse(s).
// Measurement control is by register MIPI_DSI_TOP_MEAS_CNTL bit[9:0].
// Reference clock comes from clk_rst_tst.cts_dsi_meas_clk, and is defined by HIU register HHI_VDIN_MEAS_CLK_CNTL bit[23:12].
-// Mesurement result is in MIPI_DSI_TOP_MEAS_STAT_TE0 and MIPI_DSI_TOP_MEAS_STAT_TE1, as below:
+// Measurement result is in MIPI_DSI_TOP_MEAS_STAT_TE0 and MIPI_DSI_TOP_MEAS_STAT_TE1, as below:
// edpite_meas_count[47:0]: Number of reference clock cycles counted during one measure period (non-incremental measure), or
// during all measure periods so far (incremental measure).
// edpite_meas_count_n[3:0]:Number of measure periods has been done. Number can wrap over.
@@ -9098,7 +9098,7 @@
// To measure Host's frame rate, we can use a reference clock to measure the duration of one of more Vsync pulse(s).
// Measurement control is by register MIPI_DSI_TOP_MEAS_CNTL bit[19:10].
// Reference clock comes from clk_rst_tst.cts_dsi_meas_clk, and is defined by HIU register HHI_VDIN_MEAS_CLK_CNTL bit[23:12].
-// Mesurement result is in MIPI_DSI_TOP_MEAS_STAT_VS0 and MIPI_DSI_TOP_MEAS_STAT_VS1, as below:
+// Measurement result is in MIPI_DSI_TOP_MEAS_STAT_VS0 and MIPI_DSI_TOP_MEAS_STAT_VS1, as below:
// vsync_meas_count[47:0]: Number of reference clock cycles counted during one measure period (non-incremental measure), or
// during all measure periods so far (incremental measure).
// vsync_meas_count_n[3:0]: Number of measure periods has been done. Number can wrap over.
@@ -9292,7 +9292,7 @@
// To measure display slave's frame rate, we can use a reference clock to measure the duration of one of more edpite pulse(s).
// Measurement control is by register MIPI_DSI_B_TOP_MEAS_CNTL bit[9:0].
// Reference clock comes from clk_rst_tst.cts_dsi_meas_clk, and is defined by HIU register HHI_VDIN_MEAS_CLK_CNTL bit[23:12].
-// Mesurement result is in MIPI_DSI_B_TOP_MEAS_STAT_TE0 and MIPI_DSI_B_TOP_MEAS_STAT_TE1, as below:
+// Measurement result is in MIPI_DSI_B_TOP_MEAS_STAT_TE0 and MIPI_DSI_B_TOP_MEAS_STAT_TE1, as below:
// edpite_meas_count[47:0]: Number of reference clock cycles counted during one measure period (non-incremental measure), or
// during all measure periods so far (incremental measure).
// edpite_meas_count_n[3:0]:Number of measure periods has been done. Number can wrap over.
@@ -9305,7 +9305,7 @@
// To measure Host's frame rate, we can use a reference clock to measure the duration of one of more Vsync pulse(s).
// Measurement control is by register MIPI_DSI_B_TOP_MEAS_CNTL bit[19:10].
// Reference clock comes from clk_rst_tst.cts_dsi_meas_clk, and is defined by HIU register HHI_VDIN_MEAS_CLK_CNTL bit[23:12].
-// Mesurement result is in MIPI_DSI_B_TOP_MEAS_STAT_VS0 and MIPI_DSI_B_TOP_MEAS_STAT_VS1, as below:
+// Measurement result is in MIPI_DSI_B_TOP_MEAS_STAT_VS0 and MIPI_DSI_B_TOP_MEAS_STAT_VS1, as below:
// vsync_meas_count[47:0]: Number of reference clock cycles counted during one measure period (non-incremental measure), or
// during all measure periods so far (incremental measure).
// vsync_meas_count_n[3:0]: Number of measure periods has been done. Number can wrap over.
@@ -14200,7 +14200,7 @@
// 1=ABH read request burst size 24;
// 2=ABH read request burst size 32;
// 3=ABH read request burst size 48.
-// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logics except register.
+// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logic except register.
// Bit 0 RW ctrl_free_clk_enable. 0=Default, Enable clock gating. 1=No clock gating, enable free clock.
#define RDMA_CTRL ((0x1114 << 2) + 0xff000000)
// Read only.
@@ -14297,7 +14297,7 @@
//Bit 7:6, component0 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in
//Bit 5, input window selection function enable
//Bit 4, enable VDIN common data input, otherwise there will be no video data input
-//Bit 3:0 vdin selection, 1: mpeg_in from dram, 2: bt656 input, 3: component input, 4: tvdecoder input, 5: hdmi rx input, 6: digtial video input, 7: loopback from Viu1, 8: MIPI.
+//Bit 3:0 vdin selection, 1: mpeg_in from dram, 2: bt656 input, 3: component input, 4: tvdecoder input, 5: hdmi rx input, 6: digital video input, 7: loopback from Viu1, 8: MIPI.
#define VDIN_COM_CTRL0 ((0x1202 << 2) + 0xff000000)
//Bit 28:16 active_max_pix_cnt, readonly
//Bit 12:0 active_max_pix_cnt_shadow, readonly
@@ -15942,7 +15942,7 @@
//Bit 0 reg_ldc_gain_lut_wr // unsigned , RW, default = 0 1:software write 0:software read.
#define LDC_GAIN_LUT_CTRL1 ((0x1475 << 2) + 0xff000000)
//Bit 31: 1 reserved
-//Bit 0 reg_ldc_gain_lut_str // unsigned , RW, default = 0 0->1:one software write/read start,postive edge valid.
+//Bit 0 reg_ldc_gain_lut_str // unsigned , RW, default = 0 0->1:one software write/read start,positive edge valid.
#define LDC_ADJ_VS_CTRL ((0x1476 << 2) + 0xff000000)
//Bit 31:16 reserved
//Bit 15:0 reg_ldc_blk_intsty_calc_intvl // unsigned , RW, default = 200 delay for one block intensity calculation period
@@ -15957,7 +15957,7 @@
//Bit 26 reg_ldc_prt_func_en //unsigned , RW, default = 0 1: enable LDC output protect function 0:disable LDC output protect function
//Bit 25 reg_ldc_bl_input_sft_ctr_en //unsigned , RW, default = 0 1: software control backlight info write index enable
//Bit 24:23 reg_ldc_bl_input_sft_wr_idx //unsigned , RW, default = 0 backlight info write index, for debug only
-//Bit 22 reg_ldc_vsync_get_bl_info_en //unsigned , RW, default = 1 0:get backlight info every block line (no vsync interrupt) 1:get backlight info accroding to vsync
+//Bit 22 reg_ldc_vsync_get_bl_info_en //unsigned , RW, default = 1 0:get backlight info every block line (no vsync interrupt) 1:get backlight info according to vsync
//Bit 21:20 reg_ldc_hist_burst_len //unsigned , RW, default = 0 0:2 times 128bit 1:4 times 128bit 2,3:6 times 128bit
//Bit 19:18 reg_ldc_blk_intsty_burst_len //unsigned , RW, default = 0 0:2 times 128bit 1:4 times 128bit 2:6 times 128bit 3:8 times 128bit
//Bit 17 reg_ldc_vs_edge_sel //unsigned , RW, default = 1 1:posedge vs sync 0:negedge vs sync
@@ -16446,7 +16446,7 @@
//bit 15: 8, mtn_minth
//bit 7: 0, mtn_maxth
#define DI_MTN_1_CTRL5 ((0x1744 << 2) + 0xff000000)
-//bit 31:28, mtn_m1b_extnd
+//bit 31:28, mtn_m1b_extend
//bit 27:24, mtn_m1b_errod
//bit 21:20, mtn_mot_txt_mode
//bit 19:18, mtn_replace_cbyy
@@ -17292,7 +17292,7 @@
//bit 15:8, reg_ei_int_drtdelay2_notver_sadth
//bit 7:0, reg_ei_int_drtdelay2_vlddrt_sadth
#define DI_MTN_1_CTRL6 ((0x17a9 << 2) + 0xff000000)
-//bit 31:24, mtn_m1b_extnd
+//bit 31:24, mtn_m1b_extend
//bit 23:16, mtn_m1b_errod
//bit 15: 8, mtn_core_ykinter
//bit 7: 0, mtn_core_ckinter
@@ -18248,9 +18248,9 @@
// Bit 15:13 v0_gofld_sel, 000: display go_field, 001: DI pre_frame_rst, 010: vdin0 go_field, 011: vdin1 go_field, otherwise: force go_field by
// reg_v0_go_field(bit19)
// Bit 12:6 hole_lines for d2d3 depth read interface
-// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 fomart output), 2'b10: scale output, otherwise nothing as v1
+// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 format output), 2'b10: scale output, otherwise nothing as v1
// Bit 3 use_vdin_eol, if true, use vdin eol as the v0_eol, otherwise using length to get the v0_eol
-// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 fomart output), 101: vpp scale output
+// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 format output), 101: vpp scale output
//
// `define D2D3_INTF_CTRL0 8'h09
#define VD1_AFBCD0_MISC_CTRL ((0x1a0a << 2) + 0xff000000)
@@ -18263,7 +18263,7 @@
// OSD1 registers 0x10-0x2f
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -18390,7 +18390,7 @@
// OSD2 registers 0x30-0x4f 0x64 -0x67
//------------------------------------------------------------------------------
// Bit 31 Reserved
-// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logic;
// 0=use gated clock for low power.
// Bit 29 R, test_rd_dsr
// Bit 28 R, osd_done
@@ -20110,9 +20110,9 @@
// Bit 0 SMOKE1 preblend enable only when preblend osd1 is not enable
#define VPP_SMOKE_CTRL ((0x1d29 << 2) + 0xff000000)
//smoke can be used only when that blending is disable and then be used as smoke function
-//smoke1 for OSD1 chanel
-//smoke2 for OSD2 chanel
-//smoke3 for VD2 chanel
+//smoke1 for OSD1 channel
+//smoke2 for OSD2 channel
+//smoke3 for VD2 channel
//31:24 Y
//23:16 Cb
//15:8 Cr
@@ -21751,7 +21751,7 @@
//`define DI_IF0_GEN_REG3 8'h42
//bit 31:1, reversed
//bit 0, cntl_64bit_rev
-// di arbtration :
+// di arbitration :
// the segment is 8'h50-8'h5f
//
// Reading file: ./di_arb_axi_regs.h
@@ -21959,13 +21959,13 @@
//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
//Bit 19 reserved
-//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
//Bit 11 reserved
//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
@@ -22377,13 +22377,13 @@
//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
//Bit 19 reserved
-//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
//Bit 11 reserved
//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
@@ -24290,7 +24290,7 @@
#define VPU_VENC_RGN_CTRL ((0x2789 << 2) + 0xff000000)
#define VPU_VENC_RGN_RSIZE ((0x278a << 2) + 0xff000000)
#define VPU_DISP_WRAP_CTRL ((0x278b << 2) + 0xff000000)
-// vpu arbtration :
+// vpu arbitration :
// the segment is 8'h90-8'hc8
//
// Reading file: ./vpu_arb_axi_regs.h
@@ -24524,8 +24524,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE1 ((0x27a6 << 2) + 0xff000000)
@@ -24537,8 +24537,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE2 ((0x27a7 << 2) + 0xff000000)
@@ -24550,8 +24550,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE3 ((0x27a8 << 2) + 0xff000000)
@@ -24563,8 +24563,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_RD_MODE4 ((0x27a9 << 2) + 0xff000000)
@@ -24576,8 +24576,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
#define VPU_ASYNC_WR_MODE0 ((0x27aa << 2) + 0xff000000)
@@ -24589,8 +24589,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_WR_MODE1 ((0x27ab << 2) + 0xff000000)
@@ -24602,8 +24602,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_WR_MODE2 ((0x27ac << 2) + 0xff000000)
@@ -24615,8 +24615,8 @@
//Bit 10:9, arugt_sel unsigned , default = 0
// 00 : use auto fifo arugt generate the output arugt.
// 01 : use the register bit control
-// 00 : use the input arguent
-//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+// 00 : use the input argument
+//Bit 8, argument_cfg unsigned , default = 0 register argument control bit
//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
#define VPU_ASYNC_STAT ((0x27ad << 2) + 0xff000000)
@@ -26746,7 +26746,7 @@
// 0: unable; 1: enable, use neighboring mvs in refinement, default = 1
//Bit 11, reserved
//Bit 10, reg_mcdi_referrfrqchken
-// 0: unable; 1: enable, enable mv frquency check while finding min err in ref, default = 1
+// 0: unable; 1: enable, enable mv frequency check while finding min err in ref, default = 1
//Bit 9, reg_mcdi_refen
// 0: unable; 1: enable, enable mv refinement, default = 1
//Bit 8, reg_mcdi_horlineen
@@ -26830,7 +26830,7 @@
//Bit 19:16, reg_mcdi_chkedgedifthd0. thd0 for edge dif check (>=), default = 15
//Bit :15, reserved.
//Bit 14:10, reg_mcdi_chkedgechklen. total check length for edge check, 1~24 (>0), default = 24
-//Bit 9: 8, reg_mcdi_chkedgeedgesel. final edge select mode, 0: original start edge, 1: lpf start edge, 2: orignal start+end edge, 3: lpf start+end edge, default = 1
+//Bit 9: 8, reg_mcdi_chkedgeedgesel. final edge select mode, 0: original start edge, 1: lpf start edge, 2: original start+end edge, 3: lpf start+end edge, default = 1
//Bit 7: 3, reg_mcdi_chkedgesaddstgain. distance gain for sad calc while getting edges, default = 4
//Bit 2, reg_mcdi_chkedgechkmode. edge used in check mode, 0: original edge, 1: lpf edge, default = 1
//Bit 1, reg_mcdi_chkedgestartedge. edge mode for start edge, 0: original edge, 1: lpf edge, default = 0
@@ -26840,7 +26840,7 @@
//Bit 14:12, reg_mcdi_lmvvalidmode valid mode for lmv calc., 100b: use char det, 010b: use flt, 001b: use hori flg
//Bit 11:10, reg_mcdi_lmvgainmvmode four modes of mv selection for lmv weight calculation, default = 1
// 0: cur(x-3), lst(x-1,x,x+1); 1: cur(x-4,x-3), lst(x,x+1); 2: cur(x-5,x-4,x-3), lst(x-1,x,x+1,x+2,x+3); 3: cur(x-6,x-5,x-4,x-3), lst(x-1,x,x+1,x+2);
-//Bit 9, reg_mcdi_lmvinitmode initial lmvs at first row of input field, 0: intial value = 0; 1: inital = 32 (invalid), default = 0
+//Bit 9, reg_mcdi_lmvinitmode initial lmvs at first row of input field, 0: initial value = 0; 1: inital = 32 (invalid), default = 0
//Bit 8, reserved
//Bit 7: 4, reg_mcdi_lmvrt0 ratio of max mv, default = 5
//Bit 3: 0, reg_mcdi_lmvrt1 ratio of second max mv, default = 5
@@ -26953,15 +26953,15 @@
//Bit 3: 0, reg_mcdi_referrgmvgain. (locked) gmv gain for err calc. in ref, normalized to 8 as '1', default = 0
#define MCDI_REF_ERR_FRQ_CHK ((0x2f1d << 2) + 0xff000000)
//Bit 31:28, reserved
-//Bit 27:24, reg_mcdi_referrfrqgain. gain for mv frquency, normalized to 4 as '1', default = 10
+//Bit 27:24, reg_mcdi_referrfrqgain. gain for mv frequency, normalized to 4 as '1', default = 10
//Bit 23:21, reserved
-//Bit 20:16, reg_mcdi_referrfrqmax. max gain for mv frquency check, default = 31
+//Bit 20:16, reg_mcdi_referrfrqmax. max gain for mv frequency check, default = 31
//Bit 15, reserved
-//Bit 14:12, reg_mcdi_ref_errfrqmvdifthd2. mv dif threshold 2 (<) for mv frquency check, default = 3
+//Bit 14:12, reg_mcdi_ref_errfrqmvdifthd2. mv dif threshold 2 (<) for mv frequency check, default = 3
//Bit 11, reserved
-//Bit 10: 8, reg_mcdi_ref_errfrqmvdifthd1. mv dif threshold 1 (<) for mv frquency check, default = 2
+//Bit 10: 8, reg_mcdi_ref_errfrqmvdifthd1. mv dif threshold 1 (<) for mv frequency check, default = 2
//Bit 7, reserved
-//Bit 6: 4, reg_mcdi_ref_errfrqmvdifthd0. mv dif threshold 0 (<) for mv frquency check, default = 1
+//Bit 6: 4, reg_mcdi_ref_errfrqmvdifthd0. mv dif threshold 0 (<) for mv frequency check, default = 1
//Bit 3: 0, reserved
#define MCDI_QME_LPF_MSK ((0x2f1e << 2) + 0xff000000)
//Bit 31:28, reserved
@@ -29705,7 +29705,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 1 debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 1 debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -31668,13 +31668,13 @@
//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
//Bit 19 reserved
-//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
-//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: disable
//Bit 11 reserved
//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
@@ -31974,7 +31974,7 @@
//bit[30] R-RW 0~1 0 reg_id_check : check the id of data path and req path
//bit[29] R-RW 0~1 0 reg_clear_fifo : manually reset bit
//bit[28] R-RW 0~1 0 reg_vsync_rst : soft_rst auto reset enable
-//bit[27] R-RW 0~1 0 reg_update_addr : manually udpate start addr
+//bit[27] R-RW 0~1 0 reg_update_addr : manually update start addr
//bit[26] R-RW 0~1 0 reg_addr_auto : auto update start addr enable
//bit[25] R-RW 0~1 0 reg_keep_receive : data path keep receive
//bit[24:19] R-RW 0~63 0 reg_req_th : fifo_room > req_th, then send the request
@@ -32482,7 +32482,7 @@
//Bit 3: 2, reg_nr_cti_blend_mode : blend mode of nr and lti result: 0: nr; 1:cti; 2: (nr+cti)/2; 3:cti + dlt_nr . unsigned , default = 1
//Bit 1: 0, reg_nr_lti_blend_mode : blend mode of nr and lti result: 0: nr; 1:lti; 2: (nr+lti)/2; 3:lti + dlt_nr . unsigned , default = 2
////////////////////////////////////////////////////////////////////////////////
-// new ti regsters from here
+// new ti registers from here
////////////////////////////////////////////////////////////////////////////////
#define LTI_DIR_CORE_ALPHA ((0x502a << 2) + 0xff000000)
//Bit 31:30, reserved
@@ -32783,7 +32783,7 @@
//Bit 23:16, reg_sr3_pk_hp_hvcon_replace8lv_gain //u8: gain to local variant before calculating the hv gain for peaking, normalized to 32 as "1" default = 32;
//Bit 15:8, reg_sr3_pk_bp_hvcon_replace8lv_gain //u8: gain to local variant before calculating the hv gain for peaking, normalized to 32 as "1" default = 32;
//Bit 7, reg_sr3_sad_intlev_mode //u1: interleave detection xerr mode: 0 max; 1:sum default=1
-//Bit 6, reg_sr3_sad_intlev_mode1 //u1: mode 1 of using diagonal protection: 0: no digonal protection; 1: with diagonal protection default=1
+//Bit 6, reg_sr3_sad_intlev_mode1 //u1: mode 1 of using diagonal protection: 0: no diagonal protection; 1: with diagonal protection default=1
//Bit 5:0, reg_sr3_sad_intlev_gain //u6: interleave detection for sad gain applied, normalized to 8 as 1 default=12
#define SHARP_DEJ_CTRL ((0x5064 << 2) + 0xff000000)
//Bit 31:4 reserved
@@ -32862,7 +32862,7 @@
#define SHARP_SR3_DERING_LUMA2PKGAIN_4TO6 ((0x506d << 2) + 0xff000000)
//Bit 31:24 reserved
//Bit 23:16 reg_sr3_dering_luma2pkgain6 // u8: rate1 (for bpcon>th1) of curve for dering pkgain based on LPF luma level. default =24
-//Bit 15:8 reg_sr3_dering_luma2pkgain5 // u8: rate0 (for bpcon<th0) of curve for dering pkgain based on LPF luma level. dfault =50
+//Bit 15:8 reg_sr3_dering_luma2pkgain5 // u8: rate0 (for bpcon<th0) of curve for dering pkgain based on LPF luma level. default =50
//Bit 7:0 reg_sr3_dering_luma2pkgain4 // u8: level limit(for bpcon>th1) of curve for dering pkgain based on LPF luma level. default =255
#define SHARP_SR3_DERING_LUMA2PKOS_0TO3 ((0x506e << 2) + 0xff000000)
//Bit 31:24 reg_sr3_dering_luma2pkos3 // u8: level limit(for th0<bpcon<th1) of curve for dering pkOS based on LPF luma level. default=255
@@ -32872,7 +32872,7 @@
#define SHARP_SR3_DERING_LUMA2PKOS_4TO6 ((0x506f << 2) + 0xff000000)
//Bit 31:24 reserved
//Bit 23:16 reg_sr3_dering_luma2pkos6 // u8: rate1 (for bpcon>th1) of curve for dering pkOS based on LPF luma level. default =24
-//Bit 15:8 reg_sr3_dering_luma2pkos5 // u8: rate0 (for bpcon<th0) of curve for dering pkOS based on LPF luma level. dfault =50
+//Bit 15:8 reg_sr3_dering_luma2pkos5 // u8: rate0 (for bpcon<th0) of curve for dering pkOS based on LPF luma level. default =50
//Bit 7:0 reg_sr3_dering_luma2pkos4 // u8: level limit(for bpcon>th1) of curve for dering pkOS based on LPF luma level. default =255
#define SHARP_SR3_DERING_GAINVS_MADSAD ((0x5070 << 2) + 0xff000000)
//Bit 31:28 reg_sr3_dering_gainvs_maxsad7 //u4: pkgain vs maxsad value, 8 node interpolations, default = 0
@@ -32919,7 +32919,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 1 debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 1 debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -33422,8 +33422,8 @@
//Bit 31:12 reserved
//Bit 11:10 reg_fmeter_vwin_mm //u2, vertical window size, 0:1 cloumn, 1:3cloumn, 2or3: 5cloumn .unsigned , default = 0
//Bit 9 : 8 reg_fmeter_hwin_mm //u2, horizontal window size, 0:1x7, 1:1x9, 2or3: 1x11 .unsigned , default = 0
-//Bit 7 reg_fmeter_d2_mode //u1, selectino filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
-//Bit 6 reg_fmeter_v2_mode //u1, selectino filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 7 reg_fmeter_d2_mode //u1, selection filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 6 reg_fmeter_v2_mode //u1, selection filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
//Bit 5: 4 reg_fmeter_h2_mode //u2, selection filter H2, 0: [0 0 0 -2 0 0 2 0 0], 1: [-2 0 0 0 2], 2or3: [0-2 0 0 0 0 0 2 0] .unsigned , default = 0
//Bit 3: 1 reserved
//Bit 0 reg_freq_meter_en //u1, freq meter enable .unsigned , default = 0
@@ -36487,7 +36487,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -36656,7 +36656,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -36825,7 +36825,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -36994,7 +36994,7 @@
//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
-//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
//Bit 16 reserved
//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
@@ -37766,7 +37766,7 @@
//Bit 6 reg_dnlp_en // unsigned , RW, default = 0 enable dnlp contrast
//Bit 5 reg_pk_en // unsigned , RW, default = 0 enable peaking for sharpness
//Bit 4 reg_nr_en // unsigned , RW, default = 0 enable noise reduction for sharpness
-//Bit 3 reg_fmeter_en // unsigned , RW, default = 1 enable fmeter fucntion
+//Bit 3 reg_fmeter_en // unsigned , RW, default = 1 enable fmeter function
//Bit 2 reg_grph_en // unsigned , RW, default = 1 enable graphic statistic
//Bit 1: 0 reg_yhs_sta_en // unsigned , RW, default = 1
#define ISP_TOP_3A_STAT_CRTL ((0x0109 << 2) + 0xfe3b4000)
@@ -38202,7 +38202,7 @@
//Bit 11:10 reserved
//Bit 9: 8 reg_dpc_xphs_ofst // unsigned , RW, default = 1
//Bit 7: 5 reserved
-//Bit 4 reg_dpc_det_en // unsigned , RW, default = 1 1 = enable defect pixel detection, 0 = diable
+//Bit 4 reg_dpc_det_en // unsigned , RW, default = 1 1 = enable defect pixel detection, 0 = disable
//Bit 3: 1 reserved
//Bit 0 reg_dpc_cor_en // unsigned , RW, default = 1 1 = enable defect pixel correction, 0 = disable
#define ISP_DPC0_AVG_GAIN0 ((0x0261 << 2) + 0xfe3b4000)
@@ -38262,9 +38262,9 @@
//Bit 7: 0 reg_dpc_max_min_bias_thd // unsigned , RW, default = 20 is used to set the threshold between maximum standard bias and minimum one
#define ISP_DPC0_AVG_MOD ((0x0268 << 2) + 0xfe3b4000)
//Bit 31:24 reserved
-//Bit 23:10 reg_dpc_low_thd // unsigned , RW, default = 50 is used to set the low theshold for dp_x6
+//Bit 23:10 reg_dpc_low_thd // unsigned , RW, default = 50 is used to set the low threshold for dp_x6
//Bit 9: 8 reg_dpc_avg_mode // unsigned , RW, default = 3 0 = auto selection average value between avg6 and avg4,1 = avg6, 2 = avg4, 3 = avg8
-//Bit 7: 0 reg_dpc_avg_bias_thd // unsigned , RW, default = 40 it is used to set theshold for selecting the average value
+//Bit 7: 0 reg_dpc_avg_bias_thd // unsigned , RW, default = 40 it is used to set threshold for selecting the average value
#define ISP_DPC0_AVG_DEV ((0x0269 << 2) + 0xfe3b4000)
//Bit 31:30 reserved
//Bit 29:28 reg_dpc_avg_dev_sft // unsigned , RW, default = 3 it is used to set the avg_dev shift
@@ -38280,7 +38280,7 @@
//Bit 11: 0 reg_dpc_dev_dp_slope // unsigned , RW, default = 82 it is used to set the slope for deviation mapping
#define ISP_DPC0_X1_2_CTRL ((0x026b << 2) + 0xfe3b4000)
//Bit 31:22 reserved
-//Bit 21: 8 reg_dpc_low_thd_top // unsigned , RW, default = 50 is used to set the low theshold for top
+//Bit 21: 8 reg_dpc_low_thd_top // unsigned , RW, default = 50 is used to set the low threshold for top
//Bit 7: 3 reserved
//Bit 2: 0 reg_dpc_x2_rank_lim // unsigned , RW, default = 2 it is used to set the rank limit.
#define ISP_DPC0_X6_CTRL ((0x026c << 2) + 0xfe3b4000)
@@ -38296,7 +38296,7 @@
//Bit 15 reserved
//Bit 14:12 reg_dpc_vote_thd // unsigned , RW, default = 3 it is used to set the vote threshold.
//Bit 11 reserved
-//Bit 10: 8 reg_dpc_ud_mode // unsigned , RW, default = 4 it is used to set the mode for un-diretioanal estimation.0= auto,1=median,2= avg6, 3=avg4,4=avg8,
+//Bit 10: 8 reg_dpc_ud_mode // unsigned , RW, default = 4 it is used to set the mode for un-directional estimation.0= auto,1=median,2= avg6, 3=avg4,4=avg8,
//Bit 7: 5 reserved
//Bit 4 reg_dpc_highlight_en // unsigned , RW, default = 0 it is used to enable highlighting the defect pixels. 1= enbale, 0=disable
//Bit 3: 2 reserved
@@ -38744,7 +38744,7 @@
//Bit 11:10 reserved
//Bit 9: 8 reg_dpc_xphs_ofst // unsigned , RW, default = 1
//Bit 7: 5 reserved
-//Bit 4 reg_dpc_det_en // unsigned , RW, default = 1 1 = enable defect pixel detection, 0 = diable
+//Bit 4 reg_dpc_det_en // unsigned , RW, default = 1 1 = enable defect pixel detection, 0 = disable
//Bit 3: 1 reserved
//Bit 0 reg_dpc_cor_en // unsigned , RW, default = 1 1 = enable defect pixel correction, 0 = disable
#define ISP_DPC1_AVG_GAIN0 ((0x0361 << 2) + 0xfe3b4000)
@@ -38804,9 +38804,9 @@
//Bit 7: 0 reg_dpc_max_min_bias_thd // unsigned , RW, default = 20 is used to set the threshold between maximum standard bias and minimum one
#define ISP_DPC1_AVG_MOD ((0x0368 << 2) + 0xfe3b4000)
//Bit 31:24 reserved
-//Bit 23:10 reg_dpc_low_thd // unsigned , RW, default = 50 is used to set the low theshold for dp_x6
+//Bit 23:10 reg_dpc_low_thd // unsigned , RW, default = 50 is used to set the low threshold for dp_x6
//Bit 9: 8 reg_dpc_avg_mode // unsigned , RW, default = 3 0 = auto selection average value between avg6 and avg4,1 = avg6, 2 = avg4, 3 = avg8
-//Bit 7: 0 reg_dpc_avg_bias_thd // unsigned , RW, default = 40 it is used to set theshold for selecting the average value
+//Bit 7: 0 reg_dpc_avg_bias_thd // unsigned , RW, default = 40 it is used to set threshold for selecting the average value
#define ISP_DPC1_AVG_DEV ((0x0369 << 2) + 0xfe3b4000)
//Bit 31:30 reserved
//Bit 29:28 reg_dpc_avg_dev_sft // unsigned , RW, default = 3 it is used to set the avg_dev shift
@@ -38822,7 +38822,7 @@
//Bit 11: 0 reg_dpc_dev_dp_slope // unsigned , RW, default = 82 it is used to set the slope for deviation mapping
#define ISP_DPC1_X1_2_CTRL ((0x036b << 2) + 0xfe3b4000)
//Bit 31:22 reserved
-//Bit 21: 8 reg_dpc_low_thd_top // unsigned , RW, default = 50 is used to set the low theshold for top
+//Bit 21: 8 reg_dpc_low_thd_top // unsigned , RW, default = 50 is used to set the low threshold for top
//Bit 7: 3 reserved
//Bit 2: 0 reg_dpc_x2_rank_lim // unsigned , RW, default = 2 it is used to set the rank limit.
#define ISP_DPC1_X6_CTRL ((0x036c << 2) + 0xfe3b4000)
@@ -38838,7 +38838,7 @@
//Bit 15 reserved
//Bit 14:12 reg_dpc_vote_thd // unsigned , RW, default = 3 it is used to set the vote threshold.
//Bit 11 reserved
-//Bit 10: 8 reg_dpc_ud_mode // unsigned , RW, default = 4 it is used to set the mode for un-diretioanal estimation.0= auto,1=median,2= avg6, 3=avg4,4=avg8,
+//Bit 10: 8 reg_dpc_ud_mode // unsigned , RW, default = 4 it is used to set the mode for un-directional estimation.0= auto,1=median,2= avg6, 3=avg4,4=avg8,
//Bit 7: 5 reserved
//Bit 4 reg_dpc_highlight_en // unsigned , RW, default = 0 it is used to enable highlighting the defect pixels. 1= enbale, 0=disable
//Bit 3: 2 reserved
@@ -38938,7 +38938,7 @@
//Bit 31:18 reserved
//Bit 17:16 reg_inp_fmt_chn // unsigned , RW, default = 1 the data channels after input formatter, support (1+inp_fmt_chn) as 1/2/3/4
//Bit 15:13 reserved
-//Bit 12 reg_inp_fmt_diag_mux // unsigned , RW, default = 0 0: select 0 or (0,1), 1: select 1 or (1,0), ouput mux for diagonal split
+//Bit 12 reg_inp_fmt_diag_mux // unsigned , RW, default = 0 0: select 0 or (0,1), 1: select 1 or (1,0), output mux for diagonal split
//Bit 11: 8 reg_inp_fmt_split_sbit // unsigned , RW, default = 4 short exp bits split for combined split
//Bit 7: 6 reserved
//Bit 5: 4 reg_inp_fmt_split_mode // unsigned , RW, default = 0 0: bypass, 1: long/short split, 2or3: diag sum split for quadra, channel0 split mode for input formatter
@@ -39322,7 +39322,7 @@
//Bit 31:22 reserved
//Bit 21 reg_wdr_expcomb_maxavg_winsize // unsigned , RW, default = 1 5x5, 1: 5x9
//Bit 20:18 reg_wdr_expcomb_maxavg_mode // unsigned , RW, default = 3 original long and short data, 1: check G w/ BLC, 2: check G w/o BLC, 3: check G & C w/ BLC, 4: check G & C w/o BLC
-//Bit 17:14 reg_wdr_expcomb_maxavg_ratio // unsigned , RW, default = 4 indx calculated by ratio of max and avg, #/16, 0->using max, 16->using avg
+//Bit 17:14 reg_wdr_expcomb_maxavg_ratio // unsigned , RW, default = 4 index calculated by ratio of max and avg, #/16, 0->using max, 16->using avg
//Bit 13:10 reg_wdr_expcomb_slope_weight // unsigned , RW, default = 6 weight for exp combine
//Bit 9: 0 reg_wdr_expcomb_blend_slope // unsigned , RW, default = 0 slope for exp combine
#define ISP_WDR_EXPCOMB_SATTHD0 ((0x0537 << 2) + 0xfe3b4000)
@@ -39982,7 +39982,7 @@
//Bit 7: 0 reg_snr_bl_ratio // unsigned , RW, default = 192 adjest apl ,16 is "1"
#define ISP_SNR_SAD_CURV ((0x0908 << 2) + 0xfe3b4000)
//Bit 31:25 reserved
-//Bit 24 reg_snr_sad_th_mode // unsigned , RW, default = 0 of sad th calcuate, 0: avg and avg_l bland , 1: avg and avg_h bland
+//Bit 24 reg_snr_sad_th_mode // unsigned , RW, default = 0 of sad th calculate, 0: avg and avg_l bland , 1: avg and avg_h bland
//Bit 23:21 reserved
//Bit 20:16 reg_snr_sad_avg_alpha // unsigned , RW, default = 8 of avg when bland with avg_l or avg_h 16 is "1" (0-16)
//Bit 15: 8 reg_snr_sad_min_th // unsigned , RW, default = 255 threshold of sad min th
@@ -40210,13 +40210,13 @@
//Bit 28:24 reg_snr_lpf_mm_diff_ratio // unsigned , RW, default = 16 of min/max
//Bit 23:12 reg_snr_lpf_mm_diff_th // unsigned , RW, default = 1024 of min/max diff
//Bit 11: 0 reg_snr_lpf_max_th // unsigned , RW, default = 100 of max in calculate lpf
-#define ISP_SNR_STRENGHT ((0x092f << 2) + 0xfe3b4000)
+#define ISP_SNR_STRENGTH ((0x092f << 2) + 0xfe3b4000)
//Bit 31 reserved
//Bit 30:28 reg_snr_dbg_wt_sft // unsigned , RW, default = 2 weigh sum shift num
//Bit 27:20 reg_snr_wt_th // unsigned , RW, default = 64 of wt used to calculate count sum
//Bit 19:17 reserved
-//Bit 16:12 reg_snr_strenght_count_th // unsigned , RW, default = 16 of count sum reflect snr strenght
-//Bit 11: 0 reg_snr_strenght_wt_th // unsigned , RW, default = 1024 of wt sum reflect snr strenght
+//Bit 16:12 reg_snr_strength_count_th // unsigned , RW, default = 16 of count sum reflect snr strength
+//Bit 11: 0 reg_snr_strength_wt_th // unsigned , RW, default = 1024 of wt sum reflect snr strength
#define ISP_SNR_VAR_FLAT_LUMA_SCAL_0 ((0x0930 << 2) + 0xfe3b4000)
//Bit 31:24 reg_snr_var_flat_luma_gain_3 // unsigned , RW, default = 64
//Bit 23:16 reg_snr_var_flat_luma_gain_2 // unsigned , RW, default = 64
@@ -40390,23 +40390,23 @@
//Bit 17: 0 reserved
#define ISP_CUBICT_CHNMIXGAIN_LUT_0 ((0x0a02 << 2) + 0xfe3b4000)
//Bit 31:26 reserved
-//Bit 25:24 reg_chnmix_gain_0 // unsigned , RW, default = 1 gain to each channel data for mixxing
+//Bit 25:24 reg_chnmix_gain_0 // unsigned , RW, default = 1 gain to each channel data for mixing
//Bit 23: 0 reserved
#define ISP_CUBICT_CHNMIXGAIN_LUT_1 ((0x0a03 << 2) + 0xfe3b4000)
//Bit 31:26 reserved
-//Bit 25:24 reg_chnmix_gain_1 // unsigned , RW, default = 1 gain to each channel data for mixxing
+//Bit 25:24 reg_chnmix_gain_1 // unsigned , RW, default = 1 gain to each channel data for mixing
//Bit 23: 0 reserved
#define ISP_CUBICT_CHNMIXGAIN_LUT_2 ((0x0a04 << 2) + 0xfe3b4000)
//Bit 31:26 reserved
-//Bit 25:24 reg_chnmix_gain_2 // unsigned , RW, default = 1 gain to each channel data for mixxing
+//Bit 25:24 reg_chnmix_gain_2 // unsigned , RW, default = 1 gain to each channel data for mixing
//Bit 23: 0 reserved
#define ISP_CUBICT_CHNMIXGAIN_LUT_3 ((0x0a05 << 2) + 0xfe3b4000)
//Bit 31:26 reserved
-//Bit 25:24 reg_chnmix_gain_3 // unsigned , RW, default = 1 gain to each channel data for mixxing
+//Bit 25:24 reg_chnmix_gain_3 // unsigned , RW, default = 1 gain to each channel data for mixing
//Bit 23: 0 reserved
#define ISP_CUBICT_CHNMIXGAIN_LUT_4 ((0x0a06 << 2) + 0xfe3b4000)
//Bit 31:26 reserved
-//Bit 25:24 reg_chnmix_gain_4 // unsigned , RW, default = 1 gain to each channel data for mixxing
+//Bit 25:24 reg_chnmix_gain_4 // unsigned , RW, default = 1 gain to each channel data for mixing
//Bit 23: 0 reserved
// synopsys translate_off
// synopsys translate_on
@@ -42139,8 +42139,8 @@
#define ISP_DMS_CT_PARAM0 ((0x1006 << 2) + 0xfe3b4000)
//Bit 31:16 reserved
//Bit 15: 8 reg_ctran_coring // unsigned , RW, default = 30 coring to the color transition_level, ignore small color transition
-//Bit 7: 6 reg_ctran_h_dial_win // unsigned , RW, default = 2 horizontal dialation window size for ctran_h, 0: no dialation else (x+1)
-//Bit 5: 4 reg_ctran_v_dial_win // unsigned , RW, default = 2 horizontal dialation window size for ctran_v, 0: no dialation, else (x+1)
+//Bit 7: 6 reg_ctran_h_dial_win // unsigned , RW, default = 2 horizontal dilation window size for ctran_h, 0: no dilation else (x+1)
+//Bit 5: 4 reg_ctran_v_dial_win // unsigned , RW, default = 2 horizontal dilation window size for ctran_v, 0: no dilation, else (x+1)
//Bit 3 reg_ctran_powersaving // unsigned , RW, default = 0 enable bit gate the ctran clock for power saving, just output cdf_l
//Bit 2 reg_ctrs_csat_max_en // unsigned , RW, default = 1 enable bit to do ctrs and csat max to get ctrans, default = 1
//Bit 1 reg_ctran_h_lpf_en // unsigned , RW, default = 1 enable bit to do horizontal [12221] lpf for lbuf_ctran_h_lpf, default = 1
@@ -42182,7 +42182,7 @@
//Bit 23:16 reg_drt_grad_calp_for_color_transition // unsigned , RW, default = 50 color error alpha for final error blend, normalized to 32 as 1.0
//Bit 15: 4 reg_drt_hfrq_coring // unsigned , RW, default = 16 coring threshold for high frequency count in drt
//Bit 3: 1 reserved
-//Bit 0 reg_drt_grad_err_mode // unsigned , RW, default = 0 0: orginal error, 1: blended error, error mode for final error ouput
+//Bit 0 reg_drt_grad_err_mode // unsigned , RW, default = 0 0: original error, 1: blended error, error mode for final error output
#define ISP_DMS_DRT_HFRQ0 ((0x100d << 2) + 0xfe3b4000)
//Bit 31:28 reserved
//Bit 27:16 reg_drt_hfrq_dif_thd_1 // unsigned , RW, default = 256 dif threshold1 for dif to gain calc. for high frequency count in drt
@@ -42956,7 +42956,7 @@
//Bit 23:17 reserved
//Bit 16 reg_pst_sta_hst_lpf // unsigned , RW, default = 0 STAhist statistics on [1 2 1]/4 filtered results
//Bit 15:10 reserved
-//Bit 9: 8 reg_dnlp_sta_sel // unsigned , RW, default = 0 DNLP global hst sta source data sel reg, 0: post_proc NR Y_input; 1: post_proc NR_ouput; 2: post_proc Gaussian Y_output; 3 MAX_RGB of CCM output;
+//Bit 9: 8 reg_dnlp_sta_sel // unsigned , RW, default = 0 DNLP global hst sta source data sel reg, 0: post_proc NR Y_input; 1: post_proc NR_output; 2: post_proc Gaussian Y_output; 3 MAX_RGB of CCM output;
//Bit 7: 5 reserved
//Bit 4 reg_dnlp_sta_mode // unsigned , RW, default = 0 DNLP global hst sta on 64bins: 0: Y-only; 1: MAX(R,G,B),
//Bit 3: 1 reserved
@@ -43166,16 +43166,16 @@
//Bit 23:20 reg_nry_sigma_rate // unsigned , RW, default = 4 sigma= Max(k*|max-min|, ofst_luma) for adaptive sigma, the larger of this rate, the more LPF.
//Bit 19: 8 reserved
//Bit 7: 4 reg_nry_burst_num // unsigned , RW, default = 0 number of homo pixels in SGM threshold for burst noise detection, the larger of this threshold, the easier burst detected, default=3;
-//Bit 3: 0 reg_nry_burst_rate // unsigned , RW, default = 4 burst detection thresold delta= range*rate/16, the large this rate, the difficult to detect as burst, default=4;
+//Bit 3: 0 reg_nry_burst_rate // unsigned , RW, default = 4 burst detection threshold delta= range*rate/16, the large this rate, the difficult to detect as burst, default=4;
#define ISP_POST_NRY_ALPHA_MAX_LUT ((0x1208 << 2) + 0xfe3b4000)
-//Bit 31:28 reg_nry_alpha0_maxerr_lut_7 // unsigned , RW, default = 15 channel: alpha curv for blending gau_sigma filter results and orignal signal.[0, 8, 16, 32, 64, 128, 192,256]
-//Bit 27:24 reg_nry_alpha0_maxerr_lut_6 // unsigned , RW, default = 15 channel: alpha curv for blending gau_sigma filter results and orignal signal.[0, 8, 16, 32, 64, 128, 192,256]
-//Bit 23:20 reg_nry_alpha0_maxerr_lut_5 // unsigned , RW, default = 15 channel: alpha curv for blending gau_sigma filter results and orignal signal.[0, 8, 16, 32, 64, 128, 192,256]
-//Bit 19:16 reg_nry_alpha0_maxerr_lut_4 // unsigned , RW, default = 15 channel: alpha curv for blending gau_sigma filter results and orignal signal.[0, 8, 16, 32, 64, 128, 192,256]
-//Bit 15:12 reg_nry_alpha0_maxerr_lut_3 // unsigned , RW, default = 14 channel: alpha curv for blending gau_sigma filter results and orignal signal.[0, 8, 16, 32, 64, 128, 192,256]
-//Bit 11: 8 reg_nry_alpha0_maxerr_lut_2 // unsigned , RW, default = 12 channel: alpha curv for blending gau_sigma filter results and orignal signal.[0, 8, 16, 32, 64, 128, 192,256]
-//Bit 7: 4 reg_nry_alpha0_maxerr_lut_1 // unsigned , RW, default = 3 channel: alpha curv for blending gau_sigma filter results and orignal signal.[0, 8, 16, 32, 64, 128, 192,256]
-//Bit 3: 0 reg_nry_alpha0_maxerr_lut_0 // unsigned , RW, default = 0 channel: alpha curv for blending gau_sigma filter results and orignal signal.[0, 8, 16, 32, 64, 128, 192,256]
+//Bit 31:28 reg_nry_alpha0_maxerr_lut_7 // unsigned , RW, default = 15 channel: alpha curv for blending gau_sigma filter results and original signal.[0, 8, 16, 32, 64, 128, 192,256]
+//Bit 27:24 reg_nry_alpha0_maxerr_lut_6 // unsigned , RW, default = 15 channel: alpha curv for blending gau_sigma filter results and original signal.[0, 8, 16, 32, 64, 128, 192,256]
+//Bit 23:20 reg_nry_alpha0_maxerr_lut_5 // unsigned , RW, default = 15 channel: alpha curv for blending gau_sigma filter results and original signal.[0, 8, 16, 32, 64, 128, 192,256]
+//Bit 19:16 reg_nry_alpha0_maxerr_lut_4 // unsigned , RW, default = 15 channel: alpha curv for blending gau_sigma filter results and original signal.[0, 8, 16, 32, 64, 128, 192,256]
+//Bit 15:12 reg_nry_alpha0_maxerr_lut_3 // unsigned , RW, default = 14 channel: alpha curv for blending gau_sigma filter results and original signal.[0, 8, 16, 32, 64, 128, 192,256]
+//Bit 11: 8 reg_nry_alpha0_maxerr_lut_2 // unsigned , RW, default = 12 channel: alpha curv for blending gau_sigma filter results and original signal.[0, 8, 16, 32, 64, 128, 192,256]
+//Bit 7: 4 reg_nry_alpha0_maxerr_lut_1 // unsigned , RW, default = 3 channel: alpha curv for blending gau_sigma filter results and original signal.[0, 8, 16, 32, 64, 128, 192,256]
+//Bit 3: 0 reg_nry_alpha0_maxerr_lut_0 // unsigned , RW, default = 0 channel: alpha curv for blending gau_sigma filter results and original signal.[0, 8, 16, 32, 64, 128, 192,256]
#define ISP_POST_NRC_GAU_FILTER ((0x1209 << 2) + 0xfe3b4000)
//Bit 31:24 reserved
//Bit 23:22 reg_nrc_gau_horz // unsigned , RW, default = 0 gaussian filter mode for chroma. 0: [1 2 1]/4; 1: [1 2 2 2 1]/8, 2/3: [1 2 3 4 3 2 1]/16
@@ -43194,7 +43194,7 @@
//Bit 23:22 reserved
//Bit 21:16 reg_pk_sad_core_rate // unsigned , RW, default = 6 rate of coring for sad(theta) - sad(theta+pi/2)*rate/64
//Bit 15 reg_pk_sad_intlev_mode // unsigned , RW, default = 1 interleave detection xerr mode: 0 max; 1:sum ;
-//Bit 14 reg_pk_sad_intlev_mod1 // unsigned , RW, default = 1 mode 1 of using diagonal protection: 0: no digonal protection; 1: with diagonal protection
+//Bit 14 reg_pk_sad_intlev_mod1 // unsigned , RW, default = 1 mode 1 of using diagonal protection: 0: no diagonal protection; 1: with diagonal protection
//Bit 13: 8 reg_pk_sad_intlev_gain // unsigned , RW, default = 12 interleave detection for sad gain applied, normalized to 8 as 1
//Bit 7: 0 reg_pk_drtdif_min2sad_th // unsigned , RW, default = 16 for min2_sad threshold for ambiguity ignoring, if (min_sad<min2_sad/2 && min2_sad>thrd) drt_dif=1;
#define ISP_POST_PK_CIR_HP_GAIN ((0x120f << 2) + 0xfe3b4000)
@@ -43915,7 +43915,7 @@
//Bit 11 reserved
//Bit 10: 8 reg_pst_yrnd_bandrand // unsigned , RW, default = 6 strength of the noise to added to Y
//Bit 7: 4 reg_pst_yrnd_randlsft // unsigned , RW, default = 5 left shift of rand noise before feeding to randslut, 0
-//Bit 3 reg_pst_yrnd_randmode // unsigned , RW, default = 1 mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs
+//Bit 3 reg_pst_yrnd_randmode // unsigned , RW, default = 1 mode of rand noise adding, 0: same noise strength for all difs; else: strength of noise will not exceed the difs
//Bit 2 reg_pst_yrnd_lpf_mode // unsigned , RW, default = 0 lpf mode, 0: 3x3, 1:3x5
//Bit 1 reg_pst_yrnd_hpxor // unsigned , RW, default = 1 random hp portion xor, [0] for luma, [1] for chroma, same for below
//Bit 0 reg_pst_yrnd_en // unsigned , RW, default = 0 enable adding y random noise for post proc.
@@ -43954,21 +43954,21 @@
//Bit 7: 0 reg_pst_yrnd_min_adp_margin_0 // signed , RW, default = -1 of the variation for min Y val after add random noise
#define ISP_POST_YRND_LUT ((0x1298 << 2) + 0xfe3b4000)
//Bit 31 reserved
-//Bit 30:28 reg_pst_yrnd_randslut_7 // unsigned , RW, default = 0 strenght of randon noise adding base on different luma level
+//Bit 30:28 reg_pst_yrnd_randslut_7 // unsigned , RW, default = 0 strength of randon noise adding base on different luma level
//Bit 27 reserved
-//Bit 26:24 reg_pst_yrnd_randslut_6 // unsigned , RW, default = 1 strenght of randon noise adding base on different luma level
+//Bit 26:24 reg_pst_yrnd_randslut_6 // unsigned , RW, default = 1 strength of randon noise adding base on different luma level
//Bit 23 reserved
-//Bit 22:20 reg_pst_yrnd_randslut_5 // unsigned , RW, default = 2 strenght of randon noise adding base on different luma level
+//Bit 22:20 reg_pst_yrnd_randslut_5 // unsigned , RW, default = 2 strength of randon noise adding base on different luma level
//Bit 19 reserved
-//Bit 18:16 reg_pst_yrnd_randslut_4 // unsigned , RW, default = 3 strenght of randon noise adding base on different luma level
+//Bit 18:16 reg_pst_yrnd_randslut_4 // unsigned , RW, default = 3 strength of randon noise adding base on different luma level
//Bit 15 reserved
-//Bit 14:12 reg_pst_yrnd_randslut_3 // unsigned , RW, default = 4 strenght of randon noise adding base on different luma level
+//Bit 14:12 reg_pst_yrnd_randslut_3 // unsigned , RW, default = 4 strength of randon noise adding base on different luma level
//Bit 11 reserved
-//Bit 10: 8 reg_pst_yrnd_randslut_2 // unsigned , RW, default = 3 strenght of randon noise adding base on different luma level
+//Bit 10: 8 reg_pst_yrnd_randslut_2 // unsigned , RW, default = 3 strength of randon noise adding base on different luma level
//Bit 7 reserved
-//Bit 6: 4 reg_pst_yrnd_randslut_1 // unsigned , RW, default = 2 strenght of randon noise adding base on different luma level
+//Bit 6: 4 reg_pst_yrnd_randslut_1 // unsigned , RW, default = 2 strength of randon noise adding base on different luma level
//Bit 3 reserved
-//Bit 2: 0 reg_pst_yrnd_randslut_0 // unsigned , RW, default = 2 strenght of randon noise adding base on different luma level
+//Bit 2: 0 reg_pst_yrnd_randslut_0 // unsigned , RW, default = 2 strength of randon noise adding base on different luma level
#define ISP_POST_YRND_SEED ((0x1299 << 2) + 0xfe3b4000)
//Bit 31 reg_pst_yrnd_seed_start // unsigned , RW, default = 1 random seed start
//Bit 30: 0 reg_pst_yrnd_seed // unsigned , RW, default = 31'h60a52f20 noise adding seed for Y. seed[0], 0x60a52f20); as default);
@@ -45690,14 +45690,14 @@
//Bit 10: 0 reg_af_fir1_coring_lmt // unsigned , RW, default = 2000 it is used to set the limit in FIR1 coring
#define ISP_AF_HOR_THD ((0x142b << 2) + 0xfe3b4000)
//Bit 31:27 reserved
-//Bit 26:16 reg_af_h0_thd // unsigned , RW, default = 0 it is used to set the horizontal theshold
+//Bit 26:16 reg_af_h0_thd // unsigned , RW, default = 0 it is used to set the horizontal threshold
//Bit 15:11 reserved
-//Bit 10: 0 reg_af_h1_thd // unsigned , RW, default = 0 it is used to set the horizontal theshold
+//Bit 10: 0 reg_af_h1_thd // unsigned , RW, default = 0 it is used to set the horizontal threshold
#define ISP_AF_VER_THD ((0x142c << 2) + 0xfe3b4000)
//Bit 31:27 reserved
-//Bit 26:16 reg_af_v0_thd // unsigned , RW, default = 0 it is used to set the vertical theshold
+//Bit 26:16 reg_af_v0_thd // unsigned , RW, default = 0 it is used to set the vertical threshold
//Bit 15:11 reserved
-//Bit 10: 0 reg_af_v1_thd // unsigned , RW, default = 0 it is used to set the vertical theshold
+//Bit 10: 0 reg_af_v1_thd // unsigned , RW, default = 0 it is used to set the vertical threshold
#define ISP_AF_STA_SHIFT ((0x142d << 2) + 0xfe3b4000)
//Bit 31:28 reg_af_h0_sft // unsigned , RW, default = 8 it is used to set the shift for horizontal statistics0
//Bit 27:24 reg_af_h1_sft // unsigned , RW, default = 8 it is used to set the shift for horizontal statistics1
@@ -45711,7 +45711,7 @@
//Bit 31:20 reserved
//Bit 19:16 reg_af_y_sft // unsigned , RW, default = 8 it is used to set the shift for y statistics
//Bit 15:12 reg_af_ycnt_sft // unsigned , RW, default = 3 it is used to set the shift for y counter
-//Bit 11: 0 reg_af_y_thd // unsigned , RW, default = 0 it is used to set the Y theshold
+//Bit 11: 0 reg_af_y_thd // unsigned , RW, default = 0 it is used to set the Y threshold
#define ISP_AF_ROI0_STA_SHIFT ((0x142f << 2) + 0xfe3b4000)
//Bit 31:28 reg_af_roi_h0_sft_0 // unsigned , RW, default = 8 it is used to set the shift for horizontal ROI0 statistics0
//Bit 27:24 reg_af_roi_h1_sft_0 // unsigned , RW, default = 8 it is used to set the shift for horizontal ROI0 statistics1
@@ -45960,10 +45960,10 @@
//Bit 7 reg_ae_input_2ln // unsigned , RW, default = 1 input buffer 2 lines together, reg_ae_stat_switch=0, set 1, otherwise set to 0
//Bit 6 reserved
//Bit 5 reg_ae_histo_useweight // unsigned , RW, default = 1 hist1024 use regional weight, default=1
-//Bit 4 reg_ae_glbal_useweight // unsigned , RW, default = 1 global use regional weight, default=1
+//Bit 4 reg_ae_global_useweight // unsigned , RW, default = 1 global use regional weight, default=1
//Bit 3: 2 reg_ae_stat_local_mode // unsigned , RW, default = 0 AE statisic local sta mode: 0: BIN0/1/3/4 in pack0 and pack1; 1: Gr/R/B/Gb/Ir_avg in pack0 and pack1; 2o3: mean/max/min/sat/unsat etc packed. default=0
//Bit 1 reg_ae_stat_hist_sel // unsigned , RW, default = 0 0: global win, 1: roi window, histogram from global window or roi window for ae stats
-//Bit 0 reg_ae_stat_glbal_mode // unsigned , RW, default = 0 AE statisic global sta mode: 0: BIN0/1/3/4 in pack0 and pack1; 1: Gr/R/B/Gb/Ir_avg in pack0 and pack1; default=0
+//Bit 0 reg_ae_stat_global_mode // unsigned , RW, default = 0 AE statisic global sta mode: 0: BIN0/1/3/4 in pack0 and pack1; 1: Gr/R/B/Gb/Ir_avg in pack0 and pack1; default=0
#define ISP_AE_CRTL2_0 ((0x1513 << 2) + 0xfe3b4000)
//Bit 31:25 reserved
//Bit 24 reg_ae_luma_coef_0 // unsigned , RW, default = 1 luma estimate coef for AE, 0: not included in lumat estimate, 1: included; default, , 1 1 1 1 1;
@@ -46148,10 +46148,10 @@
//Bit 8 reg_awb_stat_input_format // unsigned , RW, default = 0 input frame buffer format: 0: raw; 1: RGB; default = 0;
//Bit 7 reserved
//Bit 6 reg_awb_grn_use_avg // unsigned , RW, default = 0 enable of Gb=Gr=(Gb+Gr+1)/2, 0: no average, 1: average
-//Bit 5 reg_awb_glbal_useweight // unsigned , RW, default = 1 global use regional weight, default=1
+//Bit 5 reg_awb_global_useweight // unsigned , RW, default = 1 global use regional weight, default=1
//Bit 4: 3 reg_awb_stat_luma_div_mode // unsigned , RW, default = 0 AWB separate STATS on Luma (x+1) ranges, Total STATS RAM same size, needs to reduce hblk_num/vblk_num if x>0. 0: no division; 1: div to 2 range; ...3: div to 4 ranges
//Bit 2 reg_awb_stat_local_mode // unsigned , RW, default = 0 AWB statisic local sta mode: 0: ratio_bg/rg in pack0 and cnt in pack1; 1: (AVG_G<<16)+ AVG_R in pack0 and (Nrm_cnt<<16)+ avg_B in pack1; default,0
-//Bit 1 reg_awb_stat_glbal_mode // unsigned , RW, default = 0 AWB statisic global sta mode: 0: ratio_bg/rg in pack0 and cnt in pack1; 1: (AVG_G<<16)+ AVG_R in pack0 and (Nrm_cnt<<16)+ avg_B in pack1; default,0
+//Bit 1 reg_awb_stat_global_mode // unsigned , RW, default = 0 AWB statisic global sta mode: 0: ratio_bg/rg in pack0 and cnt in pack1; 1: (AVG_G<<16)+ AVG_R in pack0 and (Nrm_cnt<<16)+ avg_B in pack1; default,0
//Bit 0 reg_awb_stat_satur_vald // unsigned , RW, default = 0 AWB statistic over saturation control
#define ISP_AWB_STAT_BLC20_0 ((0x1617 << 2) + 0xfe3b4000)
//Bit 31:20 reserved
@@ -51669,7 +51669,7 @@
#define PFIFO_WR_PTR ((0x3866 << 2) + 0xfdf00000)
// bit 9:0 -- point to byte address
#define PFIFO_RD_PTR ((0x3867 << 2) + 0xfdf00000)
-// bit 31:0 -- 8/16/24/32 bits data acording to pfifo_data_width
+// bit 31:0 -- 8/16/24/32 bits data according to pfifo_data_width
#define PFIFO_DATA ((0x3868 << 2) + 0xfdf00000)
// bit 31:0 -- parser search pattern
#define PARSER_SEARCH_PATTERN ((0x3869 << 2) + 0xfdf00000)
@@ -51704,7 +51704,7 @@
#define PARSER_PARAMETER ((0x386f << 2) + 0xfdf00000)
// bit 31:0 -- insert data // write only
// write to PARSER_CONTROL will reset the write position
-// continous write to this address can write upto 16 bytes
+// continuous write to this address can write upto 16 bytes
#define PARSER_INSERT_DATA ((0x3870 << 2) + 0xfdf00000)
// Bit 31:24 -- Reserved Stream_ID
// Bit 23:16 -- Sub Stream_ID
@@ -51873,7 +51873,7 @@
#define PARSER_B_PFIFO_WR_PTR ((0x1166 << 2) + 0xfdf00000)
// bit 9:0 -- point to byte address
#define PARSER_B_PFIFO_RD_PTR ((0x1167 << 2) + 0xfdf00000)
-// bit 31:0 -- 8/16/24/32 bits data acording to pfifo_data_width
+// bit 31:0 -- 8/16/24/32 bits data according to pfifo_data_width
#define PARSER_B_PFIFO_DATA ((0x1168 << 2) + 0xfdf00000)
// bit 31:0 -- parser search pattern
#define PARSER_B_PARSER_SEARCH_PATTERN ((0x1169 << 2) + 0xfdf00000)
@@ -51908,7 +51908,7 @@
#define PARSER_B_PARSER_PARAMETER ((0x116f << 2) + 0xfdf00000)
// bit 31:0 -- insert data // write only
// write to PARSER_CONTROL will reset the write position
-// continous write to this address can write upto 16 bytes
+// continuous write to this address can write upto 16 bytes
#define PARSER_B_PARSER_INSERT_DATA ((0x1170 << 2) + 0xfdf00000)
// Bit 31:24 -- Reserved Stream_ID
// Bit 23:16 -- Sub Stream_ID
diff --git a/demos/amlogic/n200/interrupt_control_eclic.c b/demos/amlogic/n200/interrupt_control_eclic.c
index c25ab29..04ae8ca 100644
--- a/demos/amlogic/n200/interrupt_control_eclic.c
+++ b/demos/amlogic/n200/interrupt_control_eclic.c
@@ -6,7 +6,7 @@
static uint8_t CLICINTCTLBITS;
- // Configure PMP to make all the address space accesable and executable
+ // Configure PMP to make all the address space accessible and executable
void eclic_init ( uint32_t num_irq )
{
diff --git a/demos/amlogic/n200/n200_func.c b/demos/amlogic/n200/n200_func.c
index e9be3e6..8905496 100644
--- a/demos/amlogic/n200/n200_func.c
+++ b/demos/amlogic/n200/n200_func.c
@@ -12,7 +12,7 @@
#include "n200_timer.h"
#include "FreeRTOS.h"
- // Configure PMP to make all the address space accesable and executable
+ // Configure PMP to make all the address space accessible and executable
void pmp_open_all_space(void){
// Config entry0 addr to all 1s to make the range cover all space
asm volatile ("li x6, 0xffffffff":::"x6");
diff --git a/demos/amlogic/n200/start.S b/demos/amlogic/n200/start.S
index b44ddc7..e0993db 100644
--- a/demos/amlogic/n200/start.S
+++ b/demos/amlogic/n200/start.S
@@ -14,16 +14,16 @@
li t0, (0x1 << 9);
csrs CSR_MMISC_CTL, t0
-/* Intial the mtvt*/
+/* Initial the mtvt*/
la t0, vector_base
csrw CSR_MTVT, t0
-/* Intial the mtvt2 and enable it*/
+/* Initial the mtvt2 and enable it*/
la t0, irq_entry
csrw CSR_MTVT2, t0
csrs CSR_MTVT2, 0x1
- /* Intial the CSR MTVEC for the Trap ane NMI base addr*/
+ /* Initial the CSR MTVEC for the Trap ane NMI base addr*/
la t0, trap_entry
li t1, 0x3 // use ucliec
or t0, t0, t1
@@ -59,7 +59,7 @@
la sp, _sp
#if defined (SOC_t3)
- /* Fixme T3 axi_ram access issuse */
+ /* Fixme T3 axi_ram access issue */
lw a0, _data_start
lw a1, _data_end
lw a2, _data_img
diff --git a/lib/FreeRTOS/portable/GCC/RISC_V_N205/portasm.S b/lib/FreeRTOS/portable/GCC/RISC_V_N205/portasm.S
index af7b1a7..fe45bea 100644
--- a/lib/FreeRTOS/portable/GCC/RISC_V_N205/portasm.S
+++ b/lib/FreeRTOS/portable/GCC/RISC_V_N205/portasm.S
@@ -378,7 +378,7 @@
.endm
-/* Saves current return adress (RA) as task program counter */
+/* Saves current return address (RA) as task program counter */
.macro portSAVE_RA
LOAD t0, 1 * REGBYTES(sp)
STORE t0, 33 * REGBYTES(sp)
@@ -402,7 +402,7 @@
/* Check for interrupt */
pushREGFILE
csrr a0, mcause
- //Bob: we dont need to check interrupt here because N200 have seperated entry to IRQ
+ //Bob: we dont need to check interrupt here because N200 have separated entry to IRQ
//blt a0,zero,interrupt
/* synchronous interrupt*/
diff --git a/lib/FreeRTOS/portable/GCC/RISC_V_N205/portasm_reva.S b/lib/FreeRTOS/portable/GCC/RISC_V_N205/portasm_reva.S
index 9229e6b..08801cd 100644
--- a/lib/FreeRTOS/portable/GCC/RISC_V_N205/portasm_reva.S
+++ b/lib/FreeRTOS/portable/GCC/RISC_V_N205/portasm_reva.S
@@ -378,7 +378,7 @@
.endm
-/* Saves current return adress (RA) as task program counter */
+/* Saves current return address (RA) as task program counter */
.macro portSAVE_RA
LOAD t0, 1 * REGBYTES(sp)
STORE t0, 33 * REGBYTES(sp)
@@ -402,7 +402,7 @@
/* Check for interrupt */
pushREGFILE
csrr a0, mcause
- //Bob: we dont need to check interrupt here because N200 have seperated entry to IRQ
+ //Bob: we dont need to check interrupt here because N200 have separated entry to IRQ
//blt a0,zero,interrupt
/* synchronous interrupt*/