commit 065fd7a git:spl branch:amlogic-dev ddr:ecc7021
Author: Jian Hu <jian.hu@amlogic.com>
Date: Tue May 14 09:26:57 2024 +0000
clk: set cpu_axi_clk to half of dsu_clk [1/1]
PD#SWPL-169597
Problem:
cpu_axi_clk equal dsu_clk/3 will cause low performance
Solution:
set cpu_axi_clk to dsu_clk/2
Verify:
t5w
Change-Id: Ia4144d2bae66fa69db1f9d5a251fa5f95ae66bf8
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
a1 build ok
axg build ok
c1 build ok
g12a build ok
g12b build ok
gxb build ok
gxl build ok
gxtvbb build ok
t5 build ok
t5d build ok
t5w build ok
tl1 build ok
tm2 build ok
txhd build ok
txl build ok
txlx build ok
txhd2 build ok
Change-Id: I30190b6bc8c9cf09d436569caa721414cea95c5b
17 files changed