commit f3d5621a6ee41b1c536af3de1be0c6ec54023f95
author Jenkins SH <jenkins.sh@amlogic.com> Mon Jul 31 12:04:50 2023 +0000
committer Jenkins SH <jenkins.sh@amlogic.com> Mon Jul 31 12:04:50 2023 +0000
tree ab4b7736c11387f01ecc48b09726b2acf662f14c
parent 020569150469e7a3b1970f8b42849e97ea815b08

commit 8a105087f3c2e210c1ff9822d724a98333779f07
Author: jiaxing.ye <jiaxing.ye@amlogic.com>
Date:   Mon Jul 31 18:20:19 2023 +0800

    bl2: ddr s1a ddr real phy fine tune ac delay [1/1]

    PD#SWPL-133017

    Problem:
    ddr s1a ddr real phy fine tune ac delay

    Solution:
    1      ddr s1a ddr real phy fine tune ac delay

    Verify:
    test s1a skt pass

    Change-Id: Iaf5c27928a6cbbf4dbbaaf6403e048cacc455e5e
    Signed-off-by: jiaxing.ye <jiaxing.ye@amlogic.com>
txhd2    build ok

Change-Id: Ida477358e4a4c898ad0198aa790eb64358ade01d