commit 3ca4e4eeb3d8f2c19b49c99631230a78059d37e7
Author: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
Date: Thu Aug 25 21:50:42 2022 +0800
bl30: avoid cpub clk register parallel access [1/1]
PD#SWPL-92581
Problem:
cpub clk register parallel access
Solution:
avoid cpub clk register parallel access
Verify:
G12B
Change-Id: Idfb1cf89aaa87b3a38de3ed5b60000c2cfb06c52
Signed-off-by: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
gxb build ok
gxtvbb build ok
gxl build ok
txl build ok
txlx build ok
axg build ok
txhd build ok
g12a build ok
g12b build ok
tl1 build ok
tm2 build ok
Change-Id: Icd20d936cefbecc37d46c2ca6fb69ef769b5a9e4
11 files changed