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Linus Walleij6c009ab2010-09-13 00:35:22 +02001/*
2 * drivers/mtd/nand/fsmc_nand.c
3 *
4 * ST Microelectronics
5 * Flexible Static Memory Controller (FSMC)
6 * Driver for NAND portions
7 *
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
10 * Ashish Priyadarshi
11 *
12 * Based on drivers/mtd/nand/nomadik_nand.c
13 *
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
17 */
18
19#include <linux/clk.h>
Vipin Kumar4774fb02012-03-14 11:47:18 +053020#include <linux/completion.h>
21#include <linux/dmaengine.h>
22#include <linux/dma-direction.h>
23#include <linux/dma-mapping.h>
Linus Walleij6c009ab2010-09-13 00:35:22 +020024#include <linux/err.h>
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/resource.h>
28#include <linux/sched.h>
29#include <linux/types.h>
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/nand.h>
32#include <linux/mtd/nand_ecc.h>
33#include <linux/platform_device.h>
Stefan Roeseeea62812012-03-16 10:19:31 +010034#include <linux/of.h>
Linus Walleij6c009ab2010-09-13 00:35:22 +020035#include <linux/mtd/partitions.h>
36#include <linux/io.h>
37#include <linux/slab.h>
Linus Walleij593cd872010-11-29 13:52:19 +010038#include <linux/amba/bus.h>
Linus Walleij6c009ab2010-09-13 00:35:22 +020039#include <mtd/mtd-abi.h>
40
Linus Walleij4404d7d2016-12-18 12:34:55 +010041/* fsmc controller registers for NOR flash */
42#define CTRL 0x0
43 /* ctrl register definitions */
44 #define BANK_ENABLE (1 << 0)
45 #define MUXED (1 << 1)
46 #define NOR_DEV (2 << 2)
47 #define WIDTH_8 (0 << 4)
48 #define WIDTH_16 (1 << 4)
49 #define RSTPWRDWN (1 << 6)
50 #define WPROT (1 << 7)
51 #define WRT_ENABLE (1 << 12)
52 #define WAIT_ENB (1 << 13)
53
54#define CTRL_TIM 0x4
55 /* ctrl_tim register definitions */
56
57#define FSMC_NOR_BANK_SZ 0x8
58#define FSMC_NOR_REG_SIZE 0x40
59
60#define FSMC_NOR_REG(base, bank, reg) (base + \
61 FSMC_NOR_BANK_SZ * (bank) + \
62 reg)
63
64/* fsmc controller registers for NAND flash */
65#define PC 0x00
66 /* pc register definitions */
67 #define FSMC_RESET (1 << 0)
68 #define FSMC_WAITON (1 << 1)
69 #define FSMC_ENABLE (1 << 2)
70 #define FSMC_DEVTYPE_NAND (1 << 3)
71 #define FSMC_DEVWID_8 (0 << 4)
72 #define FSMC_DEVWID_16 (1 << 4)
73 #define FSMC_ECCEN (1 << 6)
74 #define FSMC_ECCPLEN_512 (0 << 7)
75 #define FSMC_ECCPLEN_256 (1 << 7)
76 #define FSMC_TCLR_1 (1)
77 #define FSMC_TCLR_SHIFT (9)
78 #define FSMC_TCLR_MASK (0xF)
79 #define FSMC_TAR_1 (1)
80 #define FSMC_TAR_SHIFT (13)
81 #define FSMC_TAR_MASK (0xF)
82#define STS 0x04
83 /* sts register definitions */
84 #define FSMC_CODE_RDY (1 << 15)
85#define COMM 0x08
86 /* comm register definitions */
87 #define FSMC_TSET_0 0
88 #define FSMC_TSET_SHIFT 0
89 #define FSMC_TSET_MASK 0xFF
90 #define FSMC_TWAIT_6 6
91 #define FSMC_TWAIT_SHIFT 8
92 #define FSMC_TWAIT_MASK 0xFF
93 #define FSMC_THOLD_4 4
94 #define FSMC_THOLD_SHIFT 16
95 #define FSMC_THOLD_MASK 0xFF
96 #define FSMC_THIZ_1 1
97 #define FSMC_THIZ_SHIFT 24
98 #define FSMC_THIZ_MASK 0xFF
99#define ATTRIB 0x0C
100#define IOATA 0x10
101#define ECC1 0x14
102#define ECC2 0x18
103#define ECC3 0x1C
104#define FSMC_NAND_BANK_SZ 0x20
105
106#define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
107 (FSMC_NAND_BANK_SZ * (bank)) + \
108 reg)
109
110#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
111
112struct fsmc_nand_timings {
113 uint8_t tclr;
114 uint8_t tar;
115 uint8_t thiz;
116 uint8_t thold;
117 uint8_t twait;
118 uint8_t tset;
119};
120
121enum access_mode {
122 USE_DMA_ACCESS = 1,
123 USE_WORD_ACCESS,
124};
125
126/**
Thomas Petazzonie7cda012017-03-21 11:03:56 +0100127 * struct fsmc_nand_data - structure for FSMC NAND device state
128 *
129 * @pid: Part ID on the AMBA PrimeCell format
130 * @mtd: MTD info for a NAND flash.
131 * @nand: Chip related info for a NAND flash.
132 * @partitions: Partition info for a NAND Flash.
133 * @nr_partitions: Total number of partition of a NAND flash.
134 *
135 * @bank: Bank number for probed device.
136 * @clk: Clock structure for FSMC.
137 *
138 * @read_dma_chan: DMA channel for read access
139 * @write_dma_chan: DMA channel for write access to NAND
140 * @dma_access_complete: Completion structure
141 *
142 * @data_pa: NAND Physical port for Data.
143 * @data_va: NAND port for Data.
144 * @cmd_va: NAND port for Command.
145 * @addr_va: NAND port for Address.
146 * @regs_va: FSMC regs base address.
147 */
148struct fsmc_nand_data {
149 u32 pid;
150 struct nand_chip nand;
Thomas Petazzonie7cda012017-03-21 11:03:56 +0100151
152 unsigned int bank;
153 struct device *dev;
154 enum access_mode mode;
155 struct clk *clk;
156
157 /* DMA related objects */
158 struct dma_chan *read_dma_chan;
159 struct dma_chan *write_dma_chan;
160 struct completion dma_access_complete;
161
162 struct fsmc_nand_timings *dev_timings;
163
164 dma_addr_t data_pa;
165 void __iomem *data_va;
166 void __iomem *cmd_va;
167 void __iomem *addr_va;
168 void __iomem *regs_va;
Thomas Petazzonie7cda012017-03-21 11:03:56 +0100169};
170
Boris Brezillon22b46952016-02-03 20:01:42 +0100171static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
172 struct mtd_oob_region *oobregion)
173{
174 struct nand_chip *chip = mtd_to_nand(mtd);
175
176 if (section >= chip->ecc.steps)
177 return -ERANGE;
178
179 oobregion->offset = (section * 16) + 2;
180 oobregion->length = 3;
181
182 return 0;
183}
184
185static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
186 struct mtd_oob_region *oobregion)
187{
188 struct nand_chip *chip = mtd_to_nand(mtd);
189
190 if (section >= chip->ecc.steps)
191 return -ERANGE;
192
193 oobregion->offset = (section * 16) + 8;
194
195 if (section < chip->ecc.steps - 1)
196 oobregion->length = 8;
197 else
198 oobregion->length = mtd->oobsize - oobregion->offset;
199
200 return 0;
201}
202
203static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
204 .ecc = fsmc_ecc1_ooblayout_ecc,
205 .free = fsmc_ecc1_ooblayout_free,
206};
207
Boris Brezillon04a123a2016-02-09 15:01:21 +0100208/*
209 * ECC placement definitions in oobfree type format.
210 * There are 13 bytes of ecc for every 512 byte block and it has to be read
211 * consecutively and immediately after the 512 byte data block for hardware to
212 * generate the error bit offsets in 512 byte data.
213 */
Boris Brezillon22b46952016-02-03 20:01:42 +0100214static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
215 struct mtd_oob_region *oobregion)
216{
217 struct nand_chip *chip = mtd_to_nand(mtd);
218
219 if (section >= chip->ecc.steps)
220 return -ERANGE;
221
222 oobregion->length = chip->ecc.bytes;
223
224 if (!section && mtd->writesize <= 512)
225 oobregion->offset = 0;
226 else
227 oobregion->offset = (section * 16) + 2;
228
229 return 0;
230}
231
232static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
233 struct mtd_oob_region *oobregion)
234{
235 struct nand_chip *chip = mtd_to_nand(mtd);
236
237 if (section >= chip->ecc.steps)
238 return -ERANGE;
239
240 oobregion->offset = (section * 16) + 15;
241
242 if (section < chip->ecc.steps - 1)
243 oobregion->length = 3;
244 else
245 oobregion->length = mtd->oobsize - oobregion->offset;
246
247 return 0;
248}
249
250static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
251 .ecc = fsmc_ecc4_ooblayout_ecc,
252 .free = fsmc_ecc4_ooblayout_free,
253};
254
Boris BREZILLON277af422015-12-10 08:59:46 +0100255static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd)
256{
Boris BREZILLONbdf3a552015-12-10 09:00:05 +0100257 return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand);
Boris BREZILLON277af422015-12-10 08:59:46 +0100258}
259
Linus Walleij6c009ab2010-09-13 00:35:22 +0200260/*
261 * fsmc_cmd_ctrl - For facilitaing Hardware access
262 * This routine allows hardware specific access to control-lines(ALE,CLE)
263 */
264static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
265{
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100266 struct nand_chip *this = mtd_to_nand(mtd);
Boris BREZILLON277af422015-12-10 08:59:46 +0100267 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
Vipin Kumar605add72012-10-09 16:14:43 +0530268 void __iomem *regs = host->regs_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200269 unsigned int bank = host->bank;
270
271 if (ctrl & NAND_CTRL_CHANGE) {
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530272 u32 pc;
273
Linus Walleij6c009ab2010-09-13 00:35:22 +0200274 if (ctrl & NAND_CLE) {
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530275 this->IO_ADDR_R = host->cmd_va;
276 this->IO_ADDR_W = host->cmd_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200277 } else if (ctrl & NAND_ALE) {
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530278 this->IO_ADDR_R = host->addr_va;
279 this->IO_ADDR_W = host->addr_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200280 } else {
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530281 this->IO_ADDR_R = host->data_va;
282 this->IO_ADDR_W = host->data_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200283 }
284
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530285 pc = readl(FSMC_NAND_REG(regs, bank, PC));
286 if (ctrl & NAND_NCE)
287 pc |= FSMC_ENABLE;
288 else
289 pc &= ~FSMC_ENABLE;
Vipin Kumara4742d52012-10-09 16:14:50 +0530290 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200291 }
292
293 mb();
294
295 if (cmd != NAND_CMD_NONE)
Vipin Kumara4742d52012-10-09 16:14:50 +0530296 writeb_relaxed(cmd, this->IO_ADDR_W);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200297}
298
299/*
300 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
301 *
302 * This routine initializes timing parameters related to NAND memory access in
303 * FSMC registers
304 */
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530305static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
Vipin Kumare2f6bce2012-03-14 11:47:14 +0530306 uint32_t busw, struct fsmc_nand_timings *timings)
Linus Walleij6c009ab2010-09-13 00:35:22 +0200307{
308 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
Vipin Kumare2f6bce2012-03-14 11:47:14 +0530309 uint32_t tclr, tar, thiz, thold, twait, tset;
310 struct fsmc_nand_timings *tims;
311 struct fsmc_nand_timings default_timings = {
312 .tclr = FSMC_TCLR_1,
313 .tar = FSMC_TAR_1,
314 .thiz = FSMC_THIZ_1,
315 .thold = FSMC_THOLD_4,
316 .twait = FSMC_TWAIT_6,
317 .tset = FSMC_TSET_0,
318 };
319
320 if (timings)
321 tims = timings;
322 else
323 tims = &default_timings;
324
325 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
326 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
327 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
328 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
329 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
330 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200331
332 if (busw)
Vipin Kumara4742d52012-10-09 16:14:50 +0530333 writel_relaxed(value | FSMC_DEVWID_16,
334 FSMC_NAND_REG(regs, bank, PC));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200335 else
Vipin Kumara4742d52012-10-09 16:14:50 +0530336 writel_relaxed(value | FSMC_DEVWID_8,
337 FSMC_NAND_REG(regs, bank, PC));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200338
Vipin Kumara4742d52012-10-09 16:14:50 +0530339 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530340 FSMC_NAND_REG(regs, bank, PC));
Vipin Kumara4742d52012-10-09 16:14:50 +0530341 writel_relaxed(thiz | thold | twait | tset,
342 FSMC_NAND_REG(regs, bank, COMM));
343 writel_relaxed(thiz | thold | twait | tset,
344 FSMC_NAND_REG(regs, bank, ATTRIB));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200345}
346
347/*
348 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
349 */
350static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
351{
Boris BREZILLON277af422015-12-10 08:59:46 +0100352 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530353 void __iomem *regs = host->regs_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200354 uint32_t bank = host->bank;
355
Vipin Kumara4742d52012-10-09 16:14:50 +0530356 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530357 FSMC_NAND_REG(regs, bank, PC));
Vipin Kumara4742d52012-10-09 16:14:50 +0530358 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530359 FSMC_NAND_REG(regs, bank, PC));
Vipin Kumara4742d52012-10-09 16:14:50 +0530360 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530361 FSMC_NAND_REG(regs, bank, PC));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200362}
363
364/*
365 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300366 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
Linus Walleij6c009ab2010-09-13 00:35:22 +0200367 * max of 8-bits)
368 */
369static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
370 uint8_t *ecc)
371{
Boris BREZILLON277af422015-12-10 08:59:46 +0100372 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530373 void __iomem *regs = host->regs_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200374 uint32_t bank = host->bank;
375 uint32_t ecc_tmp;
376 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
377
378 do {
Vipin Kumara4742d52012-10-09 16:14:50 +0530379 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
Linus Walleij6c009ab2010-09-13 00:35:22 +0200380 break;
381 else
382 cond_resched();
383 } while (!time_after_eq(jiffies, deadline));
384
Vipin Kumar712c4ad2012-03-14 11:47:16 +0530385 if (time_after_eq(jiffies, deadline)) {
386 dev_err(host->dev, "calculate ecc timed out\n");
387 return -ETIMEDOUT;
388 }
389
Vipin Kumara4742d52012-10-09 16:14:50 +0530390 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200391 ecc[0] = (uint8_t) (ecc_tmp >> 0);
392 ecc[1] = (uint8_t) (ecc_tmp >> 8);
393 ecc[2] = (uint8_t) (ecc_tmp >> 16);
394 ecc[3] = (uint8_t) (ecc_tmp >> 24);
395
Vipin Kumara4742d52012-10-09 16:14:50 +0530396 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200397 ecc[4] = (uint8_t) (ecc_tmp >> 0);
398 ecc[5] = (uint8_t) (ecc_tmp >> 8);
399 ecc[6] = (uint8_t) (ecc_tmp >> 16);
400 ecc[7] = (uint8_t) (ecc_tmp >> 24);
401
Vipin Kumara4742d52012-10-09 16:14:50 +0530402 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200403 ecc[8] = (uint8_t) (ecc_tmp >> 0);
404 ecc[9] = (uint8_t) (ecc_tmp >> 8);
405 ecc[10] = (uint8_t) (ecc_tmp >> 16);
406 ecc[11] = (uint8_t) (ecc_tmp >> 24);
407
Vipin Kumara4742d52012-10-09 16:14:50 +0530408 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200409 ecc[12] = (uint8_t) (ecc_tmp >> 16);
410
411 return 0;
412}
413
414/*
415 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300416 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
Linus Walleij6c009ab2010-09-13 00:35:22 +0200417 * max of 1-bit)
418 */
419static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
420 uint8_t *ecc)
421{
Boris BREZILLON277af422015-12-10 08:59:46 +0100422 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530423 void __iomem *regs = host->regs_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200424 uint32_t bank = host->bank;
425 uint32_t ecc_tmp;
426
Vipin Kumara4742d52012-10-09 16:14:50 +0530427 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200428 ecc[0] = (uint8_t) (ecc_tmp >> 0);
429 ecc[1] = (uint8_t) (ecc_tmp >> 8);
430 ecc[2] = (uint8_t) (ecc_tmp >> 16);
431
432 return 0;
433}
434
Vipin Kumar519300c2012-03-07 17:00:49 +0530435/* Count the number of 0's in buff upto a max of max_bits */
436static int count_written_bits(uint8_t *buff, int size, int max_bits)
437{
438 int k, written_bits = 0;
439
440 for (k = 0; k < size; k++) {
441 written_bits += hweight8(~buff[k]);
442 if (written_bits > max_bits)
443 break;
444 }
445
446 return written_bits;
447}
448
Vipin Kumar4774fb02012-03-14 11:47:18 +0530449static void dma_complete(void *param)
450{
451 struct fsmc_nand_data *host = param;
452
453 complete(&host->dma_access_complete);
454}
455
456static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
457 enum dma_data_direction direction)
458{
459 struct dma_chan *chan;
460 struct dma_device *dma_dev;
461 struct dma_async_tx_descriptor *tx;
462 dma_addr_t dma_dst, dma_src, dma_addr;
463 dma_cookie_t cookie;
464 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
465 int ret;
Nicholas Mc Guire818a45b2015-03-13 07:54:46 -0400466 unsigned long time_left;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530467
468 if (direction == DMA_TO_DEVICE)
469 chan = host->write_dma_chan;
470 else if (direction == DMA_FROM_DEVICE)
471 chan = host->read_dma_chan;
472 else
473 return -EINVAL;
474
475 dma_dev = chan->device;
476 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
477
478 if (direction == DMA_TO_DEVICE) {
479 dma_src = dma_addr;
480 dma_dst = host->data_pa;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530481 } else {
482 dma_src = host->data_pa;
483 dma_dst = dma_addr;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530484 }
485
486 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
487 len, flags);
Vipin Kumar4774fb02012-03-14 11:47:18 +0530488 if (!tx) {
489 dev_err(host->dev, "device_prep_dma_memcpy error\n");
Bartlomiej Zolnierkiewiczd1806a52012-11-05 10:00:14 +0000490 ret = -EIO;
491 goto unmap_dma;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530492 }
493
494 tx->callback = dma_complete;
495 tx->callback_param = host;
496 cookie = tx->tx_submit(tx);
497
498 ret = dma_submit_error(cookie);
499 if (ret) {
500 dev_err(host->dev, "dma_submit_error %d\n", cookie);
Bartlomiej Zolnierkiewiczd1806a52012-11-05 10:00:14 +0000501 goto unmap_dma;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530502 }
503
504 dma_async_issue_pending(chan);
505
Nicholas Mc Guire818a45b2015-03-13 07:54:46 -0400506 time_left =
Vipin Kumar928aa2a2012-10-09 16:14:48 +0530507 wait_for_completion_timeout(&host->dma_access_complete,
Vipin Kumar4774fb02012-03-14 11:47:18 +0530508 msecs_to_jiffies(3000));
Nicholas Mc Guire818a45b2015-03-13 07:54:46 -0400509 if (time_left == 0) {
Vinod Koulb177ea32014-10-11 21:10:32 +0530510 dmaengine_terminate_all(chan);
Vipin Kumar4774fb02012-03-14 11:47:18 +0530511 dev_err(host->dev, "wait_for_completion_timeout\n");
Nicholas Mc Guire0bda3e12015-03-13 07:54:45 -0400512 ret = -ETIMEDOUT;
Bartlomiej Zolnierkiewiczd1806a52012-11-05 10:00:14 +0000513 goto unmap_dma;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530514 }
515
Bartlomiej Zolnierkiewiczd1806a52012-11-05 10:00:14 +0000516 ret = 0;
517
518unmap_dma:
519 dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
520
521 return ret;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530522}
523
Linus Walleij6c009ab2010-09-13 00:35:22 +0200524/*
Vipin Kumar604e7542012-03-14 11:47:17 +0530525 * fsmc_write_buf - write buffer to chip
526 * @mtd: MTD device structure
527 * @buf: data buffer
528 * @len: number of bytes to write
529 */
530static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
531{
532 int i;
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100533 struct nand_chip *chip = mtd_to_nand(mtd);
Vipin Kumar604e7542012-03-14 11:47:17 +0530534
535 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
536 IS_ALIGNED(len, sizeof(uint32_t))) {
537 uint32_t *p = (uint32_t *)buf;
538 len = len >> 2;
539 for (i = 0; i < len; i++)
Vipin Kumara4742d52012-10-09 16:14:50 +0530540 writel_relaxed(p[i], chip->IO_ADDR_W);
Vipin Kumar604e7542012-03-14 11:47:17 +0530541 } else {
542 for (i = 0; i < len; i++)
Vipin Kumara4742d52012-10-09 16:14:50 +0530543 writeb_relaxed(buf[i], chip->IO_ADDR_W);
Vipin Kumar604e7542012-03-14 11:47:17 +0530544 }
545}
546
547/*
548 * fsmc_read_buf - read chip data into buffer
549 * @mtd: MTD device structure
550 * @buf: buffer to store date
551 * @len: number of bytes to read
552 */
553static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
554{
555 int i;
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100556 struct nand_chip *chip = mtd_to_nand(mtd);
Vipin Kumar604e7542012-03-14 11:47:17 +0530557
558 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
559 IS_ALIGNED(len, sizeof(uint32_t))) {
560 uint32_t *p = (uint32_t *)buf;
561 len = len >> 2;
562 for (i = 0; i < len; i++)
Vipin Kumara4742d52012-10-09 16:14:50 +0530563 p[i] = readl_relaxed(chip->IO_ADDR_R);
Vipin Kumar604e7542012-03-14 11:47:17 +0530564 } else {
565 for (i = 0; i < len; i++)
Vipin Kumara4742d52012-10-09 16:14:50 +0530566 buf[i] = readb_relaxed(chip->IO_ADDR_R);
Vipin Kumar604e7542012-03-14 11:47:17 +0530567 }
568}
569
570/*
Vipin Kumar4774fb02012-03-14 11:47:18 +0530571 * fsmc_read_buf_dma - read chip data into buffer
572 * @mtd: MTD device structure
573 * @buf: buffer to store date
574 * @len: number of bytes to read
575 */
576static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
577{
Boris BREZILLON277af422015-12-10 08:59:46 +0100578 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
Vipin Kumar4774fb02012-03-14 11:47:18 +0530579
Vipin Kumar4774fb02012-03-14 11:47:18 +0530580 dma_xfer(host, buf, len, DMA_FROM_DEVICE);
581}
582
583/*
584 * fsmc_write_buf_dma - write buffer to chip
585 * @mtd: MTD device structure
586 * @buf: data buffer
587 * @len: number of bytes to write
588 */
589static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
590 int len)
591{
Boris BREZILLON277af422015-12-10 08:59:46 +0100592 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
Vipin Kumar4774fb02012-03-14 11:47:18 +0530593
Vipin Kumar4774fb02012-03-14 11:47:18 +0530594 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
595}
596
597/*
Linus Walleij6c009ab2010-09-13 00:35:22 +0200598 * fsmc_read_page_hwecc
599 * @mtd: mtd info structure
600 * @chip: nand chip info structure
601 * @buf: buffer to store read data
Brian Norris1fbb9382012-05-02 10:14:55 -0700602 * @oob_required: caller expects OOB data read to chip->oob_poi
Linus Walleij6c009ab2010-09-13 00:35:22 +0200603 * @page: page number to read
604 *
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300605 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
Linus Walleij6c009ab2010-09-13 00:35:22 +0200606 * performed in a strict sequence as follows:
607 * data(512 byte) -> ecc(13 byte)
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300608 * After this read, fsmc hardware generates and reports error data bits(up to a
Linus Walleij6c009ab2010-09-13 00:35:22 +0200609 * max of 8 bits)
610 */
611static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
Brian Norris1fbb9382012-05-02 10:14:55 -0700612 uint8_t *buf, int oob_required, int page)
Linus Walleij6c009ab2010-09-13 00:35:22 +0200613{
Linus Walleij6c009ab2010-09-13 00:35:22 +0200614 int i, j, s, stat, eccsize = chip->ecc.size;
615 int eccbytes = chip->ecc.bytes;
616 int eccsteps = chip->ecc.steps;
617 uint8_t *p = buf;
618 uint8_t *ecc_calc = chip->buffers->ecccalc;
619 uint8_t *ecc_code = chip->buffers->ecccode;
620 int off, len, group = 0;
621 /*
622 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
623 * end up reading 14 bytes (7 words) from oob. The local array is
624 * to maintain word alignment
625 */
626 uint16_t ecc_oob[7];
627 uint8_t *oob = (uint8_t *)&ecc_oob[0];
Mike Dunn3f91e942012-04-25 12:06:09 -0700628 unsigned int max_bitflips = 0;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200629
630 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
Linus Walleij6c009ab2010-09-13 00:35:22 +0200631 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
632 chip->ecc.hwctl(mtd, NAND_ECC_READ);
633 chip->read_buf(mtd, p, eccsize);
634
635 for (j = 0; j < eccbytes;) {
Boris Brezillon04a123a2016-02-09 15:01:21 +0100636 struct mtd_oob_region oobregion;
637 int ret;
638
639 ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
640 if (ret)
641 return ret;
642
643 off = oobregion.offset;
644 len = oobregion.length;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200645
646 /*
Vipin Kumar4cbe1bf02012-03-14 11:47:09 +0530647 * length is intentionally kept a higher multiple of 2
648 * to read at least 13 bytes even in case of 16 bit NAND
649 * devices
650 */
Vipin Kumaraea686b2012-03-14 11:47:10 +0530651 if (chip->options & NAND_BUSWIDTH_16)
652 len = roundup(len, 2);
653
Linus Walleij6c009ab2010-09-13 00:35:22 +0200654 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
655 chip->read_buf(mtd, oob + j, len);
656 j += len;
657 }
658
Vipin Kumar519300c2012-03-07 17:00:49 +0530659 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200660 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
661
662 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
Mike Dunn3f91e942012-04-25 12:06:09 -0700663 if (stat < 0) {
Linus Walleij6c009ab2010-09-13 00:35:22 +0200664 mtd->ecc_stats.failed++;
Mike Dunn3f91e942012-04-25 12:06:09 -0700665 } else {
Linus Walleij6c009ab2010-09-13 00:35:22 +0200666 mtd->ecc_stats.corrected += stat;
Mike Dunn3f91e942012-04-25 12:06:09 -0700667 max_bitflips = max_t(unsigned int, max_bitflips, stat);
668 }
Linus Walleij6c009ab2010-09-13 00:35:22 +0200669 }
670
Mike Dunn3f91e942012-04-25 12:06:09 -0700671 return max_bitflips;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200672}
673
674/*
Armando Visconti753e0132012-03-07 17:00:54 +0530675 * fsmc_bch8_correct_data
Linus Walleij6c009ab2010-09-13 00:35:22 +0200676 * @mtd: mtd info structure
677 * @dat: buffer of read data
678 * @read_ecc: ecc read from device spare area
679 * @calc_ecc: ecc calculated from read data
680 *
681 * calc_ecc is a 104 bit information containing maximum of 8 error
682 * offset informations of 13 bits each in 512 bytes of read data.
683 */
Armando Visconti753e0132012-03-07 17:00:54 +0530684static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
Linus Walleij6c009ab2010-09-13 00:35:22 +0200685 uint8_t *read_ecc, uint8_t *calc_ecc)
686{
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100687 struct nand_chip *chip = mtd_to_nand(mtd);
Boris BREZILLON277af422015-12-10 08:59:46 +0100688 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530689 void __iomem *regs = host->regs_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200690 unsigned int bank = host->bank;
Armando Viscontia612c2a2012-03-07 17:00:53 +0530691 uint32_t err_idx[8];
Linus Walleij6c009ab2010-09-13 00:35:22 +0200692 uint32_t num_err, i;
Armando Visconti753e0132012-03-07 17:00:54 +0530693 uint32_t ecc1, ecc2, ecc3, ecc4;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200694
Vipin Kumara4742d52012-10-09 16:14:50 +0530695 num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
Vipin Kumar519300c2012-03-07 17:00:49 +0530696
697 /* no bit flipping */
698 if (likely(num_err == 0))
699 return 0;
700
701 /* too many errors */
702 if (unlikely(num_err > 8)) {
703 /*
704 * This is a temporary erase check. A newly erased page read
705 * would result in an ecc error because the oob data is also
706 * erased to FF and the calculated ecc for an FF data is not
707 * FF..FF.
708 * This is a workaround to skip performing correction in case
709 * data is FF..FF
710 *
711 * Logic:
712 * For every page, each bit written as 0 is counted until these
713 * number of bits are greater than 8 (the maximum correction
714 * capability of FSMC for each 512 + 13 bytes)
715 */
716
717 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
718 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
719
720 if ((bits_ecc + bits_data) <= 8) {
721 if (bits_data)
722 memset(dat, 0xff, chip->ecc.size);
723 return bits_data;
724 }
725
726 return -EBADMSG;
727 }
728
Linus Walleij6c009ab2010-09-13 00:35:22 +0200729 /*
730 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
731 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
732 *
733 * calc_ecc is a 104 bit information containing maximum of 8 error
734 * offset informations of 13 bits each. calc_ecc is copied into a
735 * uint64_t array and error offset indexes are populated in err_idx
736 * array
737 */
Vipin Kumara4742d52012-10-09 16:14:50 +0530738 ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
739 ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
740 ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
741 ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200742
Armando Visconti753e0132012-03-07 17:00:54 +0530743 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
744 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
745 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
746 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
747 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
748 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
749 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
750 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200751
752 i = 0;
753 while (num_err--) {
754 change_bit(0, (unsigned long *)&err_idx[i]);
755 change_bit(1, (unsigned long *)&err_idx[i]);
756
Vipin Kumarb533f8d2012-03-14 11:47:11 +0530757 if (err_idx[i] < chip->ecc.size * 8) {
Linus Walleij6c009ab2010-09-13 00:35:22 +0200758 change_bit(err_idx[i], (unsigned long *)dat);
759 i++;
760 }
761 }
762 return i;
763}
764
Vipin Kumar4774fb02012-03-14 11:47:18 +0530765static bool filter(struct dma_chan *chan, void *slave)
766{
767 chan->private = slave;
768 return true;
769}
770
Bill Pemberton06f25512012-11-19 13:23:07 -0500771static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
Thomas Petazzonia1b1e1d2017-03-21 11:04:02 +0100772 struct fsmc_nand_data *host,
773 struct nand_chip *nand)
Stefan Roeseeea62812012-03-16 10:19:31 +0100774{
Thomas Petazzonia1b1e1d2017-03-21 11:04:02 +0100775 struct device_node *np = pdev->dev.of_node;
Stefan Roeseeea62812012-03-16 10:19:31 +0100776 u32 val;
Stefan Roese62b57f42015-03-19 14:34:29 +0100777 int ret;
Stefan Roeseeea62812012-03-16 10:19:31 +0100778
Thomas Petazzonia1b1e1d2017-03-21 11:04:02 +0100779 nand->options = 0;
Thomas Petazzoniee568742017-03-21 11:03:53 +0100780
Stefan Roeseeea62812012-03-16 10:19:31 +0100781 if (!of_property_read_u32(np, "bank-width", &val)) {
782 if (val == 2) {
Thomas Petazzonia1b1e1d2017-03-21 11:04:02 +0100783 nand->options |= NAND_BUSWIDTH_16;
Stefan Roeseeea62812012-03-16 10:19:31 +0100784 } else if (val != 1) {
785 dev_err(&pdev->dev, "invalid bank-width %u\n", val);
786 return -EINVAL;
787 }
788 }
Thomas Petazzoniee568742017-03-21 11:03:53 +0100789
Stefan Roeseeea62812012-03-16 10:19:31 +0100790 if (of_get_property(np, "nand-skip-bbtscan", NULL))
Thomas Petazzonia1b1e1d2017-03-21 11:04:02 +0100791 nand->options |= NAND_SKIP_BBTSCAN;
Stefan Roeseeea62812012-03-16 10:19:31 +0100792
Thomas Petazzonia1b1e1d2017-03-21 11:04:02 +0100793 host->dev_timings = devm_kzalloc(&pdev->dev,
794 sizeof(*host->dev_timings), GFP_KERNEL);
795 if (!host->dev_timings)
Mian Yousaf Kaukab64ddba42013-04-29 14:07:48 +0200796 return -ENOMEM;
Thomas Petazzonia1b1e1d2017-03-21 11:04:02 +0100797 ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
798 sizeof(*host->dev_timings));
Stefan Roese62b57f42015-03-19 14:34:29 +0100799 if (ret) {
800 dev_info(&pdev->dev, "No timings in dts specified, using default timings!\n");
Thomas Petazzonia1b1e1d2017-03-21 11:04:02 +0100801 host->dev_timings = NULL;
Stefan Roese62b57f42015-03-19 14:34:29 +0100802 }
Mian Yousaf Kaukab64ddba42013-04-29 14:07:48 +0200803
804 /* Set default NAND bank to 0 */
Thomas Petazzonia1b1e1d2017-03-21 11:04:02 +0100805 host->bank = 0;
Mian Yousaf Kaukab64ddba42013-04-29 14:07:48 +0200806 if (!of_property_read_u32(np, "bank", &val)) {
807 if (val > 3) {
808 dev_err(&pdev->dev, "invalid bank %u\n", val);
809 return -EINVAL;
810 }
Thomas Petazzonia1b1e1d2017-03-21 11:04:02 +0100811 host->bank = val;
Mian Yousaf Kaukab64ddba42013-04-29 14:07:48 +0200812 }
Stefan Roeseeea62812012-03-16 10:19:31 +0100813 return 0;
814}
Stefan Roeseeea62812012-03-16 10:19:31 +0100815
Linus Walleij6c009ab2010-09-13 00:35:22 +0200816/*
817 * fsmc_nand_probe - Probe function
818 * @pdev: platform device structure
819 */
820static int __init fsmc_nand_probe(struct platform_device *pdev)
821{
Linus Walleij6c009ab2010-09-13 00:35:22 +0200822 struct fsmc_nand_data *host;
823 struct mtd_info *mtd;
824 struct nand_chip *nand;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200825 struct resource *res;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530826 dma_cap_mask_t mask;
Linus Walleij4ad916b2010-11-29 13:52:06 +0100827 int ret = 0;
Linus Walleij593cd872010-11-29 13:52:19 +0100828 u32 pid;
829 int i;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200830
Linus Walleij6c009ab2010-09-13 00:35:22 +0200831 /* Allocate memory for the device structure (and zero it) */
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530832 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
Jingoo Hand9a21ae2013-12-26 12:16:38 +0900833 if (!host)
Linus Walleij6c009ab2010-09-13 00:35:22 +0200834 return -ENOMEM;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200835
Thomas Petazzonia1b1e1d2017-03-21 11:04:02 +0100836 nand = &host->nand;
837
838 ret = fsmc_nand_probe_config_dt(pdev, host, nand);
839 if (ret)
840 return ret;
841
Linus Walleij6c009ab2010-09-13 00:35:22 +0200842 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
Thierry Redingb0de7742013-01-21 11:09:12 +0100843 host->data_va = devm_ioremap_resource(&pdev->dev, res);
844 if (IS_ERR(host->data_va))
845 return PTR_ERR(host->data_va);
Stefan Roesecbf29b82015-10-02 12:40:20 +0200846
Jean-Christophe PLAGNIOL-VILLARD6d7b42a2012-10-04 15:14:16 +0200847 host->data_pa = (dma_addr_t)res->start;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200848
Jean-Christophe PLAGNIOL-VILLARD6d7b42a2012-10-04 15:14:16 +0200849 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
Thierry Redingb0de7742013-01-21 11:09:12 +0100850 host->addr_va = devm_ioremap_resource(&pdev->dev, res);
851 if (IS_ERR(host->addr_va))
852 return PTR_ERR(host->addr_va);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200853
Jean-Christophe PLAGNIOL-VILLARD6d7b42a2012-10-04 15:14:16 +0200854 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
Thierry Redingb0de7742013-01-21 11:09:12 +0100855 host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
856 if (IS_ERR(host->cmd_va))
857 return PTR_ERR(host->cmd_va);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200858
859 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
Thierry Redingb0de7742013-01-21 11:09:12 +0100860 host->regs_va = devm_ioremap_resource(&pdev->dev, res);
861 if (IS_ERR(host->regs_va))
862 return PTR_ERR(host->regs_va);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200863
Thomas Petazzonifb8ed2c2017-03-21 11:04:03 +0100864 host->clk = devm_clk_get(&pdev->dev, NULL);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200865 if (IS_ERR(host->clk)) {
866 dev_err(&pdev->dev, "failed to fetch block clock\n");
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530867 return PTR_ERR(host->clk);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200868 }
869
Viresh Kumare25da1c2012-04-17 17:07:57 +0530870 ret = clk_prepare_enable(host->clk);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200871 if (ret)
Thomas Petazzonifb8ed2c2017-03-21 11:04:03 +0100872 return ret;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200873
Linus Walleij593cd872010-11-29 13:52:19 +0100874 /*
875 * This device ID is actually a common AMBA ID as used on the
876 * AMBA PrimeCell bus. However it is not a PrimeCell.
877 */
878 for (pid = 0, i = 0; i < 4; i++)
879 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
880 host->pid = pid;
881 dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
882 "revision %02x, config %02x\n",
883 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
884 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
885
Vipin Kumar712c4ad2012-03-14 11:47:16 +0530886 host->dev = &pdev->dev;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530887
888 if (host->mode == USE_DMA_ACCESS)
889 init_completion(&host->dma_access_complete);
890
Linus Walleij6c009ab2010-09-13 00:35:22 +0200891 /* Link all private pointers */
Boris BREZILLONbdf3a552015-12-10 09:00:05 +0100892 mtd = nand_to_mtd(&host->nand);
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100893 nand_set_controller_data(nand, host);
Thomas Petazzonia1b1e1d2017-03-21 11:04:02 +0100894 nand_set_flash_node(nand, pdev->dev.of_node);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200895
Boris BREZILLONbdf3a552015-12-10 09:00:05 +0100896 mtd->dev.parent = &pdev->dev;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200897 nand->IO_ADDR_R = host->data_va;
898 nand->IO_ADDR_W = host->data_va;
899 nand->cmd_ctrl = fsmc_cmd_ctrl;
900 nand->chip_delay = 30;
901
Stefan Roesee278fc72015-10-19 08:40:13 +0200902 /*
903 * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
904 * can overwrite this value if the DT provides a different value.
905 */
Linus Walleij6c009ab2010-09-13 00:35:22 +0200906 nand->ecc.mode = NAND_ECC_HW;
907 nand->ecc.hwctl = fsmc_enable_hwecc;
908 nand->ecc.size = 512;
Vipin Kumar467e6e72012-03-14 11:47:12 +0530909 nand->badblockbits = 7;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200910
Vipin Kumar4774fb02012-03-14 11:47:18 +0530911 switch (host->mode) {
912 case USE_DMA_ACCESS:
913 dma_cap_zero(mask);
914 dma_cap_set(DMA_MEMCPY, mask);
Thomas Petazzonifeb1e572017-03-21 11:03:59 +0100915 host->read_dma_chan = dma_request_channel(mask, filter, NULL);
Vipin Kumar4774fb02012-03-14 11:47:18 +0530916 if (!host->read_dma_chan) {
917 dev_err(&pdev->dev, "Unable to get read dma channel\n");
918 goto err_req_read_chnl;
919 }
Thomas Petazzonifeb1e572017-03-21 11:03:59 +0100920 host->write_dma_chan = dma_request_channel(mask, filter, NULL);
Vipin Kumar4774fb02012-03-14 11:47:18 +0530921 if (!host->write_dma_chan) {
922 dev_err(&pdev->dev, "Unable to get write dma channel\n");
923 goto err_req_write_chnl;
924 }
925 nand->read_buf = fsmc_read_buf_dma;
926 nand->write_buf = fsmc_write_buf_dma;
927 break;
928
929 default:
930 case USE_WORD_ACCESS:
Vipin Kumar604e7542012-03-14 11:47:17 +0530931 nand->read_buf = fsmc_read_buf;
932 nand->write_buf = fsmc_write_buf;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530933 break;
Vipin Kumar604e7542012-03-14 11:47:17 +0530934 }
935
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530936 fsmc_nand_setup(host->regs_va, host->bank,
937 nand->options & NAND_BUSWIDTH_16,
Vipin Kumare2f6bce2012-03-14 11:47:14 +0530938 host->dev_timings);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200939
Linus Walleij593cd872010-11-29 13:52:19 +0100940 if (AMBA_REV_BITS(host->pid) >= 8) {
Linus Walleij6c009ab2010-09-13 00:35:22 +0200941 nand->ecc.read_page = fsmc_read_page_hwecc;
942 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
Armando Visconti753e0132012-03-07 17:00:54 +0530943 nand->ecc.correct = fsmc_bch8_correct_data;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200944 nand->ecc.bytes = 13;
Mike Dunn6a918ba2012-03-11 14:21:11 -0700945 nand->ecc.strength = 8;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200946 }
947
948 /*
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300949 * Scan to find existence of the device
Linus Walleij6c009ab2010-09-13 00:35:22 +0200950 */
Masahiro Yamadaad5678e2016-11-04 19:43:00 +0900951 ret = nand_scan_ident(mtd, 1, NULL);
952 if (ret) {
Linus Walleij6c009ab2010-09-13 00:35:22 +0200953 dev_err(&pdev->dev, "No NAND Device found!\n");
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530954 goto err_scan_ident;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200955 }
956
Linus Walleij593cd872010-11-29 13:52:19 +0100957 if (AMBA_REV_BITS(host->pid) >= 8) {
Boris BREZILLONbdf3a552015-12-10 09:00:05 +0100958 switch (mtd->oobsize) {
Bhavna Yadave29ee572012-03-07 17:00:50 +0530959 case 16:
Bhavna Yadave29ee572012-03-07 17:00:50 +0530960 case 64:
Bhavna Yadave29ee572012-03-07 17:00:50 +0530961 case 128:
Armando Visconti0c78e932012-03-07 17:00:55 +0530962 case 224:
Bhavna Yadave29ee572012-03-07 17:00:50 +0530963 case 256:
Bhavna Yadave29ee572012-03-07 17:00:50 +0530964 break;
965 default:
Jingoo Han67b19a62013-12-26 12:31:25 +0900966 dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
967 mtd->oobsize);
Stefan Roese6efadcf2015-10-02 12:40:21 +0200968 ret = -EINVAL;
969 goto err_probe;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200970 }
Boris Brezillon22b46952016-02-03 20:01:42 +0100971
972 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200973 } else {
Stefan Roesee278fc72015-10-19 08:40:13 +0200974 switch (nand->ecc.mode) {
975 case NAND_ECC_HW:
976 dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
977 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
978 nand->ecc.correct = nand_correct_data;
979 nand->ecc.bytes = 3;
980 nand->ecc.strength = 1;
Bhavna Yadave29ee572012-03-07 17:00:50 +0530981 break;
Stefan Roesee278fc72015-10-19 08:40:13 +0200982
Rafał Miłeckief296dc2016-04-17 22:53:04 +0200983 case NAND_ECC_SOFT:
Rafał Miłeckief296dc2016-04-17 22:53:04 +0200984 if (nand->ecc.algo == NAND_ECC_BCH) {
985 dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
986 break;
987 }
Stefan Roesee278fc72015-10-19 08:40:13 +0200988
Bhavna Yadave29ee572012-03-07 17:00:50 +0530989 default:
Stefan Roesee278fc72015-10-19 08:40:13 +0200990 dev_err(&pdev->dev, "Unsupported ECC mode!\n");
Stefan Roese6efadcf2015-10-02 12:40:21 +0200991 goto err_probe;
Bhavna Yadave29ee572012-03-07 17:00:50 +0530992 }
Stefan Roesee278fc72015-10-19 08:40:13 +0200993
994 /*
995 * Don't set layout for BCH4 SW ECC. This will be
996 * generated later in nand_bch_init() later.
997 */
Rafał Miłeckie4225ae2016-04-17 22:53:07 +0200998 if (nand->ecc.mode == NAND_ECC_HW) {
Boris BREZILLONbdf3a552015-12-10 09:00:05 +0100999 switch (mtd->oobsize) {
Stefan Roesee278fc72015-10-19 08:40:13 +02001000 case 16:
Stefan Roesee278fc72015-10-19 08:40:13 +02001001 case 64:
Stefan Roesee278fc72015-10-19 08:40:13 +02001002 case 128:
Boris Brezillon22b46952016-02-03 20:01:42 +01001003 mtd_set_ooblayout(mtd,
1004 &fsmc_ecc1_ooblayout_ops);
Stefan Roesee278fc72015-10-19 08:40:13 +02001005 break;
1006 default:
1007 dev_warn(&pdev->dev,
1008 "No oob scheme defined for oobsize %d\n",
1009 mtd->oobsize);
1010 ret = -EINVAL;
1011 goto err_probe;
1012 }
1013 }
Linus Walleij6c009ab2010-09-13 00:35:22 +02001014 }
1015
1016 /* Second stage of scan to fill MTD data-structures */
Masahiro Yamadaad5678e2016-11-04 19:43:00 +09001017 ret = nand_scan_tail(mtd);
1018 if (ret)
Linus Walleij6c009ab2010-09-13 00:35:22 +02001019 goto err_probe;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001020
Boris BREZILLONbdf3a552015-12-10 09:00:05 +01001021 mtd->name = "nand";
Thomas Petazzoniede29a02017-03-21 11:04:00 +01001022 ret = mtd_device_register(mtd, NULL, 0);
Jamie Iles99335d02011-05-23 10:23:23 +01001023 if (ret)
Linus Walleij6c009ab2010-09-13 00:35:22 +02001024 goto err_probe;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001025
1026 platform_set_drvdata(pdev, host);
1027 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1028 return 0;
1029
1030err_probe:
Vipin Kumar82b9dbe2012-03-14 11:47:15 +05301031err_scan_ident:
Vipin Kumar4774fb02012-03-14 11:47:18 +05301032 if (host->mode == USE_DMA_ACCESS)
1033 dma_release_channel(host->write_dma_chan);
1034err_req_write_chnl:
1035 if (host->mode == USE_DMA_ACCESS)
1036 dma_release_channel(host->read_dma_chan);
1037err_req_read_chnl:
Viresh Kumare25da1c2012-04-17 17:07:57 +05301038 clk_disable_unprepare(host->clk);
Linus Walleij6c009ab2010-09-13 00:35:22 +02001039 return ret;
1040}
1041
1042/*
1043 * Clean up routine
1044 */
1045static int fsmc_nand_remove(struct platform_device *pdev)
1046{
1047 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1048
Linus Walleij6c009ab2010-09-13 00:35:22 +02001049 if (host) {
Boris BREZILLONbdf3a552015-12-10 09:00:05 +01001050 nand_release(nand_to_mtd(&host->nand));
Vipin Kumar4774fb02012-03-14 11:47:18 +05301051
1052 if (host->mode == USE_DMA_ACCESS) {
1053 dma_release_channel(host->write_dma_chan);
1054 dma_release_channel(host->read_dma_chan);
1055 }
Viresh Kumare25da1c2012-04-17 17:07:57 +05301056 clk_disable_unprepare(host->clk);
Linus Walleij6c009ab2010-09-13 00:35:22 +02001057 }
Vipin Kumar82b9dbe2012-03-14 11:47:15 +05301058
Linus Walleij6c009ab2010-09-13 00:35:22 +02001059 return 0;
1060}
1061
Jingoo Han80ce4dd2013-03-26 15:53:48 +09001062#ifdef CONFIG_PM_SLEEP
Linus Walleij6c009ab2010-09-13 00:35:22 +02001063static int fsmc_nand_suspend(struct device *dev)
1064{
1065 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1066 if (host)
Viresh Kumare25da1c2012-04-17 17:07:57 +05301067 clk_disable_unprepare(host->clk);
Linus Walleij6c009ab2010-09-13 00:35:22 +02001068 return 0;
1069}
1070
1071static int fsmc_nand_resume(struct device *dev)
1072{
1073 struct fsmc_nand_data *host = dev_get_drvdata(dev);
Shiraz Hashimf63acb72012-03-14 11:47:13 +05301074 if (host) {
Viresh Kumare25da1c2012-04-17 17:07:57 +05301075 clk_prepare_enable(host->clk);
Shiraz Hashimf63acb72012-03-14 11:47:13 +05301076 fsmc_nand_setup(host->regs_va, host->bank,
Vipin Kumare2f6bce2012-03-14 11:47:14 +05301077 host->nand.options & NAND_BUSWIDTH_16,
1078 host->dev_timings);
Shiraz Hashimf63acb72012-03-14 11:47:13 +05301079 }
Linus Walleij6c009ab2010-09-13 00:35:22 +02001080 return 0;
1081}
Jingoo Han80ce4dd2013-03-26 15:53:48 +09001082#endif
Linus Walleij6c009ab2010-09-13 00:35:22 +02001083
Shiraz Hashimf63acb72012-03-14 11:47:13 +05301084static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
Linus Walleij6c009ab2010-09-13 00:35:22 +02001085
Stefan Roeseeea62812012-03-16 10:19:31 +01001086static const struct of_device_id fsmc_nand_id_table[] = {
1087 { .compatible = "st,spear600-fsmc-nand" },
Linus Walleijba785202013-01-05 22:28:32 +01001088 { .compatible = "stericsson,fsmc-nand" },
Stefan Roeseeea62812012-03-16 10:19:31 +01001089 {}
1090};
1091MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
Stefan Roeseeea62812012-03-16 10:19:31 +01001092
Linus Walleij6c009ab2010-09-13 00:35:22 +02001093static struct platform_driver fsmc_nand_driver = {
1094 .remove = fsmc_nand_remove,
1095 .driver = {
Linus Walleij6c009ab2010-09-13 00:35:22 +02001096 .name = "fsmc-nand",
Thomas Petazzoni33575b22017-03-21 11:04:05 +01001097 .of_match_table = fsmc_nand_id_table,
Linus Walleij6c009ab2010-09-13 00:35:22 +02001098 .pm = &fsmc_nand_pm_ops,
Linus Walleij6c009ab2010-09-13 00:35:22 +02001099 },
1100};
1101
Jingoo Han307d2a512013-03-05 13:30:36 +09001102module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
Linus Walleij6c009ab2010-09-13 00:35:22 +02001103
1104MODULE_LICENSE("GPL");
1105MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1106MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");