| Stefan Wahren | 88bbe85 | 2017-08-06 17:52:02 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Root interrupt controller for the BCM2836 (Raspberry Pi 2). |
| 3 | * |
| 4 | * Copyright 2015 Broadcom |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #define LOCAL_CONTROL 0x000 |
| 18 | #define LOCAL_PRESCALER 0x008 |
| 19 | |
| 20 | /* |
| 21 | * The low 2 bits identify the CPU that the GPU IRQ goes to, and the |
| 22 | * next 2 bits identify the CPU that the GPU FIQ goes to. |
| 23 | */ |
| 24 | #define LOCAL_GPU_ROUTING 0x00c |
| 25 | /* When setting bits 0-3, enables PMU interrupts on that CPU. */ |
| 26 | #define LOCAL_PM_ROUTING_SET 0x010 |
| 27 | /* When setting bits 0-3, disables PMU interrupts on that CPU. */ |
| 28 | #define LOCAL_PM_ROUTING_CLR 0x014 |
| 29 | /* |
| 30 | * The low 4 bits of this are the CPU's timer IRQ enables, and the |
| 31 | * next 4 bits are the CPU's timer FIQ enables (which override the IRQ |
| 32 | * bits). |
| 33 | */ |
| 34 | #define LOCAL_TIMER_INT_CONTROL0 0x040 |
| 35 | /* |
| 36 | * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and |
| 37 | * the next 4 bits are the CPU's per-mailbox FIQ enables (which |
| 38 | * override the IRQ bits). |
| 39 | */ |
| 40 | #define LOCAL_MAILBOX_INT_CONTROL0 0x050 |
| 41 | /* |
| 42 | * The CPU's interrupt status register. Bits are defined by the the |
| 43 | * LOCAL_IRQ_* bits below. |
| 44 | */ |
| 45 | #define LOCAL_IRQ_PENDING0 0x060 |
| 46 | /* Same status bits as above, but for FIQ. */ |
| 47 | #define LOCAL_FIQ_PENDING0 0x070 |
| 48 | /* |
| 49 | * Mailbox write-to-set bits. There are 16 mailboxes, 4 per CPU, and |
| 50 | * these bits are organized by mailbox number and then CPU number. We |
| 51 | * use mailbox 0 for IPIs. The mailbox's interrupt is raised while |
| 52 | * any bit is set. |
| 53 | */ |
| 54 | #define LOCAL_MAILBOX0_SET0 0x080 |
| 55 | #define LOCAL_MAILBOX3_SET0 0x08c |
| 56 | /* Mailbox write-to-clear bits. */ |
| 57 | #define LOCAL_MAILBOX0_CLR0 0x0c0 |
| 58 | #define LOCAL_MAILBOX3_CLR0 0x0cc |
| 59 | |
| 60 | #define LOCAL_IRQ_CNTPSIRQ 0 |
| 61 | #define LOCAL_IRQ_CNTPNSIRQ 1 |
| 62 | #define LOCAL_IRQ_CNTHPIRQ 2 |
| 63 | #define LOCAL_IRQ_CNTVIRQ 3 |
| 64 | #define LOCAL_IRQ_MAILBOX0 4 |
| 65 | #define LOCAL_IRQ_MAILBOX1 5 |
| 66 | #define LOCAL_IRQ_MAILBOX2 6 |
| 67 | #define LOCAL_IRQ_MAILBOX3 7 |
| 68 | #define LOCAL_IRQ_GPU_FAST 8 |
| 69 | #define LOCAL_IRQ_PMU_FAST 9 |
| 70 | #define LAST_IRQ LOCAL_IRQ_PMU_FAST |