blob: 2a0c1e93f82e1532abf4a3fe0248c7405e4e8549 [file] [log] [blame]
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
Thierry Reding9eb9b222013-09-24 16:32:47 +020011#include <linux/debugfs.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020012#include <linux/iommu.h>
Thierry Redingb9ff7ae2017-08-21 16:35:17 +020013#include <linux/of_device.h>
Thierry Reding33a8eb82015-08-03 13:20:49 +020014#include <linux/pm_runtime.h>
Stephen Warrenca480802013-11-06 16:20:54 -070015#include <linux/reset.h>
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000016
Thierry Reding9c012702014-07-07 15:32:53 +020017#include <soc/tegra/pmc.h>
18
Arto Merilainende2ba662013-03-22 16:34:08 +020019#include "dc.h"
20#include "drm.h"
21#include "gem.h"
Thierry Reding47307952017-08-30 17:42:54 +020022#include "hub.h"
Thierry Reding5acd3512017-11-10 15:27:25 +010023#include "plane.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000024
Thierry Reding9d441892014-11-24 17:02:53 +010025#include <drm/drm_atomic.h>
Thierry Reding4aa3df72014-11-24 16:27:13 +010026#include <drm/drm_atomic_helper.h>
Daniel Vetter3cb9ae42014-10-29 10:03:57 +010027#include <drm/drm_plane_helper.h>
28
Thierry Reding791ddb12015-07-28 21:27:05 +020029static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
30{
31 stats->frames = 0;
32 stats->vblank = 0;
33 stats->underflow = 0;
34 stats->overflow = 0;
35}
36
Thierry Reding1087fac2017-12-14 13:37:53 +010037/* Reads the active copy of a register. */
Thierry Reding86df2562014-12-08 16:03:53 +010038static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
39{
Thierry Reding86df2562014-12-08 16:03:53 +010040 u32 value;
41
Thierry Reding86df2562014-12-08 16:03:53 +010042 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
43 value = tegra_dc_readl(dc, offset);
44 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
45
Thierry Reding86df2562014-12-08 16:03:53 +010046 return value;
47}
48
Thierry Reding1087fac2017-12-14 13:37:53 +010049static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
50 unsigned int offset)
51{
52 if (offset >= 0x500 && offset <= 0x638) {
53 offset = 0x000 + (offset - 0x500);
54 return plane->offset + offset;
55 }
56
57 if (offset >= 0x700 && offset <= 0x719) {
58 offset = 0x180 + (offset - 0x700);
59 return plane->offset + offset;
60 }
61
62 if (offset >= 0x800 && offset <= 0x839) {
63 offset = 0x1c0 + (offset - 0x800);
64 return plane->offset + offset;
65 }
66
67 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
68
69 return plane->offset + offset;
70}
71
72static inline u32 tegra_plane_readl(struct tegra_plane *plane,
73 unsigned int offset)
74{
75 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
76}
77
78static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
79 unsigned int offset)
80{
81 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
82}
83
Thierry Redingc57997b2017-10-12 19:12:57 +020084bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
85{
86 struct device_node *np = dc->dev->of_node;
87 struct of_phandle_iterator it;
88 int err;
89
90 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
91 if (it.node == dev->of_node)
92 return true;
93
94 return false;
95}
96
Thierry Reding86df2562014-12-08 16:03:53 +010097/*
Thierry Redingd700ba72014-12-08 15:50:04 +010098 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
99 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
100 * Latching happens mmediately if the display controller is in STOP mode or
101 * on the next frame boundary otherwise.
102 *
103 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
104 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
105 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
106 * into the ACTIVE copy, either immediately if the display controller is in
107 * STOP mode, or at the next frame boundary otherwise.
108 */
Thierry Reding62b9e062014-11-21 17:33:33 +0100109void tegra_dc_commit(struct tegra_dc *dc)
Thierry Reding205d48e2014-10-21 13:41:46 +0200110{
111 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
112 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
113}
114
Thierry Reding10288ee2014-03-14 09:54:58 +0100115static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
116 unsigned int bpp)
117{
118 fixed20_12 outf = dfixed_init(out);
119 fixed20_12 inf = dfixed_init(in);
120 u32 dda_inc;
121 int max;
122
123 if (v)
124 max = 15;
125 else {
126 switch (bpp) {
127 case 2:
128 max = 8;
129 break;
130
131 default:
132 WARN_ON_ONCE(1);
133 /* fallthrough */
134 case 4:
135 max = 4;
136 break;
137 }
138 }
139
140 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
141 inf.full -= dfixed_const(1);
142
143 dda_inc = dfixed_div(inf, outf);
144 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
145
146 return dda_inc;
147}
148
149static inline u32 compute_initial_dda(unsigned int in)
150{
151 fixed20_12 inf = dfixed_init(in);
152 return dfixed_frac(inf);
153}
154
Thierry Redingab7d3f52017-12-14 13:46:20 +0100155static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
156{
157 /*
158 * Disable blending and assume Window A is the bottom-most window,
159 * Window C is the top-most window and Window B is in the middle.
160 */
161 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_NOKEY);
162 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_1WIN);
163
164 switch (plane->index) {
165 case 0:
166 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_2WIN_X);
167 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_2WIN_Y);
168 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_3WIN_XY);
169 break;
170
171 case 1:
172 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_2WIN_X);
173 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_2WIN_Y);
174 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_3WIN_XY);
175 break;
176
177 case 2:
178 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_2WIN_X);
179 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_2WIN_Y);
180 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_3WIN_XY);
181 break;
182 }
183}
184
185static void tegra_plane_setup_blending(struct tegra_plane *plane,
186 const struct tegra_dc_window *window)
187{
188 u32 value;
189
190 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
191 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
192 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
193 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
194
195 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
196 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
197 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
198 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
199
200 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
201 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
202}
203
Thierry Reding1087fac2017-12-14 13:37:53 +0100204static void tegra_dc_setup_window(struct tegra_plane *plane,
Thierry Reding4aa3df72014-11-24 16:27:13 +0100205 const struct tegra_dc_window *window)
Thierry Reding10288ee2014-03-14 09:54:58 +0100206{
207 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
Thierry Reding1087fac2017-12-14 13:37:53 +0100208 struct tegra_dc *dc = plane->dc;
Thierry Reding10288ee2014-03-14 09:54:58 +0100209 bool yuv, planar;
Thierry Reding1087fac2017-12-14 13:37:53 +0100210 u32 value;
Thierry Reding10288ee2014-03-14 09:54:58 +0100211
212 /*
213 * For YUV planar modes, the number of bytes per pixel takes into
214 * account only the luma component and therefore is 1.
215 */
Thierry Reding5acd3512017-11-10 15:27:25 +0100216 yuv = tegra_plane_format_is_yuv(window->format, &planar);
Thierry Reding10288ee2014-03-14 09:54:58 +0100217 if (!yuv)
218 bpp = window->bits_per_pixel / 8;
219 else
220 bpp = planar ? 1 : 2;
221
Thierry Reding1087fac2017-12-14 13:37:53 +0100222 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
223 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
Thierry Reding10288ee2014-03-14 09:54:58 +0100224
225 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
Thierry Reding1087fac2017-12-14 13:37:53 +0100226 tegra_plane_writel(plane, value, DC_WIN_POSITION);
Thierry Reding10288ee2014-03-14 09:54:58 +0100227
228 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
Thierry Reding1087fac2017-12-14 13:37:53 +0100229 tegra_plane_writel(plane, value, DC_WIN_SIZE);
Thierry Reding10288ee2014-03-14 09:54:58 +0100230
231 h_offset = window->src.x * bpp;
232 v_offset = window->src.y;
233 h_size = window->src.w * bpp;
234 v_size = window->src.h;
235
236 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
Thierry Reding1087fac2017-12-14 13:37:53 +0100237 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
Thierry Reding10288ee2014-03-14 09:54:58 +0100238
239 /*
240 * For DDA computations the number of bytes per pixel for YUV planar
241 * modes needs to take into account all Y, U and V components.
242 */
243 if (yuv && planar)
244 bpp = 2;
245
246 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
247 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
248
249 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
Thierry Reding1087fac2017-12-14 13:37:53 +0100250 tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
Thierry Reding10288ee2014-03-14 09:54:58 +0100251
252 h_dda = compute_initial_dda(window->src.x);
253 v_dda = compute_initial_dda(window->src.y);
254
Thierry Reding1087fac2017-12-14 13:37:53 +0100255 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
256 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
Thierry Reding10288ee2014-03-14 09:54:58 +0100257
Thierry Reding1087fac2017-12-14 13:37:53 +0100258 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
259 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
Thierry Reding10288ee2014-03-14 09:54:58 +0100260
Thierry Reding1087fac2017-12-14 13:37:53 +0100261 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
Thierry Reding10288ee2014-03-14 09:54:58 +0100262
263 if (yuv && planar) {
Thierry Reding1087fac2017-12-14 13:37:53 +0100264 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
265 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
Thierry Reding10288ee2014-03-14 09:54:58 +0100266 value = window->stride[1] << 16 | window->stride[0];
Thierry Reding1087fac2017-12-14 13:37:53 +0100267 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
Thierry Reding10288ee2014-03-14 09:54:58 +0100268 } else {
Thierry Reding1087fac2017-12-14 13:37:53 +0100269 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
Thierry Reding10288ee2014-03-14 09:54:58 +0100270 }
271
272 if (window->bottom_up)
273 v_offset += window->src.h - 1;
274
Thierry Reding1087fac2017-12-14 13:37:53 +0100275 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
276 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
Thierry Reding10288ee2014-03-14 09:54:58 +0100277
Thierry Redingc134f012014-06-03 14:48:12 +0200278 if (dc->soc->supports_block_linear) {
279 unsigned long height = window->tiling.value;
Thierry Reding10288ee2014-03-14 09:54:58 +0100280
Thierry Redingc134f012014-06-03 14:48:12 +0200281 switch (window->tiling.mode) {
282 case TEGRA_BO_TILING_MODE_PITCH:
283 value = DC_WINBUF_SURFACE_KIND_PITCH;
284 break;
285
286 case TEGRA_BO_TILING_MODE_TILED:
287 value = DC_WINBUF_SURFACE_KIND_TILED;
288 break;
289
290 case TEGRA_BO_TILING_MODE_BLOCK:
291 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
292 DC_WINBUF_SURFACE_KIND_BLOCK;
293 break;
294 }
295
Thierry Reding1087fac2017-12-14 13:37:53 +0100296 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
Thierry Redingc134f012014-06-03 14:48:12 +0200297 } else {
298 switch (window->tiling.mode) {
299 case TEGRA_BO_TILING_MODE_PITCH:
300 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
301 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
302 break;
303
304 case TEGRA_BO_TILING_MODE_TILED:
305 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
306 DC_WIN_BUFFER_ADDR_MODE_TILE;
307 break;
308
309 case TEGRA_BO_TILING_MODE_BLOCK:
Thierry Reding4aa3df72014-11-24 16:27:13 +0100310 /*
311 * No need to handle this here because ->atomic_check
312 * will already have filtered it out.
313 */
314 break;
Thierry Redingc134f012014-06-03 14:48:12 +0200315 }
316
Thierry Reding1087fac2017-12-14 13:37:53 +0100317 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
Thierry Redingc134f012014-06-03 14:48:12 +0200318 }
Thierry Reding10288ee2014-03-14 09:54:58 +0100319
320 value = WIN_ENABLE;
321
322 if (yuv) {
323 /* setup default colorspace conversion coefficients */
Thierry Reding1087fac2017-12-14 13:37:53 +0100324 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
325 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
326 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
327 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
328 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
329 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
330 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
331 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
Thierry Reding10288ee2014-03-14 09:54:58 +0100332
333 value |= CSC_ENABLE;
334 } else if (window->bits_per_pixel < 24) {
335 value |= COLOR_EXPAND;
336 }
337
338 if (window->bottom_up)
339 value |= V_DIRECTION;
340
Thierry Reding1087fac2017-12-14 13:37:53 +0100341 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
Thierry Reding10288ee2014-03-14 09:54:58 +0100342
Thierry Redingab7d3f52017-12-14 13:46:20 +0100343 if (dc->soc->supports_blending)
344 tegra_plane_setup_blending(plane, window);
345 else
346 tegra_plane_setup_blending_legacy(plane);
Thierry Redingc7679302014-10-21 13:51:53 +0200347}
348
Thierry Reding511c7022017-11-14 16:07:40 +0100349static const u32 tegra20_primary_formats[] = {
350 DRM_FORMAT_ARGB4444,
351 DRM_FORMAT_ARGB1555,
Thierry Redingc7679302014-10-21 13:51:53 +0200352 DRM_FORMAT_RGB565,
Thierry Reding511c7022017-11-14 16:07:40 +0100353 DRM_FORMAT_RGBA5551,
354 DRM_FORMAT_ABGR8888,
355 DRM_FORMAT_ARGB8888,
356};
357
358static const u32 tegra114_primary_formats[] = {
359 DRM_FORMAT_ARGB4444,
360 DRM_FORMAT_ARGB1555,
361 DRM_FORMAT_RGB565,
362 DRM_FORMAT_RGBA5551,
363 DRM_FORMAT_ABGR8888,
364 DRM_FORMAT_ARGB8888,
365 /* new on Tegra114 */
366 DRM_FORMAT_ABGR4444,
367 DRM_FORMAT_ABGR1555,
368 DRM_FORMAT_BGRA5551,
369 DRM_FORMAT_XRGB1555,
370 DRM_FORMAT_RGBX5551,
371 DRM_FORMAT_XBGR1555,
372 DRM_FORMAT_BGRX5551,
373 DRM_FORMAT_BGR565,
374 DRM_FORMAT_BGRA8888,
375 DRM_FORMAT_RGBA8888,
376 DRM_FORMAT_XRGB8888,
377 DRM_FORMAT_XBGR8888,
378};
379
380static const u32 tegra124_primary_formats[] = {
381 DRM_FORMAT_ARGB4444,
382 DRM_FORMAT_ARGB1555,
383 DRM_FORMAT_RGB565,
384 DRM_FORMAT_RGBA5551,
385 DRM_FORMAT_ABGR8888,
386 DRM_FORMAT_ARGB8888,
387 /* new on Tegra114 */
388 DRM_FORMAT_ABGR4444,
389 DRM_FORMAT_ABGR1555,
390 DRM_FORMAT_BGRA5551,
391 DRM_FORMAT_XRGB1555,
392 DRM_FORMAT_RGBX5551,
393 DRM_FORMAT_XBGR1555,
394 DRM_FORMAT_BGRX5551,
395 DRM_FORMAT_BGR565,
396 DRM_FORMAT_BGRA8888,
397 DRM_FORMAT_RGBA8888,
398 DRM_FORMAT_XRGB8888,
399 DRM_FORMAT_XBGR8888,
400 /* new on Tegra124 */
401 DRM_FORMAT_RGBX8888,
402 DRM_FORMAT_BGRX8888,
Thierry Redingc7679302014-10-21 13:51:53 +0200403};
404
Thierry Reding4aa3df72014-11-24 16:27:13 +0100405static int tegra_plane_atomic_check(struct drm_plane *plane,
406 struct drm_plane_state *state)
407{
Thierry Reding8f604f82014-11-28 13:14:55 +0100408 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
409 struct tegra_bo_tiling *tiling = &plane_state->tiling;
Thierry Reding47802b02014-11-26 12:28:39 +0100410 struct tegra_plane *tegra = to_tegra_plane(plane);
Thierry Reding4aa3df72014-11-24 16:27:13 +0100411 struct tegra_dc *dc = to_tegra_dc(state->crtc);
Thierry Redingc7679302014-10-21 13:51:53 +0200412 int err;
413
Thierry Reding4aa3df72014-11-24 16:27:13 +0100414 /* no need for further checks if the plane is being disabled */
415 if (!state->crtc)
416 return 0;
417
Thierry Reding5acd3512017-11-10 15:27:25 +0100418 err = tegra_plane_format(state->fb->format->format,
419 &plane_state->format,
420 &plane_state->swap);
Thierry Reding4aa3df72014-11-24 16:27:13 +0100421 if (err < 0)
422 return err;
423
Thierry Reding8f604f82014-11-28 13:14:55 +0100424 err = tegra_fb_get_tiling(state->fb, tiling);
425 if (err < 0)
426 return err;
427
428 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
Thierry Reding4aa3df72014-11-24 16:27:13 +0100429 !dc->soc->supports_block_linear) {
430 DRM_ERROR("hardware doesn't support block linear mode\n");
431 return -EINVAL;
432 }
433
434 /*
435 * Tegra doesn't support different strides for U and V planes so we
436 * error out if the user tries to display a framebuffer with such a
437 * configuration.
438 */
Ville Syrjäläbcb0b462016-12-14 23:30:22 +0200439 if (state->fb->format->num_planes > 2) {
Thierry Reding4aa3df72014-11-24 16:27:13 +0100440 if (state->fb->pitches[2] != state->fb->pitches[1]) {
441 DRM_ERROR("unsupported UV-plane configuration\n");
442 return -EINVAL;
443 }
444 }
445
Thierry Reding47802b02014-11-26 12:28:39 +0100446 err = tegra_plane_state_add(tegra, state);
447 if (err < 0)
448 return err;
449
Thierry Reding4aa3df72014-11-24 16:27:13 +0100450 return 0;
451}
452
Thierry Redinga4bfa092017-08-30 17:34:10 +0200453static void tegra_plane_atomic_disable(struct drm_plane *plane,
454 struct drm_plane_state *old_state)
Dmitry Osipenko80d3eef2017-06-15 02:18:31 +0300455{
Thierry Redinga4bfa092017-08-30 17:34:10 +0200456 struct tegra_plane *p = to_tegra_plane(plane);
Dmitry Osipenko80d3eef2017-06-15 02:18:31 +0300457 u32 value;
458
Thierry Redinga4bfa092017-08-30 17:34:10 +0200459 /* rien ne va plus */
460 if (!old_state || !old_state->crtc)
461 return;
462
Thierry Reding1087fac2017-12-14 13:37:53 +0100463 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
Dmitry Osipenko80d3eef2017-06-15 02:18:31 +0300464 value &= ~WIN_ENABLE;
Thierry Reding1087fac2017-12-14 13:37:53 +0100465 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
Dmitry Osipenko80d3eef2017-06-15 02:18:31 +0300466}
467
Thierry Reding4aa3df72014-11-24 16:27:13 +0100468static void tegra_plane_atomic_update(struct drm_plane *plane,
469 struct drm_plane_state *old_state)
470{
Thierry Reding8f604f82014-11-28 13:14:55 +0100471 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
Thierry Reding4aa3df72014-11-24 16:27:13 +0100472 struct drm_framebuffer *fb = plane->state->fb;
473 struct tegra_plane *p = to_tegra_plane(plane);
474 struct tegra_dc_window window;
475 unsigned int i;
Thierry Reding4aa3df72014-11-24 16:27:13 +0100476
477 /* rien ne va plus */
478 if (!plane->state->crtc || !plane->state->fb)
479 return;
480
Dmitry Osipenko80d3eef2017-06-15 02:18:31 +0300481 if (!plane->state->visible)
Thierry Redinga4bfa092017-08-30 17:34:10 +0200482 return tegra_plane_atomic_disable(plane, old_state);
Dmitry Osipenko80d3eef2017-06-15 02:18:31 +0300483
Thierry Redingc7679302014-10-21 13:51:53 +0200484 memset(&window, 0, sizeof(window));
Dmitry Osipenko7d205852017-06-15 02:18:30 +0300485 window.src.x = plane->state->src.x1 >> 16;
486 window.src.y = plane->state->src.y1 >> 16;
487 window.src.w = drm_rect_width(&plane->state->src) >> 16;
488 window.src.h = drm_rect_height(&plane->state->src) >> 16;
489 window.dst.x = plane->state->dst.x1;
490 window.dst.y = plane->state->dst.y1;
491 window.dst.w = drm_rect_width(&plane->state->dst);
492 window.dst.h = drm_rect_height(&plane->state->dst);
Ville Syrjälä272725c2016-12-14 23:32:20 +0200493 window.bits_per_pixel = fb->format->cpp[0] * 8;
Thierry Redingc7679302014-10-21 13:51:53 +0200494 window.bottom_up = tegra_fb_is_bottom_up(fb);
495
Thierry Reding8f604f82014-11-28 13:14:55 +0100496 /* copy from state */
Thierry Redingab7d3f52017-12-14 13:46:20 +0100497 window.zpos = plane->state->normalized_zpos;
Thierry Reding8f604f82014-11-28 13:14:55 +0100498 window.tiling = state->tiling;
499 window.format = state->format;
500 window.swap = state->swap;
Thierry Redingc7679302014-10-21 13:51:53 +0200501
Ville Syrjäläbcb0b462016-12-14 23:30:22 +0200502 for (i = 0; i < fb->format->num_planes; i++) {
Thierry Reding4aa3df72014-11-24 16:27:13 +0100503 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
Thierry Redingc7679302014-10-21 13:51:53 +0200504
Thierry Reding4aa3df72014-11-24 16:27:13 +0100505 window.base[i] = bo->paddr + fb->offsets[i];
Dmitry Osipenko08ee0172016-08-21 11:57:58 +0300506
507 /*
508 * Tegra uses a shared stride for UV planes. Framebuffers are
509 * already checked for this in the tegra_plane_atomic_check()
510 * function, so it's safe to ignore the V-plane pitch here.
511 */
512 if (i < 2)
513 window.stride[i] = fb->pitches[i];
Thierry Reding4aa3df72014-11-24 16:27:13 +0100514 }
Thierry Redingc7679302014-10-21 13:51:53 +0200515
Thierry Reding1087fac2017-12-14 13:37:53 +0100516 tegra_dc_setup_window(p, &window);
Thierry Redingc7679302014-10-21 13:51:53 +0200517}
518
Thierry Redinga4bfa092017-08-30 17:34:10 +0200519static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
Thierry Reding4aa3df72014-11-24 16:27:13 +0100520 .atomic_check = tegra_plane_atomic_check,
Thierry Reding4aa3df72014-11-24 16:27:13 +0100521 .atomic_disable = tegra_plane_atomic_disable,
Thierry Redinga4bfa092017-08-30 17:34:10 +0200522 .atomic_update = tegra_plane_atomic_update,
Thierry Redingc7679302014-10-21 13:51:53 +0200523};
524
Thierry Reding47307952017-08-30 17:42:54 +0200525static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
526 struct tegra_dc *dc)
Thierry Redingc7679302014-10-21 13:51:53 +0200527{
Thierry Reding518e6222014-12-16 18:04:08 +0100528 /*
529 * Ideally this would use drm_crtc_mask(), but that would require the
530 * CRTC to already be in the mode_config's list of CRTCs. However, it
531 * will only be added to that list in the drm_crtc_init_with_planes()
532 * (in tegra_dc_init()), which in turn requires registration of these
533 * planes. So we have ourselves a nice little chicken and egg problem
534 * here.
535 *
536 * We work around this by manually creating the mask from the number
537 * of CRTCs that have been registered, and should therefore always be
538 * the same as drm_crtc_index() after registration.
539 */
540 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
Thierry Reding47307952017-08-30 17:42:54 +0200541 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
Thierry Redingc7679302014-10-21 13:51:53 +0200542 struct tegra_plane *plane;
543 unsigned int num_formats;
544 const u32 *formats;
545 int err;
546
547 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
548 if (!plane)
549 return ERR_PTR(-ENOMEM);
550
Thierry Reding1087fac2017-12-14 13:37:53 +0100551 /* Always use window A as primary window */
552 plane->offset = 0xa00;
Thierry Redingc4755fb2017-11-13 11:08:13 +0100553 plane->index = 0;
Thierry Reding1087fac2017-12-14 13:37:53 +0100554 plane->dc = dc;
555
556 num_formats = dc->soc->num_primary_formats;
557 formats = dc->soc->primary_formats;
Thierry Redingc4755fb2017-11-13 11:08:13 +0100558
Thierry Reding518e6222014-12-16 18:04:08 +0100559 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
Thierry Redingc1cb4b62017-08-30 18:04:12 +0200560 &tegra_plane_funcs, formats,
Thierry Reding47307952017-08-30 17:42:54 +0200561 num_formats, NULL, type, NULL);
Thierry Redingc7679302014-10-21 13:51:53 +0200562 if (err < 0) {
563 kfree(plane);
564 return ERR_PTR(err);
565 }
566
Thierry Redinga4bfa092017-08-30 17:34:10 +0200567 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
Thierry Reding4aa3df72014-11-24 16:27:13 +0100568
Thierry Redingab7d3f52017-12-14 13:46:20 +0100569 if (dc->soc->supports_blending)
570 drm_plane_create_zpos_property(&plane->base, 0, 0, 255);
571
Thierry Redingc7679302014-10-21 13:51:53 +0200572 return &plane->base;
573}
574
575static const u32 tegra_cursor_plane_formats[] = {
576 DRM_FORMAT_RGBA8888,
577};
578
Thierry Reding4aa3df72014-11-24 16:27:13 +0100579static int tegra_cursor_atomic_check(struct drm_plane *plane,
580 struct drm_plane_state *state)
Thierry Redingc7679302014-10-21 13:51:53 +0200581{
Thierry Reding47802b02014-11-26 12:28:39 +0100582 struct tegra_plane *tegra = to_tegra_plane(plane);
583 int err;
584
Thierry Reding4aa3df72014-11-24 16:27:13 +0100585 /* no need for further checks if the plane is being disabled */
586 if (!state->crtc)
587 return 0;
Thierry Redingc7679302014-10-21 13:51:53 +0200588
589 /* scaling not supported for cursor */
Thierry Reding4aa3df72014-11-24 16:27:13 +0100590 if ((state->src_w >> 16 != state->crtc_w) ||
591 (state->src_h >> 16 != state->crtc_h))
Thierry Redingc7679302014-10-21 13:51:53 +0200592 return -EINVAL;
593
594 /* only square cursors supported */
Thierry Reding4aa3df72014-11-24 16:27:13 +0100595 if (state->src_w != state->src_h)
Thierry Redingc7679302014-10-21 13:51:53 +0200596 return -EINVAL;
597
Thierry Reding4aa3df72014-11-24 16:27:13 +0100598 if (state->crtc_w != 32 && state->crtc_w != 64 &&
599 state->crtc_w != 128 && state->crtc_w != 256)
600 return -EINVAL;
601
Thierry Reding47802b02014-11-26 12:28:39 +0100602 err = tegra_plane_state_add(tegra, state);
603 if (err < 0)
604 return err;
605
Thierry Reding4aa3df72014-11-24 16:27:13 +0100606 return 0;
607}
608
609static void tegra_cursor_atomic_update(struct drm_plane *plane,
610 struct drm_plane_state *old_state)
611{
612 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
613 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
614 struct drm_plane_state *state = plane->state;
615 u32 value = CURSOR_CLIP_DISPLAY;
616
617 /* rien ne va plus */
618 if (!plane->state->crtc || !plane->state->fb)
619 return;
620
621 switch (state->crtc_w) {
Thierry Redingc7679302014-10-21 13:51:53 +0200622 case 32:
623 value |= CURSOR_SIZE_32x32;
624 break;
625
626 case 64:
627 value |= CURSOR_SIZE_64x64;
628 break;
629
630 case 128:
631 value |= CURSOR_SIZE_128x128;
632 break;
633
634 case 256:
635 value |= CURSOR_SIZE_256x256;
636 break;
637
638 default:
Thierry Reding4aa3df72014-11-24 16:27:13 +0100639 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
640 state->crtc_h);
641 return;
Thierry Redingc7679302014-10-21 13:51:53 +0200642 }
643
644 value |= (bo->paddr >> 10) & 0x3fffff;
645 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
646
647#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
648 value = (bo->paddr >> 32) & 0x3;
649 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
650#endif
651
652 /* enable cursor and set blend mode */
653 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
654 value |= CURSOR_ENABLE;
655 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
656
657 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
658 value &= ~CURSOR_DST_BLEND_MASK;
659 value &= ~CURSOR_SRC_BLEND_MASK;
660 value |= CURSOR_MODE_NORMAL;
661 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
662 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
663 value |= CURSOR_ALPHA;
664 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
665
666 /* position the cursor */
Thierry Reding4aa3df72014-11-24 16:27:13 +0100667 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
Thierry Redingc7679302014-10-21 13:51:53 +0200668 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
Thierry Redingc7679302014-10-21 13:51:53 +0200669}
670
Thierry Reding4aa3df72014-11-24 16:27:13 +0100671static void tegra_cursor_atomic_disable(struct drm_plane *plane,
672 struct drm_plane_state *old_state)
Thierry Redingc7679302014-10-21 13:51:53 +0200673{
Thierry Reding4aa3df72014-11-24 16:27:13 +0100674 struct tegra_dc *dc;
Thierry Redingc7679302014-10-21 13:51:53 +0200675 u32 value;
676
Thierry Reding4aa3df72014-11-24 16:27:13 +0100677 /* rien ne va plus */
678 if (!old_state || !old_state->crtc)
679 return;
680
681 dc = to_tegra_dc(old_state->crtc);
Thierry Redingc7679302014-10-21 13:51:53 +0200682
683 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
684 value &= ~CURSOR_ENABLE;
685 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
Thierry Redingc7679302014-10-21 13:51:53 +0200686}
687
Thierry Reding4aa3df72014-11-24 16:27:13 +0100688static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
Thierry Reding4aa3df72014-11-24 16:27:13 +0100689 .atomic_check = tegra_cursor_atomic_check,
690 .atomic_update = tegra_cursor_atomic_update,
691 .atomic_disable = tegra_cursor_atomic_disable,
Thierry Redingc7679302014-10-21 13:51:53 +0200692};
693
694static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
695 struct tegra_dc *dc)
696{
697 struct tegra_plane *plane;
698 unsigned int num_formats;
699 const u32 *formats;
700 int err;
701
702 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
703 if (!plane)
704 return ERR_PTR(-ENOMEM);
705
Thierry Reding47802b02014-11-26 12:28:39 +0100706 /*
Thierry Redinga1df3b22015-07-21 16:42:30 +0200707 * This index is kind of fake. The cursor isn't a regular plane, but
708 * its update and activation request bits in DC_CMD_STATE_CONTROL do
709 * use the same programming. Setting this fake index here allows the
710 * code in tegra_add_plane_state() to do the right thing without the
711 * need to special-casing the cursor plane.
Thierry Reding47802b02014-11-26 12:28:39 +0100712 */
713 plane->index = 6;
Thierry Reding1087fac2017-12-14 13:37:53 +0100714 plane->dc = dc;
Thierry Reding47802b02014-11-26 12:28:39 +0100715
Thierry Redingc7679302014-10-21 13:51:53 +0200716 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
717 formats = tegra_cursor_plane_formats;
718
719 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
Thierry Redingc1cb4b62017-08-30 18:04:12 +0200720 &tegra_plane_funcs, formats,
Ben Widawskye6fc3b62017-07-23 20:46:38 -0700721 num_formats, NULL,
722 DRM_PLANE_TYPE_CURSOR, NULL);
Thierry Redingc7679302014-10-21 13:51:53 +0200723 if (err < 0) {
724 kfree(plane);
725 return ERR_PTR(err);
726 }
727
Thierry Reding4aa3df72014-11-24 16:27:13 +0100728 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
729
Thierry Redingc7679302014-10-21 13:51:53 +0200730 return &plane->base;
731}
732
Thierry Reding511c7022017-11-14 16:07:40 +0100733static const u32 tegra20_overlay_formats[] = {
734 DRM_FORMAT_ARGB4444,
735 DRM_FORMAT_ARGB1555,
Thierry Redingdbe4d9a2013-03-22 15:37:30 +0100736 DRM_FORMAT_RGB565,
Thierry Reding511c7022017-11-14 16:07:40 +0100737 DRM_FORMAT_RGBA5551,
738 DRM_FORMAT_ABGR8888,
739 DRM_FORMAT_ARGB8888,
740 /* planar formats */
741 DRM_FORMAT_UYVY,
742 DRM_FORMAT_YUYV,
743 DRM_FORMAT_YUV420,
744 DRM_FORMAT_YUV422,
745};
746
747static const u32 tegra114_overlay_formats[] = {
748 DRM_FORMAT_ARGB4444,
749 DRM_FORMAT_ARGB1555,
750 DRM_FORMAT_RGB565,
751 DRM_FORMAT_RGBA5551,
752 DRM_FORMAT_ABGR8888,
753 DRM_FORMAT_ARGB8888,
754 /* new on Tegra114 */
755 DRM_FORMAT_ABGR4444,
756 DRM_FORMAT_ABGR1555,
757 DRM_FORMAT_BGRA5551,
758 DRM_FORMAT_XRGB1555,
759 DRM_FORMAT_RGBX5551,
760 DRM_FORMAT_XBGR1555,
761 DRM_FORMAT_BGRX5551,
762 DRM_FORMAT_BGR565,
763 DRM_FORMAT_BGRA8888,
764 DRM_FORMAT_RGBA8888,
765 DRM_FORMAT_XRGB8888,
766 DRM_FORMAT_XBGR8888,
767 /* planar formats */
768 DRM_FORMAT_UYVY,
769 DRM_FORMAT_YUYV,
770 DRM_FORMAT_YUV420,
771 DRM_FORMAT_YUV422,
772};
773
774static const u32 tegra124_overlay_formats[] = {
775 DRM_FORMAT_ARGB4444,
776 DRM_FORMAT_ARGB1555,
777 DRM_FORMAT_RGB565,
778 DRM_FORMAT_RGBA5551,
779 DRM_FORMAT_ABGR8888,
780 DRM_FORMAT_ARGB8888,
781 /* new on Tegra114 */
782 DRM_FORMAT_ABGR4444,
783 DRM_FORMAT_ABGR1555,
784 DRM_FORMAT_BGRA5551,
785 DRM_FORMAT_XRGB1555,
786 DRM_FORMAT_RGBX5551,
787 DRM_FORMAT_XBGR1555,
788 DRM_FORMAT_BGRX5551,
789 DRM_FORMAT_BGR565,
790 DRM_FORMAT_BGRA8888,
791 DRM_FORMAT_RGBA8888,
792 DRM_FORMAT_XRGB8888,
793 DRM_FORMAT_XBGR8888,
794 /* new on Tegra124 */
795 DRM_FORMAT_RGBX8888,
796 DRM_FORMAT_BGRX8888,
797 /* planar formats */
Thierry Redingf34bc782012-11-04 21:47:13 +0100798 DRM_FORMAT_UYVY,
Thierry Redingf9253902014-01-29 20:31:17 +0100799 DRM_FORMAT_YUYV,
Thierry Redingf34bc782012-11-04 21:47:13 +0100800 DRM_FORMAT_YUV420,
801 DRM_FORMAT_YUV422,
802};
803
Thierry Redingc7679302014-10-21 13:51:53 +0200804static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
805 struct tegra_dc *dc,
806 unsigned int index)
807{
808 struct tegra_plane *plane;
809 unsigned int num_formats;
810 const u32 *formats;
811 int err;
812
813 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
814 if (!plane)
815 return ERR_PTR(-ENOMEM);
816
Thierry Reding1087fac2017-12-14 13:37:53 +0100817 plane->offset = 0xa00 + 0x200 * index;
Thierry Redingc7679302014-10-21 13:51:53 +0200818 plane->index = index;
Thierry Reding1087fac2017-12-14 13:37:53 +0100819 plane->dc = dc;
Thierry Redingc7679302014-10-21 13:51:53 +0200820
Thierry Reding511c7022017-11-14 16:07:40 +0100821 num_formats = dc->soc->num_overlay_formats;
822 formats = dc->soc->overlay_formats;
Thierry Redingc7679302014-10-21 13:51:53 +0200823
824 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
Thierry Reding301e0dd2017-08-30 18:04:12 +0200825 &tegra_plane_funcs, formats,
Ben Widawskye6fc3b62017-07-23 20:46:38 -0700826 num_formats, NULL,
827 DRM_PLANE_TYPE_OVERLAY, NULL);
Thierry Redingc7679302014-10-21 13:51:53 +0200828 if (err < 0) {
829 kfree(plane);
830 return ERR_PTR(err);
831 }
832
Thierry Redinga4bfa092017-08-30 17:34:10 +0200833 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
Thierry Reding4aa3df72014-11-24 16:27:13 +0100834
Thierry Redingab7d3f52017-12-14 13:46:20 +0100835 if (dc->soc->supports_blending)
836 drm_plane_create_zpos_property(&plane->base, 0, 0, 255);
837
Thierry Redingc7679302014-10-21 13:51:53 +0200838 return &plane->base;
839}
840
Thierry Reding47307952017-08-30 17:42:54 +0200841static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
842 struct tegra_dc *dc)
Thierry Redingf34bc782012-11-04 21:47:13 +0100843{
Thierry Reding47307952017-08-30 17:42:54 +0200844 struct drm_plane *plane, *primary = NULL;
845 unsigned int i, j;
846
847 for (i = 0; i < dc->soc->num_wgrps; i++) {
848 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
849
850 if (wgrp->dc == dc->pipe) {
851 for (j = 0; j < wgrp->num_windows; j++) {
852 unsigned int index = wgrp->windows[j];
853
854 plane = tegra_shared_plane_create(drm, dc,
855 wgrp->index,
856 index);
857 if (IS_ERR(plane))
858 return plane;
859
860 /*
861 * Choose the first shared plane owned by this
862 * head as the primary plane.
863 */
864 if (!primary) {
865 plane->type = DRM_PLANE_TYPE_PRIMARY;
866 primary = plane;
867 }
868 }
869 }
870 }
871
872 return primary;
873}
874
875static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
876 struct tegra_dc *dc)
877{
878 struct drm_plane *plane, *primary;
Thierry Redingf34bc782012-11-04 21:47:13 +0100879 unsigned int i;
Thierry Redingf34bc782012-11-04 21:47:13 +0100880
Thierry Reding47307952017-08-30 17:42:54 +0200881 primary = tegra_primary_plane_create(drm, dc);
882 if (IS_ERR(primary))
883 return primary;
884
Thierry Redingf34bc782012-11-04 21:47:13 +0100885 for (i = 0; i < 2; i++) {
Thierry Redingc7679302014-10-21 13:51:53 +0200886 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
Thierry Reding47307952017-08-30 17:42:54 +0200887 if (IS_ERR(plane)) {
888 /* XXX tegra_plane_destroy() */
889 drm_plane_cleanup(primary);
890 kfree(primary);
891 return plane;
892 }
Thierry Redingf34bc782012-11-04 21:47:13 +0100893 }
894
Thierry Reding47307952017-08-30 17:42:54 +0200895 return primary;
Thierry Redingf34bc782012-11-04 21:47:13 +0100896}
897
Thierry Redingf002abc2013-10-14 14:06:02 +0200898static void tegra_dc_destroy(struct drm_crtc *crtc)
899{
900 drm_crtc_cleanup(crtc);
Thierry Redingf002abc2013-10-14 14:06:02 +0200901}
902
Thierry Redingca915b12014-12-08 16:14:45 +0100903static void tegra_crtc_reset(struct drm_crtc *crtc)
904{
905 struct tegra_dc_state *state;
906
Thierry Reding3b59b7ac2015-01-28 15:01:22 +0100907 if (crtc->state)
Daniel Vetterec2dc6a2016-05-09 16:34:09 +0200908 __drm_atomic_helper_crtc_destroy_state(crtc->state);
Thierry Reding3b59b7ac2015-01-28 15:01:22 +0100909
Thierry Redingca915b12014-12-08 16:14:45 +0100910 kfree(crtc->state);
911 crtc->state = NULL;
912
913 state = kzalloc(sizeof(*state), GFP_KERNEL);
Thierry Reding332bbe72015-01-28 15:03:31 +0100914 if (state) {
Thierry Redingca915b12014-12-08 16:14:45 +0100915 crtc->state = &state->base;
Thierry Reding332bbe72015-01-28 15:03:31 +0100916 crtc->state->crtc = crtc;
917 }
Thierry Reding31930d42015-07-02 17:04:06 +0200918
919 drm_crtc_vblank_reset(crtc);
Thierry Redingca915b12014-12-08 16:14:45 +0100920}
921
922static struct drm_crtc_state *
923tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
924{
925 struct tegra_dc_state *state = to_dc_state(crtc->state);
926 struct tegra_dc_state *copy;
927
Thierry Reding3b59b7ac2015-01-28 15:01:22 +0100928 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
Thierry Redingca915b12014-12-08 16:14:45 +0100929 if (!copy)
930 return NULL;
931
Thierry Reding3b59b7ac2015-01-28 15:01:22 +0100932 __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
933 copy->clk = state->clk;
934 copy->pclk = state->pclk;
935 copy->div = state->div;
936 copy->planes = state->planes;
Thierry Redingca915b12014-12-08 16:14:45 +0100937
938 return &copy->base;
939}
940
941static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
942 struct drm_crtc_state *state)
943{
Daniel Vetterec2dc6a2016-05-09 16:34:09 +0200944 __drm_atomic_helper_crtc_destroy_state(state);
Thierry Redingca915b12014-12-08 16:14:45 +0100945 kfree(state);
946}
947
Thierry Redingb95800e2017-11-08 13:40:54 +0100948#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
949
950static const struct debugfs_reg32 tegra_dc_regs[] = {
951 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
952 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
953 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
954 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
955 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
956 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
957 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
958 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
959 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
960 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
961 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
962 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
963 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
964 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
965 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
966 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
967 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
968 DEBUGFS_REG32(DC_CMD_INT_STATUS),
969 DEBUGFS_REG32(DC_CMD_INT_MASK),
970 DEBUGFS_REG32(DC_CMD_INT_ENABLE),
971 DEBUGFS_REG32(DC_CMD_INT_TYPE),
972 DEBUGFS_REG32(DC_CMD_INT_POLARITY),
973 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
974 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
975 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
976 DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
977 DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
978 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
979 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
980 DEBUGFS_REG32(DC_COM_CRC_CONTROL),
981 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
982 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
983 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
984 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
985 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
986 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
987 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
988 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
989 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
990 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
991 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
992 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
993 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
994 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
995 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
996 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
997 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
998 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
999 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1000 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1001 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1002 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1003 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1004 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1005 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1006 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1007 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1008 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1009 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1010 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1011 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1012 DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1013 DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1014 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1015 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1016 DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1017 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1018 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1019 DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1020 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1021 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1022 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1023 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1024 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1025 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1026 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1027 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1028 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1029 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1030 DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1031 DEBUGFS_REG32(DC_DISP_ACTIVE),
1032 DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1033 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1034 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1035 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1036 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1037 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1038 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1039 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1040 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1041 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1042 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1043 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1044 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1045 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1046 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1047 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1048 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1049 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1050 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1051 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1052 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1053 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1054 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1055 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1056 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1057 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1058 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1059 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1060 DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1061 DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1062 DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1063 DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1064 DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1065 DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1066 DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1067 DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1068 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1069 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1070 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1071 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1072 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1073 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1074 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1075 DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1076 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1077 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1078 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1079 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1080 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1081 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1082 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1083 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1084 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1085 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1086 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1087 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1088 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1089 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1090 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1091 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1092 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1093 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1094 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1095 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1096 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1097 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1098 DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1099 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1100 DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1101 DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1102 DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1103 DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1104 DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1105 DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1106 DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1107 DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1108 DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1109 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1110 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1111 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1112 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1113 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1114 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1115 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1116 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1117 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1118 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1119 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1120 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1121 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1122 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1123 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1124 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1125 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1126 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1127 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1128 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1129 DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1130 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1131 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1132 DEBUGFS_REG32(DC_WIN_POSITION),
1133 DEBUGFS_REG32(DC_WIN_SIZE),
1134 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1135 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1136 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1137 DEBUGFS_REG32(DC_WIN_DDA_INC),
1138 DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1139 DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1140 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1141 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1142 DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1143 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1144 DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1145 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1146 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1147 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1148 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1149 DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1150 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1151 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1152 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1153 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1154 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1155 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1156 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1157 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1158 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1159 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1160 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1161 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1162 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1163};
1164
1165static int tegra_dc_show_regs(struct seq_file *s, void *data)
1166{
1167 struct drm_info_node *node = s->private;
1168 struct tegra_dc *dc = node->info_ent->data;
1169 unsigned int i;
1170 int err = 0;
1171
1172 drm_modeset_lock(&dc->base.mutex, NULL);
1173
1174 if (!dc->base.state->active) {
1175 err = -EBUSY;
1176 goto unlock;
1177 }
1178
1179 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1180 unsigned int offset = tegra_dc_regs[i].offset;
1181
1182 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1183 offset, tegra_dc_readl(dc, offset));
1184 }
1185
1186unlock:
1187 drm_modeset_unlock(&dc->base.mutex);
1188 return err;
1189}
1190
1191static int tegra_dc_show_crc(struct seq_file *s, void *data)
1192{
1193 struct drm_info_node *node = s->private;
1194 struct tegra_dc *dc = node->info_ent->data;
1195 int err = 0;
1196 u32 value;
1197
1198 drm_modeset_lock(&dc->base.mutex, NULL);
1199
1200 if (!dc->base.state->active) {
1201 err = -EBUSY;
1202 goto unlock;
1203 }
1204
1205 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1206 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1207 tegra_dc_commit(dc);
1208
1209 drm_crtc_wait_one_vblank(&dc->base);
1210 drm_crtc_wait_one_vblank(&dc->base);
1211
1212 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1213 seq_printf(s, "%08x\n", value);
1214
1215 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1216
1217unlock:
1218 drm_modeset_unlock(&dc->base.mutex);
1219 return err;
1220}
1221
1222static int tegra_dc_show_stats(struct seq_file *s, void *data)
1223{
1224 struct drm_info_node *node = s->private;
1225 struct tegra_dc *dc = node->info_ent->data;
1226
1227 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1228 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1229 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1230 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1231
1232 return 0;
1233}
1234
1235static struct drm_info_list debugfs_files[] = {
1236 { "regs", tegra_dc_show_regs, 0, NULL },
1237 { "crc", tegra_dc_show_crc, 0, NULL },
1238 { "stats", tegra_dc_show_stats, 0, NULL },
1239};
1240
1241static int tegra_dc_late_register(struct drm_crtc *crtc)
1242{
1243 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1244 struct drm_minor *minor = crtc->dev->primary;
Arnd Bergmann39f55c62017-12-18 14:44:46 +01001245 struct dentry *root;
Thierry Redingb95800e2017-11-08 13:40:54 +01001246 struct tegra_dc *dc = to_tegra_dc(crtc);
1247 int err;
1248
Arnd Bergmann39f55c62017-12-18 14:44:46 +01001249#ifdef CONFIG_DEBUG_FS
1250 root = crtc->debugfs_entry;
1251#else
1252 root = NULL;
1253#endif
1254
Thierry Redingb95800e2017-11-08 13:40:54 +01001255 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1256 GFP_KERNEL);
1257 if (!dc->debugfs_files)
1258 return -ENOMEM;
1259
1260 for (i = 0; i < count; i++)
1261 dc->debugfs_files[i].data = dc;
1262
1263 err = drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1264 if (err < 0)
1265 goto free;
1266
1267 return 0;
1268
1269free:
1270 kfree(dc->debugfs_files);
1271 dc->debugfs_files = NULL;
1272
1273 return err;
1274}
1275
1276static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1277{
1278 unsigned int count = ARRAY_SIZE(debugfs_files);
1279 struct drm_minor *minor = crtc->dev->primary;
1280 struct tegra_dc *dc = to_tegra_dc(crtc);
1281
1282 drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1283 kfree(dc->debugfs_files);
1284 dc->debugfs_files = NULL;
1285}
1286
Thierry Redingc49c81e2017-11-08 13:32:05 +01001287static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1288{
1289 struct tegra_dc *dc = to_tegra_dc(crtc);
1290
Thierry Reding47307952017-08-30 17:42:54 +02001291 /* XXX vblank syncpoints don't work with nvdisplay yet */
1292 if (dc->syncpt && !dc->soc->has_nvdisplay)
Thierry Redingc49c81e2017-11-08 13:32:05 +01001293 return host1x_syncpt_read(dc->syncpt);
1294
1295 /* fallback to software emulated VBLANK counter */
1296 return drm_crtc_vblank_count(&dc->base);
1297}
1298
1299static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1300{
1301 struct tegra_dc *dc = to_tegra_dc(crtc);
Thierry Reding363541e2017-12-14 13:50:19 +01001302 u32 value;
Thierry Redingc49c81e2017-11-08 13:32:05 +01001303
1304 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1305 value |= VBLANK_INT;
1306 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1307
Thierry Redingc49c81e2017-11-08 13:32:05 +01001308 return 0;
1309}
1310
1311static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1312{
1313 struct tegra_dc *dc = to_tegra_dc(crtc);
Thierry Reding363541e2017-12-14 13:50:19 +01001314 u32 value;
Thierry Redingc49c81e2017-11-08 13:32:05 +01001315
1316 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1317 value &= ~VBLANK_INT;
1318 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
Thierry Redingc49c81e2017-11-08 13:32:05 +01001319}
1320
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001321static const struct drm_crtc_funcs tegra_crtc_funcs = {
Thierry Reding1503ca42014-11-24 17:41:23 +01001322 .page_flip = drm_atomic_helper_page_flip,
Thierry Reding74f48792014-11-24 17:08:20 +01001323 .set_config = drm_atomic_helper_set_config,
Thierry Redingf002abc2013-10-14 14:06:02 +02001324 .destroy = tegra_dc_destroy,
Thierry Redingca915b12014-12-08 16:14:45 +01001325 .reset = tegra_crtc_reset,
1326 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1327 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
Thierry Redingb95800e2017-11-08 13:40:54 +01001328 .late_register = tegra_dc_late_register,
1329 .early_unregister = tegra_dc_early_unregister,
Shawn Guo10437d92017-02-07 17:16:32 +08001330 .get_vblank_counter = tegra_dc_get_vblank_counter,
1331 .enable_vblank = tegra_dc_enable_vblank,
1332 .disable_vblank = tegra_dc_disable_vblank,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001333};
1334
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001335static int tegra_dc_set_timings(struct tegra_dc *dc,
1336 struct drm_display_mode *mode)
1337{
Thierry Reding0444c0f2014-04-16 09:22:38 +02001338 unsigned int h_ref_to_sync = 1;
1339 unsigned int v_ref_to_sync = 1;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001340 unsigned long value;
1341
Thierry Reding47307952017-08-30 17:42:54 +02001342 if (!dc->soc->has_nvdisplay) {
1343 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001344
Thierry Reding47307952017-08-30 17:42:54 +02001345 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1346 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1347 }
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001348
1349 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1350 ((mode->hsync_end - mode->hsync_start) << 0);
1351 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1352
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001353 value = ((mode->vtotal - mode->vsync_end) << 16) |
1354 ((mode->htotal - mode->hsync_end) << 0);
Lucas Stach40495082012-12-19 21:38:52 +00001355 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1356
1357 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1358 ((mode->hsync_start - mode->hdisplay) << 0);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001359 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1360
1361 value = (mode->vdisplay << 16) | mode->hdisplay;
1362 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1363
1364 return 0;
1365}
1366
Thierry Reding9d910b62015-01-28 15:25:54 +01001367/**
1368 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1369 * state
1370 * @dc: display controller
1371 * @crtc_state: CRTC atomic state
1372 * @clk: parent clock for display controller
1373 * @pclk: pixel clock
1374 * @div: shift clock divider
1375 *
1376 * Returns:
1377 * 0 on success or a negative error-code on failure.
1378 */
Thierry Redingca915b12014-12-08 16:14:45 +01001379int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1380 struct drm_crtc_state *crtc_state,
1381 struct clk *clk, unsigned long pclk,
1382 unsigned int div)
1383{
1384 struct tegra_dc_state *state = to_dc_state(crtc_state);
1385
Thierry Redingd2982742015-01-22 08:48:25 +01001386 if (!clk_has_parent(dc->clk, clk))
1387 return -EINVAL;
1388
Thierry Redingca915b12014-12-08 16:14:45 +01001389 state->clk = clk;
1390 state->pclk = pclk;
1391 state->div = div;
1392
1393 return 0;
1394}
1395
Thierry Reding76d59ed2014-12-19 15:09:16 +01001396static void tegra_dc_commit_state(struct tegra_dc *dc,
1397 struct tegra_dc_state *state)
1398{
1399 u32 value;
1400 int err;
1401
1402 err = clk_set_parent(dc->clk, state->clk);
1403 if (err < 0)
1404 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1405
1406 /*
1407 * Outputs may not want to change the parent clock rate. This is only
1408 * relevant to Tegra20 where only a single display PLL is available.
1409 * Since that PLL would typically be used for HDMI, an internal LVDS
1410 * panel would need to be driven by some other clock such as PLL_P
1411 * which is shared with other peripherals. Changing the clock rate
1412 * should therefore be avoided.
1413 */
1414 if (state->pclk > 0) {
1415 err = clk_set_rate(state->clk, state->pclk);
1416 if (err < 0)
1417 dev_err(dc->dev,
1418 "failed to set clock rate to %lu Hz\n",
1419 state->pclk);
1420 }
1421
1422 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1423 state->div);
1424 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1425
Thierry Reding47307952017-08-30 17:42:54 +02001426 if (!dc->soc->has_nvdisplay) {
1427 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1428 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1429 }
Thierry Reding39e08af2017-08-30 17:38:39 +02001430
1431 err = clk_set_rate(dc->clk, state->pclk);
1432 if (err < 0)
1433 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1434 dc->clk, state->pclk, err);
Thierry Reding76d59ed2014-12-19 15:09:16 +01001435}
1436
Thierry Reding003fc842015-08-03 13:16:26 +02001437static void tegra_dc_stop(struct tegra_dc *dc)
1438{
1439 u32 value;
1440
1441 /* stop the display controller */
1442 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1443 value &= ~DISP_CTRL_MODE_MASK;
1444 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1445
1446 tegra_dc_commit(dc);
1447}
1448
1449static bool tegra_dc_idle(struct tegra_dc *dc)
1450{
1451 u32 value;
1452
1453 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1454
1455 return (value & DISP_CTRL_MODE_MASK) == 0;
1456}
1457
1458static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1459{
1460 timeout = jiffies + msecs_to_jiffies(timeout);
1461
1462 while (time_before(jiffies, timeout)) {
1463 if (tegra_dc_idle(dc))
1464 return 0;
1465
1466 usleep_range(1000, 2000);
1467 }
1468
1469 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1470 return -ETIMEDOUT;
1471}
1472
Laurent Pinchart64581712017-06-30 12:36:45 +03001473static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1474 struct drm_crtc_state *old_state)
Thierry Reding003fc842015-08-03 13:16:26 +02001475{
1476 struct tegra_dc *dc = to_tegra_dc(crtc);
1477 u32 value;
1478
1479 if (!tegra_dc_idle(dc)) {
1480 tegra_dc_stop(dc);
1481
1482 /*
1483 * Ignore the return value, there isn't anything useful to do
1484 * in case this fails.
1485 */
1486 tegra_dc_wait_idle(dc, 100);
1487 }
1488
1489 /*
1490 * This should really be part of the RGB encoder driver, but clearing
1491 * these bits has the side-effect of stopping the display controller.
1492 * When that happens no VBLANK interrupts will be raised. At the same
1493 * time the encoder is disabled before the display controller, so the
1494 * above code is always going to timeout waiting for the controller
1495 * to go idle.
1496 *
1497 * Given the close coupling between the RGB encoder and the display
1498 * controller doing it here is still kind of okay. None of the other
1499 * encoder drivers require these bits to be cleared.
1500 *
1501 * XXX: Perhaps given that the display controller is switched off at
1502 * this point anyway maybe clearing these bits isn't even useful for
1503 * the RGB encoder?
1504 */
1505 if (dc->rgb) {
1506 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1507 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1508 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1509 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1510 }
1511
1512 tegra_dc_stats_reset(&dc->stats);
1513 drm_crtc_vblank_off(crtc);
Thierry Reding33a8eb82015-08-03 13:20:49 +02001514
Thierry Reding9d99ab62017-10-12 17:40:46 +02001515 spin_lock_irq(&crtc->dev->event_lock);
1516
1517 if (crtc->state->event) {
1518 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1519 crtc->state->event = NULL;
1520 }
1521
1522 spin_unlock_irq(&crtc->dev->event_lock);
1523
Thierry Reding33a8eb82015-08-03 13:20:49 +02001524 pm_runtime_put_sync(dc->dev);
Thierry Reding003fc842015-08-03 13:16:26 +02001525}
1526
Laurent Pinchart0b20a0f2017-06-30 12:36:44 +03001527static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1528 struct drm_crtc_state *old_state)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001529{
Thierry Reding4aa3df72014-11-24 16:27:13 +01001530 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
Thierry Reding76d59ed2014-12-19 15:09:16 +01001531 struct tegra_dc_state *state = to_dc_state(crtc->state);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001532 struct tegra_dc *dc = to_tegra_dc(crtc);
Thierry Redingdbb3f2f2014-03-26 12:32:14 +01001533 u32 value;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001534
Thierry Reding33a8eb82015-08-03 13:20:49 +02001535 pm_runtime_get_sync(dc->dev);
1536
1537 /* initialize display controller */
1538 if (dc->syncpt) {
Thierry Reding47307952017-08-30 17:42:54 +02001539 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
1540
1541 if (dc->soc->has_nvdisplay)
1542 enable = 1 << 31;
1543 else
1544 enable = 1 << 8;
Thierry Reding33a8eb82015-08-03 13:20:49 +02001545
1546 value = SYNCPT_CNTRL_NO_STALL;
1547 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1548
Thierry Reding47307952017-08-30 17:42:54 +02001549 value = enable | syncpt;
Thierry Reding33a8eb82015-08-03 13:20:49 +02001550 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1551 }
1552
Thierry Reding47307952017-08-30 17:42:54 +02001553 if (dc->soc->has_nvdisplay) {
1554 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1555 DSC_OBUF_UF_INT;
1556 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
Thierry Reding33a8eb82015-08-03 13:20:49 +02001557
Thierry Reding47307952017-08-30 17:42:54 +02001558 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1559 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
1560 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
1561 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
1562 VBLANK_INT | FRAME_END_INT;
1563 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
Thierry Reding33a8eb82015-08-03 13:20:49 +02001564
Thierry Reding47307952017-08-30 17:42:54 +02001565 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
1566 FRAME_END_INT;
1567 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
Thierry Reding33a8eb82015-08-03 13:20:49 +02001568
Thierry Reding47307952017-08-30 17:42:54 +02001569 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
1570 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
Thierry Reding33a8eb82015-08-03 13:20:49 +02001571
Thierry Reding47307952017-08-30 17:42:54 +02001572 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
1573 } else {
1574 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1575 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1576 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
Thierry Reding33a8eb82015-08-03 13:20:49 +02001577
Thierry Reding47307952017-08-30 17:42:54 +02001578 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1579 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1580 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1581
1582 /* initialize timer */
1583 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1584 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1585 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1586
1587 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1588 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1589 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1590
1591 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1592 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1593 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1594
1595 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1596 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1597 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1598 }
Thierry Reding33a8eb82015-08-03 13:20:49 +02001599
Thierry Reding7116e9a2017-11-13 11:20:48 +01001600 if (dc->soc->supports_background_color)
1601 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
1602 else
Thierry Reding33a8eb82015-08-03 13:20:49 +02001603 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1604
1605 /* apply PLL and pixel clock changes */
Thierry Reding76d59ed2014-12-19 15:09:16 +01001606 tegra_dc_commit_state(dc, state);
1607
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001608 /* program display mode */
1609 tegra_dc_set_timings(dc, mode);
1610
Thierry Reding8620fc62013-12-12 11:03:59 +01001611 /* interlacing isn't supported yet, so disable it */
1612 if (dc->soc->supports_interlacing) {
1613 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1614 value &= ~INTERLACE_ENABLE;
1615 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1616 }
Thierry Reding666cb872014-12-08 16:32:47 +01001617
1618 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1619 value &= ~DISP_CTRL_MODE_MASK;
1620 value |= DISP_CTRL_MODE_C_DISPLAY;
1621 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1622
Thierry Reding47307952017-08-30 17:42:54 +02001623 if (!dc->soc->has_nvdisplay) {
1624 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1625 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1626 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1627 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1628 }
1629
1630 /* enable underflow reporting and display red for missing pixels */
1631 if (dc->soc->has_nvdisplay) {
1632 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
1633 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
1634 }
Thierry Reding666cb872014-12-08 16:32:47 +01001635
1636 tegra_dc_commit(dc);
Thierry Reding23fb4742012-11-28 11:38:24 +01001637
Thierry Reding8ff64c12014-10-08 14:48:51 +02001638 drm_crtc_vblank_on(crtc);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001639}
1640
Thierry Reding4aa3df72014-11-24 16:27:13 +01001641static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1642 struct drm_crtc_state *state)
1643{
Thierry Redingc4755fb2017-11-13 11:08:13 +01001644 struct tegra_atomic_state *s = to_tegra_atomic_state(state->state);
1645 struct tegra_dc_state *tegra = to_dc_state(state);
1646
1647 /*
1648 * The display hub display clock needs to be fed by the display clock
1649 * with the highest frequency to ensure proper functioning of all the
1650 * displays.
1651 *
1652 * Note that this isn't used before Tegra186, but it doesn't hurt and
1653 * conditionalizing it would make the code less clean.
1654 */
1655 if (state->active) {
1656 if (!s->clk_disp || tegra->pclk > s->rate) {
1657 s->dc = to_tegra_dc(crtc);
1658 s->clk_disp = s->dc->clk;
1659 s->rate = tegra->pclk;
1660 }
1661 }
1662
Thierry Reding4aa3df72014-11-24 16:27:13 +01001663 return 0;
1664}
1665
Maarten Lankhorst613d2b22015-07-21 13:28:58 +02001666static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1667 struct drm_crtc_state *old_crtc_state)
Thierry Reding4aa3df72014-11-24 16:27:13 +01001668{
Thierry Reding9d99ab62017-10-12 17:40:46 +02001669 unsigned long flags;
Thierry Reding1503ca42014-11-24 17:41:23 +01001670
1671 if (crtc->state->event) {
Thierry Reding9d99ab62017-10-12 17:40:46 +02001672 spin_lock_irqsave(&crtc->dev->event_lock, flags);
Thierry Reding1503ca42014-11-24 17:41:23 +01001673
Thierry Reding9d99ab62017-10-12 17:40:46 +02001674 if (drm_crtc_vblank_get(crtc) != 0)
1675 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1676 else
1677 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
Thierry Reding1503ca42014-11-24 17:41:23 +01001678
Thierry Reding9d99ab62017-10-12 17:40:46 +02001679 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1680
Thierry Reding1503ca42014-11-24 17:41:23 +01001681 crtc->state->event = NULL;
1682 }
Thierry Reding4aa3df72014-11-24 16:27:13 +01001683}
1684
Maarten Lankhorst613d2b22015-07-21 13:28:58 +02001685static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1686 struct drm_crtc_state *old_crtc_state)
Thierry Reding4aa3df72014-11-24 16:27:13 +01001687{
Thierry Reding47802b02014-11-26 12:28:39 +01001688 struct tegra_dc_state *state = to_dc_state(crtc->state);
1689 struct tegra_dc *dc = to_tegra_dc(crtc);
Thierry Reding47307952017-08-30 17:42:54 +02001690 u32 value;
Thierry Reding47802b02014-11-26 12:28:39 +01001691
Thierry Reding47307952017-08-30 17:42:54 +02001692 value = state->planes << 8 | GENERAL_UPDATE;
1693 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1694 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1695
1696 value = state->planes | GENERAL_ACT_REQ;
1697 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1698 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
Thierry Reding4aa3df72014-11-24 16:27:13 +01001699}
1700
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001701static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
Thierry Reding4aa3df72014-11-24 16:27:13 +01001702 .atomic_check = tegra_crtc_atomic_check,
1703 .atomic_begin = tegra_crtc_atomic_begin,
1704 .atomic_flush = tegra_crtc_atomic_flush,
Laurent Pinchart0b20a0f2017-06-30 12:36:44 +03001705 .atomic_enable = tegra_crtc_atomic_enable,
Laurent Pinchart64581712017-06-30 12:36:45 +03001706 .atomic_disable = tegra_crtc_atomic_disable,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001707};
1708
Thierry Reding6e5ff992012-11-28 11:45:47 +01001709static irqreturn_t tegra_dc_irq(int irq, void *data)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001710{
1711 struct tegra_dc *dc = data;
1712 unsigned long status;
1713
1714 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1715 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1716
1717 if (status & FRAME_END_INT) {
1718 /*
1719 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1720 */
Thierry Reding791ddb12015-07-28 21:27:05 +02001721 dc->stats.frames++;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001722 }
1723
1724 if (status & VBLANK_INT) {
1725 /*
1726 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1727 */
Thierry Redinged7dae52014-12-16 16:03:13 +01001728 drm_crtc_handle_vblank(&dc->base);
Thierry Reding791ddb12015-07-28 21:27:05 +02001729 dc->stats.vblank++;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001730 }
1731
1732 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1733 /*
1734 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1735 */
Thierry Reding791ddb12015-07-28 21:27:05 +02001736 dc->stats.underflow++;
1737 }
1738
1739 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1740 /*
1741 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1742 */
1743 dc->stats.overflow++;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001744 }
1745
Thierry Reding47307952017-08-30 17:42:54 +02001746 if (status & HEAD_UF_INT) {
1747 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
1748 dc->stats.underflow++;
1749 }
1750
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001751 return IRQ_HANDLED;
1752}
1753
Thierry Reding53fa7f72013-09-24 15:35:40 +02001754static int tegra_dc_init(struct host1x_client *client)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001755{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001756 struct drm_device *drm = dev_get_drvdata(client->parent);
Thierry Redingbc8828b2017-10-12 17:43:33 +02001757 struct iommu_group *group = iommu_group_get(client->dev);
Thierry Reding2bcdcbf2015-08-24 14:47:10 +02001758 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
Thierry Reding776dc382013-10-14 14:43:22 +02001759 struct tegra_dc *dc = host1x_client_to_dc(client);
Thierry Redingd1f3e1e2014-07-11 08:29:14 +02001760 struct tegra_drm *tegra = drm->dev_private;
Thierry Redingc7679302014-10-21 13:51:53 +02001761 struct drm_plane *primary = NULL;
1762 struct drm_plane *cursor = NULL;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001763 int err;
1764
Thierry Reding617dd7c2017-08-30 12:48:31 +02001765 dc->syncpt = host1x_syncpt_request(client, flags);
Thierry Reding2bcdcbf2015-08-24 14:47:10 +02001766 if (!dc->syncpt)
1767 dev_warn(dc->dev, "failed to allocate syncpoint\n");
1768
Thierry Redingbc8828b2017-10-12 17:43:33 +02001769 if (group && tegra->domain) {
1770 if (group != tegra->group) {
1771 err = iommu_attach_group(tegra->domain, group);
1772 if (err < 0) {
1773 dev_err(dc->dev,
1774 "failed to attach to domain: %d\n",
1775 err);
1776 return err;
1777 }
1778
1779 tegra->group = group;
Thierry Redingdf06b752014-06-26 21:41:53 +02001780 }
1781
1782 dc->domain = tegra->domain;
1783 }
1784
Thierry Reding47307952017-08-30 17:42:54 +02001785 if (dc->soc->wgrps)
1786 primary = tegra_dc_add_shared_planes(drm, dc);
1787 else
1788 primary = tegra_dc_add_planes(drm, dc);
1789
Thierry Redingc7679302014-10-21 13:51:53 +02001790 if (IS_ERR(primary)) {
1791 err = PTR_ERR(primary);
1792 goto cleanup;
1793 }
1794
1795 if (dc->soc->supports_cursor) {
1796 cursor = tegra_dc_cursor_plane_create(drm, dc);
1797 if (IS_ERR(cursor)) {
1798 err = PTR_ERR(cursor);
1799 goto cleanup;
1800 }
1801 }
1802
1803 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
Ville Syrjäläf9882872015-12-09 16:19:31 +02001804 &tegra_crtc_funcs, NULL);
Thierry Redingc7679302014-10-21 13:51:53 +02001805 if (err < 0)
1806 goto cleanup;
1807
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001808 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1809
Thierry Redingd1f3e1e2014-07-11 08:29:14 +02001810 /*
1811 * Keep track of the minimum pitch alignment across all display
1812 * controllers.
1813 */
1814 if (dc->soc->pitch_align > tegra->pitch_align)
1815 tegra->pitch_align = dc->soc->pitch_align;
1816
Thierry Reding9910f5c2014-05-22 09:57:15 +02001817 err = tegra_dc_rgb_init(drm, dc);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001818 if (err < 0 && err != -ENODEV) {
1819 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
Thierry Redingc7679302014-10-21 13:51:53 +02001820 goto cleanup;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001821 }
1822
Thierry Reding6e5ff992012-11-28 11:45:47 +01001823 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001824 dev_name(dc->dev), dc);
1825 if (err < 0) {
1826 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1827 err);
Thierry Redingc7679302014-10-21 13:51:53 +02001828 goto cleanup;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001829 }
1830
1831 return 0;
Thierry Redingc7679302014-10-21 13:51:53 +02001832
1833cleanup:
Thierry Reding47307952017-08-30 17:42:54 +02001834 if (!IS_ERR_OR_NULL(cursor))
Thierry Redingc7679302014-10-21 13:51:53 +02001835 drm_plane_cleanup(cursor);
1836
Thierry Reding47307952017-08-30 17:42:54 +02001837 if (!IS_ERR(primary))
Thierry Redingc7679302014-10-21 13:51:53 +02001838 drm_plane_cleanup(primary);
1839
Thierry Redingbc8828b2017-10-12 17:43:33 +02001840 if (group && tegra->domain) {
1841 iommu_detach_group(tegra->domain, group);
Thierry Redingc7679302014-10-21 13:51:53 +02001842 dc->domain = NULL;
1843 }
1844
1845 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001846}
1847
Thierry Reding53fa7f72013-09-24 15:35:40 +02001848static int tegra_dc_exit(struct host1x_client *client)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001849{
Thierry Redingbc8828b2017-10-12 17:43:33 +02001850 struct iommu_group *group = iommu_group_get(client->dev);
Thierry Reding776dc382013-10-14 14:43:22 +02001851 struct tegra_dc *dc = host1x_client_to_dc(client);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001852 int err;
1853
1854 devm_free_irq(dc->dev, dc->irq, dc);
1855
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001856 err = tegra_dc_rgb_exit(dc);
1857 if (err) {
1858 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1859 return err;
1860 }
1861
Thierry Redingbc8828b2017-10-12 17:43:33 +02001862 if (group && dc->domain) {
1863 iommu_detach_group(dc->domain, group);
Thierry Redingdf06b752014-06-26 21:41:53 +02001864 dc->domain = NULL;
1865 }
1866
Thierry Reding2bcdcbf2015-08-24 14:47:10 +02001867 host1x_syncpt_free(dc->syncpt);
1868
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001869 return 0;
1870}
1871
1872static const struct host1x_client_ops dc_client_ops = {
Thierry Reding53fa7f72013-09-24 15:35:40 +02001873 .init = tegra_dc_init,
1874 .exit = tegra_dc_exit,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001875};
1876
Thierry Reding8620fc62013-12-12 11:03:59 +01001877static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
Thierry Reding7116e9a2017-11-13 11:20:48 +01001878 .supports_background_color = false,
Thierry Reding8620fc62013-12-12 11:03:59 +01001879 .supports_interlacing = false,
Thierry Redinge6876512013-12-20 13:58:33 +01001880 .supports_cursor = false,
Thierry Redingc134f012014-06-03 14:48:12 +02001881 .supports_block_linear = false,
Thierry Redingab7d3f52017-12-14 13:46:20 +01001882 .supports_blending = false,
Thierry Redingd1f3e1e2014-07-11 08:29:14 +02001883 .pitch_align = 8,
Thierry Reding9c012702014-07-07 15:32:53 +02001884 .has_powergate = false,
Dmitry Osipenkof68ba692017-12-20 18:46:10 +03001885 .coupled_pm = true,
Thierry Reding47307952017-08-30 17:42:54 +02001886 .has_nvdisplay = false,
Thierry Reding511c7022017-11-14 16:07:40 +01001887 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
1888 .primary_formats = tegra20_primary_formats,
1889 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
1890 .overlay_formats = tegra20_overlay_formats,
Thierry Reding8620fc62013-12-12 11:03:59 +01001891};
1892
1893static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
Thierry Reding7116e9a2017-11-13 11:20:48 +01001894 .supports_background_color = false,
Thierry Reding8620fc62013-12-12 11:03:59 +01001895 .supports_interlacing = false,
Thierry Redinge6876512013-12-20 13:58:33 +01001896 .supports_cursor = false,
Thierry Redingc134f012014-06-03 14:48:12 +02001897 .supports_block_linear = false,
Thierry Redingab7d3f52017-12-14 13:46:20 +01001898 .supports_blending = false,
Thierry Redingd1f3e1e2014-07-11 08:29:14 +02001899 .pitch_align = 8,
Thierry Reding9c012702014-07-07 15:32:53 +02001900 .has_powergate = false,
Dmitry Osipenkof68ba692017-12-20 18:46:10 +03001901 .coupled_pm = false,
Thierry Reding47307952017-08-30 17:42:54 +02001902 .has_nvdisplay = false,
Thierry Reding511c7022017-11-14 16:07:40 +01001903 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
1904 .primary_formats = tegra20_primary_formats,
1905 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
1906 .overlay_formats = tegra20_overlay_formats,
Thierry Redingd1f3e1e2014-07-11 08:29:14 +02001907};
1908
1909static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
Thierry Reding7116e9a2017-11-13 11:20:48 +01001910 .supports_background_color = false,
Thierry Redingd1f3e1e2014-07-11 08:29:14 +02001911 .supports_interlacing = false,
1912 .supports_cursor = false,
1913 .supports_block_linear = false,
Thierry Redingab7d3f52017-12-14 13:46:20 +01001914 .supports_blending = false,
Thierry Redingd1f3e1e2014-07-11 08:29:14 +02001915 .pitch_align = 64,
Thierry Reding9c012702014-07-07 15:32:53 +02001916 .has_powergate = true,
Dmitry Osipenkof68ba692017-12-20 18:46:10 +03001917 .coupled_pm = false,
Thierry Reding47307952017-08-30 17:42:54 +02001918 .has_nvdisplay = false,
Thierry Reding511c7022017-11-14 16:07:40 +01001919 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
1920 .primary_formats = tegra114_primary_formats,
1921 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
1922 .overlay_formats = tegra114_overlay_formats,
Thierry Reding8620fc62013-12-12 11:03:59 +01001923};
1924
1925static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
Thierry Reding7116e9a2017-11-13 11:20:48 +01001926 .supports_background_color = true,
Thierry Reding8620fc62013-12-12 11:03:59 +01001927 .supports_interlacing = true,
Thierry Redinge6876512013-12-20 13:58:33 +01001928 .supports_cursor = true,
Thierry Redingc134f012014-06-03 14:48:12 +02001929 .supports_block_linear = true,
Thierry Redingab7d3f52017-12-14 13:46:20 +01001930 .supports_blending = true,
Thierry Redingd1f3e1e2014-07-11 08:29:14 +02001931 .pitch_align = 64,
Thierry Reding9c012702014-07-07 15:32:53 +02001932 .has_powergate = true,
Dmitry Osipenkof68ba692017-12-20 18:46:10 +03001933 .coupled_pm = false,
Thierry Reding47307952017-08-30 17:42:54 +02001934 .has_nvdisplay = false,
Thierry Reding511c7022017-11-14 16:07:40 +01001935 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
1936 .primary_formats = tegra114_primary_formats,
1937 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
1938 .overlay_formats = tegra114_overlay_formats,
Thierry Reding8620fc62013-12-12 11:03:59 +01001939};
1940
Thierry Reding5b4f5162015-03-27 10:31:58 +01001941static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
Thierry Reding7116e9a2017-11-13 11:20:48 +01001942 .supports_background_color = true,
Thierry Reding5b4f5162015-03-27 10:31:58 +01001943 .supports_interlacing = true,
1944 .supports_cursor = true,
1945 .supports_block_linear = true,
Thierry Redingab7d3f52017-12-14 13:46:20 +01001946 .supports_blending = true,
Thierry Reding5b4f5162015-03-27 10:31:58 +01001947 .pitch_align = 64,
1948 .has_powergate = true,
Dmitry Osipenkof68ba692017-12-20 18:46:10 +03001949 .coupled_pm = false,
Thierry Reding47307952017-08-30 17:42:54 +02001950 .has_nvdisplay = false,
Thierry Reding511c7022017-11-14 16:07:40 +01001951 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
1952 .primary_formats = tegra114_primary_formats,
1953 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
1954 .overlay_formats = tegra114_overlay_formats,
Thierry Reding47307952017-08-30 17:42:54 +02001955};
1956
1957static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
1958 {
1959 .index = 0,
1960 .dc = 0,
1961 .windows = (const unsigned int[]) { 0 },
1962 .num_windows = 1,
1963 }, {
1964 .index = 1,
1965 .dc = 1,
1966 .windows = (const unsigned int[]) { 1 },
1967 .num_windows = 1,
1968 }, {
1969 .index = 2,
1970 .dc = 1,
1971 .windows = (const unsigned int[]) { 2 },
1972 .num_windows = 1,
1973 }, {
1974 .index = 3,
1975 .dc = 2,
1976 .windows = (const unsigned int[]) { 3 },
1977 .num_windows = 1,
1978 }, {
1979 .index = 4,
1980 .dc = 2,
1981 .windows = (const unsigned int[]) { 4 },
1982 .num_windows = 1,
1983 }, {
1984 .index = 5,
1985 .dc = 2,
1986 .windows = (const unsigned int[]) { 5 },
1987 .num_windows = 1,
1988 },
1989};
1990
1991static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
1992 .supports_background_color = true,
1993 .supports_interlacing = true,
1994 .supports_cursor = true,
1995 .supports_block_linear = true,
Thierry Redingab7d3f52017-12-14 13:46:20 +01001996 .supports_blending = true,
Thierry Reding47307952017-08-30 17:42:54 +02001997 .pitch_align = 64,
1998 .has_powergate = false,
Dmitry Osipenkof68ba692017-12-20 18:46:10 +03001999 .coupled_pm = false,
Thierry Reding47307952017-08-30 17:42:54 +02002000 .has_nvdisplay = true,
2001 .wgrps = tegra186_dc_wgrps,
2002 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
Thierry Reding5b4f5162015-03-27 10:31:58 +01002003};
2004
Thierry Reding8620fc62013-12-12 11:03:59 +01002005static const struct of_device_id tegra_dc_of_match[] = {
2006 {
Thierry Reding47307952017-08-30 17:42:54 +02002007 .compatible = "nvidia,tegra186-dc",
2008 .data = &tegra186_dc_soc_info,
2009 }, {
Thierry Reding5b4f5162015-03-27 10:31:58 +01002010 .compatible = "nvidia,tegra210-dc",
2011 .data = &tegra210_dc_soc_info,
2012 }, {
Thierry Reding8620fc62013-12-12 11:03:59 +01002013 .compatible = "nvidia,tegra124-dc",
2014 .data = &tegra124_dc_soc_info,
2015 }, {
Thierry Reding9c012702014-07-07 15:32:53 +02002016 .compatible = "nvidia,tegra114-dc",
2017 .data = &tegra114_dc_soc_info,
2018 }, {
Thierry Reding8620fc62013-12-12 11:03:59 +01002019 .compatible = "nvidia,tegra30-dc",
2020 .data = &tegra30_dc_soc_info,
2021 }, {
2022 .compatible = "nvidia,tegra20-dc",
2023 .data = &tegra20_dc_soc_info,
2024 }, {
2025 /* sentinel */
2026 }
2027};
Stephen Warrenef707282014-06-18 16:21:55 -06002028MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
Thierry Reding8620fc62013-12-12 11:03:59 +01002029
Thierry Reding13411dd2014-01-09 17:08:36 +01002030static int tegra_dc_parse_dt(struct tegra_dc *dc)
2031{
2032 struct device_node *np;
2033 u32 value = 0;
2034 int err;
2035
2036 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
2037 if (err < 0) {
2038 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
2039
2040 /*
2041 * If the nvidia,head property isn't present, try to find the
2042 * correct head number by looking up the position of this
2043 * display controller's node within the device tree. Assuming
2044 * that the nodes are ordered properly in the DTS file and
2045 * that the translation into a flattened device tree blob
2046 * preserves that ordering this will actually yield the right
2047 * head number.
2048 *
2049 * If those assumptions don't hold, this will still work for
2050 * cases where only a single display controller is used.
2051 */
2052 for_each_matching_node(np, tegra_dc_of_match) {
Julia Lawallcf6b1742015-10-24 16:42:31 +02002053 if (np == dc->dev->of_node) {
2054 of_node_put(np);
Thierry Reding13411dd2014-01-09 17:08:36 +01002055 break;
Julia Lawallcf6b1742015-10-24 16:42:31 +02002056 }
Thierry Reding13411dd2014-01-09 17:08:36 +01002057
2058 value++;
2059 }
2060 }
2061
2062 dc->pipe = value;
2063
2064 return 0;
2065}
2066
Dmitry Osipenkof68ba692017-12-20 18:46:10 +03002067static int tegra_dc_match_by_pipe(struct device *dev, void *data)
2068{
2069 struct tegra_dc *dc = dev_get_drvdata(dev);
2070 unsigned int pipe = (unsigned long)data;
2071
2072 return dc->pipe == pipe;
2073}
2074
2075static int tegra_dc_couple(struct tegra_dc *dc)
2076{
2077 /*
2078 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
2079 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
2080 * POWER_CONTROL registers during CRTC enabling.
2081 */
2082 if (dc->soc->coupled_pm && dc->pipe == 1) {
2083 u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE;
2084 struct device_link *link;
2085 struct device *partner;
2086
2087 partner = driver_find_device(dc->dev->driver, NULL, 0,
2088 tegra_dc_match_by_pipe);
2089 if (!partner)
2090 return -EPROBE_DEFER;
2091
2092 link = device_link_add(dc->dev, partner, flags);
2093 if (!link) {
2094 dev_err(dc->dev, "failed to link controllers\n");
2095 return -EINVAL;
2096 }
2097
2098 dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner));
2099 }
2100
2101 return 0;
2102}
2103
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00002104static int tegra_dc_probe(struct platform_device *pdev)
2105{
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00002106 struct resource *regs;
2107 struct tegra_dc *dc;
2108 int err;
2109
2110 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
2111 if (!dc)
2112 return -ENOMEM;
2113
Thierry Redingb9ff7ae2017-08-21 16:35:17 +02002114 dc->soc = of_device_get_match_data(&pdev->dev);
Thierry Reding8620fc62013-12-12 11:03:59 +01002115
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00002116 INIT_LIST_HEAD(&dc->list);
2117 dc->dev = &pdev->dev;
2118
Thierry Reding13411dd2014-01-09 17:08:36 +01002119 err = tegra_dc_parse_dt(dc);
2120 if (err < 0)
2121 return err;
2122
Dmitry Osipenkof68ba692017-12-20 18:46:10 +03002123 err = tegra_dc_couple(dc);
2124 if (err < 0)
2125 return err;
2126
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00002127 dc->clk = devm_clk_get(&pdev->dev, NULL);
2128 if (IS_ERR(dc->clk)) {
2129 dev_err(&pdev->dev, "failed to get clock\n");
2130 return PTR_ERR(dc->clk);
2131 }
2132
Stephen Warrenca480802013-11-06 16:20:54 -07002133 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
2134 if (IS_ERR(dc->rst)) {
2135 dev_err(&pdev->dev, "failed to get reset\n");
2136 return PTR_ERR(dc->rst);
2137 }
2138
Thierry Redinga2f2f742017-08-30 17:41:00 +02002139 /* assert reset and disable clock */
Dmitry Osipenkof68ba692017-12-20 18:46:10 +03002140 err = clk_prepare_enable(dc->clk);
2141 if (err < 0)
2142 return err;
Thierry Redinga2f2f742017-08-30 17:41:00 +02002143
Dmitry Osipenkof68ba692017-12-20 18:46:10 +03002144 usleep_range(2000, 4000);
Thierry Redinga2f2f742017-08-30 17:41:00 +02002145
Dmitry Osipenkof68ba692017-12-20 18:46:10 +03002146 err = reset_control_assert(dc->rst);
2147 if (err < 0)
2148 return err;
Thierry Redinga2f2f742017-08-30 17:41:00 +02002149
Dmitry Osipenkof68ba692017-12-20 18:46:10 +03002150 usleep_range(2000, 4000);
Thierry Redinga2f2f742017-08-30 17:41:00 +02002151
Dmitry Osipenkof68ba692017-12-20 18:46:10 +03002152 clk_disable_unprepare(dc->clk);
Thierry Reding33a8eb82015-08-03 13:20:49 +02002153
Thierry Reding9c012702014-07-07 15:32:53 +02002154 if (dc->soc->has_powergate) {
2155 if (dc->pipe == 0)
2156 dc->powergate = TEGRA_POWERGATE_DIS;
2157 else
2158 dc->powergate = TEGRA_POWERGATE_DISB;
2159
Thierry Reding33a8eb82015-08-03 13:20:49 +02002160 tegra_powergate_power_off(dc->powergate);
Thierry Reding9c012702014-07-07 15:32:53 +02002161 }
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00002162
2163 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Redingd4ed6022013-01-21 11:09:02 +01002164 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2165 if (IS_ERR(dc->regs))
2166 return PTR_ERR(dc->regs);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00002167
2168 dc->irq = platform_get_irq(pdev, 0);
2169 if (dc->irq < 0) {
2170 dev_err(&pdev->dev, "failed to get IRQ\n");
2171 return -ENXIO;
2172 }
2173
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00002174 err = tegra_dc_rgb_probe(dc);
2175 if (err < 0 && err != -ENODEV) {
2176 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2177 return err;
2178 }
2179
Thierry Reding33a8eb82015-08-03 13:20:49 +02002180 platform_set_drvdata(pdev, dc);
2181 pm_runtime_enable(&pdev->dev);
2182
2183 INIT_LIST_HEAD(&dc->client.list);
2184 dc->client.ops = &dc_client_ops;
2185 dc->client.dev = &pdev->dev;
2186
Thierry Reding776dc382013-10-14 14:43:22 +02002187 err = host1x_client_register(&dc->client);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00002188 if (err < 0) {
2189 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2190 err);
2191 return err;
2192 }
2193
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00002194 return 0;
2195}
2196
2197static int tegra_dc_remove(struct platform_device *pdev)
2198{
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00002199 struct tegra_dc *dc = platform_get_drvdata(pdev);
2200 int err;
2201
Thierry Reding776dc382013-10-14 14:43:22 +02002202 err = host1x_client_unregister(&dc->client);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00002203 if (err < 0) {
2204 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2205 err);
2206 return err;
2207 }
2208
Thierry Reding59d29c02013-10-14 14:26:42 +02002209 err = tegra_dc_rgb_remove(dc);
2210 if (err < 0) {
2211 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2212 return err;
2213 }
2214
Thierry Reding33a8eb82015-08-03 13:20:49 +02002215 pm_runtime_disable(&pdev->dev);
2216
2217 return 0;
2218}
2219
2220#ifdef CONFIG_PM
2221static int tegra_dc_suspend(struct device *dev)
2222{
2223 struct tegra_dc *dc = dev_get_drvdata(dev);
2224 int err;
2225
Dmitry Osipenkof68ba692017-12-20 18:46:10 +03002226 err = reset_control_assert(dc->rst);
2227 if (err < 0) {
2228 dev_err(dev, "failed to assert reset: %d\n", err);
2229 return err;
Thierry Reding33a8eb82015-08-03 13:20:49 +02002230 }
Thierry Reding9c012702014-07-07 15:32:53 +02002231
2232 if (dc->soc->has_powergate)
2233 tegra_powergate_power_off(dc->powergate);
2234
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00002235 clk_disable_unprepare(dc->clk);
2236
2237 return 0;
2238}
2239
Thierry Reding33a8eb82015-08-03 13:20:49 +02002240static int tegra_dc_resume(struct device *dev)
2241{
2242 struct tegra_dc *dc = dev_get_drvdata(dev);
2243 int err;
2244
2245 if (dc->soc->has_powergate) {
2246 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2247 dc->rst);
2248 if (err < 0) {
2249 dev_err(dev, "failed to power partition: %d\n", err);
2250 return err;
2251 }
2252 } else {
2253 err = clk_prepare_enable(dc->clk);
2254 if (err < 0) {
2255 dev_err(dev, "failed to enable clock: %d\n", err);
2256 return err;
2257 }
2258
Dmitry Osipenkof68ba692017-12-20 18:46:10 +03002259 err = reset_control_deassert(dc->rst);
2260 if (err < 0) {
2261 dev_err(dev, "failed to deassert reset: %d\n", err);
2262 return err;
Thierry Reding33a8eb82015-08-03 13:20:49 +02002263 }
2264 }
2265
2266 return 0;
2267}
2268#endif
2269
2270static const struct dev_pm_ops tegra_dc_pm_ops = {
2271 SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL)
2272};
2273
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00002274struct platform_driver tegra_dc_driver = {
2275 .driver = {
2276 .name = "tegra-dc",
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00002277 .of_match_table = tegra_dc_of_match,
Thierry Reding33a8eb82015-08-03 13:20:49 +02002278 .pm = &tegra_dc_pm_ops,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00002279 },
2280 .probe = tegra_dc_probe,
2281 .remove = tegra_dc_remove,
2282};