blob: 33bea520f50a6df158b66947b6e5caf3d14f4aab [file] [log] [blame]
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001/*
2 * Cryptographic API.
3 *
4 * Support for OMAP SHA1/MD5 HW acceleration.
5 *
6 * Copyright (c) 2010 Nokia Corporation
7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
Mark A. Greer0d373d62012-12-21 10:04:08 -07008 * Copyright (c) 2011 Texas Instruments Incorporated
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08009 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 *
14 * Some ideas are from old omap-sha1-md5.c driver.
15 */
16
17#define pr_fmt(fmt) "%s: " fmt, __func__
18
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +080019#include <linux/err.h>
20#include <linux/device.h>
21#include <linux/module.h>
22#include <linux/init.h>
23#include <linux/errno.h>
24#include <linux/interrupt.h>
25#include <linux/kernel.h>
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +080026#include <linux/irq.h>
27#include <linux/io.h>
28#include <linux/platform_device.h>
29#include <linux/scatterlist.h>
30#include <linux/dma-mapping.h>
Mark A. Greerdfd061d2012-12-21 10:04:04 -070031#include <linux/dmaengine.h>
Mark A. Greerb359f032012-12-21 10:04:02 -070032#include <linux/pm_runtime.h>
Mark A. Greer03feec92012-12-21 10:04:06 -070033#include <linux/of.h>
34#include <linux/of_device.h>
35#include <linux/of_address.h>
36#include <linux/of_irq.h>
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +080037#include <linux/delay.h>
38#include <linux/crypto.h>
39#include <linux/cryptohash.h>
40#include <crypto/scatterwalk.h>
41#include <crypto/algapi.h>
42#include <crypto/sha.h>
43#include <crypto/hash.h>
44#include <crypto/internal/hash.h>
45
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +080046#define MD5_DIGEST_SIZE 16
47
Mark A. Greer0d373d62012-12-21 10:04:08 -070048#define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04))
49#define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04))
50#define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs)
51
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +053052#define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04))
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +080053
54#define SHA_REG_CTRL 0x18
55#define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5)
56#define SHA_REG_CTRL_CLOSE_HASH (1 << 4)
57#define SHA_REG_CTRL_ALGO_CONST (1 << 3)
58#define SHA_REG_CTRL_ALGO (1 << 2)
59#define SHA_REG_CTRL_INPUT_READY (1 << 1)
60#define SHA_REG_CTRL_OUTPUT_READY (1 << 0)
61
Mark A. Greer0d373d62012-12-21 10:04:08 -070062#define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +080063
Mark A. Greer0d373d62012-12-21 10:04:08 -070064#define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +080065#define SHA_REG_MASK_DMA_EN (1 << 3)
66#define SHA_REG_MASK_IT_EN (1 << 2)
67#define SHA_REG_MASK_SOFTRESET (1 << 1)
68#define SHA_REG_AUTOIDLE (1 << 0)
69
Mark A. Greer0d373d62012-12-21 10:04:08 -070070#define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +080071#define SHA_REG_SYSSTATUS_RESETDONE (1 << 0)
72
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +053073#define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs)
Mark A. Greer0d373d62012-12-21 10:04:08 -070074#define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7)
75#define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5)
76#define SHA_REG_MODE_CLOSE_HASH (1 << 4)
77#define SHA_REG_MODE_ALGO_CONSTANT (1 << 3)
Mark A. Greer0d373d62012-12-21 10:04:08 -070078
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +053079#define SHA_REG_MODE_ALGO_MASK (7 << 0)
80#define SHA_REG_MODE_ALGO_MD5_128 (0 << 1)
81#define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1)
82#define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1)
83#define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1)
84#define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0)
85#define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0)
86
87#define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs)
Mark A. Greer0d373d62012-12-21 10:04:08 -070088
89#define SHA_REG_IRQSTATUS 0x118
90#define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3)
91#define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
92#define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1)
93#define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0)
94
95#define SHA_REG_IRQENA 0x11C
96#define SHA_REG_IRQENA_CTX_RDY (1 << 3)
97#define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2)
98#define SHA_REG_IRQENA_INPUT_RDY (1 << 1)
99#define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0)
100
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800101#define DEFAULT_TIMEOUT_INTERVAL HZ
102
Tero Kristoe93f7672016-06-22 16:23:34 +0300103#define DEFAULT_AUTOSUSPEND_DELAY 1000
104
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300105/* mostly device flags */
106#define FLAGS_BUSY 0
107#define FLAGS_FINAL 1
108#define FLAGS_DMA_ACTIVE 2
109#define FLAGS_OUTPUT_READY 3
110#define FLAGS_INIT 4
111#define FLAGS_CPU 5
Dmitry Kasatkin6c63db82011-06-02 21:10:10 +0300112#define FLAGS_DMA_READY 6
Mark A. Greer0d373d62012-12-21 10:04:08 -0700113#define FLAGS_AUTO_XOR 7
114#define FLAGS_BE32_SHA1 8
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300115/* context flags */
116#define FLAGS_FINUP 16
117#define FLAGS_SG 17
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800118
Mark A. Greer0d373d62012-12-21 10:04:08 -0700119#define FLAGS_MODE_SHIFT 18
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530120#define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
121#define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
122#define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
123#define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
124#define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
125#define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
126#define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
127
128#define FLAGS_HMAC 21
129#define FLAGS_ERROR 22
Mark A. Greer0d373d62012-12-21 10:04:08 -0700130
131#define OP_UPDATE 1
132#define OP_FINAL 2
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800133
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +0200134#define OMAP_ALIGN_MASK (sizeof(u32)-1)
135#define OMAP_ALIGNED __attribute__((aligned(sizeof(u32))))
136
Mark A. Greer0d373d62012-12-21 10:04:08 -0700137#define BUFLEN PAGE_SIZE
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +0200138
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800139struct omap_sham_dev;
140
141struct omap_sham_reqctx {
142 struct omap_sham_dev *dd;
143 unsigned long flags;
144 unsigned long op;
145
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530146 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800147 size_t digcnt;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800148 size_t bufcnt;
149 size_t buflen;
150 dma_addr_t dma_addr;
151
152 /* walk state */
153 struct scatterlist *sg;
Tero Kristo8addf572016-09-19 18:22:14 +0300154 struct scatterlist sgl_tmp;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800155 unsigned int offset; /* offset in current sg */
156 unsigned int total; /* total request */
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +0200157
158 u8 buffer[0] OMAP_ALIGNED;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800159};
160
161struct omap_sham_hmac_ctx {
162 struct crypto_shash *shash;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530163 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
164 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800165};
166
167struct omap_sham_ctx {
168 struct omap_sham_dev *dd;
169
170 unsigned long flags;
171
172 /* fallback stuff */
173 struct crypto_shash *fallback;
174
175 struct omap_sham_hmac_ctx base[0];
176};
177
Tero Kristo65e7a542016-06-22 16:23:35 +0300178#define OMAP_SHAM_QUEUE_LENGTH 10
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800179
Mark A. Greerd20fb182012-12-21 10:04:09 -0700180struct omap_sham_algs_info {
181 struct ahash_alg *algs_list;
182 unsigned int size;
183 unsigned int registered;
184};
185
Mark A. Greer0d373d62012-12-21 10:04:08 -0700186struct omap_sham_pdata {
Mark A. Greerd20fb182012-12-21 10:04:09 -0700187 struct omap_sham_algs_info *algs_info;
188 unsigned int algs_info_size;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700189 unsigned long flags;
190 int digest_size;
191
192 void (*copy_hash)(struct ahash_request *req, int out);
193 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
194 int final, int dma);
195 void (*trigger)(struct omap_sham_dev *dd, size_t length);
196 int (*poll_irq)(struct omap_sham_dev *dd);
197 irqreturn_t (*intr_hdlr)(int irq, void *dev_id);
198
199 u32 odigest_ofs;
200 u32 idigest_ofs;
201 u32 din_ofs;
202 u32 digcnt_ofs;
203 u32 rev_ofs;
204 u32 mask_ofs;
205 u32 sysstatus_ofs;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530206 u32 mode_ofs;
207 u32 length_ofs;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700208
209 u32 major_mask;
210 u32 major_shift;
211 u32 minor_mask;
212 u32 minor_shift;
213};
214
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800215struct omap_sham_dev {
216 struct list_head list;
217 unsigned long phys_base;
218 struct device *dev;
219 void __iomem *io_base;
220 int irq;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800221 spinlock_t lock;
Dmitry Kasatkin3e133c82010-11-19 16:04:24 +0200222 int err;
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700223 struct dma_chan *dma_lch;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800224 struct tasklet_struct done_task;
Lokesh Vutlab8411cc2013-08-20 20:32:34 +0530225 u8 polling_mode;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800226
227 unsigned long flags;
228 struct crypto_queue queue;
229 struct ahash_request *req;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700230
231 const struct omap_sham_pdata *pdata;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800232};
233
234struct omap_sham_drv {
235 struct list_head dev_list;
236 spinlock_t lock;
237 unsigned long flags;
238};
239
240static struct omap_sham_drv sham = {
241 .dev_list = LIST_HEAD_INIT(sham.dev_list),
242 .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
243};
244
245static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
246{
247 return __raw_readl(dd->io_base + offset);
248}
249
250static inline void omap_sham_write(struct omap_sham_dev *dd,
251 u32 offset, u32 value)
252{
253 __raw_writel(value, dd->io_base + offset);
254}
255
256static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
257 u32 value, u32 mask)
258{
259 u32 val;
260
261 val = omap_sham_read(dd, address);
262 val &= ~mask;
263 val |= value;
264 omap_sham_write(dd, address, val);
265}
266
267static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
268{
269 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
270
271 while (!(omap_sham_read(dd, offset) & bit)) {
272 if (time_is_before_jiffies(timeout))
273 return -ETIMEDOUT;
274 }
275
276 return 0;
277}
278
Mark A. Greer0d373d62012-12-21 10:04:08 -0700279static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800280{
281 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
Mark A. Greer0d373d62012-12-21 10:04:08 -0700282 struct omap_sham_dev *dd = ctx->dd;
Dmitry Kasatkin0c3cf4c2010-11-19 16:04:22 +0200283 u32 *hash = (u32 *)ctx->digest;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800284 int i;
285
Mark A. Greer0d373d62012-12-21 10:04:08 -0700286 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
Dmitry Kasatkin3c8d7582010-11-19 16:04:27 +0200287 if (out)
Mark A. Greer0d373d62012-12-21 10:04:08 -0700288 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
Dmitry Kasatkin3c8d7582010-11-19 16:04:27 +0200289 else
Mark A. Greer0d373d62012-12-21 10:04:08 -0700290 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
Dmitry Kasatkin3c8d7582010-11-19 16:04:27 +0200291 }
292}
293
Mark A. Greer0d373d62012-12-21 10:04:08 -0700294static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
295{
296 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
297 struct omap_sham_dev *dd = ctx->dd;
298 int i;
299
300 if (ctx->flags & BIT(FLAGS_HMAC)) {
301 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
302 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
303 struct omap_sham_hmac_ctx *bctx = tctx->base;
304 u32 *opad = (u32 *)bctx->opad;
305
306 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
307 if (out)
308 opad[i] = omap_sham_read(dd,
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530309 SHA_REG_ODIGEST(dd, i));
Mark A. Greer0d373d62012-12-21 10:04:08 -0700310 else
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530311 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
Mark A. Greer0d373d62012-12-21 10:04:08 -0700312 opad[i]);
313 }
314 }
315
316 omap_sham_copy_hash_omap2(req, out);
317}
318
Dmitry Kasatkin3c8d7582010-11-19 16:04:27 +0200319static void omap_sham_copy_ready_hash(struct ahash_request *req)
320{
321 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
322 u32 *in = (u32 *)ctx->digest;
323 u32 *hash = (u32 *)req->result;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700324 int i, d, big_endian = 0;
Dmitry Kasatkin3c8d7582010-11-19 16:04:27 +0200325
326 if (!hash)
327 return;
328
Mark A. Greer0d373d62012-12-21 10:04:08 -0700329 switch (ctx->flags & FLAGS_MODE_MASK) {
330 case FLAGS_MODE_MD5:
331 d = MD5_DIGEST_SIZE / sizeof(u32);
332 break;
333 case FLAGS_MODE_SHA1:
334 /* OMAP2 SHA1 is big endian */
335 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
336 big_endian = 1;
337 d = SHA1_DIGEST_SIZE / sizeof(u32);
338 break;
Mark A. Greerd20fb182012-12-21 10:04:09 -0700339 case FLAGS_MODE_SHA224:
340 d = SHA224_DIGEST_SIZE / sizeof(u32);
341 break;
342 case FLAGS_MODE_SHA256:
343 d = SHA256_DIGEST_SIZE / sizeof(u32);
344 break;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530345 case FLAGS_MODE_SHA384:
346 d = SHA384_DIGEST_SIZE / sizeof(u32);
347 break;
348 case FLAGS_MODE_SHA512:
349 d = SHA512_DIGEST_SIZE / sizeof(u32);
350 break;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700351 default:
352 d = 0;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800353 }
Mark A. Greer0d373d62012-12-21 10:04:08 -0700354
355 if (big_endian)
356 for (i = 0; i < d; i++)
357 hash[i] = be32_to_cpu(in[i]);
358 else
359 for (i = 0; i < d; i++)
360 hash[i] = le32_to_cpu(in[i]);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800361}
362
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +0200363static int omap_sham_hw_init(struct omap_sham_dev *dd)
364{
Pali Rohár604c3102015-03-08 11:01:01 +0100365 int err;
366
367 err = pm_runtime_get_sync(dd->dev);
368 if (err < 0) {
369 dev_err(dd->dev, "failed to get sync: %d\n", err);
370 return err;
371 }
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +0200372
Dmitry Kasatkina929cbe2011-06-02 21:10:06 +0300373 if (!test_bit(FLAGS_INIT, &dd->flags)) {
Dmitry Kasatkina929cbe2011-06-02 21:10:06 +0300374 set_bit(FLAGS_INIT, &dd->flags);
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +0200375 dd->err = 0;
376 }
377
378 return 0;
379}
380
Mark A. Greer0d373d62012-12-21 10:04:08 -0700381static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800382 int final, int dma)
383{
384 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
385 u32 val = length << 5, mask;
386
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +0200387 if (likely(ctx->digcnt))
Mark A. Greer0d373d62012-12-21 10:04:08 -0700388 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800389
Mark A. Greer0d373d62012-12-21 10:04:08 -0700390 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800391 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
392 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
393 /*
394 * Setting ALGO_CONST only for the first iteration
395 * and CLOSE_HASH only for the last one.
396 */
Mark A. Greer0d373d62012-12-21 10:04:08 -0700397 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800398 val |= SHA_REG_CTRL_ALGO;
399 if (!ctx->digcnt)
400 val |= SHA_REG_CTRL_ALGO_CONST;
401 if (final)
402 val |= SHA_REG_CTRL_CLOSE_HASH;
403
404 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
405 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
406
407 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800408}
409
Mark A. Greer0d373d62012-12-21 10:04:08 -0700410static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
411{
412}
413
414static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
415{
416 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
417}
418
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530419static int get_block_size(struct omap_sham_reqctx *ctx)
420{
421 int d;
422
423 switch (ctx->flags & FLAGS_MODE_MASK) {
424 case FLAGS_MODE_MD5:
425 case FLAGS_MODE_SHA1:
426 d = SHA1_BLOCK_SIZE;
427 break;
428 case FLAGS_MODE_SHA224:
429 case FLAGS_MODE_SHA256:
430 d = SHA256_BLOCK_SIZE;
431 break;
432 case FLAGS_MODE_SHA384:
433 case FLAGS_MODE_SHA512:
434 d = SHA512_BLOCK_SIZE;
435 break;
436 default:
437 d = 0;
438 }
439
440 return d;
441}
442
Mark A. Greer0d373d62012-12-21 10:04:08 -0700443static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
444 u32 *value, int count)
445{
446 for (; count--; value++, offset += 4)
447 omap_sham_write(dd, offset, *value);
448}
449
450static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
451 int final, int dma)
452{
453 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
454 u32 val, mask;
455
456 /*
457 * Setting ALGO_CONST only for the first iteration and
458 * CLOSE_HASH only for the last one. Note that flags mode bits
459 * correspond to algorithm encoding in mode register.
460 */
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530461 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
Mark A. Greer0d373d62012-12-21 10:04:08 -0700462 if (!ctx->digcnt) {
463 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
464 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
465 struct omap_sham_hmac_ctx *bctx = tctx->base;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530466 int bs, nr_dr;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700467
468 val |= SHA_REG_MODE_ALGO_CONSTANT;
469
470 if (ctx->flags & BIT(FLAGS_HMAC)) {
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530471 bs = get_block_size(ctx);
472 nr_dr = bs / (2 * sizeof(u32));
Mark A. Greer0d373d62012-12-21 10:04:08 -0700473 val |= SHA_REG_MODE_HMAC_KEY_PROC;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530474 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
475 (u32 *)bctx->ipad, nr_dr);
476 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
477 (u32 *)bctx->ipad + nr_dr, nr_dr);
478 ctx->digcnt += bs;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700479 }
480 }
481
482 if (final) {
483 val |= SHA_REG_MODE_CLOSE_HASH;
484
485 if (ctx->flags & BIT(FLAGS_HMAC))
486 val |= SHA_REG_MODE_HMAC_OUTER_HASH;
487 }
488
489 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
490 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
491 SHA_REG_MODE_HMAC_KEY_PROC;
492
493 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530494 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
Mark A. Greer0d373d62012-12-21 10:04:08 -0700495 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
496 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
497 SHA_REG_MASK_IT_EN |
498 (dma ? SHA_REG_MASK_DMA_EN : 0),
499 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
500}
501
502static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
503{
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530504 omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
Mark A. Greer0d373d62012-12-21 10:04:08 -0700505}
506
507static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
508{
509 return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
510 SHA_REG_IRQSTATUS_INPUT_RDY);
511}
512
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800513static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
514 size_t length, int final)
515{
516 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
Lokesh Vutlab8411cc2013-08-20 20:32:34 +0530517 int count, len32, bs32, offset = 0;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800518 const u32 *buffer = (const u32 *)buf;
519
520 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
521 ctx->digcnt, length, final);
522
Mark A. Greer0d373d62012-12-21 10:04:08 -0700523 dd->pdata->write_ctrl(dd, length, final, 0);
524 dd->pdata->trigger(dd, length);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800525
Dmitry Kasatkin3e133c82010-11-19 16:04:24 +0200526 /* should be non-zero before next lines to disable clocks later */
527 ctx->digcnt += length;
528
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800529 if (final)
Dmitry Kasatkined3ea9a82011-06-02 21:10:07 +0300530 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800531
Dmitry Kasatkin6c63db82011-06-02 21:10:10 +0300532 set_bit(FLAGS_CPU, &dd->flags);
533
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800534 len32 = DIV_ROUND_UP(length, sizeof(u32));
Lokesh Vutlab8411cc2013-08-20 20:32:34 +0530535 bs32 = get_block_size(ctx) / sizeof(u32);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800536
Lokesh Vutlab8411cc2013-08-20 20:32:34 +0530537 while (len32) {
538 if (dd->pdata->poll_irq(dd))
539 return -ETIMEDOUT;
540
541 for (count = 0; count < min(len32, bs32); count++, offset++)
542 omap_sham_write(dd, SHA_REG_DIN(dd, count),
543 buffer[offset]);
544 len32 -= min(len32, bs32);
545 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800546
547 return -EINPROGRESS;
548}
549
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700550static void omap_sham_dma_callback(void *param)
551{
552 struct omap_sham_dev *dd = param;
553
554 set_bit(FLAGS_DMA_READY, &dd->flags);
555 tasklet_schedule(&dd->done_task);
556}
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700557
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800558static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700559 size_t length, int final, int is_sg)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800560{
561 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700562 struct dma_async_tx_descriptor *tx;
563 struct dma_slave_config cfg;
Lokesh Vutlaf5e46262013-08-20 20:32:35 +0530564 int len32, ret, dma_min = get_block_size(ctx);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800565
566 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
567 ctx->digcnt, length, final);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800568
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700569 memset(&cfg, 0, sizeof(cfg));
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800570
Mark A. Greer0d373d62012-12-21 10:04:08 -0700571 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700572 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
Lokesh Vutlaf5e46262013-08-20 20:32:35 +0530573 cfg.dst_maxburst = dma_min / DMA_SLAVE_BUSWIDTH_4_BYTES;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800574
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700575 ret = dmaengine_slave_config(dd->dma_lch, &cfg);
576 if (ret) {
577 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
578 return ret;
579 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800580
Lokesh Vutlaf5e46262013-08-20 20:32:35 +0530581 len32 = DIV_ROUND_UP(length, dma_min) * dma_min;
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700582
583 if (is_sg) {
584 /*
585 * The SG entry passed in may not have the 'length' member
Tero Kristo8addf572016-09-19 18:22:14 +0300586 * set correctly so use a local SG entry (sgl_tmp) with the
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700587 * proper value for 'length' instead. If this is not done,
588 * the dmaengine may try to DMA the incorrect amount of data.
589 */
Tero Kristo8addf572016-09-19 18:22:14 +0300590 sg_init_table(&ctx->sgl_tmp, 1);
591 sg_assign_page(&ctx->sgl_tmp, sg_page(ctx->sg));
592 ctx->sgl_tmp.offset = ctx->sg->offset;
593 sg_dma_len(&ctx->sgl_tmp) = len32;
594 sg_dma_address(&ctx->sgl_tmp) = sg_dma_address(ctx->sg);
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700595
Tero Kristo8addf572016-09-19 18:22:14 +0300596 tx = dmaengine_prep_slave_sg(dd->dma_lch, &ctx->sgl_tmp, 1,
597 DMA_MEM_TO_DEV,
598 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700599 } else {
600 tx = dmaengine_prep_slave_single(dd->dma_lch, dma_addr, len32,
601 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
602 }
603
604 if (!tx) {
605 dev_err(dd->dev, "prep_slave_sg/single() failed\n");
606 return -EINVAL;
607 }
608
609 tx->callback = omap_sham_dma_callback;
610 tx->callback_param = dd;
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700611
Mark A. Greer0d373d62012-12-21 10:04:08 -0700612 dd->pdata->write_ctrl(dd, length, final, 1);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800613
614 ctx->digcnt += length;
615
616 if (final)
Dmitry Kasatkined3ea9a82011-06-02 21:10:07 +0300617 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800618
Dmitry Kasatkina929cbe2011-06-02 21:10:06 +0300619 set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800620
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700621 dmaengine_submit(tx);
622 dma_async_issue_pending(dd->dma_lch);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800623
Mark A. Greer0d373d62012-12-21 10:04:08 -0700624 dd->pdata->trigger(dd, length);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800625
626 return -EINPROGRESS;
627}
628
629static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx,
630 const u8 *data, size_t length)
631{
632 size_t count = min(length, ctx->buflen - ctx->bufcnt);
633
634 count = min(count, ctx->total);
635 if (count <= 0)
636 return 0;
637 memcpy(ctx->buffer + ctx->bufcnt, data, count);
638 ctx->bufcnt += count;
639
640 return count;
641}
642
643static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx)
644{
645 size_t count;
Joel Fernandes26a05482014-03-07 10:28:46 -0600646 const u8 *vaddr;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800647
648 while (ctx->sg) {
Joel Fernandes26a05482014-03-07 10:28:46 -0600649 vaddr = kmap_atomic(sg_page(ctx->sg));
Vutla, Lokesh13cf3942015-04-02 15:32:45 +0530650 vaddr += ctx->sg->offset;
Joel Fernandes26a05482014-03-07 10:28:46 -0600651
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800652 count = omap_sham_append_buffer(ctx,
Joel Fernandes26a05482014-03-07 10:28:46 -0600653 vaddr + ctx->offset,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800654 ctx->sg->length - ctx->offset);
Joel Fernandes26a05482014-03-07 10:28:46 -0600655
656 kunmap_atomic((void *)vaddr);
657
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800658 if (!count)
659 break;
660 ctx->offset += count;
661 ctx->total -= count;
662 if (ctx->offset == ctx->sg->length) {
663 ctx->sg = sg_next(ctx->sg);
664 if (ctx->sg)
665 ctx->offset = 0;
666 else
667 ctx->total = 0;
668 }
669 }
670
671 return 0;
672}
673
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +0200674static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
675 struct omap_sham_reqctx *ctx,
676 size_t length, int final)
677{
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700678 int ret;
679
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +0200680 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
681 DMA_TO_DEVICE);
682 if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
683 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
684 return -EINVAL;
685 }
686
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300687 ctx->flags &= ~BIT(FLAGS_SG);
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200688
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700689 ret = omap_sham_xmit_dma(dd, ctx->dma_addr, length, final, 0);
Mark A. Greer0d373d62012-12-21 10:04:08 -0700690 if (ret != -EINPROGRESS)
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700691 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
692 DMA_TO_DEVICE);
693
694 return ret;
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +0200695}
696
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800697static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
698{
699 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
700 unsigned int final;
701 size_t count;
702
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800703 omap_sham_append_sg(ctx);
704
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300705 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800706
707 dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
708 ctx->bufcnt, ctx->digcnt, final);
709
710 if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
711 count = ctx->bufcnt;
712 ctx->bufcnt = 0;
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +0200713 return omap_sham_xmit_dma_map(dd, ctx, count, final);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800714 }
715
716 return 0;
717}
718
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200719/* Start address alignment */
720#define SG_AA(sg) (IS_ALIGNED(sg->offset, sizeof(u32)))
721/* SHA1 block size alignment */
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530722#define SG_SA(sg, bs) (IS_ALIGNED(sg->length, bs))
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200723
724static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800725{
726 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200727 unsigned int length, final, tail;
728 struct scatterlist *sg;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530729 int ret, bs;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800730
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200731 if (!ctx->total)
732 return 0;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800733
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200734 if (ctx->bufcnt || ctx->offset)
735 return omap_sham_update_dma_slow(dd);
736
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700737 /*
738 * Don't use the sg interface when the transfer size is less
739 * than the number of elements in a DMA frame. Otherwise,
740 * the dmaengine infrastructure will calculate that it needs
741 * to transfer 0 frames which ultimately fails.
742 */
Lokesh Vutlaf5e46262013-08-20 20:32:35 +0530743 if (ctx->total < get_block_size(ctx))
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700744 return omap_sham_update_dma_slow(dd);
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700745
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200746 dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
747 ctx->digcnt, ctx->bufcnt, ctx->total);
748
749 sg = ctx->sg;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530750 bs = get_block_size(ctx);
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200751
752 if (!SG_AA(sg))
753 return omap_sham_update_dma_slow(dd);
754
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530755 if (!sg_is_last(sg) && !SG_SA(sg, bs))
756 /* size is not BLOCK_SIZE aligned */
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200757 return omap_sham_update_dma_slow(dd);
758
759 length = min(ctx->total, sg->length);
760
761 if (sg_is_last(sg)) {
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300762 if (!(ctx->flags & BIT(FLAGS_FINUP))) {
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530763 /* not last sg must be BLOCK_SIZE aligned */
764 tail = length & (bs - 1);
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200765 /* without finup() we need one block to close hash */
766 if (!tail)
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530767 tail = bs;
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200768 length -= tail;
769 }
770 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800771
772 if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
773 dev_err(dd->dev, "dma_map_sg error\n");
774 return -EINVAL;
775 }
776
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300777 ctx->flags |= BIT(FLAGS_SG);
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200778
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800779 ctx->total -= length;
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200780 ctx->offset = length; /* offset where to start slow */
781
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300782 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800783
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700784 ret = omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final, 1);
Mark A. Greer0d373d62012-12-21 10:04:08 -0700785 if (ret != -EINPROGRESS)
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700786 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
787
788 return ret;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800789}
790
791static int omap_sham_update_cpu(struct omap_sham_dev *dd)
792{
793 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
Lokesh Vutlab8411cc2013-08-20 20:32:34 +0530794 int bufcnt, final;
795
796 if (!ctx->total)
797 return 0;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800798
799 omap_sham_append_sg(ctx);
Lokesh Vutlab8411cc2013-08-20 20:32:34 +0530800
801 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
802
803 dev_dbg(dd->dev, "cpu: bufcnt: %u, digcnt: %d, final: %d\n",
804 ctx->bufcnt, ctx->digcnt, final);
805
Lokesh Vutlaacef7b02013-12-18 19:03:33 +0530806 if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
807 bufcnt = ctx->bufcnt;
808 ctx->bufcnt = 0;
809 return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, final);
810 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800811
Lokesh Vutlaacef7b02013-12-18 19:03:33 +0530812 return 0;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800813}
814
815static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
816{
817 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
818
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700819
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300820 if (ctx->flags & BIT(FLAGS_SG)) {
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800821 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200822 if (ctx->sg->length == ctx->offset) {
823 ctx->sg = sg_next(ctx->sg);
824 if (ctx->sg)
825 ctx->offset = 0;
826 }
827 } else {
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +0200828 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
829 DMA_TO_DEVICE);
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200830 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800831
832 return 0;
833}
834
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800835static int omap_sham_init(struct ahash_request *req)
836{
837 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
838 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
839 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
840 struct omap_sham_dev *dd = NULL, *tmp;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530841 int bs = 0;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800842
843 spin_lock_bh(&sham.lock);
844 if (!tctx->dd) {
845 list_for_each_entry(tmp, &sham.dev_list, list) {
846 dd = tmp;
847 break;
848 }
849 tctx->dd = dd;
850 } else {
851 dd = tctx->dd;
852 }
853 spin_unlock_bh(&sham.lock);
854
855 ctx->dd = dd;
856
857 ctx->flags = 0;
858
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800859 dev_dbg(dd->dev, "init: digest size: %d\n",
860 crypto_ahash_digestsize(tfm));
861
Mark A. Greer0d373d62012-12-21 10:04:08 -0700862 switch (crypto_ahash_digestsize(tfm)) {
863 case MD5_DIGEST_SIZE:
864 ctx->flags |= FLAGS_MODE_MD5;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530865 bs = SHA1_BLOCK_SIZE;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700866 break;
867 case SHA1_DIGEST_SIZE:
868 ctx->flags |= FLAGS_MODE_SHA1;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530869 bs = SHA1_BLOCK_SIZE;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700870 break;
Mark A. Greerd20fb182012-12-21 10:04:09 -0700871 case SHA224_DIGEST_SIZE:
872 ctx->flags |= FLAGS_MODE_SHA224;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530873 bs = SHA224_BLOCK_SIZE;
Mark A. Greerd20fb182012-12-21 10:04:09 -0700874 break;
875 case SHA256_DIGEST_SIZE:
876 ctx->flags |= FLAGS_MODE_SHA256;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530877 bs = SHA256_BLOCK_SIZE;
878 break;
879 case SHA384_DIGEST_SIZE:
880 ctx->flags |= FLAGS_MODE_SHA384;
881 bs = SHA384_BLOCK_SIZE;
882 break;
883 case SHA512_DIGEST_SIZE:
884 ctx->flags |= FLAGS_MODE_SHA512;
885 bs = SHA512_BLOCK_SIZE;
Mark A. Greerd20fb182012-12-21 10:04:09 -0700886 break;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700887 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800888
889 ctx->bufcnt = 0;
890 ctx->digcnt = 0;
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +0200891 ctx->buflen = BUFLEN;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800892
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300893 if (tctx->flags & BIT(FLAGS_HMAC)) {
Mark A. Greer0d373d62012-12-21 10:04:08 -0700894 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
895 struct omap_sham_hmac_ctx *bctx = tctx->base;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800896
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530897 memcpy(ctx->buffer, bctx->ipad, bs);
898 ctx->bufcnt = bs;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700899 }
900
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300901 ctx->flags |= BIT(FLAGS_HMAC);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800902 }
903
904 return 0;
905
906}
907
908static int omap_sham_update_req(struct omap_sham_dev *dd)
909{
910 struct ahash_request *req = dd->req;
911 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
912 int err;
913
914 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300915 ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800916
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300917 if (ctx->flags & BIT(FLAGS_CPU))
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800918 err = omap_sham_update_cpu(dd);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800919 else
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200920 err = omap_sham_update_dma_start(dd);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800921
922 /* wait for dma completion before can take more data */
923 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
924
925 return err;
926}
927
928static int omap_sham_final_req(struct omap_sham_dev *dd)
929{
930 struct ahash_request *req = dd->req;
931 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
932 int err = 0, use_dma = 1;
933
Lokesh Vutlab8411cc2013-08-20 20:32:34 +0530934 if ((ctx->bufcnt <= get_block_size(ctx)) || dd->polling_mode)
935 /*
936 * faster to handle last block with cpu or
937 * use cpu when dma is not present.
938 */
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800939 use_dma = 0;
940
941 if (use_dma)
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +0200942 err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800943 else
944 err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
945
946 ctx->bufcnt = 0;
947
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800948 dev_dbg(dd->dev, "final_req: err: %d\n", err);
949
950 return err;
951}
952
Dmitry Kasatkinbf362752011-04-20 13:34:58 +0300953static int omap_sham_finish_hmac(struct ahash_request *req)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800954{
955 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
956 struct omap_sham_hmac_ctx *bctx = tctx->base;
957 int bs = crypto_shash_blocksize(bctx->shash);
958 int ds = crypto_shash_digestsize(bctx->shash);
Behan Webster7bc53c32014-04-04 18:18:00 -0300959 SHASH_DESC_ON_STACK(shash, bctx->shash);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800960
Behan Webster7bc53c32014-04-04 18:18:00 -0300961 shash->tfm = bctx->shash;
962 shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800963
Behan Webster7bc53c32014-04-04 18:18:00 -0300964 return crypto_shash_init(shash) ?:
965 crypto_shash_update(shash, bctx->opad, bs) ?:
966 crypto_shash_finup(shash, req->result, ds, req->result);
Dmitry Kasatkinbf362752011-04-20 13:34:58 +0300967}
968
969static int omap_sham_finish(struct ahash_request *req)
970{
971 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
972 struct omap_sham_dev *dd = ctx->dd;
973 int err = 0;
974
975 if (ctx->digcnt) {
976 omap_sham_copy_ready_hash(req);
Mark A. Greer0d373d62012-12-21 10:04:08 -0700977 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
978 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
Dmitry Kasatkinbf362752011-04-20 13:34:58 +0300979 err = omap_sham_finish_hmac(req);
980 }
981
982 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
983
984 return err;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800985}
986
987static void omap_sham_finish_req(struct ahash_request *req, int err)
988{
989 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +0200990 struct omap_sham_dev *dd = ctx->dd;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800991
992 if (!err) {
Mark A. Greer0d373d62012-12-21 10:04:08 -0700993 dd->pdata->copy_hash(req, 1);
Dmitry Kasatkined3ea9a82011-06-02 21:10:07 +0300994 if (test_bit(FLAGS_FINAL, &dd->flags))
Dmitry Kasatkinbf362752011-04-20 13:34:58 +0300995 err = omap_sham_finish(req);
Dmitry Kasatkin3e133c82010-11-19 16:04:24 +0200996 } else {
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300997 ctx->flags |= BIT(FLAGS_ERROR);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800998 }
999
Dmitry Kasatkin0efd4d82011-06-02 21:10:12 +03001000 /* atomic operation is not needed here */
1001 dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1002 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
Mark A. Greerb359f032012-12-21 10:04:02 -07001003
Tero Kristoe93f7672016-06-22 16:23:34 +03001004 pm_runtime_mark_last_busy(dd->dev);
1005 pm_runtime_put_autosuspend(dd->dev);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001006
1007 if (req->base.complete)
1008 req->base.complete(&req->base, err);
1009}
1010
Dmitry Kasatkina5d87232010-11-19 16:04:25 +02001011static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1012 struct ahash_request *req)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001013{
Dmitry Kasatkin6c39d112010-12-29 21:52:04 +11001014 struct crypto_async_request *async_req, *backlog;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001015 struct omap_sham_reqctx *ctx;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001016 unsigned long flags;
Dmitry Kasatkina5d87232010-11-19 16:04:25 +02001017 int err = 0, ret = 0;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001018
Tero Kristo4e7813a2016-08-04 13:28:36 +03001019retry:
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001020 spin_lock_irqsave(&dd->lock, flags);
Dmitry Kasatkina5d87232010-11-19 16:04:25 +02001021 if (req)
1022 ret = ahash_enqueue_request(&dd->queue, req);
Dmitry Kasatkina929cbe2011-06-02 21:10:06 +03001023 if (test_bit(FLAGS_BUSY, &dd->flags)) {
Dmitry Kasatkina5d87232010-11-19 16:04:25 +02001024 spin_unlock_irqrestore(&dd->lock, flags);
1025 return ret;
1026 }
Dmitry Kasatkin6c39d112010-12-29 21:52:04 +11001027 backlog = crypto_get_backlog(&dd->queue);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001028 async_req = crypto_dequeue_request(&dd->queue);
Dmitry Kasatkin6c39d112010-12-29 21:52:04 +11001029 if (async_req)
Dmitry Kasatkina929cbe2011-06-02 21:10:06 +03001030 set_bit(FLAGS_BUSY, &dd->flags);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001031 spin_unlock_irqrestore(&dd->lock, flags);
1032
1033 if (!async_req)
Dmitry Kasatkina5d87232010-11-19 16:04:25 +02001034 return ret;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001035
1036 if (backlog)
1037 backlog->complete(backlog, -EINPROGRESS);
1038
1039 req = ahash_request_cast(async_req);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001040 dd->req = req;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001041 ctx = ahash_request_ctx(req);
1042
1043 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1044 ctx->op, req->nbytes);
1045
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +02001046 err = omap_sham_hw_init(dd);
1047 if (err)
1048 goto err1;
1049
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +02001050 if (ctx->digcnt)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001051 /* request has changed - restore hash */
Mark A. Greer0d373d62012-12-21 10:04:08 -07001052 dd->pdata->copy_hash(req, 0);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001053
1054 if (ctx->op == OP_UPDATE) {
1055 err = omap_sham_update_req(dd);
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +03001056 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001057 /* no final() after finup() */
1058 err = omap_sham_final_req(dd);
1059 } else if (ctx->op == OP_FINAL) {
1060 err = omap_sham_final_req(dd);
1061 }
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +02001062err1:
Tero Kristo4e7813a2016-08-04 13:28:36 +03001063 dev_dbg(dd->dev, "exit, err: %d\n", err);
1064
1065 if (err != -EINPROGRESS) {
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001066 /* done_task will not finish it, so do it here */
1067 omap_sham_finish_req(req, err);
Tero Kristo4e7813a2016-08-04 13:28:36 +03001068 req = NULL;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001069
Tero Kristo4e7813a2016-08-04 13:28:36 +03001070 /*
1071 * Execute next request immediately if there is anything
1072 * in queue.
1073 */
1074 goto retry;
1075 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001076
Dmitry Kasatkina5d87232010-11-19 16:04:25 +02001077 return ret;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001078}
1079
1080static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1081{
1082 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1083 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1084 struct omap_sham_dev *dd = tctx->dd;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001085
1086 ctx->op = op;
1087
Dmitry Kasatkina5d87232010-11-19 16:04:25 +02001088 return omap_sham_handle_queue(dd, req);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001089}
1090
1091static int omap_sham_update(struct ahash_request *req)
1092{
1093 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
Lokesh Vutlab8411cc2013-08-20 20:32:34 +05301094 struct omap_sham_dev *dd = ctx->dd;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +05301095 int bs = get_block_size(ctx);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001096
1097 if (!req->nbytes)
1098 return 0;
1099
1100 ctx->total = req->nbytes;
1101 ctx->sg = req->src;
1102 ctx->offset = 0;
1103
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +03001104 if (ctx->flags & BIT(FLAGS_FINUP)) {
Bin Liu85e06872016-06-22 16:23:37 +03001105 if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 240) {
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001106 /*
1107 * OMAP HW accel works only with buffers >= 9
1108 * will switch to bypass in final()
1109 * final has the same request and data
1110 */
1111 omap_sham_append_sg(ctx);
1112 return 0;
Lokesh Vutlab8411cc2013-08-20 20:32:34 +05301113 } else if ((ctx->bufcnt + ctx->total <= bs) ||
1114 dd->polling_mode) {
Dmitry Kasatkin887c8832010-11-19 16:04:29 +02001115 /*
Lokesh Vutlab8411cc2013-08-20 20:32:34 +05301116 * faster to use CPU for short transfers or
1117 * use cpu when dma is not present.
1118 */
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +03001119 ctx->flags |= BIT(FLAGS_CPU);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001120 }
Dmitry Kasatkin887c8832010-11-19 16:04:29 +02001121 } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001122 omap_sham_append_sg(ctx);
1123 return 0;
1124 }
1125
Lokesh Vutlaacef7b02013-12-18 19:03:33 +05301126 if (dd->polling_mode)
1127 ctx->flags |= BIT(FLAGS_CPU);
1128
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001129 return omap_sham_enqueue(req, OP_UPDATE);
1130}
1131
Behan Webster7bc53c32014-04-04 18:18:00 -03001132static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001133 const u8 *data, unsigned int len, u8 *out)
1134{
Behan Webster7bc53c32014-04-04 18:18:00 -03001135 SHASH_DESC_ON_STACK(shash, tfm);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001136
Behan Webster7bc53c32014-04-04 18:18:00 -03001137 shash->tfm = tfm;
1138 shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001139
Behan Webster7bc53c32014-04-04 18:18:00 -03001140 return crypto_shash_digest(shash, data, len, out);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001141}
1142
1143static int omap_sham_final_shash(struct ahash_request *req)
1144{
1145 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1146 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
Tero Kristocb8d5c82016-08-04 13:28:40 +03001147 int offset = 0;
1148
1149 /*
1150 * If we are running HMAC on limited hardware support, skip
1151 * the ipad in the beginning of the buffer if we are going for
1152 * software fallback algorithm.
1153 */
1154 if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1155 !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1156 offset = get_block_size(ctx);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001157
1158 return omap_sham_shash_digest(tctx->fallback, req->base.flags,
Tero Kristocb8d5c82016-08-04 13:28:40 +03001159 ctx->buffer + offset,
1160 ctx->bufcnt - offset, req->result);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001161}
1162
1163static int omap_sham_final(struct ahash_request *req)
1164{
1165 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001166
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +03001167 ctx->flags |= BIT(FLAGS_FINUP);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001168
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +03001169 if (ctx->flags & BIT(FLAGS_ERROR))
Dmitry Kasatkinbf362752011-04-20 13:34:58 +03001170 return 0; /* uncompleted hash is not needed */
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001171
Bin Liu85e06872016-06-22 16:23:37 +03001172 /*
1173 * OMAP HW accel works only with buffers >= 9.
1174 * HMAC is always >= 9 because ipad == block size.
1175 * If buffersize is less than 240, we use fallback SW encoding,
1176 * as using DMA + HW in this case doesn't provide any benefit.
1177 */
Tero Kristo5a793bc2016-08-04 13:28:39 +03001178 if (!ctx->digcnt && ctx->bufcnt < 240)
Dmitry Kasatkinbf362752011-04-20 13:34:58 +03001179 return omap_sham_final_shash(req);
1180 else if (ctx->bufcnt)
1181 return omap_sham_enqueue(req, OP_FINAL);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001182
Dmitry Kasatkinbf362752011-04-20 13:34:58 +03001183 /* copy ready hash (+ finalize hmac) */
1184 return omap_sham_finish(req);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001185}
1186
1187static int omap_sham_finup(struct ahash_request *req)
1188{
1189 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1190 int err1, err2;
1191
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +03001192 ctx->flags |= BIT(FLAGS_FINUP);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001193
1194 err1 = omap_sham_update(req);
Markku Kylanpaa455e3382011-04-20 13:34:55 +03001195 if (err1 == -EINPROGRESS || err1 == -EBUSY)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001196 return err1;
1197 /*
1198 * final() has to be always called to cleanup resources
1199 * even if udpate() failed, except EINPROGRESS
1200 */
1201 err2 = omap_sham_final(req);
1202
1203 return err1 ?: err2;
1204}
1205
1206static int omap_sham_digest(struct ahash_request *req)
1207{
1208 return omap_sham_init(req) ?: omap_sham_finup(req);
1209}
1210
1211static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1212 unsigned int keylen)
1213{
1214 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1215 struct omap_sham_hmac_ctx *bctx = tctx->base;
1216 int bs = crypto_shash_blocksize(bctx->shash);
1217 int ds = crypto_shash_digestsize(bctx->shash);
Mark A. Greer0d373d62012-12-21 10:04:08 -07001218 struct omap_sham_dev *dd = NULL, *tmp;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001219 int err, i;
Mark A. Greer0d373d62012-12-21 10:04:08 -07001220
1221 spin_lock_bh(&sham.lock);
1222 if (!tctx->dd) {
1223 list_for_each_entry(tmp, &sham.dev_list, list) {
1224 dd = tmp;
1225 break;
1226 }
1227 tctx->dd = dd;
1228 } else {
1229 dd = tctx->dd;
1230 }
1231 spin_unlock_bh(&sham.lock);
1232
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001233 err = crypto_shash_setkey(tctx->fallback, key, keylen);
1234 if (err)
1235 return err;
1236
1237 if (keylen > bs) {
1238 err = omap_sham_shash_digest(bctx->shash,
1239 crypto_shash_get_flags(bctx->shash),
1240 key, keylen, bctx->ipad);
1241 if (err)
1242 return err;
1243 keylen = ds;
1244 } else {
1245 memcpy(bctx->ipad, key, keylen);
1246 }
1247
1248 memset(bctx->ipad + keylen, 0, bs - keylen);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001249
Mark A. Greer0d373d62012-12-21 10:04:08 -07001250 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1251 memcpy(bctx->opad, bctx->ipad, bs);
1252
1253 for (i = 0; i < bs; i++) {
1254 bctx->ipad[i] ^= 0x36;
1255 bctx->opad[i] ^= 0x5c;
1256 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001257 }
1258
1259 return err;
1260}
1261
1262static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1263{
1264 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1265 const char *alg_name = crypto_tfm_alg_name(tfm);
1266
1267 /* Allocate a fallback and abort if it failed. */
1268 tctx->fallback = crypto_alloc_shash(alg_name, 0,
1269 CRYPTO_ALG_NEED_FALLBACK);
1270 if (IS_ERR(tctx->fallback)) {
1271 pr_err("omap-sham: fallback driver '%s' "
1272 "could not be loaded.\n", alg_name);
1273 return PTR_ERR(tctx->fallback);
1274 }
1275
1276 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +02001277 sizeof(struct omap_sham_reqctx) + BUFLEN);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001278
1279 if (alg_base) {
1280 struct omap_sham_hmac_ctx *bctx = tctx->base;
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +03001281 tctx->flags |= BIT(FLAGS_HMAC);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001282 bctx->shash = crypto_alloc_shash(alg_base, 0,
1283 CRYPTO_ALG_NEED_FALLBACK);
1284 if (IS_ERR(bctx->shash)) {
1285 pr_err("omap-sham: base driver '%s' "
1286 "could not be loaded.\n", alg_base);
1287 crypto_free_shash(tctx->fallback);
1288 return PTR_ERR(bctx->shash);
1289 }
1290
1291 }
1292
1293 return 0;
1294}
1295
1296static int omap_sham_cra_init(struct crypto_tfm *tfm)
1297{
1298 return omap_sham_cra_init_alg(tfm, NULL);
1299}
1300
1301static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1302{
1303 return omap_sham_cra_init_alg(tfm, "sha1");
1304}
1305
Mark A. Greerd20fb182012-12-21 10:04:09 -07001306static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1307{
1308 return omap_sham_cra_init_alg(tfm, "sha224");
1309}
1310
1311static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1312{
1313 return omap_sham_cra_init_alg(tfm, "sha256");
1314}
1315
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001316static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1317{
1318 return omap_sham_cra_init_alg(tfm, "md5");
1319}
1320
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +05301321static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1322{
1323 return omap_sham_cra_init_alg(tfm, "sha384");
1324}
1325
1326static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1327{
1328 return omap_sham_cra_init_alg(tfm, "sha512");
1329}
1330
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001331static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1332{
1333 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1334
1335 crypto_free_shash(tctx->fallback);
1336 tctx->fallback = NULL;
1337
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +03001338 if (tctx->flags & BIT(FLAGS_HMAC)) {
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001339 struct omap_sham_hmac_ctx *bctx = tctx->base;
1340 crypto_free_shash(bctx->shash);
1341 }
1342}
1343
Tero Kristo99a7fff2016-09-19 18:22:12 +03001344static int omap_sham_export(struct ahash_request *req, void *out)
1345{
1346 return -ENOTSUPP;
1347}
1348
1349static int omap_sham_import(struct ahash_request *req, const void *in)
1350{
1351 return -ENOTSUPP;
1352}
1353
Mark A. Greerd20fb182012-12-21 10:04:09 -07001354static struct ahash_alg algs_sha1_md5[] = {
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001355{
1356 .init = omap_sham_init,
1357 .update = omap_sham_update,
1358 .final = omap_sham_final,
1359 .finup = omap_sham_finup,
1360 .digest = omap_sham_digest,
1361 .halg.digestsize = SHA1_DIGEST_SIZE,
1362 .halg.base = {
1363 .cra_name = "sha1",
1364 .cra_driver_name = "omap-sha1",
Bin Liueb354782016-06-30 14:04:11 -05001365 .cra_priority = 400,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001366 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
Nikos Mavrogiannopoulosd912bb72011-11-01 13:39:56 +01001367 CRYPTO_ALG_KERN_DRIVER_ONLY |
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001368 CRYPTO_ALG_ASYNC |
1369 CRYPTO_ALG_NEED_FALLBACK,
1370 .cra_blocksize = SHA1_BLOCK_SIZE,
1371 .cra_ctxsize = sizeof(struct omap_sham_ctx),
Tero Kristo744e6862016-09-19 18:22:13 +03001372 .cra_alignmask = OMAP_ALIGN_MASK,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001373 .cra_module = THIS_MODULE,
1374 .cra_init = omap_sham_cra_init,
1375 .cra_exit = omap_sham_cra_exit,
1376 }
1377},
1378{
1379 .init = omap_sham_init,
1380 .update = omap_sham_update,
1381 .final = omap_sham_final,
1382 .finup = omap_sham_finup,
1383 .digest = omap_sham_digest,
1384 .halg.digestsize = MD5_DIGEST_SIZE,
1385 .halg.base = {
1386 .cra_name = "md5",
1387 .cra_driver_name = "omap-md5",
Bin Liueb354782016-06-30 14:04:11 -05001388 .cra_priority = 400,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001389 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
Nikos Mavrogiannopoulosd912bb72011-11-01 13:39:56 +01001390 CRYPTO_ALG_KERN_DRIVER_ONLY |
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001391 CRYPTO_ALG_ASYNC |
1392 CRYPTO_ALG_NEED_FALLBACK,
1393 .cra_blocksize = SHA1_BLOCK_SIZE,
1394 .cra_ctxsize = sizeof(struct omap_sham_ctx),
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +02001395 .cra_alignmask = OMAP_ALIGN_MASK,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001396 .cra_module = THIS_MODULE,
1397 .cra_init = omap_sham_cra_init,
1398 .cra_exit = omap_sham_cra_exit,
1399 }
1400},
1401{
1402 .init = omap_sham_init,
1403 .update = omap_sham_update,
1404 .final = omap_sham_final,
1405 .finup = omap_sham_finup,
1406 .digest = omap_sham_digest,
1407 .setkey = omap_sham_setkey,
1408 .halg.digestsize = SHA1_DIGEST_SIZE,
1409 .halg.base = {
1410 .cra_name = "hmac(sha1)",
1411 .cra_driver_name = "omap-hmac-sha1",
Bin Liueb354782016-06-30 14:04:11 -05001412 .cra_priority = 400,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001413 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
Nikos Mavrogiannopoulosd912bb72011-11-01 13:39:56 +01001414 CRYPTO_ALG_KERN_DRIVER_ONLY |
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001415 CRYPTO_ALG_ASYNC |
1416 CRYPTO_ALG_NEED_FALLBACK,
1417 .cra_blocksize = SHA1_BLOCK_SIZE,
1418 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1419 sizeof(struct omap_sham_hmac_ctx),
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +02001420 .cra_alignmask = OMAP_ALIGN_MASK,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001421 .cra_module = THIS_MODULE,
1422 .cra_init = omap_sham_cra_sha1_init,
1423 .cra_exit = omap_sham_cra_exit,
1424 }
1425},
1426{
1427 .init = omap_sham_init,
1428 .update = omap_sham_update,
1429 .final = omap_sham_final,
1430 .finup = omap_sham_finup,
1431 .digest = omap_sham_digest,
1432 .setkey = omap_sham_setkey,
1433 .halg.digestsize = MD5_DIGEST_SIZE,
1434 .halg.base = {
1435 .cra_name = "hmac(md5)",
1436 .cra_driver_name = "omap-hmac-md5",
Bin Liueb354782016-06-30 14:04:11 -05001437 .cra_priority = 400,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001438 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
Nikos Mavrogiannopoulosd912bb72011-11-01 13:39:56 +01001439 CRYPTO_ALG_KERN_DRIVER_ONLY |
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001440 CRYPTO_ALG_ASYNC |
1441 CRYPTO_ALG_NEED_FALLBACK,
1442 .cra_blocksize = SHA1_BLOCK_SIZE,
1443 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1444 sizeof(struct omap_sham_hmac_ctx),
Dmitry Kasatkin798eed5d2010-11-19 16:04:26 +02001445 .cra_alignmask = OMAP_ALIGN_MASK,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001446 .cra_module = THIS_MODULE,
1447 .cra_init = omap_sham_cra_md5_init,
1448 .cra_exit = omap_sham_cra_exit,
1449 }
1450}
1451};
1452
Mark A. Greerd20fb182012-12-21 10:04:09 -07001453/* OMAP4 has some algs in addition to what OMAP2 has */
1454static struct ahash_alg algs_sha224_sha256[] = {
1455{
1456 .init = omap_sham_init,
1457 .update = omap_sham_update,
1458 .final = omap_sham_final,
1459 .finup = omap_sham_finup,
1460 .digest = omap_sham_digest,
1461 .halg.digestsize = SHA224_DIGEST_SIZE,
1462 .halg.base = {
1463 .cra_name = "sha224",
1464 .cra_driver_name = "omap-sha224",
Bin Liueb354782016-06-30 14:04:11 -05001465 .cra_priority = 400,
Mark A. Greerd20fb182012-12-21 10:04:09 -07001466 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1467 CRYPTO_ALG_ASYNC |
1468 CRYPTO_ALG_NEED_FALLBACK,
1469 .cra_blocksize = SHA224_BLOCK_SIZE,
1470 .cra_ctxsize = sizeof(struct omap_sham_ctx),
Tero Kristo744e6862016-09-19 18:22:13 +03001471 .cra_alignmask = OMAP_ALIGN_MASK,
Mark A. Greerd20fb182012-12-21 10:04:09 -07001472 .cra_module = THIS_MODULE,
1473 .cra_init = omap_sham_cra_init,
1474 .cra_exit = omap_sham_cra_exit,
1475 }
1476},
1477{
1478 .init = omap_sham_init,
1479 .update = omap_sham_update,
1480 .final = omap_sham_final,
1481 .finup = omap_sham_finup,
1482 .digest = omap_sham_digest,
1483 .halg.digestsize = SHA256_DIGEST_SIZE,
1484 .halg.base = {
1485 .cra_name = "sha256",
1486 .cra_driver_name = "omap-sha256",
Bin Liueb354782016-06-30 14:04:11 -05001487 .cra_priority = 400,
Mark A. Greerd20fb182012-12-21 10:04:09 -07001488 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1489 CRYPTO_ALG_ASYNC |
1490 CRYPTO_ALG_NEED_FALLBACK,
1491 .cra_blocksize = SHA256_BLOCK_SIZE,
1492 .cra_ctxsize = sizeof(struct omap_sham_ctx),
Tero Kristo744e6862016-09-19 18:22:13 +03001493 .cra_alignmask = OMAP_ALIGN_MASK,
Mark A. Greerd20fb182012-12-21 10:04:09 -07001494 .cra_module = THIS_MODULE,
1495 .cra_init = omap_sham_cra_init,
1496 .cra_exit = omap_sham_cra_exit,
1497 }
1498},
1499{
1500 .init = omap_sham_init,
1501 .update = omap_sham_update,
1502 .final = omap_sham_final,
1503 .finup = omap_sham_finup,
1504 .digest = omap_sham_digest,
1505 .setkey = omap_sham_setkey,
1506 .halg.digestsize = SHA224_DIGEST_SIZE,
1507 .halg.base = {
1508 .cra_name = "hmac(sha224)",
1509 .cra_driver_name = "omap-hmac-sha224",
Bin Liueb354782016-06-30 14:04:11 -05001510 .cra_priority = 400,
Mark A. Greerd20fb182012-12-21 10:04:09 -07001511 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1512 CRYPTO_ALG_ASYNC |
1513 CRYPTO_ALG_NEED_FALLBACK,
1514 .cra_blocksize = SHA224_BLOCK_SIZE,
1515 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1516 sizeof(struct omap_sham_hmac_ctx),
1517 .cra_alignmask = OMAP_ALIGN_MASK,
1518 .cra_module = THIS_MODULE,
1519 .cra_init = omap_sham_cra_sha224_init,
1520 .cra_exit = omap_sham_cra_exit,
1521 }
1522},
1523{
1524 .init = omap_sham_init,
1525 .update = omap_sham_update,
1526 .final = omap_sham_final,
1527 .finup = omap_sham_finup,
1528 .digest = omap_sham_digest,
1529 .setkey = omap_sham_setkey,
1530 .halg.digestsize = SHA256_DIGEST_SIZE,
1531 .halg.base = {
1532 .cra_name = "hmac(sha256)",
1533 .cra_driver_name = "omap-hmac-sha256",
Bin Liueb354782016-06-30 14:04:11 -05001534 .cra_priority = 400,
Mark A. Greerd20fb182012-12-21 10:04:09 -07001535 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1536 CRYPTO_ALG_ASYNC |
1537 CRYPTO_ALG_NEED_FALLBACK,
1538 .cra_blocksize = SHA256_BLOCK_SIZE,
1539 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1540 sizeof(struct omap_sham_hmac_ctx),
1541 .cra_alignmask = OMAP_ALIGN_MASK,
1542 .cra_module = THIS_MODULE,
1543 .cra_init = omap_sham_cra_sha256_init,
1544 .cra_exit = omap_sham_cra_exit,
1545 }
1546},
1547};
1548
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +05301549static struct ahash_alg algs_sha384_sha512[] = {
1550{
1551 .init = omap_sham_init,
1552 .update = omap_sham_update,
1553 .final = omap_sham_final,
1554 .finup = omap_sham_finup,
1555 .digest = omap_sham_digest,
1556 .halg.digestsize = SHA384_DIGEST_SIZE,
1557 .halg.base = {
1558 .cra_name = "sha384",
1559 .cra_driver_name = "omap-sha384",
Bin Liueb354782016-06-30 14:04:11 -05001560 .cra_priority = 400,
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +05301561 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1562 CRYPTO_ALG_ASYNC |
1563 CRYPTO_ALG_NEED_FALLBACK,
1564 .cra_blocksize = SHA384_BLOCK_SIZE,
1565 .cra_ctxsize = sizeof(struct omap_sham_ctx),
Tero Kristo744e6862016-09-19 18:22:13 +03001566 .cra_alignmask = OMAP_ALIGN_MASK,
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +05301567 .cra_module = THIS_MODULE,
1568 .cra_init = omap_sham_cra_init,
1569 .cra_exit = omap_sham_cra_exit,
1570 }
1571},
1572{
1573 .init = omap_sham_init,
1574 .update = omap_sham_update,
1575 .final = omap_sham_final,
1576 .finup = omap_sham_finup,
1577 .digest = omap_sham_digest,
1578 .halg.digestsize = SHA512_DIGEST_SIZE,
1579 .halg.base = {
1580 .cra_name = "sha512",
1581 .cra_driver_name = "omap-sha512",
Bin Liueb354782016-06-30 14:04:11 -05001582 .cra_priority = 400,
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +05301583 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1584 CRYPTO_ALG_ASYNC |
1585 CRYPTO_ALG_NEED_FALLBACK,
1586 .cra_blocksize = SHA512_BLOCK_SIZE,
1587 .cra_ctxsize = sizeof(struct omap_sham_ctx),
Tero Kristo744e6862016-09-19 18:22:13 +03001588 .cra_alignmask = OMAP_ALIGN_MASK,
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +05301589 .cra_module = THIS_MODULE,
1590 .cra_init = omap_sham_cra_init,
1591 .cra_exit = omap_sham_cra_exit,
1592 }
1593},
1594{
1595 .init = omap_sham_init,
1596 .update = omap_sham_update,
1597 .final = omap_sham_final,
1598 .finup = omap_sham_finup,
1599 .digest = omap_sham_digest,
1600 .setkey = omap_sham_setkey,
1601 .halg.digestsize = SHA384_DIGEST_SIZE,
1602 .halg.base = {
1603 .cra_name = "hmac(sha384)",
1604 .cra_driver_name = "omap-hmac-sha384",
Bin Liueb354782016-06-30 14:04:11 -05001605 .cra_priority = 400,
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +05301606 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1607 CRYPTO_ALG_ASYNC |
1608 CRYPTO_ALG_NEED_FALLBACK,
1609 .cra_blocksize = SHA384_BLOCK_SIZE,
1610 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1611 sizeof(struct omap_sham_hmac_ctx),
1612 .cra_alignmask = OMAP_ALIGN_MASK,
1613 .cra_module = THIS_MODULE,
1614 .cra_init = omap_sham_cra_sha384_init,
1615 .cra_exit = omap_sham_cra_exit,
1616 }
1617},
1618{
1619 .init = omap_sham_init,
1620 .update = omap_sham_update,
1621 .final = omap_sham_final,
1622 .finup = omap_sham_finup,
1623 .digest = omap_sham_digest,
1624 .setkey = omap_sham_setkey,
1625 .halg.digestsize = SHA512_DIGEST_SIZE,
1626 .halg.base = {
1627 .cra_name = "hmac(sha512)",
1628 .cra_driver_name = "omap-hmac-sha512",
Bin Liueb354782016-06-30 14:04:11 -05001629 .cra_priority = 400,
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +05301630 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1631 CRYPTO_ALG_ASYNC |
1632 CRYPTO_ALG_NEED_FALLBACK,
1633 .cra_blocksize = SHA512_BLOCK_SIZE,
1634 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1635 sizeof(struct omap_sham_hmac_ctx),
1636 .cra_alignmask = OMAP_ALIGN_MASK,
1637 .cra_module = THIS_MODULE,
1638 .cra_init = omap_sham_cra_sha512_init,
1639 .cra_exit = omap_sham_cra_exit,
1640 }
1641},
1642};
1643
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001644static void omap_sham_done_task(unsigned long data)
1645{
1646 struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
Dmitry Kasatkin6c63db82011-06-02 21:10:10 +03001647 int err = 0;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001648
Dmitry Kasatkin6cb3ffe2011-06-02 21:10:09 +03001649 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1650 omap_sham_handle_queue(dd, NULL);
1651 return;
1652 }
1653
Dmitry Kasatkin6c63db82011-06-02 21:10:10 +03001654 if (test_bit(FLAGS_CPU, &dd->flags)) {
Lokesh Vutlab8411cc2013-08-20 20:32:34 +05301655 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1656 /* hash or semi-hash ready */
1657 err = omap_sham_update_cpu(dd);
1658 if (err != -EINPROGRESS)
1659 goto finish;
1660 }
Dmitry Kasatkin6c63db82011-06-02 21:10:10 +03001661 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1662 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1663 omap_sham_update_dma_stop(dd);
1664 if (dd->err) {
1665 err = dd->err;
1666 goto finish;
1667 }
1668 }
1669 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1670 /* hash or semi-hash ready */
1671 clear_bit(FLAGS_DMA_READY, &dd->flags);
Dmitry Kasatkin887c8832010-11-19 16:04:29 +02001672 err = omap_sham_update_dma_start(dd);
Dmitry Kasatkin6c63db82011-06-02 21:10:10 +03001673 if (err != -EINPROGRESS)
1674 goto finish;
1675 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001676 }
1677
Dmitry Kasatkin6c63db82011-06-02 21:10:10 +03001678 return;
Dmitry Kasatkin3e133c82010-11-19 16:04:24 +02001679
Dmitry Kasatkin6c63db82011-06-02 21:10:10 +03001680finish:
1681 dev_dbg(dd->dev, "update done: err: %d\n", err);
1682 /* finish curent request */
1683 omap_sham_finish_req(dd->req, err);
Tero Kristo4e7813a2016-08-04 13:28:36 +03001684
1685 /* If we are not busy, process next req */
1686 if (!test_bit(FLAGS_BUSY, &dd->flags))
1687 omap_sham_handle_queue(dd, NULL);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001688}
1689
Mark A. Greer0d373d62012-12-21 10:04:08 -07001690static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1691{
1692 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1693 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1694 } else {
1695 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1696 tasklet_schedule(&dd->done_task);
1697 }
1698
1699 return IRQ_HANDLED;
1700}
1701
1702static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001703{
1704 struct omap_sham_dev *dd = dev_id;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001705
Dmitry Kasatkined3ea9a82011-06-02 21:10:07 +03001706 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001707 /* final -> allow device to go to power-saving mode */
1708 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1709
1710 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1711 SHA_REG_CTRL_OUTPUT_READY);
1712 omap_sham_read(dd, SHA_REG_CTRL);
1713
Mark A. Greer0d373d62012-12-21 10:04:08 -07001714 return omap_sham_irq_common(dd);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001715}
1716
Mark A. Greer0d373d62012-12-21 10:04:08 -07001717static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001718{
Mark A. Greer0d373d62012-12-21 10:04:08 -07001719 struct omap_sham_dev *dd = dev_id;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001720
Mark A. Greer0d373d62012-12-21 10:04:08 -07001721 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
Dmitry Kasatkin3e133c82010-11-19 16:04:24 +02001722
Mark A. Greer0d373d62012-12-21 10:04:08 -07001723 return omap_sham_irq_common(dd);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001724}
1725
Mark A. Greerd20fb182012-12-21 10:04:09 -07001726static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1727 {
1728 .algs_list = algs_sha1_md5,
1729 .size = ARRAY_SIZE(algs_sha1_md5),
1730 },
1731};
1732
Mark A. Greer0d373d62012-12-21 10:04:08 -07001733static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
Mark A. Greerd20fb182012-12-21 10:04:09 -07001734 .algs_info = omap_sham_algs_info_omap2,
1735 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
Mark A. Greer0d373d62012-12-21 10:04:08 -07001736 .flags = BIT(FLAGS_BE32_SHA1),
1737 .digest_size = SHA1_DIGEST_SIZE,
1738 .copy_hash = omap_sham_copy_hash_omap2,
1739 .write_ctrl = omap_sham_write_ctrl_omap2,
1740 .trigger = omap_sham_trigger_omap2,
1741 .poll_irq = omap_sham_poll_irq_omap2,
1742 .intr_hdlr = omap_sham_irq_omap2,
1743 .idigest_ofs = 0x00,
1744 .din_ofs = 0x1c,
1745 .digcnt_ofs = 0x14,
1746 .rev_ofs = 0x5c,
1747 .mask_ofs = 0x60,
1748 .sysstatus_ofs = 0x64,
1749 .major_mask = 0xf0,
1750 .major_shift = 4,
1751 .minor_mask = 0x0f,
1752 .minor_shift = 0,
1753};
1754
Mark A. Greer03feec92012-12-21 10:04:06 -07001755#ifdef CONFIG_OF
Mark A. Greerd20fb182012-12-21 10:04:09 -07001756static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1757 {
1758 .algs_list = algs_sha1_md5,
1759 .size = ARRAY_SIZE(algs_sha1_md5),
1760 },
1761 {
1762 .algs_list = algs_sha224_sha256,
1763 .size = ARRAY_SIZE(algs_sha224_sha256),
1764 },
1765};
1766
Mark A. Greer0d373d62012-12-21 10:04:08 -07001767static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
Mark A. Greerd20fb182012-12-21 10:04:09 -07001768 .algs_info = omap_sham_algs_info_omap4,
1769 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
Mark A. Greer0d373d62012-12-21 10:04:08 -07001770 .flags = BIT(FLAGS_AUTO_XOR),
1771 .digest_size = SHA256_DIGEST_SIZE,
1772 .copy_hash = omap_sham_copy_hash_omap4,
1773 .write_ctrl = omap_sham_write_ctrl_omap4,
1774 .trigger = omap_sham_trigger_omap4,
1775 .poll_irq = omap_sham_poll_irq_omap4,
1776 .intr_hdlr = omap_sham_irq_omap4,
1777 .idigest_ofs = 0x020,
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +05301778 .odigest_ofs = 0x0,
Mark A. Greer0d373d62012-12-21 10:04:08 -07001779 .din_ofs = 0x080,
1780 .digcnt_ofs = 0x040,
1781 .rev_ofs = 0x100,
1782 .mask_ofs = 0x110,
1783 .sysstatus_ofs = 0x114,
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +05301784 .mode_ofs = 0x44,
1785 .length_ofs = 0x48,
Mark A. Greer0d373d62012-12-21 10:04:08 -07001786 .major_mask = 0x0700,
1787 .major_shift = 8,
1788 .minor_mask = 0x003f,
1789 .minor_shift = 0,
1790};
1791
Lokesh Vutla7d7c7042013-07-26 12:29:15 +05301792static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1793 {
1794 .algs_list = algs_sha1_md5,
1795 .size = ARRAY_SIZE(algs_sha1_md5),
1796 },
1797 {
1798 .algs_list = algs_sha224_sha256,
1799 .size = ARRAY_SIZE(algs_sha224_sha256),
1800 },
1801 {
1802 .algs_list = algs_sha384_sha512,
1803 .size = ARRAY_SIZE(algs_sha384_sha512),
1804 },
1805};
1806
1807static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1808 .algs_info = omap_sham_algs_info_omap5,
1809 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1810 .flags = BIT(FLAGS_AUTO_XOR),
1811 .digest_size = SHA512_DIGEST_SIZE,
1812 .copy_hash = omap_sham_copy_hash_omap4,
1813 .write_ctrl = omap_sham_write_ctrl_omap4,
1814 .trigger = omap_sham_trigger_omap4,
1815 .poll_irq = omap_sham_poll_irq_omap4,
1816 .intr_hdlr = omap_sham_irq_omap4,
1817 .idigest_ofs = 0x240,
1818 .odigest_ofs = 0x200,
1819 .din_ofs = 0x080,
1820 .digcnt_ofs = 0x280,
1821 .rev_ofs = 0x100,
1822 .mask_ofs = 0x110,
1823 .sysstatus_ofs = 0x114,
1824 .mode_ofs = 0x284,
1825 .length_ofs = 0x288,
1826 .major_mask = 0x0700,
1827 .major_shift = 8,
1828 .minor_mask = 0x003f,
1829 .minor_shift = 0,
1830};
1831
Mark A. Greer03feec92012-12-21 10:04:06 -07001832static const struct of_device_id omap_sham_of_match[] = {
1833 {
1834 .compatible = "ti,omap2-sham",
Mark A. Greer0d373d62012-12-21 10:04:08 -07001835 .data = &omap_sham_pdata_omap2,
1836 },
1837 {
Pali Roháreddca852015-02-26 14:49:53 +01001838 .compatible = "ti,omap3-sham",
1839 .data = &omap_sham_pdata_omap2,
1840 },
1841 {
Mark A. Greer0d373d62012-12-21 10:04:08 -07001842 .compatible = "ti,omap4-sham",
1843 .data = &omap_sham_pdata_omap4,
Mark A. Greer03feec92012-12-21 10:04:06 -07001844 },
Lokesh Vutla7d7c7042013-07-26 12:29:15 +05301845 {
1846 .compatible = "ti,omap5-sham",
1847 .data = &omap_sham_pdata_omap5,
1848 },
Mark A. Greer03feec92012-12-21 10:04:06 -07001849 {},
1850};
1851MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1852
1853static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1854 struct device *dev, struct resource *res)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001855{
Mark A. Greer03feec92012-12-21 10:04:06 -07001856 struct device_node *node = dev->of_node;
1857 const struct of_device_id *match;
1858 int err = 0;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001859
Mark A. Greer03feec92012-12-21 10:04:06 -07001860 match = of_match_device(of_match_ptr(omap_sham_of_match), dev);
1861 if (!match) {
1862 dev_err(dev, "no compatible OF match\n");
1863 err = -EINVAL;
1864 goto err;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001865 }
Samu Onkalo584db6a2010-09-03 19:20:19 +08001866
Mark A. Greer03feec92012-12-21 10:04:06 -07001867 err = of_address_to_resource(node, 0, res);
1868 if (err < 0) {
1869 dev_err(dev, "can't translate OF node address\n");
1870 err = -EINVAL;
1871 goto err;
1872 }
1873
Thierry Redingf7578492013-09-18 15:24:44 +02001874 dd->irq = irq_of_parse_and_map(node, 0);
Mark A. Greer03feec92012-12-21 10:04:06 -07001875 if (!dd->irq) {
1876 dev_err(dev, "can't translate OF irq value\n");
1877 err = -EINVAL;
1878 goto err;
1879 }
1880
Mark A. Greer0d373d62012-12-21 10:04:08 -07001881 dd->pdata = match->data;
Mark A. Greer03feec92012-12-21 10:04:06 -07001882
1883err:
1884 return err;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001885}
Mark A. Greer03feec92012-12-21 10:04:06 -07001886#else
Mark A. Greerc3c3b322013-01-15 13:53:02 -07001887static const struct of_device_id omap_sham_of_match[] = {
1888 {},
1889};
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001890
Mark A. Greerc3c3b322013-01-15 13:53:02 -07001891static int omap_sham_get_res_of(struct omap_sham_dev *dd,
Mark A. Greer03feec92012-12-21 10:04:06 -07001892 struct device *dev, struct resource *res)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001893{
Mark A. Greer03feec92012-12-21 10:04:06 -07001894 return -EINVAL;
1895}
1896#endif
1897
1898static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1899 struct platform_device *pdev, struct resource *res)
1900{
1901 struct device *dev = &pdev->dev;
1902 struct resource *r;
1903 int err = 0;
1904
1905 /* Get the base address */
1906 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1907 if (!r) {
1908 dev_err(dev, "no MEM resource info\n");
1909 err = -ENODEV;
1910 goto err;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001911 }
Mark A. Greer03feec92012-12-21 10:04:06 -07001912 memcpy(res, r, sizeof(*res));
1913
1914 /* Get the IRQ */
1915 dd->irq = platform_get_irq(pdev, 0);
1916 if (dd->irq < 0) {
1917 dev_err(dev, "no IRQ resource info\n");
1918 err = dd->irq;
1919 goto err;
1920 }
1921
Mark A. Greer0d373d62012-12-21 10:04:08 -07001922 /* Only OMAP2/3 can be non-DT */
1923 dd->pdata = &omap_sham_pdata_omap2;
1924
Mark A. Greer03feec92012-12-21 10:04:06 -07001925err:
1926 return err;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001927}
1928
Greg Kroah-Hartman49cfe4d2012-12-21 13:14:09 -08001929static int omap_sham_probe(struct platform_device *pdev)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001930{
1931 struct omap_sham_dev *dd;
1932 struct device *dev = &pdev->dev;
Mark A. Greer03feec92012-12-21 10:04:06 -07001933 struct resource res;
Mark A. Greerdfd061d2012-12-21 10:04:04 -07001934 dma_cap_mask_t mask;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001935 int err, i, j;
Mark A. Greer0d373d62012-12-21 10:04:08 -07001936 u32 rev;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001937
Lokesh Vutla7a7e4b72013-07-26 12:29:17 +05301938 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001939 if (dd == NULL) {
1940 dev_err(dev, "unable to alloc data struct.\n");
1941 err = -ENOMEM;
1942 goto data_err;
1943 }
1944 dd->dev = dev;
1945 platform_set_drvdata(pdev, dd);
1946
1947 INIT_LIST_HEAD(&dd->list);
1948 spin_lock_init(&dd->lock);
1949 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001950 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
1951
Mark A. Greer03feec92012-12-21 10:04:06 -07001952 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
1953 omap_sham_get_res_pdev(dd, pdev, &res);
1954 if (err)
Lokesh Vutla7a7e4b72013-07-26 12:29:17 +05301955 goto data_err;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001956
Laurent Navet30862282013-05-02 14:00:38 +02001957 dd->io_base = devm_ioremap_resource(dev, &res);
1958 if (IS_ERR(dd->io_base)) {
1959 err = PTR_ERR(dd->io_base);
Lokesh Vutla7a7e4b72013-07-26 12:29:17 +05301960 goto data_err;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001961 }
Mark A. Greer03feec92012-12-21 10:04:06 -07001962 dd->phys_base = res.start;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001963
Lokesh Vutla0de9c382013-07-26 12:29:16 +05301964 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
1965 IRQF_TRIGGER_NONE, dev_name(dev), dd);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001966 if (err) {
Lokesh Vutla0de9c382013-07-26 12:29:16 +05301967 dev_err(dev, "unable to request irq %d, err = %d\n",
1968 dd->irq, err);
Lokesh Vutla7a7e4b72013-07-26 12:29:17 +05301969 goto data_err;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001970 }
1971
Mark A. Greerdfd061d2012-12-21 10:04:04 -07001972 dma_cap_zero(mask);
1973 dma_cap_set(DMA_SLAVE, mask);
1974
Peter Ujfalusidbe24622016-04-29 16:03:41 +03001975 dd->dma_lch = dma_request_chan(dev, "rx");
1976 if (IS_ERR(dd->dma_lch)) {
1977 err = PTR_ERR(dd->dma_lch);
1978 if (err == -EPROBE_DEFER)
1979 goto data_err;
1980
Lokesh Vutlab8411cc2013-08-20 20:32:34 +05301981 dd->polling_mode = 1;
1982 dev_dbg(dev, "using polling mode instead of dma\n");
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001983 }
1984
Mark A. Greer0d373d62012-12-21 10:04:08 -07001985 dd->flags |= dd->pdata->flags;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001986
Tero Kristoe93f7672016-06-22 16:23:34 +03001987 pm_runtime_use_autosuspend(dev);
1988 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
1989
Mark A. Greerb359f032012-12-21 10:04:02 -07001990 pm_runtime_enable(dev);
Vutla, Lokeshb0a3d892015-03-31 09:52:24 +05301991 pm_runtime_irq_safe(dev);
Pali Rohár604c3102015-03-08 11:01:01 +01001992
1993 err = pm_runtime_get_sync(dev);
1994 if (err < 0) {
1995 dev_err(dev, "failed to get sync: %d\n", err);
1996 goto err_pm;
1997 }
1998
Mark A. Greer0d373d62012-12-21 10:04:08 -07001999 rev = omap_sham_read(dd, SHA_REG_REV(dd));
2000 pm_runtime_put_sync(&pdev->dev);
Mark A. Greerb359f032012-12-21 10:04:02 -07002001
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002002 dev_info(dev, "hw accel on OMAP rev %u.%u\n",
Mark A. Greer0d373d62012-12-21 10:04:08 -07002003 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2004 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002005
2006 spin_lock(&sham.lock);
2007 list_add_tail(&dd->list, &sham.dev_list);
2008 spin_unlock(&sham.lock);
2009
Mark A. Greerd20fb182012-12-21 10:04:09 -07002010 for (i = 0; i < dd->pdata->algs_info_size; i++) {
2011 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
Tero Kristo99a7fff2016-09-19 18:22:12 +03002012 struct ahash_alg *alg;
2013
2014 alg = &dd->pdata->algs_info[i].algs_list[j];
2015 alg->export = omap_sham_export;
2016 alg->import = omap_sham_import;
2017 alg->halg.statesize = sizeof(struct omap_sham_reqctx);
2018 err = crypto_register_ahash(alg);
Mark A. Greerd20fb182012-12-21 10:04:09 -07002019 if (err)
2020 goto err_algs;
2021
2022 dd->pdata->algs_info[i].registered++;
2023 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002024 }
2025
2026 return 0;
2027
2028err_algs:
Mark A. Greerd20fb182012-12-21 10:04:09 -07002029 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2030 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2031 crypto_unregister_ahash(
2032 &dd->pdata->algs_info[i].algs_list[j]);
Pali Rohár604c3102015-03-08 11:01:01 +01002033err_pm:
Mark A. Greerb359f032012-12-21 10:04:02 -07002034 pm_runtime_disable(dev);
Dan Carpenterd462e322016-05-18 13:39:05 +03002035 if (!dd->polling_mode)
Mark A. Greerf13ab862013-11-12 13:12:27 -07002036 dma_release_channel(dd->dma_lch);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002037data_err:
2038 dev_err(dev, "initialization failed.\n");
2039
2040 return err;
2041}
2042
Greg Kroah-Hartman49cfe4d2012-12-21 13:14:09 -08002043static int omap_sham_remove(struct platform_device *pdev)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002044{
2045 static struct omap_sham_dev *dd;
Mark A. Greerd20fb182012-12-21 10:04:09 -07002046 int i, j;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002047
2048 dd = platform_get_drvdata(pdev);
2049 if (!dd)
2050 return -ENODEV;
2051 spin_lock(&sham.lock);
2052 list_del(&dd->list);
2053 spin_unlock(&sham.lock);
Mark A. Greerd20fb182012-12-21 10:04:09 -07002054 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2055 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2056 crypto_unregister_ahash(
2057 &dd->pdata->algs_info[i].algs_list[j]);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002058 tasklet_kill(&dd->done_task);
Mark A. Greerb359f032012-12-21 10:04:02 -07002059 pm_runtime_disable(&pdev->dev);
Mark A. Greerf13ab862013-11-12 13:12:27 -07002060
Peter Ujfalusidbe24622016-04-29 16:03:41 +03002061 if (!dd->polling_mode)
Mark A. Greerf13ab862013-11-12 13:12:27 -07002062 dma_release_channel(dd->dma_lch);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002063
2064 return 0;
2065}
2066
Mark A. Greer3b3f4402012-12-21 10:04:03 -07002067#ifdef CONFIG_PM_SLEEP
2068static int omap_sham_suspend(struct device *dev)
2069{
2070 pm_runtime_put_sync(dev);
2071 return 0;
2072}
2073
2074static int omap_sham_resume(struct device *dev)
2075{
Pali Rohár604c3102015-03-08 11:01:01 +01002076 int err = pm_runtime_get_sync(dev);
2077 if (err < 0) {
2078 dev_err(dev, "failed to get sync: %d\n", err);
2079 return err;
2080 }
Mark A. Greer3b3f4402012-12-21 10:04:03 -07002081 return 0;
2082}
2083#endif
2084
Jingoo Hanae12fe22014-02-27 20:33:32 +09002085static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
Mark A. Greer3b3f4402012-12-21 10:04:03 -07002086
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002087static struct platform_driver omap_sham_driver = {
2088 .probe = omap_sham_probe,
2089 .remove = omap_sham_remove,
2090 .driver = {
2091 .name = "omap-sham",
Mark A. Greer3b3f4402012-12-21 10:04:03 -07002092 .pm = &omap_sham_pm_ops,
Mark A. Greer03feec92012-12-21 10:04:06 -07002093 .of_match_table = omap_sham_of_match,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002094 },
2095};
2096
Sachin Kamat02613702013-03-04 15:09:43 +05302097module_platform_driver(omap_sham_driver);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002098
2099MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2100MODULE_LICENSE("GPL v2");
2101MODULE_AUTHOR("Dmitry Kasatkin");
Joni Lapilainen718249d2013-10-26 23:00:41 +02002102MODULE_ALIAS("platform:omap-sham");