blob: 8de9085bba9e4e724ee249d7104c1e52d2163219 [file] [log] [blame]
Jeff Kirsherae06c702018-03-22 10:08:48 -07001/* SPDX-License-Identifier: GPL-2.0 */
Jeff Kirsher51dce242018-04-26 08:08:09 -07002/* Copyright(c) 2013 - 2018 Intel Corporation. */
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +00003
4#ifndef _I40E_H_
5#define _I40E_H_
6
7#include <net/tcp.h>
Joseph Gasparakis8144f0f2013-12-28 05:27:57 +00008#include <net/udp.h>
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +00009#include <linux/types.h>
10#include <linux/errno.h>
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/aer.h>
14#include <linux/netdevice.h>
15#include <linux/ioport.h>
Mitch Williams2bc7ee82015-02-06 08:52:11 +000016#include <linux/iommu.h>
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +000017#include <linux/slab.h>
18#include <linux/list.h>
Jacob Keller278e7d02016-10-05 09:30:37 -070019#include <linux/hashtable.h>
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +000020#include <linux/string.h>
21#include <linux/in.h>
22#include <linux/ip.h>
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +000023#include <linux/sctp.h>
24#include <linux/pkt_sched.h>
25#include <linux/ipv6.h>
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +000026#include <net/checksum.h>
27#include <net/ip6_checksum.h>
28#include <linux/ethtool.h>
29#include <linux/if_vlan.h>
Neerav Parikh51616012015-02-06 08:52:14 +000030#include <linux/if_bridge.h>
Jacob Kellerbeb0dff2014-01-11 05:43:19 +000031#include <linux/clocksource.h>
32#include <linux/net_tstamp.h>
33#include <linux/ptp_clock_kernel.h>
Amritha Nambiara9ce82f2017-09-07 04:00:22 -070034#include <net/pkt_cls.h>
Amritha Nambiar2f4b4112017-10-27 02:36:01 -070035#include <net/tc_act/tc_gact.h>
36#include <net/tc_act/tc_mirred.h>
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +000037#include "i40e_type.h"
38#include "i40e_prototype.h"
Anjali Singhai Jaine3219ce2016-01-20 13:40:01 -060039#include "i40e_client.h"
Jesse Brandeburg55cdfd42017-05-11 11:23:10 -070040#include <linux/avf/virtchnl.h>
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +000041#include "i40e_virtchnl_pf.h"
42#include "i40e_txrx.h"
Neerav Parikh4e3b35b2014-01-17 15:36:37 -080043#include "i40e_dcb.h"
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +000044
45/* Useful i40e defaults */
Jeff Kirsherc57c9952016-08-19 21:47:41 -070046#define I40E_MAX_VEB 16
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +000047
Jeff Kirsherc57c9952016-08-19 21:47:41 -070048#define I40E_MAX_NUM_DESCRIPTORS 4096
49#define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
50#define I40E_DEFAULT_NUM_DESCRIPTORS 512
51#define I40E_REQ_DESCRIPTOR_MULTIPLE 32
52#define I40E_MIN_NUM_DESCRIPTORS 64
53#define I40E_MIN_MSIX 2
54#define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
Akeem Abodunrin7ac4b5c2016-09-12 14:18:37 -070055#define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */
Anjali Singhai Jaine25d00b82015-06-23 19:00:04 -040056/* max 16 qps */
57#define i40e_default_queues_per_vmdq(pf) \
Jacob Kellerd36e41d2017-06-23 04:24:46 -040058 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)
Jeff Kirsherc57c9952016-08-19 21:47:41 -070059#define I40E_DEFAULT_QUEUES_PER_VF 4
Alan Bradya3f5aa92017-07-14 09:27:08 -040060#define I40E_MAX_VF_QUEUES 16
Jeff Kirsherc57c9952016-08-19 21:47:41 -070061#define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */
Anjali Singhai Jaine25d00b82015-06-23 19:00:04 -040062#define i40e_pf_get_max_q_per_tc(pf) \
Jacob Kellerd36e41d2017-06-23 04:24:46 -040063 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)
Jeff Kirsherc57c9952016-08-19 21:47:41 -070064#define I40E_FDIR_RING 0
65#define I40E_FDIR_RING_COUNT 32
Jeff Kirsherc57c9952016-08-19 21:47:41 -070066#define I40E_MAX_AQ_BUF_SIZE 4096
67#define I40E_AQ_LEN 256
68#define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
69#define I40E_MAX_USER_PRIORITY 8
David Ertmanea6acb72016-09-20 07:10:50 -070070#define I40E_DEFAULT_TRAFFIC_CLASS BIT(0)
Jeff Kirsherc57c9952016-08-19 21:47:41 -070071#define I40E_DEFAULT_MSG_ENABLE 4
72#define I40E_QUEUE_WAIT_RETRY_LIMIT 10
73#define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +000074
Jeff Kirsherc57c9952016-08-19 21:47:41 -070075#define I40E_NVM_VERSION_LO_SHIFT 0
76#define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
77#define I40E_NVM_VERSION_HI_SHIFT 12
78#define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
79#define I40E_OEM_VER_BUILD_MASK 0xffff
80#define I40E_OEM_VER_PATCH_MASK 0xff
81#define I40E_OEM_VER_BUILD_SHIFT 8
82#define I40E_OEM_VER_SHIFT 24
Kevin Scott06c0e392016-05-03 15:13:09 -070083#define I40E_PHY_DEBUG_ALL \
84 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
85 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
Anjali Singhai jainfe310702013-11-16 10:00:37 +000086
Filip Sadowski5bbb2e22017-06-07 05:43:09 -040087#define I40E_OEM_EETRACK_ID 0xffffffff
88#define I40E_OEM_GEN_SHIFT 24
89#define I40E_OEM_SNAP_MASK 0x00ff0000
90#define I40E_OEM_SNAP_SHIFT 16
91#define I40E_OEM_RELEASE_MASK 0x0000ffff
92
Anjali Singhai jainfe310702013-11-16 10:00:37 +000093/* The values in here are decimal coded as hex as is the case in the NVM map*/
Jeff Kirsherc57c9952016-08-19 21:47:41 -070094#define I40E_CURRENT_NVM_VERSION_HI 0x2
95#define I40E_CURRENT_NVM_VERSION_LO 0x40
Anjali Singhai jainfe310702013-11-16 10:00:37 +000096
Jeff Kirsherc57c9952016-08-19 21:47:41 -070097#define I40E_RX_DESC(R, i) \
Jesse Brandeburgbec60fc2016-04-18 11:33:47 -070098 (&(((union i40e_32byte_rx_desc *)((R)->desc))[i]))
Jeff Kirsherc57c9952016-08-19 21:47:41 -070099#define I40E_TX_DESC(R, i) \
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000100 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
Jeff Kirsherc57c9952016-08-19 21:47:41 -0700101#define I40E_TX_CTXTDESC(R, i) \
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000102 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
Jeff Kirsherc57c9952016-08-19 21:47:41 -0700103#define I40E_TX_FDIRDESC(R, i) \
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000104 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
105
106/* default to trying for four seconds */
Jeff Kirsherc57c9952016-08-19 21:47:41 -0700107#define I40E_TRY_LINK_TIMEOUT (4 * HZ)
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000108
Amritha Nambiar5ecae412017-09-07 04:00:27 -0700109/* BW rate limiting */
110#define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */
Alan Brady6c32e0d2017-10-09 15:48:45 -0700111#define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */
112#define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */
Amritha Nambiar5ecae412017-09-07 04:00:27 -0700113
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000114/* driver state flags */
115enum i40e_state_t {
116 __I40E_TESTING,
117 __I40E_CONFIG_BUSY,
118 __I40E_CONFIG_DONE,
119 __I40E_DOWN,
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000120 __I40E_SERVICE_SCHED,
121 __I40E_ADMINQ_EVENT_PENDING,
122 __I40E_MDD_EVENT_PENDING,
123 __I40E_VFLR_EVENT_PENDING,
124 __I40E_RESET_RECOVERY_PENDING,
Alan Bradyd5585b72018-10-29 11:27:21 -0700125 __I40E_TIMEOUT_RECOVERY_PENDING,
Jacob Kellerc17401a2017-07-14 09:27:02 -0400126 __I40E_MISC_IRQ_REQUESTED,
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000127 __I40E_RESET_INTR_RECEIVED,
128 __I40E_REINIT_REQUESTED,
129 __I40E_PF_RESET_REQUESTED,
130 __I40E_CORE_RESET_REQUESTED,
131 __I40E_GLOBAL_RESET_REQUESTED,
Shannon Nelson7823fe32013-11-16 10:00:45 +0000132 __I40E_EMP_RESET_REQUESTED,
Anjali Singhai Jain9df42d12015-01-24 09:58:40 +0000133 __I40E_EMP_RESET_INTR_RECEIVED,
Shannon Nelson9007bcc2013-11-26 10:49:23 +0000134 __I40E_SUSPENDED,
Jakub Kicinski9ce34f02014-03-15 14:55:42 +0000135 __I40E_PTP_TX_IN_PROGRESS,
Shannon Nelson4eb3f762014-03-06 08:59:58 +0000136 __I40E_BAD_EEPROM,
Neerav Parikhb5d06f02014-06-03 23:50:17 +0000137 __I40E_DOWN_REQUESTED,
Anjali Singhai Jain1e1be8f2014-07-10 08:03:26 +0000138 __I40E_FD_FLUSH_REQUESTED,
Jacob Keller134201a2018-03-16 01:26:32 -0700139 __I40E_FD_ATR_AUTO_DISABLED,
140 __I40E_FD_SB_AUTO_DISABLED,
Anjali Singhai Jaina316f652014-07-12 07:28:25 +0000141 __I40E_RESET_FAILED,
Jacob Keller34807562017-04-13 04:45:53 -0400142 __I40E_PORT_SUSPENDED,
Mitch Williams3ba9bcb2015-01-09 11:18:15 +0000143 __I40E_VF_DISABLE,
Jacob Kellerbfe040c2018-03-16 01:26:30 -0700144 __I40E_MACVLAN_SYNC_PENDING,
Jacob Keller41898c62018-03-16 01:26:31 -0700145 __I40E_UDP_FILTER_SYNC_PENDING,
Jacob Keller0605c452018-03-16 01:26:33 -0700146 __I40E_TEMP_LINK_POLLING,
Jacob Keller5f76a702018-03-16 01:26:34 -0700147 __I40E_CLIENT_SERVICE_REQUESTED,
148 __I40E_CLIENT_L2_CHANGE,
149 __I40E_CLIENT_RESET,
Jan Sokolowskif5a7b212018-10-30 10:50:45 -0700150 __I40E_VIRTCHNL_OP_PENDING,
Jacob Keller0da36b92017-04-19 09:25:55 -0400151 /* This must be last as it determines the size of the BITMAP */
152 __I40E_STATE_SIZE__,
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000153};
154
Amritha Nambiarff424182017-09-07 04:00:11 -0700155#define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED)
156
Jacob Kellerd19cb642017-04-21 13:38:05 -0700157/* VSI state flags */
158enum i40e_vsi_state_t {
159 __I40E_VSI_DOWN,
160 __I40E_VSI_NEEDS_RESTART,
161 __I40E_VSI_SYNCING_FILTERS,
162 __I40E_VSI_OVERFLOW_PROMISC,
163 __I40E_VSI_REINIT_REQUESTED,
164 __I40E_VSI_DOWN_REQUESTED,
Jacob Keller0da36b92017-04-19 09:25:55 -0400165 /* This must be last as it determines the size of the BITMAP */
166 __I40E_VSI_STATE_SIZE__,
Jacob Kellerd19cb642017-04-21 13:38:05 -0700167};
168
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000169enum i40e_interrupt_policy {
170 I40E_INTERRUPT_BEST_CASE,
171 I40E_INTERRUPT_MEDIUM,
172 I40E_INTERRUPT_LOWEST
173};
174
175struct i40e_lump_tracking {
176 u16 num_entries;
177 u16 search_hint;
178 u16 list[0];
179#define I40E_PILE_VALID_BIT 0x8000
Anjali Singhai Jaine3219ce2016-01-20 13:40:01 -0600180#define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000181};
182
183#define I40E_DEFAULT_ATR_SAMPLE_RATE 20
Anjali Singhai Jain55a5e602014-02-12 06:33:25 +0000184#define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
185#define I40E_FDIR_BUFFER_FULL_MARGIN 10
Anjali Singhai Jain12957382014-06-04 04:22:47 +0000186#define I40E_FDIR_BUFFER_HEAD_ROOM 32
Anjali Singhai Jain04294e32015-02-27 09:15:28 +0000187#define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
Anjali Singhai Jain55a5e602014-02-12 06:33:25 +0000188
Jeff Kirsherc57c9952016-08-19 21:47:41 -0700189#define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
190#define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
191#define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
Mitch A Williamsb29e13b2015-03-05 04:14:40 +0000192
Anjali Singhai Jain433c47d2014-05-22 06:32:17 +0000193enum i40e_fd_stat_idx {
194 I40E_FD_STAT_ATR,
195 I40E_FD_STAT_SB,
Anjali Singhai Jain60ccd452015-04-16 20:06:01 -0400196 I40E_FD_STAT_ATR_TUNNEL,
Anjali Singhai Jain433c47d2014-05-22 06:32:17 +0000197 I40E_FD_STAT_PF_COUNT
198};
199#define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
200#define I40E_FD_ATR_STAT_IDX(pf_id) \
201 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
202#define I40E_FD_SB_STAT_IDX(pf_id) \
203 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
Anjali Singhai Jain60ccd452015-04-16 20:06:01 -0400204#define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
205 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
Anjali Singhai Jain433c47d2014-05-22 06:32:17 +0000206
Jacob Kellere7930952017-02-06 14:38:49 -0800207/* The following structure contains the data parsed from the user-defined
208 * field of the ethtool_rx_flow_spec structure.
209 */
210struct i40e_rx_flow_userdef {
211 bool flex_filter;
212 u16 flex_word;
213 u16 flex_offset;
214};
215
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000216struct i40e_fdir_filter {
217 struct hlist_node fdir_node;
218 /* filter ipnut set */
219 u8 flow_type;
220 u8 ip4_proto;
Anjali Singhai Jain04b73bd2014-05-22 06:31:41 +0000221 /* TX packet view of src and dst */
Jacob Keller8ce43dc2017-02-06 14:38:39 -0800222 __be32 dst_ip;
223 __be32 src_ip;
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000224 __be16 src_port;
225 __be16 dst_port;
226 __be32 sctp_v_tag;
Jacob Keller0e588de2017-02-06 14:38:50 -0800227
228 /* Flexible data to match within the packet payload */
229 __be16 flex_word;
230 u16 flex_offset;
231 bool flex_filter;
232
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000233 /* filter control */
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000234 u16 q_index;
235 u8 flex_off;
236 u8 pctype;
237 u16 dest_vsi;
238 u8 dest_ctl;
239 u8 fd_status;
240 u16 cnt_index;
241 u32 fd_id;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000242};
243
Amritha Nambiar2f4b4112017-10-27 02:36:01 -0700244#define I40E_CLOUD_FIELD_OMAC 0x01
245#define I40E_CLOUD_FIELD_IMAC 0x02
246#define I40E_CLOUD_FIELD_IVLAN 0x04
247#define I40E_CLOUD_FIELD_TEN_ID 0x08
248#define I40E_CLOUD_FIELD_IIP 0x10
249
250#define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC
251#define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC
252#define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \
253 I40E_CLOUD_FIELD_IVLAN)
254#define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
255 I40E_CLOUD_FIELD_TEN_ID)
256#define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \
257 I40E_CLOUD_FIELD_IMAC | \
258 I40E_CLOUD_FIELD_TEN_ID)
259#define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
260 I40E_CLOUD_FIELD_IVLAN | \
261 I40E_CLOUD_FIELD_TEN_ID)
262#define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP
263
Amritha Nambiaraaf66502017-10-27 02:35:56 -0700264struct i40e_cloud_filter {
265 struct hlist_node cloud_node;
266 unsigned long cookie;
Amritha Nambiar2f4b4112017-10-27 02:36:01 -0700267 /* cloud filter input set follows */
268 u8 dst_mac[ETH_ALEN];
269 u8 src_mac[ETH_ALEN];
270 __be16 vlan_id;
271 u16 seid; /* filter control */
272 __be16 dst_port;
273 __be16 src_port;
274 u32 tenant_id;
275 union {
276 struct {
277 struct in_addr dst_ip;
278 struct in_addr src_ip;
279 } v4;
280 struct {
281 struct in6_addr dst_ip6;
282 struct in6_addr src_ip6;
283 } v6;
284 } ip;
285#define dst_ipv6 ip.v6.dst_ip6.s6_addr32
286#define src_ipv6 ip.v6.src_ip6.s6_addr32
287#define dst_ipv4 ip.v4.dst_ip.s_addr
288#define src_ipv4 ip.v4.src_ip.s_addr
289 u16 n_proto; /* Ethernet Protocol */
290 u8 ip_proto; /* IPPROTO value */
291 u8 flags;
292#define I40E_CLOUD_TNL_TYPE_NONE 0xff
293 u8 tunnel_type;
Amritha Nambiaraaf66502017-10-27 02:35:56 -0700294};
295
Neerav Parikh4e3b35b2014-01-17 15:36:37 -0800296#define I40E_ETH_P_LLDP 0x88cc
297
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000298#define I40E_DCB_PRIO_TYPE_STRICT 0
299#define I40E_DCB_PRIO_TYPE_ETS 1
300#define I40E_DCB_STRICT_PRIO_CREDITS 127
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000301/* DCB per TC information data structure */
302struct i40e_tc_info {
303 u16 qoffset; /* Queue offset from base queue */
304 u16 qcount; /* Total Queues */
305 u8 netdev_tc; /* Netdev TC index if netdev associated */
306};
307
308/* TC configuration data structure */
309struct i40e_tc_configuration {
310 u8 numtc; /* Total number of enabled TCs */
311 u8 enabled_tc; /* TC map */
312 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
313};
314
Alexander Duyck5305d0f2018-04-20 01:41:37 -0700315#define I40E_UDP_PORT_INDEX_UNUSED 255
Singhai, Anjali6a899022015-12-14 12:21:18 -0800316struct i40e_udp_port_config {
Jacob Kellerfe0b0cd2017-02-06 14:38:38 -0800317 /* AdminQ command interface expects port number in Host byte order */
Jacob Keller27826fd2017-04-19 09:25:50 -0400318 u16 port;
Singhai, Anjali6a899022015-12-14 12:21:18 -0800319 u8 type;
Alexander Duyck5305d0f2018-04-20 01:41:37 -0700320 u8 filter_index;
Singhai, Anjali6a899022015-12-14 12:21:18 -0800321};
322
Jacob Keller0e588de2017-02-06 14:38:50 -0800323/* macros related to FLX_PIT */
324#define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
325 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
326 I40E_PRTQF_FLX_PIT_FSIZE_MASK)
327#define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
328 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
329 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
330#define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
331 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
332 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
333#define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
334 I40E_FLEX_SET_FSIZE(fsize) | \
335 I40E_FLEX_SET_SRC_WORD(src))
336
337#define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \
338 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \
339 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)
340#define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \
341 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \
342 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)
343#define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \
344 I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \
345 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)
346
347#define I40E_MAX_FLEX_SRC_OFFSET 0x1F
348
349/* macros related to GLQF_ORT */
350#define I40E_ORT_SET_IDX(idx) (((idx) << \
351 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
352 I40E_GLQF_ORT_PIT_INDX_MASK)
353
354#define I40E_ORT_SET_COUNT(count) (((count) << \
355 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
356 I40E_GLQF_ORT_FIELD_CNT_MASK)
357
358#define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \
359 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
360 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
361
362#define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
363 I40E_ORT_SET_COUNT(count) | \
364 I40E_ORT_SET_PAYLOAD(payload))
365
366#define I40E_L3_GLQF_ORT_IDX 34
367#define I40E_L4_GLQF_ORT_IDX 35
368
369/* Flex PIT register index */
370#define I40E_FLEX_PIT_IDX_START_L2 0
371#define I40E_FLEX_PIT_IDX_START_L3 3
372#define I40E_FLEX_PIT_IDX_START_L4 6
373
374#define I40E_FLEX_PIT_TABLE_SIZE 3
375
376#define I40E_FLEX_DEST_UNUSED 63
377
378#define I40E_FLEX_INDEX_ENTRIES 8
379
380/* Flex MASK to disable all flexible entries */
381#define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
382 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
383 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
384 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
385
386struct i40e_flex_pit {
387 struct list_head list;
388 u16 src_offset;
389 u8 pit_index;
390};
391
Amritha Nambiar8f88b302017-09-07 04:00:17 -0700392struct i40e_channel {
393 struct list_head list;
394 bool initialized;
395 u8 type;
396 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */
397 u16 stat_counter_idx;
398 u16 base_queue;
399 u16 num_queue_pairs; /* Requested by user */
400 u16 seid;
401
402 u8 enabled_tc;
403 struct i40e_aqc_vsi_properties_data info;
404
Amritha Nambiar2027d4d2017-09-07 04:00:32 -0700405 u64 max_tx_rate;
406
Amritha Nambiar8f88b302017-09-07 04:00:17 -0700407 /* track this channel belongs to which VSI */
408 struct i40e_vsi *parent_vsi;
409};
410
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000411/* struct that defines the Ethernet device */
412struct i40e_pf {
413 struct pci_dev *pdev;
414 struct i40e_hw hw;
Jacob Keller0da36b92017-04-19 09:25:55 -0400415 DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000416 struct msix_entry *msix_entries;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000417 bool fc_autoneg_status;
418
419 u16 eeprom_version;
Jeff Kirsherb40c82e2015-02-27 09:18:34 +0000420 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000421 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
422 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
Rami Rosenec2f25d2017-08-19 00:20:31 +0300423 u16 num_req_vfs; /* num VFs requested for this PF */
Jeff Kirsherb40c82e2015-02-27 09:18:34 +0000424 u16 num_vf_qps; /* num queue pairs per VF */
Jeff Kirsherb40c82e2015-02-27 09:18:34 +0000425 u16 num_lan_qps; /* num lan queues this PF has set up */
426 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
Tushar Davea70e4072016-05-16 12:40:53 -0700427 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */
Anjali Singhai Jaine3219ce2016-01-20 13:40:01 -0600428 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
429 int iwarp_base_vector;
Anjali Singhai Jainf8ff1462013-11-26 10:49:19 +0000430 int queues_left; /* queues left unclaimed */
Helin Zhangacd65442015-10-26 19:44:28 -0400431 u16 alloc_rss_size; /* allocated RSS queues */
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000432 u16 rss_size_max; /* HW defined max RSS queues */
433 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
Mitch Williams505682c2014-05-20 08:01:37 +0000434 u16 num_alloc_vsi; /* num VSIs this driver supports */
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000435 u8 atr_sample_rate;
Shannon Nelson8e2773a2013-11-28 06:39:22 +0000436 bool wol_en;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000437
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000438 struct hlist_head fdir_filter_list;
439 u16 fdir_pf_active_filters;
Anjali Singhai Jain1e1be8f2014-07-10 08:03:26 +0000440 unsigned long fd_flush_timestamp;
Anjali Singhai Jain60793f4a2014-07-09 07:46:23 +0000441 u32 fd_flush_cnt;
Anjali Singhai Jain1e1be8f2014-07-10 08:03:26 +0000442 u32 fd_add_err;
443 u32 fd_atr_cnt;
Jacob Keller097dbf52017-02-06 14:38:46 -0800444
445 /* Book-keeping of side-band filter count per flow-type.
446 * This is used to detect and handle input set changes for
447 * respective flow-type.
448 */
449 u16 fd_tcp4_filter_cnt;
450 u16 fd_udp4_filter_cnt;
Jacob Kellerf223c872017-02-06 14:38:51 -0800451 u16 fd_sctp4_filter_cnt;
Jacob Keller097dbf52017-02-06 14:38:46 -0800452 u16 fd_ip4_filter_cnt;
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000453
Jacob Keller0e588de2017-02-06 14:38:50 -0800454 /* Flexible filter table values that need to be programmed into
455 * hardware, which expects L3 and L4 to be programmed separately. We
456 * need to ensure that the values are in ascended order and don't have
457 * duplicates, so we track each L3 and L4 values in separate lists.
458 */
459 struct list_head l3_flex_pit_list;
460 struct list_head l4_flex_pit_list;
461
Singhai, Anjali6a899022015-12-14 12:21:18 -0800462 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
463 u16 pending_udp_bitmap;
Jeff Kirshera1c9a9d2013-12-28 07:32:18 +0000464
Amritha Nambiaraaf66502017-10-27 02:35:56 -0700465 struct hlist_head cloud_filter_list;
466 u16 num_cloud_filters;
467
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000468 enum i40e_interrupt_policy int_policy;
469 u16 rx_itr_default;
470 u16 tx_itr_default;
Jesse Brandeburg71e61632015-02-27 09:15:22 +0000471 u32 msg_enable;
Carolyn Wybornyb294ac72014-12-11 07:06:39 +0000472 char int_name[I40E_INT_NAME_STR_LEN];
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000473 u16 adminq_work_limit; /* num of admin receive queue desc to process */
Shannon Nelson21536712014-10-25 10:35:25 +0000474 unsigned long service_timer_period;
475 unsigned long service_timer_previous;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000476 struct timer_list service_timer;
477 struct work_struct service_task;
478
Jacob Kellerb74f5712017-09-01 13:54:07 -0700479 u32 hw_features;
480#define I40E_HW_RSS_AQ_CAPABLE BIT(0)
481#define I40E_HW_128_QP_RSS_CAPABLE BIT(1)
482#define I40E_HW_ATR_EVICT_CAPABLE BIT(2)
483#define I40E_HW_WB_ON_ITR_CAPABLE BIT(3)
484#define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4)
485#define I40E_HW_NO_PCI_LINK_CHECK BIT(5)
486#define I40E_HW_100M_SGMII_CAPABLE BIT(6)
487#define I40E_HW_NO_DCB_SUPPORT BIT(7)
488#define I40E_HW_USE_SET_LLDP_MIB BIT(8)
489#define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9)
490#define I40E_HW_PTP_L4_CAPABLE BIT(10)
491#define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11)
492#define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE BIT(12)
493#define I40E_HW_HAVE_CRT_RETIMER BIT(13)
494#define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14)
495#define I40E_HW_PHY_CONTROLS_LEDS BIT(15)
496#define I40E_HW_STOP_FW_LLDP BIT(16)
497#define I40E_HW_PORT_ID_VALID BIT(17)
498#define I40E_HW_RESTART_AUTONEG BIT(18)
Jacob Kellerd36e41d2017-06-23 04:24:46 -0400499
Jacob Keller8f769dd12018-03-16 01:26:37 -0700500 u32 flags;
501#define I40E_FLAG_RX_CSUM_ENABLED BIT(0)
502#define I40E_FLAG_MSI_ENABLED BIT(1)
503#define I40E_FLAG_MSIX_ENABLED BIT(2)
504#define I40E_FLAG_RSS_ENABLED BIT(3)
505#define I40E_FLAG_VMDQ_ENABLED BIT(4)
506#define I40E_FLAG_SRIOV_ENABLED BIT(5)
507#define I40E_FLAG_DCB_CAPABLE BIT(6)
508#define I40E_FLAG_DCB_ENABLED BIT(7)
509#define I40E_FLAG_FD_SB_ENABLED BIT(8)
510#define I40E_FLAG_FD_ATR_ENABLED BIT(9)
511#define I40E_FLAG_MFP_ENABLED BIT(10)
512#define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11)
513#define I40E_FLAG_VEB_MODE_ENABLED BIT(12)
514#define I40E_FLAG_VEB_STATS_ENABLED BIT(13)
515#define I40E_FLAG_LINK_POLLING_ENABLED BIT(14)
516#define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15)
517#define I40E_FLAG_LEGACY_RX BIT(16)
518#define I40E_FLAG_PTP BIT(17)
519#define I40E_FLAG_IWARP_ENABLED BIT(18)
520#define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19)
521#define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20)
522#define I40E_FLAG_TC_MQPRIO BIT(21)
523#define I40E_FLAG_FD_SB_INACTIVE BIT(22)
524#define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23)
525#define I40E_FLAG_DISABLE_FW_LLDP BIT(24)
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000526
Mitch Williams0ef2d5a2017-01-24 10:24:00 -0800527 struct i40e_client_instance *cinst;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000528 bool stat_offsets_loaded;
529 struct i40e_hw_port_stats stats;
530 struct i40e_hw_port_stats stats_offsets;
531 u32 tx_timeout_count;
532 u32 tx_timeout_recovery_level;
533 unsigned long tx_timeout_last_recovery;
Anjali Singhai Jain810b3ae2014-07-10 07:58:25 +0000534 u32 tx_sluggish_count;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000535 u32 hw_csum_rx_error;
536 u32 led_status;
537 u16 corer_count; /* Core reset count */
538 u16 globr_count; /* Global reset count */
539 u16 empr_count; /* EMP reset count */
540 u16 pfr_count; /* PF reset count */
Shannon Nelsoncd92e722013-11-16 10:00:44 +0000541 u16 sw_int_count; /* SW interrupt count */
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000542
543 struct mutex switch_mutex;
544 u16 lan_vsi; /* our default LAN VSI */
545 u16 lan_veb; /* initial relay, if exists */
Jeff Kirsherc57c9952016-08-19 21:47:41 -0700546#define I40E_NO_VEB 0xffff
547#define I40E_NO_VSI 0xffff
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000548 u16 next_vsi; /* Next unallocated VSI - 0-based! */
549 struct i40e_vsi **vsi;
550 struct i40e_veb *veb[I40E_MAX_VEB];
551
552 struct i40e_lump_tracking *qp_pile;
553 struct i40e_lump_tracking *irq_pile;
554
555 /* switch config info */
556 u16 pf_seid;
557 u16 main_vsi_seid;
558 u16 mac_seid;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000559 struct kobject *switch_kobj;
560#ifdef CONFIG_DEBUG_FS
561 struct dentry *i40e_dbg_pf;
562#endif /* CONFIG_DEBUG_FS */
Anjali Singhai Jain92faef82015-07-28 13:02:00 -0400563 bool cur_promisc;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000564
Anjali Singhai Jain93cd7652013-11-20 10:03:01 +0000565 u16 instance; /* A unique number per i40e_pf instance in the system */
566
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000567 /* sr-iov config info */
568 struct i40e_vf *vf;
569 int num_alloc_vfs; /* actual number of VFs allocated */
570 u32 vf_aq_requests;
Mitch Williams1d0a4ad2015-12-23 12:05:48 -0800571 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000572
573 /* DCBx/DCBNL capability for PF that indicates
574 * whether DCBx is managed by firmware or host
575 * based agent (LLDPAD). Also, indicates what
576 * flavor of DCBx protocol (IEEE/CEE) is supported
577 * by the device. For now we're supporting IEEE
578 * mode only.
579 */
580 u16 dcbx_cap;
581
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000582 struct i40e_filter_control_settings filter_settings;
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000583
584 struct ptp_clock *ptp_clock;
585 struct ptp_clock_info ptp_caps;
586 struct sk_buff *ptp_tx_skb;
Jacob Keller0bc07062017-05-03 10:29:02 -0700587 unsigned long ptp_tx_start;
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000588 struct hwtstamp_config tstamp_config;
Jacob Keller19551262016-10-05 09:30:43 -0700589 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
Jacob Keller830e0dd2018-04-20 01:41:38 -0700590 u32 ptp_adj_mult;
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000591 u32 tx_hwtstamp_timeouts;
Jacob Keller2955fac2017-05-03 10:28:58 -0700592 u32 tx_hwtstamp_skipped;
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000593 u32 rx_hwtstamp_cleared;
Jacob Keller12490502016-10-05 09:30:44 -0700594 u32 latch_event_flags;
595 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
596 unsigned long latch_events[4];
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000597 bool ptp_tx;
598 bool ptp_rx;
Helin Zhangacd65442015-10-26 19:44:28 -0400599 u16 rss_table_size; /* HW RSS table size */
Shannon Nelson4fc8c672017-06-07 05:43:08 -0400600 u32 max_bw;
601 u32 min_bw;
Shannon Nelson2ac8b672015-07-23 16:54:37 -0400602
603 u32 ioremap_len;
Carolyn Wyborny3487b6c2015-08-27 11:42:38 -0400604 u32 fd_inv;
Carolyn Wyborny31b606d2016-02-17 16:12:12 -0800605 u16 phy_led_val;
Amritha Nambiar8f88b302017-09-07 04:00:17 -0700606
607 u16 override_q_count;
Amritha Nambiar2f4b4112017-10-27 02:36:01 -0700608 u16 last_sw_conf_flags;
609 u16 last_sw_conf_valid_flags;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000610};
611
Jacob Keller278e7d02016-10-05 09:30:37 -0700612/**
613 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
614 * @macaddr: the MAC Address as the base key
615 *
616 * Simply copies the address and returns it as a u64 for hashing
617 **/
618static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
619{
620 u64 key = 0;
621
622 ether_addr_copy((u8 *)&key, macaddr);
623 return key;
624}
625
Mitch Williamsc3c7ea22016-06-20 09:10:38 -0700626enum i40e_filter_state {
627 I40E_FILTER_INVALID = 0, /* Invalid state */
628 I40E_FILTER_NEW, /* New, not sent to FW yet */
629 I40E_FILTER_ACTIVE, /* Added to switch by FW */
630 I40E_FILTER_FAILED, /* Rejected by FW */
631 I40E_FILTER_REMOVE, /* To be removed */
632/* There is no 'removed' state; the filter struct is freed */
633};
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000634struct i40e_mac_filter {
Jacob Keller278e7d02016-10-05 09:30:37 -0700635 struct hlist_node hlist;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000636 u8 macaddr[ETH_ALEN];
637#define I40E_VLAN_ANY -1
638 s16 vlan;
Mitch Williamsc3c7ea22016-06-20 09:10:38 -0700639 enum i40e_filter_state state;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000640};
641
Jacob Keller671889e2016-12-02 12:33:00 -0800642/* Wrapper structure to keep track of filters while we are preparing to send
643 * firmware commands. We cannot send firmware commands while holding a
644 * spinlock, since it might sleep. To avoid this, we wrap the added filters in
645 * a separate structure, which will track the state change and update the real
646 * filter while under lock. We can't simply hold the filters in a separate
647 * list, as this opens a window for a race condition when adding new MAC
648 * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
649 */
650struct i40e_new_mac_filter {
651 struct hlist_node hlist;
652 struct i40e_mac_filter *f;
653
654 /* Track future changes to state separately */
655 enum i40e_filter_state state;
656};
657
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000658struct i40e_veb {
659 struct i40e_pf *pf;
660 u16 idx;
Jeff Kirsherc57c9952016-08-19 21:47:41 -0700661 u16 veb_idx; /* index of VEB parent */
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000662 u16 seid;
663 u16 uplink_seid;
Jeff Kirsherc57c9952016-08-19 21:47:41 -0700664 u16 stats_idx; /* index of VEB parent */
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000665 u8 enabled_tc;
Neerav Parikh51616012015-02-06 08:52:14 +0000666 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000667 u16 flags;
668 u16 bw_limit;
669 u8 bw_max_quanta;
670 bool is_abs_credits;
671 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
672 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
673 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
674 struct kobject *kobj;
675 bool stat_offsets_loaded;
676 struct i40e_eth_stats stats;
677 struct i40e_eth_stats stats_offsets;
Neerav Parikhfe860af2015-07-10 19:36:02 -0400678 struct i40e_veb_tc_stats tc_stats;
679 struct i40e_veb_tc_stats tc_stats_offsets;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000680};
681
682/* struct that defines a VSI, associated with a dev */
683struct i40e_vsi {
684 struct net_device *netdev;
685 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
686 bool netdev_registered;
687 bool stat_offsets_loaded;
688
689 u32 current_netdev_flags;
Jacob Keller0da36b92017-04-19 09:25:55 -0400690 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
Jesse Brandeburg41a1d042015-06-04 16:24:02 -0400691#define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
692#define I40E_VSI_FLAG_VEB_OWNER BIT(1)
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000693 unsigned long flags;
694
Jacob Keller278e7d02016-10-05 09:30:37 -0700695 /* Per VSI lock to protect elements/hash (MAC filter) */
696 spinlock_t mac_filter_hash_lock;
697 /* Fixed size hash table with 2^8 buckets for MAC filters */
698 DECLARE_HASHTABLE(mac_filter_hash, 8);
Jacob Kellercbebb852016-10-05 09:30:40 -0700699 bool has_vlan_filter;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000700
701 /* VSI stats */
702 struct rtnl_link_stats64 net_stats;
703 struct rtnl_link_stats64 net_stats_offsets;
704 struct i40e_eth_stats eth_stats;
705 struct i40e_eth_stats eth_stats_offsets;
706 u32 tx_restart;
707 u32 tx_busy;
Anjali Singhai Jain2fc3d712015-08-27 11:42:29 -0400708 u64 tx_linearize;
Anjali Singhai Jain164c9f52015-10-21 19:47:08 -0400709 u64 tx_force_wb;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000710 u32 rx_buf_failed;
711 u32 rx_page_failed;
712
Alexander Duyck9f65e152013-09-28 06:00:58 +0000713 /* These are containers of ring pointers, allocated at run-time */
714 struct i40e_ring **rx_rings;
715 struct i40e_ring **tx_rings;
Björn Töpel74608d12017-05-24 07:55:35 +0200716 struct i40e_ring **xdp_rings; /* XDP Tx rings */
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000717
Mitch Williamsc3c7ea22016-06-20 09:10:38 -0700718 u32 active_filters;
719 u32 promisc_threshold;
720
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000721 u16 work_limit;
Jeff Kirsherc57c9952016-08-19 21:47:41 -0700722 u16 int_rate_limit; /* value in usecs */
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000723
Jeff Kirsherc57c9952016-08-19 21:47:41 -0700724 u16 rss_table_size; /* HW RSS table size */
725 u16 rss_size; /* Allocated RSS queues */
726 u8 *rss_hkey_user; /* User configured hash keys */
727 u8 *rss_lut_user; /* User configured lookup table entries */
728
Anjali Singhai Jain5db4cb52015-02-24 06:58:49 +0000729
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000730 u16 max_frame;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000731 u16 rx_buf_len;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000732
Björn Töpel0c8493d2017-05-24 07:55:34 +0200733 struct bpf_prog *xdp_prog;
734
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000735 /* List of q_vectors allocated to this VSI */
Alexander Duyck493fb302013-09-28 07:01:44 +0000736 struct i40e_q_vector **q_vectors;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000737 int num_q_vectors;
738 int base_vector;
Shannon Nelson63741842014-04-23 04:50:16 +0000739 bool irqs_ready;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000740
Jeff Kirsherc57c9952016-08-19 21:47:41 -0700741 u16 seid; /* HW index of this VSI (absolute index) */
742 u16 id; /* VSI number */
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000743 u16 uplink_seid;
744
Jeff Kirsherc57c9952016-08-19 21:47:41 -0700745 u16 base_queue; /* vsi's first queue in hw array */
746 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
747 u16 req_queue_pairs; /* User requested queue pairs */
748 u16 num_queue_pairs; /* Used tx and rx pairs */
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000749 u16 num_desc;
750 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
Jesse Brandeburga1b5a242016-04-13 03:08:29 -0700751 s16 vf_id; /* Virtual function ID for SRIOV VSIs */
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000752
Amritha Nambiara9ce82f2017-09-07 04:00:22 -0700753 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000754 struct i40e_tc_configuration tc_config;
755 struct i40e_aqc_vsi_properties_data info;
756
757 /* VSI BW limit (absolute across all TCs) */
758 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
759 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
760
761 /* Relative TC credits across VSIs */
762 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
763 /* TC BW limit credits within VSI */
764 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
765 /* TC BW limit max quanta within VSI */
766 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
767
Jeff Kirsherc57c9952016-08-19 21:47:41 -0700768 struct i40e_pf *back; /* Backreference to associated PF */
769 u16 idx; /* index in pf->vsi[] */
770 u16 veb_idx; /* index of VEB parent */
771 struct kobject *kobj; /* sysfs object */
772 bool current_isup; /* Sync 'link up' logging */
Filip Sadowski7ec9ba12016-11-08 13:05:13 -0800773 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000774
Amritha Nambiar8f88b302017-09-07 04:00:17 -0700775 /* channel specific fields */
776 u16 cnt_q_avail; /* num of queues available for channel usage */
777 u16 orig_rss_size;
778 u16 current_rss_size;
Amritha Nambiara9ce82f2017-09-07 04:00:22 -0700779 bool reconfig_rss;
Amritha Nambiar8f88b302017-09-07 04:00:17 -0700780
781 u16 next_base_queue; /* next queue to be used for channel setup */
782
783 struct list_head ch_list;
Amritha Nambiaraa5cb02a2017-10-27 02:35:40 -0700784 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];
Amritha Nambiar8f88b302017-09-07 04:00:17 -0700785
Anjali Singhai Jaine3219ce2016-01-20 13:40:01 -0600786 void *priv; /* client driver data reference. */
787
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000788 /* VSI specific handlers */
789 irqreturn_t (*irq_handler)(int irq, void *data);
Björn Töpel0a714182018-08-28 14:44:32 +0200790
791 /* AF_XDP zero-copy */
792 struct xdp_umem **xsk_umems;
793 u16 num_xsk_umems_used;
794 u16 num_xsk_umems;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000795} ____cacheline_internodealigned_in_smp;
796
797struct i40e_netdev_priv {
798 struct i40e_vsi *vsi;
799};
800
801/* struct that defines an interrupt vector */
802struct i40e_q_vector {
803 struct i40e_vsi *vsi;
804
805 u16 v_idx; /* index in the vsi->q_vector array. */
806 u16 reg_idx; /* register index of the interrupt */
807
808 struct napi_struct napi;
809
810 struct i40e_ring_container rx;
811 struct i40e_ring_container tx;
812
Alexander Duycka0073a42017-12-29 08:52:19 -0500813 u8 itr_countdown; /* when 0 should adjust adaptive ITR */
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000814 u8 num_ringpairs; /* total number of ring pairs in vector */
815
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000816 cpumask_t affinity_mask;
Alan Brady96db7762016-09-14 16:24:38 -0700817 struct irq_affinity_notify affinity_notify;
818
Alexander Duyck493fb302013-09-28 07:01:44 +0000819 struct rcu_head rcu; /* to avoid race with update stats on free */
Carolyn Wybornyb294ac72014-12-11 07:06:39 +0000820 char name[I40E_INT_NAME_STR_LEN];
Anjali Singhai Jain8e0764b2015-06-05 12:20:30 -0400821 bool arm_wb_state;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000822} ____cacheline_internodealigned_in_smp;
823
824/* lan device */
825struct i40e_device {
826 struct list_head list;
827 struct i40e_pf *pf;
828};
829
830/**
Shannon Nelson6dec1012015-09-28 14:12:30 -0400831 * i40e_nvm_version_str - format the NVM version strings
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000832 * @hw: ptr to the hardware info
833 **/
Shannon Nelson6dec1012015-09-28 14:12:30 -0400834static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000835{
836 static char buf[32];
Carolyn Wyborny2efaad82015-10-01 14:37:39 -0400837 u32 full_ver;
Carolyn Wyborny2efaad82015-10-01 14:37:39 -0400838
839 full_ver = hw->nvm.oem_ver;
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000840
Filip Sadowski5bbb2e22017-06-07 05:43:09 -0400841 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) {
842 u8 gen, snap;
843 u16 release;
844
845 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT);
846 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >>
847 I40E_OEM_SNAP_SHIFT);
848 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK);
849
850 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release);
851 } else {
852 u8 ver, patch;
853 u16 build;
854
855 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
856 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
857 I40E_OEM_VER_BUILD_MASK);
858 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
859
860 snprintf(buf, sizeof(buf),
861 "%x.%02x 0x%x %d.%d.%d",
862 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
863 I40E_NVM_VERSION_HI_SHIFT,
864 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
865 I40E_NVM_VERSION_LO_SHIFT,
866 hw->nvm.eetrack, ver, build, patch);
867 }
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000868
869 return buf;
870}
871
872/**
873 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
874 * @netdev: the corresponding netdev
875 *
876 * Return the PF struct for the given netdev
877 **/
878static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
879{
880 struct i40e_netdev_priv *np = netdev_priv(netdev);
881 struct i40e_vsi *vsi = np->vsi;
882
883 return vsi->back;
884}
885
886static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
887 irqreturn_t (*irq_handler)(int, void *))
888{
889 vsi->irq_handler = irq_handler;
890}
891
892/**
Anjali Singhai Jain082def12014-04-09 05:59:00 +0000893 * i40e_get_fd_cnt_all - get the total FD filter space available
Jeff Kirsherb40c82e2015-02-27 09:18:34 +0000894 * @pf: pointer to the PF struct
Anjali Singhai Jain082def12014-04-09 05:59:00 +0000895 **/
896static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
897{
898 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
899}
900
Jacob Keller36777d9f2017-03-07 15:05:23 -0800901/**
902 * i40e_read_fd_input_set - reads value of flow director input set register
903 * @pf: pointer to the PF struct
904 * @addr: register addr
905 *
906 * This function reads value of flow director input set register
907 * specified by 'addr' (which is specific to flow-type)
908 **/
909static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
910{
911 u64 val;
912
913 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
914 val <<= 32;
915 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
916
917 return val;
918}
919
Jacob Keller3bcee1e2017-02-06 14:38:46 -0800920/**
921 * i40e_write_fd_input_set - writes value into flow director input set register
922 * @pf: pointer to the PF struct
923 * @addr: register addr
924 * @val: value to be written
925 *
926 * This function writes specified value to the register specified by 'addr'.
927 * This register is input set register based on flow-type.
928 **/
929static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
930 u16 addr, u64 val)
931{
932 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
933 (u32)(val >> 32));
934 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
935 (u32)(val & 0xFFFFFFFFULL));
936}
937
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000938/* needed by i40e_ethtool.c */
939int i40e_up(struct i40e_vsi *vsi);
940void i40e_down(struct i40e_vsi *vsi);
941extern const char i40e_driver_name[];
942extern const char i40e_driver_version_str[];
Anjali Singhai Jain23326182013-11-26 10:49:22 +0000943void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
Maciej Sosin373149f2017-04-05 07:50:55 -0400944void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
Helin Zhang043dd652015-10-21 19:56:23 -0400945int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
946int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
Alan Bradyf1582352016-08-24 11:33:46 -0700947void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
948 u16 rss_table_size, u16 rss_size);
Anjali Singhai Jainfdf0e0b2015-03-31 00:45:05 -0700949struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
Alexander Duyck4b816442016-10-11 15:26:53 -0700950/**
951 * i40e_find_vsi_by_type - Find and return Flow Director VSI
952 * @pf: PF to search for VSI
953 * @type: Value indicating type of VSI we are looking for
954 **/
955static inline struct i40e_vsi *
956i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
957{
958 int i;
959
960 for (i = 0; i < pf->num_alloc_vsi; i++) {
961 struct i40e_vsi *vsi = pf->vsi[i];
962
963 if (vsi && vsi->type == type)
964 return vsi;
965 }
966
967 return NULL;
968}
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000969void i40e_update_stats(struct i40e_vsi *vsi);
970void i40e_update_eth_stats(struct i40e_vsi *vsi);
971struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
972int i40e_fetch_switch_configuration(struct i40e_pf *pf,
973 bool printconfig);
974
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000975int i40e_add_del_fdir(struct i40e_vsi *vsi,
976 struct i40e_fdir_filter *input, bool add);
Anjali Singhai Jain55a5e602014-02-12 06:33:25 +0000977void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
Anjali Singhai Jain04294e32015-02-27 09:15:28 +0000978u32 i40e_get_current_fd_count(struct i40e_pf *pf);
979u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
980u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
981u32 i40e_get_global_fd_count(struct i40e_pf *pf);
Anjali Singhai Jain7c3c2882014-02-14 02:14:38 +0000982bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000983void i40e_set_ethtool_ops(struct net_device *netdev);
984struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
Jacob Keller6622f5c2016-10-05 09:30:32 -0700985 const u8 *macaddr, s16 vlan);
Jacob Keller148141b2016-11-11 12:39:36 -0800986void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
Jacob Keller6622f5c2016-10-05 09:30:32 -0700987void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
Jesse Brandeburg17652c62015-11-05 17:01:02 -0800988int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +0000989struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
990 u16 uplink, u32 param1);
991int i40e_vsi_release(struct i40e_vsi *vsi);
Anjali Singhai Jaine3219ce2016-01-20 13:40:01 -0600992void i40e_service_event_schedule(struct i40e_pf *pf);
993void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
994 u8 *msg, u16 len);
995
Harshitha Ramamurthyd0fda042018-04-20 01:41:39 -0700996int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp,
997 bool enable);
998int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable);
Filip Sadowski3aa7b742016-10-11 15:26:58 -0700999int i40e_vsi_start_rings(struct i40e_vsi *vsi);
1000void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
Jacob Kellere4b433f2017-04-13 04:45:52 -04001001void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi);
1002int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
Anjali Singhai Jainf8ff1462013-11-26 10:49:19 +00001003int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +00001004struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
1005 u16 downlink_seid, u8 enabled_tc);
1006void i40e_veb_release(struct i40e_veb *veb);
1007
Neerav Parikh4e3b35b2014-01-17 15:36:37 -08001008int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
Jesse Brandeburg4eeb1ff2015-11-18 17:35:42 -08001009int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +00001010void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
1011void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
1012void i40e_pf_reset_stats(struct i40e_pf *pf);
1013#ifdef CONFIG_DEBUG_FS
1014void i40e_dbg_pf_init(struct i40e_pf *pf);
1015void i40e_dbg_pf_exit(struct i40e_pf *pf);
1016void i40e_dbg_init(void);
1017void i40e_dbg_exit(void);
1018#else
1019static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
1020static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
1021static inline void i40e_dbg_init(void) {}
1022static inline void i40e_dbg_exit(void) {}
1023#endif /* CONFIG_DEBUG_FS*/
Anjali Singhai Jaine3219ce2016-01-20 13:40:01 -06001024/* needed by client drivers */
1025int i40e_lan_add_device(struct i40e_pf *pf);
1026int i40e_lan_del_device(struct i40e_pf *pf);
1027void i40e_client_subtask(struct i40e_pf *pf);
1028void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
Anjali Singhai Jaine3219ce2016-01-20 13:40:01 -06001029void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
1030void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
1031void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
Shiraz Saleemddbb8d52018-03-19 09:28:03 -07001032void i40e_client_update_msix_info(struct i40e_pf *pf);
Mitch Williams0ef2d5a2017-01-24 10:24:00 -08001033int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
Jesse Brandeburg02d109b2015-08-27 11:42:34 -04001034/**
1035 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
1036 * @vsi: pointer to a vsi
1037 * @vector: enable a particular Hw Interrupt vector, without base_vector
1038 **/
1039static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
1040{
1041 struct i40e_pf *pf = vsi->back;
1042 struct i40e_hw *hw = &pf->hw;
1043 u32 val;
1044
1045 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1046 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1047 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1048 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1049 /* skip the flush */
1050}
1051
Mitch Williams2ef28cf2013-11-28 06:39:32 +00001052void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
Jacob Kellerdbadbbe2017-09-07 08:05:49 -04001053void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +00001054int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
Greg Rose96664482015-02-06 08:52:13 +00001055int i40e_open(struct net_device *netdev);
Stefan Assmann08ca3872016-02-03 09:20:47 +01001056int i40e_close(struct net_device *netdev);
Elizabeth Kappler6c167f52014-02-15 07:41:38 +00001057int i40e_vsi_open(struct i40e_vsi *vsi);
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +00001058void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
Jacob Keller9af52f62016-11-11 12:39:30 -08001059int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
Jacob Kellerf94484b2016-12-07 14:05:34 -08001060int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
Jacob Keller9af52f62016-11-11 12:39:30 -08001061void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
Jacob Kellerf94484b2016-12-07 14:05:34 -08001062void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
Jacob Kellerfeffdbe2016-11-11 12:39:35 -08001063struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1064 const u8 *macaddr);
1065int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +00001066bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
Jacob Keller6622f5c2016-10-05 09:30:32 -07001067struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +00001068void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
Neerav Parikh4e3b35b2014-01-17 15:36:37 -08001069#ifdef CONFIG_I40E_DCB
1070void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
Neerav Parikh750fcbc2015-02-24 06:58:47 +00001071 struct i40e_dcbx_config *old_cfg,
Neerav Parikh4e3b35b2014-01-17 15:36:37 -08001072 struct i40e_dcbx_config *new_cfg);
1073void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
1074void i40e_dcbnl_setup(struct i40e_vsi *vsi);
1075bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
1076 struct i40e_dcbx_config *old_cfg,
1077 struct i40e_dcbx_config *new_cfg);
1078#endif /* CONFIG_I40E_DCB */
Jacob Keller61189552017-05-03 10:29:01 -07001079void i40e_ptp_rx_hang(struct i40e_pf *pf);
Jacob Keller0bc07062017-05-03 10:29:02 -07001080void i40e_ptp_tx_hang(struct i40e_pf *pf);
Jacob Kellerbeb0dff2014-01-11 05:43:19 +00001081void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
1082void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
1083void i40e_ptp_set_increment(struct i40e_pf *pf);
1084int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1085int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1086void i40e_ptp_init(struct i40e_pf *pf);
1087void i40e_ptp_stop(struct i40e_pf *pf);
Neerav Parikh51616012015-02-06 08:52:14 +00001088int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
Shannon Nelson4fc8c672017-06-07 05:43:08 -04001089i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf);
1090i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf);
1091i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf);
Matt Jaredc156f852015-08-27 11:42:39 -04001092void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
Björn Töpel0c8493d2017-05-24 07:55:34 +02001093
1094static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1095{
1096 return !!vsi->xdp_prog;
1097}
Amritha Nambiar8f88b302017-09-07 04:00:17 -07001098
Björn Töpel0a714182018-08-28 14:44:32 +02001099static inline struct xdp_umem *i40e_xsk_umem(struct i40e_ring *ring)
1100{
1101 bool xdp_on = i40e_enabled_xdp_vsi(ring->vsi);
1102 int qid = ring->queue_index;
1103
1104 if (ring_is_xdp(ring))
1105 qid -= ring->vsi->alloc_queue_pairs;
1106
1107 if (!ring->vsi->xsk_umems || !ring->vsi->xsk_umems[qid] || !xdp_on)
1108 return NULL;
1109
1110 return ring->vsi->xsk_umems[qid];
1111}
1112
Amritha Nambiar8f88b302017-09-07 04:00:17 -07001113int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch);
Amritha Nambiar5ecae412017-09-07 04:00:27 -07001114int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate);
Avinash Dayanande284fc22018-01-23 08:51:06 -08001115int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
1116 struct i40e_cloud_filter *filter,
1117 bool add);
1118int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
1119 struct i40e_cloud_filter *filter,
1120 bool add);
Jesse Brandeburg7daa6bf2013-09-11 08:40:01 +00001121#endif /* _I40E_H_ */