| commit | 16f6ad368de92db54ee7bd07efd24bb61ef45658 | [log] [tgz] |
|---|---|---|
| author | zhou.han <zhou.han@amlogic.com> | Wed Dec 18 17:02:34 2024 +0800 |
| committer | gerrit autosubmit <gerrit.autosubmit@amlogic.com> | Wed Jan 01 22:57:36 2025 -0800 |
| tree | 45912b3cb5e9a8e5e7d99c0a3dd5b24062afb2ca | |
| parent | a94b94e4421743acc479f8dada44a1993b9fed2c [diff] |
hdmitx: Optimize the hdmitx clk source switching process [2/2] PD#SWPL-174933 Problem: hdmitx encp/pixel clk is directly configured by the pll analog path. Solution: Add flag: clk_analog_path, which is 1 by default. 1:Analog frequency division 0:Digital frequency division Verify: s7d/s7 Test: DRM-TX-78 Change-Id: I22e58995b7e073e7458531827ea9bb360402e058 Signed-off-by: zhou.han <zhou.han@amlogic.com>