clk: s6: clock tree bringup [2/2]
PD#SWPL-154653
Problem:
clock tree bringup
Solution:
added
Verify:
pxp
Change-Id: I421aad497bbd7d1bd46430bf5c708cede10c7301
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
diff --git a/arch/arm64/boot/dts/amlogic/meson-s6.dtsi b/arch/arm64/boot/dts/amlogic/meson-s6.dtsi
index 11fb0bc..066c29c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s6.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s6.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/clock/axg-audio-clkc.h>
#include <dt-bindings/clock/s6-clkc.h>
+#include <dt-bindings/clock/s6-secure-clk.h>
#include <dt-bindings/clock/g12a-aoclkc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -837,7 +838,7 @@
//clocks = <&xtal>,
// <&clkc CLKID_SYS_SAR_ADC>,
// <&clkc CLKID_SAR_ADC>,
- // <&clkc CLKID_SAR_ADC_SEL>;
+ // <&clkc CLKID_SAR_ADC_MUX>;
//clock-names = "clkin", "core", "adc_clk", "adc_sel";
interrupts = <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
@@ -849,6 +850,34 @@
};
};
+ shmem@050f8e00 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x050f8e00 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x050f8e00 0x100>;
+
+ scmi_shmem: shmem@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x100>;
+ };
+ };
+
+ firmware {
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+ arm,smc-id = <0x820000C1>;
+ shmem = <&scmi_shmem>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -863,18 +892,30 @@
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
clkc: clock-controller {
- compatible = "amlogic,s7d-clkc";
+ compatible = "amlogic,s6-clkc";
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0x49c>,
<0x0 0x8000 0x0 0x384>;
reg-names = "basic", "pll";
- clocks = <&xtal>;
- clock-names = "xtal";
+ clocks = <&xtal>,
+ <&scmi_clk CLKID_OTHERPLL_IN>,
+ <&scmi_clk CLKID_HIFI0PLL_IN>,
+ <&scmi_clk CLKID_ETH_HIFI1PLL_IN>,
+ <&scmi_clk CLKID_FIXEDPLL_IN>,
+ <&scmi_clk CLKID_GP1PLL>,
+ <&scmi_clk CLKID_GP2PLL>;
+ clock-names = "xtal",
+ "otherpll_in",
+ "hifi0pll_in",
+ "eth_hifi1pll_in",
+ "fixedpll_in",
+ "gp1pll",
+ "gp2pll";
status = "okay";
};
meson_clk_msr@48000 {
- compatible = "amlogic,meson-s7d-clk-measure";
+ compatible = "amlogic,meson-s6-clk-measure";
reg = <0x0 0x48000 0x0 0x1c>;
};
@@ -948,7 +989,7 @@
reg = <0x0 0x58000 0x0 0x24>,
<0x0 0x180 0x0 0x4>;
#pwm-cells = <3>;
- //clocks = <&clkc CLKID_PWM_A_SEL>;
+ //clocks = <&clkc CLKID_PWM_A_MUX>;
//clock-names = "clkin0";
status = "disabled";
};
@@ -958,7 +999,7 @@
reg = <0x0 0x58200 0x0 0x24>,
<0x0 0x180 0x0 0x4>;
#pwm-cells = <3>;
- //clocks = <&clkc CLKID_PWM_B_SEL>;
+ //clocks = <&clkc CLKID_PWM_B_MUX>;
//clock-names = "clkin0";
status = "disabled";
};
@@ -968,7 +1009,7 @@
reg = <0x0 0x5a000 0x0 0x24>,
<0x0 0x184 0x0 0x4>;
#pwm-cells = <3>;
- //clocks = <&clkc CLKID_PWM_C_SEL>;
+ //clocks = <&clkc CLKID_PWM_C_MUX>;
//clock-names = "clkin0";
status = "disabled";
};
@@ -978,7 +1019,7 @@
reg = <0x0 0x5a000 0x0 0x24>,
<0x0 0x184 0x0 0x4>;
#pwm-cells = <3>;
- //clocks = <&clkc CLKID_PWM_D_SEL>;
+ //clocks = <&clkc CLKID_PWM_D_MUX>;
//clock-names = "clkin0";
status = "disabled";
};
@@ -988,7 +1029,7 @@
reg = <0x0 0x5c000 0x0 0x24>,
<0x0 0x188 0x0 0x4>;
#pwm-cells = <3>;
- //clocks = <&clkc CLKID_PWM_E_SEL>;
+ //clocks = <&clkc CLKID_PWM_E_MUX>;
//clock-names = "clkin0";
status = "disabled";
};
@@ -998,7 +1039,7 @@
reg = <0x0 0x5c000 0x0 0x24>,
<0x0 0x188 0x0 0x4>;
#pwm-cells = <3>;
- //clocks = <&clkc CLKID_PWM_F_SEL>;
+ //clocks = <&clkc CLKID_PWM_F_MUX>;
//clock-names = "clkin0";
status = "disabled";
};
@@ -1008,7 +1049,7 @@
reg = <0x0 0x5e000 0x0 0x24>,
<0x0 0x18c 0x0 0x4>;
#pwm-cells = <3>;
- //clocks = <&clkc CLKID_PWM_G_SEL>;
+ //clocks = <&clkc CLKID_PWM_G_MUX>;
//clock-names = "clkin0";
status = "disabled";
};
@@ -1018,7 +1059,7 @@
reg = <0x0 0x5e000 0x0 0x24>,
<0x0 0x18c 0x0 0x4>;
#pwm-cells = <3>;
- //clocks = <&clkc CLKID_PWM_H_SEL>;
+ //clocks = <&clkc CLKID_PWM_H_MUX>;
//clock-names = "clkin0";
status = "disabled";
};
@@ -1028,7 +1069,7 @@
reg = <0x0 0x60000 0x0 0x24>,
<0x0 0x190 0x0 0x4>;
#pwm-cells = <3>;
- //clocks = <&clkc CLKID_PWM_I_SEL>;
+ //clocks = <&clkc CLKID_PWM_I_MUX>;
//clock-names = "clkin0";
status = "disabled";
};
@@ -1038,7 +1079,7 @@
reg = <0x0 0x60000 0x0 0x24>,
<0x0 0x190 0x0 0x4>;
#pwm-cells = <3>;
- //clocks = <&clkc CLKID_PWM_J_SEL>;
+ //clocks = <&clkc CLKID_PWM_J_MUX>;
//clock-names = "clkin0";
status = "disabled";
};
@@ -1380,7 +1421,7 @@
interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&clkc CLKID_SYS_SD_EMMC_C>,
- <&clkc CLKID_SD_EMMC_C_SEL>,
+ <&clkc CLKID_SD_EMMC_C_MUX>,
<&clkc CLKID_SD_EMMC_C>,
<&xtal>,
<&clkc CLKID_FCLK_DIV2>,
@@ -1406,7 +1447,7 @@
interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&clkc CLKID_SYS_SD_EMMC_B>,
- <&clkc CLKID_SD_EMMC_B_SEL>,
+ <&clkc CLKID_SD_EMMC_B_MUX>,
<&clkc CLKID_SD_EMMC_B>,
<&xtal>,
<&clkc CLKID_FCLK_DIV2>;
@@ -1427,7 +1468,7 @@
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&clkc CLKID_SYS_SD_EMMC_A>,
- <&clkc CLKID_SD_EMMC_A_SEL>,
+ <&clkc CLKID_SD_EMMC_A_MUX>,
<&clkc CLKID_SD_EMMC_A>,
<&xtal>,
<&clkc CLKID_FCLK_DIV2>;
@@ -2970,7 +3011,7 @@
* free mux to safely change frequency while running.
*/
//assigned-clocks = <&clkc CLKID_GP1_PLL>,
- // <&clkc CLKID_MALI_0_SEL>,
+ // <&clkc CLKID_MALI_0_MUX>,
// <&clkc CLKID_MALI_0>,
// <&clkc CLKID_MALI>; /* Glitch free mux */
//assigned-clock-parents = <0>, /* Do Nothing */
diff --git a/arch/arm64/configs/amlogic_gki.fragment b/arch/arm64/configs/amlogic_gki.fragment
index 3e156a4..6ec9d79 100644
--- a/arch/arm64/configs/amlogic_gki.fragment
+++ b/arch/arm64/configs/amlogic_gki.fragment
@@ -70,6 +70,7 @@
CONFIG_AMLOGIC_COMMON_CLK_MESON_VID_PLL_DIV=y
CONFIG_AMLOGIC_MESON_CLK_MEASURE=y
CONFIG_AMLOGIC_CLK_DEBUG=y
+CONFIG_ARM_SCMI_PROTOCOL=y
# amlogic-clk-soc-s4.ko
CONFIG_AMLOGIC_COMMON_CLK_S4=m
@@ -98,6 +99,9 @@
# amlogic-clk-soc-s7.ko
CONFIG_AMLOGIC_COMMON_CLK_S7=m
+# amlogic-clk-soc-s6.ko
+CONFIG_AMLOGIC_COMMON_CLK_S6=m
+
# amlogic-aoclk-soc-ao-t5w.ko
CONFIG_AMLOGIC_COMMON_AO_CLK_T5W=m
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 2bf6a16..a1ea661 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -333,4 +333,15 @@
help
Support for the clock controller on Amlogic S7D
devices, aka ao s7d. Say Y if you want peripherals to work.
+
+config AMLOGIC_COMMON_CLK_S6
+ tristate "Meson S6 clock controller"
+ depends on AMLOGIC_COMMON_CLK_MESON_REGMAP
+ depends on AMLOGIC_COMMON_CLK_MESON_DUALDIV
+ depends on AMLOGIC_COMMON_CLK_MESON_PLL
+ depends on MFD_SYSCON
+ help
+ Support for the clock controller on Amlogic S6
+ devices, aka S6. Say Y if you want peripherals to work.
+
endmenu
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 927d829..e474381 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -201,3 +201,10 @@
PR_FMT_DEFINE_S7D="-Dpr_fmt(fmt)= \"[$(PR_FMT_S7D)]: \" fmt"
CFLAGS_s7d.o += $(PR_FMT_DEFINE_S7D)
+S6_MODULE_NAME = amlogic-clk-soc-s6
+obj-$(CONFIG_AMLOGIC_COMMON_CLK_S6) += $(S6_MODULE_NAME).o
+$(S6_MODULE_NAME)-y += s6.o
+PR_FMT_S6 = $(subst amlogic-,,$(S6_MODULE_NAME))
+PR_FMT_DEFINE_S6="-Dpr_fmt(fmt)= \"[$(PR_FMT_S6)]: \" fmt"
+CFLAGS_S6.o += $(PR_FMT_DEFINE_S6)
+
diff --git a/drivers/clk/meson/meson-clk-measure.c b/drivers/clk/meson/meson-clk-measure.c
index 4e6b8f3..0b12a8c 100644
--- a/drivers/clk/meson/meson-clk-measure.c
+++ b/drivers/clk/meson/meson-clk-measure.c
@@ -3488,6 +3488,117 @@
CLK_MSR_ID(191, "osc_ring_clk[11](ddr[0] 9t_14_lvt)"),
CLK_MSR_ID(192, "osc_ring_clk[12](top[0] 16_rvt)"),
};
+
+static struct meson_msr_id clk_msr_s6[] __initdata = {
+ CLK_MSR_ID(0, "cts_sys_clk"),
+ CLK_MSR_ID(1, "cts_axi_clk"),
+ CLK_MSR_ID(2, "cts_rtc_clk"),
+ CLK_MSR_ID(3, "cts_dspa_clk"),
+ CLK_MSR_ID(4, "cts_mali_stack_clk"),
+ CLK_MSR_ID(5, "cts_mali_clk"),
+ CLK_MSR_ID(6, "sys_cpu_clk_div16"),
+ CLK_MSR_ID(7, "cts_mali_ACLKM"),
+ CLK_MSR_ID(8, "cts_cecb_clk"),
+ CLK_MSR_ID(10, "fclk_div5"),
+ CLK_MSR_ID(11, "p21_usb2_ckout"),
+ CLK_MSR_ID(12, "p20_usb2_ckout"),
+ CLK_MSR_ID(13, "eth_mpll_test"),
+ CLK_MSR_ID(15, "mpll_clk_50m"),
+ CLK_MSR_ID(18, "gp1_pll_clk"),
+ CLK_MSR_ID(19, "hifi0_pll_clk"),
+ CLK_MSR_ID(20, "gp0_pll_clk"),
+ CLK_MSR_ID(21, "hifi1_pll_clk"),
+ CLK_MSR_ID(22, "eth_mppll_50m_ckout"),
+ CLK_MSR_ID(23, "sys_pll_div16"),
+ CLK_MSR_ID(24, "ddr_dpll_pt_clk"),
+ CLK_MSR_ID(25, "mod_Tsin_A_CLK_IN"),
+ CLK_MSR_ID(32, "cts_eth_clk125Mhz"),
+ CLK_MSR_ID(33, "cts_eth_clk_rmii"),
+ CLK_MSR_ID(34, "co_clkin_to_mac"),
+ CLK_MSR_ID(36, "co_rx_clk"),
+ CLK_MSR_ID(37, "co_tx_clk"),
+ CLK_MSR_ID(38, "eth_phy_rxclk"),
+ CLK_MSR_ID(39, "eth_phy_plltxclk"),
+ CLK_MSR_ID(40, "ephy_test_clk"),
+ CLK_MSR_ID(49, "hdmi_vx1_pix_clk"),
+ CLK_MSR_ID(50, "vid_pll_div_clk_out"),
+ CLK_MSR_ID(51, "cts_enci_clk"),
+ CLK_MSR_ID(52, "cts_encp_clk"),
+ CLK_MSR_ID(53, "cts_encl_clk"),
+ CLK_MSR_ID(54, "cts_vdac_clk"),
+ CLK_MSR_ID(55, "cts_cdac_clk_c"),
+ CLK_MSR_ID(57, "lcd_an_clk_ph2"),
+ CLK_MSR_ID(58, "lcd_an_clk_ph3"),
+ CLK_MSR_ID(59, "cts_hdmi_tx_pixel_clk"),
+ CLK_MSR_ID(60, "cts_vdin_meas_clk"),
+ CLK_MSR_ID(61, "cts_vpu_clk"),
+ CLK_MSR_ID(62, "cts_vpu_clkb"),
+ CLK_MSR_ID(63, "cts_vpu_clkb_tmp"),
+ CLK_MSR_ID(64, "cts_vpu_clkc"),
+ CLK_MSR_ID(65, "cts_vid_lock_clk"),
+ CLK_MSR_ID(66, "cts_vapbclk"),
+ CLK_MSR_ID(67, "cts_ge2d_clk"),
+ CLK_MSR_ID(70, "cts_dsi_meas_clk"),
+ CLK_MSR_ID(71, "cts_dsi_phy_clk"),
+ CLK_MSR_ID(72, "mipi_csi_phy0_clk"),
+ CLK_MSR_ID(73, "cts_csi2_adapt_clk"),
+ CLK_MSR_ID(74, "cts_csi2_data "),
+ CLK_MSR_ID(75, "mipi_csi_phy0_clk_out"),
+ CLK_MSR_ID(76, "hdmitx_tmds_clk"),
+ CLK_MSR_ID(77, "cts_hdmitx_sys_clk"),
+ CLK_MSR_ID(78, "cts_hdmitx_fe_clk"),
+ CLK_MSR_ID(79, "cts_rama_clk"),
+ CLK_MSR_ID(80, "cts_hdmitx_prif_clk"),
+ CLK_MSR_ID(81, "cts_hdmitx_200m_clk"),
+ CLK_MSR_ID(82, "cts_hdmitx_aud_clk"),
+ CLK_MSR_ID(84, "audio_tohdmitx_mclk"),
+ CLK_MSR_ID(85, "audio_tohdmitx_bclk"),
+ CLK_MSR_ID(86, "audio_tohdmitx_lrclk"),
+ CLK_MSR_ID(87, "audio_tohdmitx_spdif_clk"),
+ CLK_MSR_ID(88, "htx_aes_clk"),
+ CLK_MSR_ID(93, "cts_vdec_clk"),
+ CLK_MSR_ID(99, "cts_hevcf_clk"),
+ CLK_MSR_ID(106, "deskew_pll_clk_div32_out"),
+ CLK_MSR_ID(110, "cts_sc_clk"),
+ CLK_MSR_ID(111, "cts_aux_adc_clk"),
+ CLK_MSR_ID(113, "cts_sd_emmc_c_clk"),
+ CLK_MSR_ID(114, "cts_sd_emmc_b_clk"),
+ CLK_MSR_ID(115, "cts_sd_emmc_a_clk"),
+ CLK_MSR_ID(116, "gpio_msr_clk"),
+ CLK_MSR_ID(118, "cts_spicc_0_clk"),
+ CLK_MSR_ID(121, "cts_ts_clk"),
+ CLK_MSR_ID(130, "o_vad_clk"),
+ CLK_MSR_ID(132, "audio_locker_in_clk"),
+ CLK_MSR_ID(133, "audio_locker_out_clk"),
+ CLK_MSR_ID(134, "audio_tdmout_c_sclk"),
+ CLK_MSR_ID(135, "audio_tdmout_b_sclk"),
+ CLK_MSR_ID(136, "audio_tdmout_a_sclk"),
+ CLK_MSR_ID(137, "audio_tdmin_lb_sclk"),
+ CLK_MSR_ID(138, "audio_tdmin_c_sclk"),
+ CLK_MSR_ID(139, "audio_tdmin_b_sclk"),
+ CLK_MSR_ID(140, "audio_tdmin_a_sclk"),
+ CLK_MSR_ID(141, "audio_resamplea_clk"),
+ CLK_MSR_ID(142, "audio_pdm_sysclk"),
+ CLK_MSR_ID(143, "audio_spdifout_b_mst_clk"),
+ CLK_MSR_ID(144, "audio_spdifout_mst_clk"),
+ CLK_MSR_ID(145, "audio_spdifin_mst_clk"),
+ CLK_MSR_ID(147, "audio_resampleb_clk"),
+ CLK_MSR_ID(160, "pwm_j_clk"),
+ CLK_MSR_ID(161, "pwm_i_clk"),
+ CLK_MSR_ID(162, "pwm_h_clk"),
+ CLK_MSR_ID(163, "pwm_g_clk"),
+ CLK_MSR_ID(164, "pwm_f_clk"),
+ CLK_MSR_ID(165, "pwm_e_clk"),
+ CLK_MSR_ID(166, "pwm_d_clk"),
+ CLK_MSR_ID(167, "pwm_c_clk"),
+ CLK_MSR_ID(168, "pwm_b_clk"),
+ CLK_MSR_ID(169, "pwm_a_clk"),
+ CLK_MSR_ID(176, "rng_ring_clk[0]"),
+ CLK_MSR_ID(177, "rng_ring_clk[1]"),
+ CLK_MSR_ID(178, "rng_ring_clk[2]"),
+ CLK_MSR_ID(179, "rng_ring_clk[3]")
+};
+
#endif
#endif
@@ -3973,6 +4084,16 @@
.reg1_offset = 0x4,
.reg2_offset = 0x8,
};
+
+static struct meson_msr_data meson_s6_data __initdata = {
+ .msr_table = (struct meson_msr_id *)&clk_msr_s6,
+ .table_size = ARRAY_SIZE(clk_msr_s6),
+ .duty_offset = (0x6 * 4),
+ .reg0_offset = 0x0,
+ .reg1_offset = 0x4,
+ .reg2_offset = 0x8,
+};
+
#endif
#endif
@@ -4099,6 +4220,11 @@
.compatible = "amlogic,meson-s7d-clk-measure",
.data = &meson_s7d_data,
},
+ {
+ .compatible = "amlogic,meson-s6-clk-measure",
+ .data = &meson_s6_data,
+ },
+
#endif
#endif
{ /* sentinel */ }
diff --git a/drivers/clk/meson/s6.c b/drivers/clk/meson/s6.c
new file mode 100644
index 0000000..cd9bc33
--- /dev/null
+++ b/drivers/clk/meson/s6.c
@@ -0,0 +1,5840 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/clkdev.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+
+#include "clk-pll.h"
+#include "clk-regmap.h"
+#include "clk-cpu-dyndiv.h"
+#include "clk-dualdiv.h"
+#include "s6.h"
+#include <dt-bindings/clock/s6-clkc.h>
+
+static struct clk_regmap fixed_pll_vco = {
+ .data = &(struct meson_clk_pll_data) {
+ .en = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 0,
+ .width = 9,
+ },
+ .n = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 12,
+ .width = 3,
+ },
+ .frac = {
+ .reg_off = ANACTRL_FIXPLL_CTRL1,
+ .shift = 0,
+ .width = 19,
+ },
+ .od = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 20,
+ .width = 3,
+ },
+ .l = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .flags = CLK_MESON_PLL_POWER_OF_TWO | CLK_MESON_PLL_FIXED_EN0P5,
+ },
+ .hw.init = &(struct clk_init_data) {
+#ifndef CONFIG_ARM
+ .name = "fixed_pll_vco",
+#else
+ .name = "fixed_pll",
+#endif
+ .ops = &meson_clk_pll_ro_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "fixedpll_in",
+ },
+ .num_parents = 1,
+ },
+};
+
+#ifndef CONFIG_ARM
+static struct clk_regmap fixed_pll = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = ANACTRL_FIXPLL_CTRL0,
+ .shift = 20,
+ .width = 3,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "fixed_pll",
+ .ops = &clk_regmap_divider_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &fixed_pll_vco.hw,
+ },
+ .num_parents = 1,
+ },
+};
+#endif
+
+#ifdef CONFIG_ARM
+static const struct pll_params_table gp0_pll_vco_table[] = {
+ PLL_PARAMS(192, 0, 1), /* DCO = 2304M OD = 2 PLL = 1152M */
+ { /* sentinel */ }
+};
+#else
+static const struct pll_params_table gp0_pll_vco_table[] = {
+ PLL_PARAMS(192, 0), /* DCO = 2304M */
+ { /* sentinel */ }
+};
+#endif
+
+static const struct reg_sequence gp0_pll_vco_init_regs[] = {
+ { .reg = ANACTRL_GP0PLL_CTRL0, .def = 0x001100ea },
+ { .reg = ANACTRL_GP0PLL_CTRL1, .def = 0x1148cd00 },
+ { .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x1215b010 },
+ { .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x00008010 },
+ { .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x00001000 },
+ { .reg = ANACTRL_GP0PLL_CTRL0, .def = 0x101100ea, .delay_us = 20 },
+ { .reg = ANACTRL_GP0PLL_CTRL0, .def = 0x301100ea, .delay_us = 20 },
+ { .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x20008010 },
+};
+
+static struct clk_regmap gp0_pll_vco = {
+ .data = &(struct meson_clk_pll_data) {
+ .en = {
+ .reg_off = ANACTRL_GP0PLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = ANACTRL_GP0PLL_CTRL0,
+ .shift = 0,
+ .width = 9,
+ },
+ .n = {
+ .reg_off = ANACTRL_GP0PLL_CTRL0,
+ .shift = 12,
+ .width = 3,
+ },
+ .frac = {
+ .reg_off = ANACTRL_GP0PLL_CTRL1,
+ .shift = 0,
+ .width = 19,
+ },
+ .od = {
+ .reg_off = ANACTRL_GP0PLL_CTRL0,
+ .shift = 20,
+ .width = 3,
+ },
+ .l = {
+ .reg_off = ANACTRL_GP0PLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = ANACTRL_GP0PLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .table = gp0_pll_vco_table,
+ .init_regs = gp0_pll_vco_init_regs,
+ .init_count = ARRAY_SIZE(gp0_pll_vco_init_regs),
+ .flags = CLK_MESON_PLL_POWER_OF_TWO |
+ CLK_MESON_PLL_FIXED_EN0P5,
+ },
+ .hw.init = &(struct clk_init_data) {
+#ifndef CONFIG_ARM
+ .name = "gp0_pll_vco",
+#else
+ .name = "gp0_pll",
+#endif
+ .ops = &meson_clk_pll_v3_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "otherpll_in",
+ },
+ .num_parents = 1,
+ },
+};
+
+#ifndef CONFIG_ARM
+static struct clk_regmap gp0_pll = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = ANACTRL_GP0PLL_CTRL0,
+ .shift = 20,
+ .width = 3,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "gp0_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &gp0_pll_vco.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+#endif
+
+#ifdef CONFIG_ARM
+static const struct pll_params_table hifi0_pll_vco_table[] = {
+ PLL_PARAMS(150, 0, 0), /* DCO = 1800M OD = 0 PLL = 1800M */
+ PLL_PARAMS(150, 0, 2), /* DCO = 1800M OD = 4 PLL = 450M */
+ PLL_PARAMS(163, 0, 2), /* DCO = 1956M OD = 4 PLL = 489M */
+ { /* sentinel */ }
+};
+#else
+static const struct pll_params_table hifi0_pll_vco_table[] = {
+ PLL_PARAMS(150, 0), /* DCO = 1800M */
+ PLL_PARAMS(163, 0), /* DCO = 1956M */
+ { /* sentinel */ }
+};
+#endif
+
+static const struct reg_sequence hifi0_pll_vco_init_regs[] = {
+ { .reg = ANACTRL_HIFI0PLL_CTRL0, .def = 0x001100ea },
+ { .reg = ANACTRL_HIFI0PLL_CTRL1, .def = 0x11489c40 },
+ { .reg = ANACTRL_HIFI0PLL_CTRL2, .def = 0x1215b010 },
+ { .reg = ANACTRL_HIFI0PLL_CTRL3, .def = 0x00008010 },
+ { .reg = ANACTRL_HIFI0PLL_CTRL4, .def = 0x1f01110f },
+ { .reg = ANACTRL_HIFI0PLL_CTRL0, .def = 0x101100ea, .delay_us = 20 },
+ { .reg = ANACTRL_HIFI0PLL_CTRL0, .def = 0x301100ea, .delay_us = 20 },
+ { .reg = ANACTRL_HIFI0PLL_CTRL3, .def = 0x20008010 }
+};
+
+static struct clk_regmap hifi0_pll_vco = {
+ .data = &(struct meson_clk_pll_data) {
+ .en = {
+ .reg_off = ANACTRL_HIFI0PLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = ANACTRL_HIFI0PLL_CTRL0,
+ .shift = 0,
+ .width = 9,
+ },
+ .n = {
+ .reg_off = ANACTRL_HIFI0PLL_CTRL0,
+ .shift = 12,
+ .width = 3,
+ },
+ .frac = {
+ .reg_off = ANACTRL_HIFI0PLL_CTRL1,
+ .shift = 0,
+ .width = 19,
+ },
+ .od = {
+ .reg_off = ANACTRL_HIFI0PLL_CTRL0,
+ .shift = 20,
+ .width = 3,
+ },
+ .l = {
+ .reg_off = ANACTRL_HIFI0PLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = ANACTRL_HIFI0PLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .flags = CLK_MESON_PLL_ROUND_CLOSEST |
+ CLK_MESON_PLL_POWER_OF_TWO |
+ CLK_MESON_PLL_FIXED_FRAC_WEIGHT_PRECISION |
+ CLK_MESON_PLL_FIXED_EN0P5,
+ .table = hifi0_pll_vco_table,
+ .init_regs = hifi0_pll_vco_init_regs,
+ .init_count = ARRAY_SIZE(hifi0_pll_vco_init_regs),
+ },
+ .hw.init = &(struct clk_init_data) {
+#ifndef CONFIG_ARM
+ .name = "hifi0_pll_vco",
+#else
+ .name = "hifi0_pll",
+#endif
+ .ops = &meson_clk_pll_v3_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "hifi0pll_in",
+ },
+ .num_parents = 1,
+ },
+};
+
+#ifndef CONFIG_ARM
+static struct clk_regmap hifi0_pll = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = ANACTRL_HIFI0PLL_CTRL0,
+ .shift = 20,
+ .width = 3,
+ .flags = CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_ROUND_CLOSEST,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hifi0_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &hifi0_pll_vco.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+#endif
+
+#ifdef CONFIG_ARM
+static const struct pll_params_table hifi1_pll_vco_table[] = {
+ PLL_PARAMS(150, 0, 0), /* DCO = 1800M OD = 0 PLL = 1800M */
+ PLL_PARAMS(150, 0, 2), /* DCO = 1800M OD = 4 PLL = 450M */
+ PLL_PARAMS(163, 0, 2), /* DCO = 1956M OD = 4 PLL = 489M */
+ { /* sentinel */ }
+};
+#else
+static const struct pll_params_table hifi1_pll_vco_table[] = {
+ PLL_PARAMS(150, 0), /* DCO = 1800M */
+ PLL_PARAMS(163, 0), /* DCO = 1956M */
+ { /* sentinel */ }
+};
+#endif
+
+static const struct reg_sequence hifi1_pll_vco_init_regs[] = {
+ { .reg = ANACTRL_HIFI1PLL_CTRL0, .def = 0x001100ea },
+ { .reg = ANACTRL_HIFI1PLL_CTRL1, .def = 0x11489c40 },
+ { .reg = ANACTRL_HIFI1PLL_CTRL2, .def = 0x1215b010 },
+ { .reg = ANACTRL_HIFI1PLL_CTRL3, .def = 0x00008010 },
+ { .reg = ANACTRL_HIFI1PLL_CTRL4, .def = 0x00001000 },
+ { .reg = ANACTRL_HIFI1PLL_CTRL0, .def = 0x101100ea, .delay_us = 20 },
+ { .reg = ANACTRL_HIFI1PLL_CTRL0, .def = 0x301100ea, .delay_us = 20 },
+ { .reg = ANACTRL_HIFI1PLL_CTRL3, .def = 0x20008010 }
+};
+
+static struct clk_regmap hifi1_pll_vco = {
+ .data = &(struct meson_clk_pll_data) {
+ .en = {
+ .reg_off = ANACTRL_HIFI1PLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = ANACTRL_HIFI1PLL_CTRL0,
+ .shift = 0,
+ .width = 9,
+ },
+ .n = {
+ .reg_off = ANACTRL_HIFI1PLL_CTRL0,
+ .shift = 12,
+ .width = 3,
+ },
+ .frac = {
+ .reg_off = ANACTRL_HIFI1PLL_CTRL1,
+ .shift = 0,
+ .width = 19,
+ },
+ .od = {
+ .reg_off = ANACTRL_HIFI1PLL_CTRL0,
+ .shift = 20,
+ .width = 3,
+ },
+ .l = {
+ .reg_off = ANACTRL_HIFI1PLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = ANACTRL_HIFI1PLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .flags = CLK_MESON_PLL_ROUND_CLOSEST |
+ CLK_MESON_PLL_POWER_OF_TWO |
+ CLK_MESON_PLL_FIXED_FRAC_WEIGHT_PRECISION |
+ CLK_MESON_PLL_FIXED_EN0P5,
+ .table = hifi1_pll_vco_table,
+ .init_regs = hifi1_pll_vco_init_regs,
+ .init_count = ARRAY_SIZE(hifi1_pll_vco_init_regs),
+ },
+ .hw.init = &(struct clk_init_data) {
+#ifndef CONFIG_ARM
+ .name = "hifi1_pll_vco",
+#else
+ .name = "hifi1_pll",
+#endif
+ .ops = &meson_clk_pll_v3_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "eth_hifi1pll_in",
+ },
+ .num_parents = 1,
+ },
+};
+
+#ifndef CONFIG_ARM
+static struct clk_regmap hifi1_pll = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = ANACTRL_HIFI1PLL_CTRL0,
+ .shift = 20,
+ .width = 3,
+ .flags = CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_ROUND_CLOSEST,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hifi1_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &hifi1_pll_vco.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+#endif
+
+static struct clk_fixed_factor fclk50m_div = {
+ .mult = 1,
+ .div = 40,
+ .hw.init = &(struct clk_init_data) {
+ .name = "fclk50m_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &fixed_pll.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap fclk50m = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = ANACTRL_FIXPLL_CTRL1,
+ .bit_idx = 4,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "fclk50m",
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &fclk50m_div.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor fclk_div2_div = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data) {
+ .name = "fclk_div2_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &fixed_pll.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap fclk_div2 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = ANACTRL_FIXPLL_CTRL1,
+ .bit_idx = 20,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "fclk_div2",
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &fclk_div2_div.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor fclk_div2p5_div = {
+ .mult = 2,
+ .div = 5,
+ .hw.init = &(struct clk_init_data) {
+ .name = "fclk_div2p5_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &fixed_pll.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap fclk_div2p5 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = ANACTRL_FIXPLL_CTRL1,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "fclk_div2p5",
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &fclk_div2p5_div.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor fclk_div3_div = {
+ .mult = 1,
+ .div = 3,
+ .hw.init = &(struct clk_init_data) {
+ .name = "fclk_div3_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &fixed_pll.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap fclk_div3 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = ANACTRL_FIXPLL_CTRL1,
+ .bit_idx = 16,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "fclk_div3",
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &fclk_div3_div.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor fclk_div4_div = {
+ .mult = 1,
+ .div = 4,
+ .hw.init = &(struct clk_init_data) {
+ .name = "fclk_div4_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &fixed_pll.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap fclk_div4 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = ANACTRL_FIXPLL_CTRL1,
+ .bit_idx = 17,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "fclk_div4",
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &fclk_div4_div.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor fclk_div5_div = {
+ .mult = 1,
+ .div = 5,
+ .hw.init = &(struct clk_init_data) {
+ .name = "fclk_div5_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &fixed_pll.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap fclk_div5 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = ANACTRL_FIXPLL_CTRL1,
+ .bit_idx = 18,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "fclk_div5",
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &fclk_div5_div.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor fclk_div7_div = {
+ .mult = 1,
+ .div = 7,
+ .hw.init = &(struct clk_init_data) {
+ .name = "fclk_div7_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &fixed_pll.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap fclk_div7 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = ANACTRL_FIXPLL_CTRL1,
+ .bit_idx = 19,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "fclk_div7",
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &fclk_div7_div.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap rtc_dual_clkin = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_dual_clkin",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct meson_clk_dualdiv_param rtc_dual_div_table[] = {
+ { 733, 732, 8, 11, 1 },
+ { }
+};
+
+static struct clk_regmap rtc_dual_div = {
+ .data = &(struct meson_clk_dualdiv_data) {
+ .n1 = {
+ .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
+ .shift = 0,
+ .width = 12,
+ },
+ .n2 = {
+ .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
+ .shift = 12,
+ .width = 12,
+ },
+ .m1 = {
+ .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1,
+ .shift = 0,
+ .width = 12,
+ },
+ .m2 = {
+ .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1,
+ .shift = 12,
+ .width = 12,
+ },
+ .dual = {
+ .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
+ .shift = 28,
+ .width = 2,
+ },
+ .table = rtc_dual_div_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_dual_div",
+ .ops = &meson_clk_dualdiv_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &rtc_dual_clkin.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct clk_parent_data rtc_dual_parent_data[] = {
+ { .hw = &rtc_dual_div.hw },
+ { .hw = &rtc_dual_clkin.hw }
+};
+
+static struct clk_regmap rtc_dual_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_RTC_BY_OSCIN_CTRL1,
+ .mask = 0x1,
+ .shift = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_dual_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = rtc_dual_parent_data,
+ .num_parents = ARRAY_SIZE(rtc_dual_parent_data),
+ },
+};
+
+static struct clk_regmap rtc_dual = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_dual",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &rtc_dual_mux.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct clk_parent_data rtc_clk_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &rtc_dual.hw }
+};
+
+static struct clk_regmap rtc_clk = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_RTC_CTRL,
+ .mask = 0x3,
+ .shift = 0,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_clk",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = rtc_clk_parent_data,
+ .num_parents = ARRAY_SIZE(rtc_clk_parent_data),
+ },
+};
+
+static const struct clk_parent_data sys_clk_01_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div2.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div5.hw }
+};
+
+static struct clk_regmap sys_clk_0_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_SYS_CLK_CTRL0,
+ .mask = 0x7,
+ .shift = 10,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sys_clk_0_mux",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_data = sys_clk_01_parent_data,
+ .num_parents = ARRAY_SIZE(sys_clk_01_parent_data),
+ },
+};
+
+static struct clk_regmap sys_clk_0_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_SYS_CLK_CTRL0,
+ .shift = 0,
+ .width = 10,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sys_clk_0_div",
+ .ops = &clk_regmap_divider_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sys_clk_0_mux.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap sys_clk_0 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_SYS_CLK_CTRL0,
+ .bit_idx = 13,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sys_clk_0",
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sys_clk_0_div.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap sys_clk_1_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_SYS_CLK_CTRL0,
+ .mask = 0x7,
+ .shift = 26,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sys_clk_1_mux",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_data = sys_clk_01_parent_data,
+ .num_parents = ARRAY_SIZE(sys_clk_01_parent_data),
+ },
+};
+
+static struct clk_regmap sys_clk_1_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_SYS_CLK_CTRL0,
+ .shift = 16,
+ .width = 10,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sys_clk_1_div",
+ .ops = &clk_regmap_divider_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sys_clk_1_mux.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap sys_clk_1 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_SYS_CLK_CTRL0,
+ .bit_idx = 29,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sys_clk_1",
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sys_clk_1_div.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct clk_parent_data sys_clk_parent_data[] = {
+ { .hw = &sys_clk_0.hw },
+ { .hw = &sys_clk_1.hw }
+};
+
+static struct clk_regmap sys_clk = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_SYS_CLK_CTRL0,
+ .mask = 0x1,
+ .shift = 15,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sys_clk",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_data = sys_clk_parent_data,
+ .num_parents = ARRAY_SIZE(sys_clk_parent_data),
+ },
+};
+
+static const struct clk_parent_data clk_24m_in_parent_data[] = {
+ { .fw_name = "xtal" }
+};
+
+static struct clk_regmap clk_24m_in = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_CLK12_24_CTRL,
+ .bit_idx = 11,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "clk_24m_in",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = clk_24m_in_parent_data,
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor clk_12m_div = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data) {
+ .name = "clk_12m_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &clk_24m_in.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap clk_12m = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_CLK12_24_CTRL,
+ .bit_idx = 10,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "clk_12m",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &clk_12m_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static u32 axi_clk_01_parent_table[] = { 0, 1, 2, 3, 4, 6, 7 };
+static const struct clk_parent_data axi_clk_01_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div2.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div2p5.hw },
+ { .hw = &rtc_clk.hw }
+};
+
+static struct clk_regmap axi_clk_0_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_AXI_CLK_CTRL0,
+ .mask = 0x7,
+ .shift = 10,
+ .table = axi_clk_01_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "axi_clk_0_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = axi_clk_01_parent_data,
+ .num_parents = ARRAY_SIZE(axi_clk_01_parent_data),
+ },
+};
+
+static struct clk_regmap axi_clk_0_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_AXI_CLK_CTRL0,
+ .shift = 0,
+ .width = 10,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "axi_clk_0_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &axi_clk_0_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap axi_clk_0 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_AXI_CLK_CTRL0,
+ .bit_idx = 13,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "axi_clk_0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &axi_clk_0_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static struct clk_regmap axi_clk_1_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_AXI_CLK_CTRL0,
+ .mask = 0x7,
+ .shift = 26,
+ .table = axi_clk_01_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "axi_clk_1_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = axi_clk_01_parent_data,
+ .num_parents = ARRAY_SIZE(axi_clk_01_parent_data),
+ },
+};
+
+static struct clk_regmap axi_clk_1_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_AXI_CLK_CTRL0,
+ .shift = 16,
+ .width = 10,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "axi_clk_1_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &axi_clk_1_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap axi_clk_1 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_AXI_CLK_CTRL0,
+ .bit_idx = 29,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "axi_clk_1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &axi_clk_1_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static const struct clk_parent_data axi_clk_parent_data[] = {
+ { .hw = &axi_clk_0.hw },
+ { .hw = &axi_clk_1.hw }
+};
+
+static struct clk_regmap axi_clk = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_AXI_CLK_CTRL0,
+ .mask = 0x1,
+ .shift = 15,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "axi_clk",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = axi_clk_parent_data,
+ .num_parents = ARRAY_SIZE(axi_clk_parent_data),
+ .flags = CLK_IS_CRITICAL,
+ },
+};
+
+static const struct clk_parent_data sar_adc_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &sys_clk.hw },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div5.hw }
+};
+
+static struct clk_regmap sar_adc_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_SAR_CLK_CTRL0,
+ .mask = 0x3,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sar_adc_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = sar_adc_parent_data,
+ .num_parents = ARRAY_SIZE(sar_adc_parent_data),
+ },
+};
+
+static struct clk_regmap sar_adc_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_SAR_CLK_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sar_adc_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sar_adc_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap sar_adc = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_SAR_CLK_CTRL0,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sar_adc",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sar_adc_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data cecb_dual_clkin_parent_data[] = {
+ { .fw_name = "xtal" }
+};
+
+static struct clk_regmap cecb_dual_clkin = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_CECB_CTRL0,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "cecb_dual_clkin",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = cecb_dual_clkin_parent_data,
+ .num_parents = 1,
+ },
+};
+
+static const struct meson_clk_dualdiv_param cecb_dual_div_table[] = {
+ { 733, 732, 8, 11, 1 },
+ { }
+};
+
+static struct clk_regmap cecb_dual_div = {
+ .data = &(struct meson_clk_dualdiv_data) {
+ .n1 = {
+ .reg_off = CLKCTRL_CECB_CTRL0,
+ .shift = 0,
+ .width = 12,
+ },
+ .n2 = {
+ .reg_off = CLKCTRL_CECB_CTRL0,
+ .shift = 12,
+ .width = 12,
+ },
+ .m1 = {
+ .reg_off = CLKCTRL_CECB_CTRL1,
+ .shift = 0,
+ .width = 12,
+ },
+ .m2 = {
+ .reg_off = CLKCTRL_CECB_CTRL1,
+ .shift = 12,
+ .width = 12,
+ },
+ .dual = {
+ .reg_off = CLKCTRL_CECB_CTRL0,
+ .shift = 28,
+ .width = 2,
+ },
+ .table = cecb_dual_div_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "cecb_dual_div",
+ .ops = &meson_clk_dualdiv_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &cecb_dual_clkin.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct clk_parent_data cecb_dual_parent_data[] = {
+ { .hw = &cecb_dual_div.hw },
+ { .hw = &cecb_dual_clkin.hw }
+};
+
+static struct clk_regmap cecb_dual_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_CECB_CTRL1,
+ .mask = 0x1,
+ .shift = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "cecb_dual_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = cecb_dual_parent_data,
+ .num_parents = ARRAY_SIZE(cecb_dual_parent_data),
+ },
+};
+
+static struct clk_regmap cecb_dual = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_CECB_CTRL0,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "cecb_dual",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &cecb_dual_mux.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct clk_parent_data cecb_clk_parent_data[] = {
+ { .hw = &cecb_dual.hw },
+ { .hw = &rtc_clk.hw }
+};
+
+static struct clk_regmap cecb_clk = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_CECB_CTRL1,
+ .mask = 0x1,
+ .shift = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "cecb_clk",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = cecb_clk_parent_data,
+ .num_parents = ARRAY_SIZE(cecb_clk_parent_data),
+ },
+};
+
+static const struct clk_parent_data sc_pre_parent_data[] = {
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div5.hw },
+ { .fw_name = "xtal" }
+};
+
+static struct clk_regmap sc_pre_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_SC_CLK_CTRL,
+ .mask = 0x3,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sc_pre_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = sc_pre_parent_data,
+ .num_parents = ARRAY_SIZE(sc_pre_parent_data),
+ },
+};
+
+static struct clk_regmap sc_pre_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_SC_CLK_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sc_pre_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sc_pre_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap sc_pre = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_SC_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sc_pre",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sc_pre_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap sc_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_SC_CLK_CTRL,
+ .shift = 16,
+ .width = 4,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sc_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sc_pre.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data cdac_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div5.hw }
+};
+
+static struct clk_regmap cdac_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_CDAC_CLK_CTRL,
+ .mask = 0x3,
+ .shift = 16,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "cdac_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = cdac_parent_data,
+ .num_parents = ARRAY_SIZE(cdac_parent_data),
+ },
+};
+
+static struct clk_regmap cdac_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_CDAC_CLK_CTRL,
+ .shift = 0,
+ .width = 16,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "cdac_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &cdac_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap cdac = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_CDAC_CLK_CTRL,
+ .bit_idx = 20,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "cdac",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &cdac_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static u32 hdmitx_pixel_parent_table[] = { 1, 2, 4, 5, 6, 7 };
+static const struct clk_parent_data hdmitx_pixel_parent_data[] = {
+ { .hw = &gp0_pll.hw },
+ { .hw = &hifi0_pll.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw }
+};
+
+static struct clk_regmap hdmitx_pixel_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_HDMI_CLK_CTRL,
+ .mask = 0xf,
+ .shift = 16,
+ .table = hdmitx_pixel_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hdmitx_pixel_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = hdmitx_pixel_parent_data,
+ .num_parents = ARRAY_SIZE(hdmitx_pixel_parent_data),
+ },
+};
+
+static struct clk_regmap hdmitx_pixel = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VID_CLK_CTRL2,
+ .bit_idx = 5,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hdmitx_pixel",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &hdmitx_pixel_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static u32 hdmitx_fe_parent_table[] = { 1, 2, 4, 5, 6, 7 };
+static const struct clk_parent_data hdmitx_fe_parent_data[] = {
+ { .hw = &gp0_pll.hw },
+ { .hw = &hifi0_pll.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw }
+};
+
+static struct clk_regmap hdmitx_fe_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_HDMI_CLK_CTRL,
+ .mask = 0xf,
+ .shift = 20,
+ .table = hdmitx_fe_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hdmitx_fe_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = hdmitx_fe_parent_data,
+ .num_parents = ARRAY_SIZE(hdmitx_fe_parent_data),
+ },
+};
+
+static struct clk_regmap hdmitx_fe = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VID_CLK_CTRL2,
+ .bit_idx = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hdmitx_fe",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &hdmitx_fe_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+};
+
+static u32 video_src_01_parent_table[] = { 1, 2, 4, 5, 6, 7 };
+static const struct clk_parent_data video_src_01_parent_data[] = {
+ { .hw = &gp0_pll.hw },
+ { .hw = &hifi0_pll.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw }
+};
+
+static struct clk_regmap video_src0_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VID_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 16,
+ .table = video_src_01_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "video_src0_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = video_src_01_parent_data,
+ .num_parents = ARRAY_SIZE(video_src_01_parent_data),
+ },
+};
+
+static struct clk_regmap video_src0_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_VID_CLK_DIV,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "video_src0_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video_src0_mux.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap video_src0 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VID_CLK_CTRL,
+ .bit_idx = 19,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "video_src0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video_src0_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_regmap video_src1_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VIID_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 16,
+ .table = video_src_01_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "video_src1_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = video_src_01_parent_data,
+ .num_parents = ARRAY_SIZE(video_src_01_parent_data),
+ },
+};
+
+static struct clk_regmap video_src1_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_VIID_CLK_DIV,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "video_src1_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video_src1_mux.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap video_src1 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VIID_CLK_CTRL,
+ .bit_idx = 19,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "video_src1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video_src1_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_regmap video0_div1 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VID_CLK_CTRL,
+ .bit_idx = 0,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "video0_div1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video_src0.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_regmap video0_div2_gate = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VID_CLK_CTRL,
+ .bit_idx = 1,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "video0_div2_gate",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video_src0.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_fixed_factor video0_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data) {
+ .name = "video0_div2",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video0_div2_gate.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap video0_div4_gate = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VID_CLK_CTRL,
+ .bit_idx = 2,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "video0_div4_gate",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video_src0.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_fixed_factor video0_div4 = {
+ .mult = 1,
+ .div = 4,
+ .hw.init = &(struct clk_init_data) {
+ .name = "video0_div4",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video0_div4_gate.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap video0_div6_gate = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VID_CLK_CTRL,
+ .bit_idx = 3,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "video0_div6_gate",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video_src0.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_fixed_factor video0_div6 = {
+ .mult = 1,
+ .div = 6,
+ .hw.init = &(struct clk_init_data) {
+ .name = "video0_div6",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video0_div6_gate.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap video0_div12_gate = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VID_CLK_CTRL,
+ .bit_idx = 4,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "video0_div12_gate",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video_src0.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_fixed_factor video0_div12 = {
+ .mult = 1,
+ .div = 12,
+ .hw.init = &(struct clk_init_data) {
+ .name = "video0_div12",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video0_div12_gate.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap video2_div1 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VIID_CLK_CTRL,
+ .bit_idx = 0,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "video2_div1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video_src1.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_regmap video2_div2_gate = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VIID_CLK_CTRL,
+ .bit_idx = 1,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "video2_div2_gate",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video_src1.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_fixed_factor video2_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data) {
+ .name = "video2_div2",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video2_div2_gate.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap video2_div4_gate = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VIID_CLK_CTRL,
+ .bit_idx = 2,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "video2_div4_gate",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video_src1.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_fixed_factor video2_div4 = {
+ .mult = 1,
+ .div = 4,
+ .hw.init = &(struct clk_init_data) {
+ .name = "video2_div4",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video2_div4_gate.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap video2_div6_gate = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VIID_CLK_CTRL,
+ .bit_idx = 3,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "video2_div6_gate",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video_src1.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_fixed_factor video2_div6 = {
+ .mult = 1,
+ .div = 6,
+ .hw.init = &(struct clk_init_data) {
+ .name = "video2_div6",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video2_div6_gate.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap video2_div12_gate = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VIID_CLK_CTRL,
+ .bit_idx = 4,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "video2_div12_gate",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video_src1.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_fixed_factor video2_div12 = {
+ .mult = 1,
+ .div = 12,
+ .hw.init = &(struct clk_init_data) {
+ .name = "video2_div12",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &video2_div12_gate.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct clk_parent_data lcd_an_mux_parent_data[] = {
+ { .hw = &video0_div6.hw },
+ { .hw = &video0_div12.hw }
+};
+
+static struct clk_regmap lcd_an_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VIID_CLK_CTRL,
+ .mask = 0x1,
+ .shift = 11,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "lcd_an_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = lcd_an_mux_parent_data,
+ .num_parents = ARRAY_SIZE(lcd_an_mux_parent_data),
+ },
+};
+
+static struct clk_regmap lcd_an_ph2 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VID_CLK_CTRL2,
+ .bit_idx = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "lcd_an_ph2",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &lcd_an_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_regmap lcd_an_ph3 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VID_CLK_CTRL2,
+ .bit_idx = 6,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "lcd_an_ph3",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &lcd_an_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static u32 enci_parent_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
+static const struct clk_parent_data enci_parent_data[] = {
+ { .hw = &video0_div1.hw },
+ { .hw = &video0_div2.hw },
+ { .hw = &video0_div4.hw },
+ { .hw = &video0_div6.hw },
+ { .hw = &video0_div12.hw },
+ { .hw = &video2_div1.hw },
+ { .hw = &video2_div2.hw },
+ { .hw = &video2_div4.hw },
+ { .hw = &video2_div6.hw },
+ { .hw = &video2_div12.hw }
+};
+
+static struct clk_regmap enci_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VID_CLK_DIV,
+ .mask = 0xf,
+ .shift = 28,
+ .table = enci_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "enci_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = enci_parent_data,
+ .num_parents = ARRAY_SIZE(enci_parent_data),
+ },
+};
+
+static struct clk_regmap enci = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VID_CLK_CTRL2,
+ .bit_idx = 0,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "enci",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &enci_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static u32 encp_parent_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
+static const struct clk_parent_data encp_parent_data[] = {
+ { .hw = &video0_div1.hw },
+ { .hw = &video0_div2.hw },
+ { .hw = &video0_div4.hw },
+ { .hw = &video0_div6.hw },
+ { .hw = &video0_div12.hw },
+ { .hw = &video2_div1.hw },
+ { .hw = &video2_div2.hw },
+ { .hw = &video2_div4.hw },
+ { .hw = &video2_div6.hw },
+ { .hw = &video2_div12.hw }
+};
+
+static struct clk_regmap encp_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VID_CLK_DIV,
+ .mask = 0xf,
+ .shift = 24,
+ .table = encp_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "encp_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = encp_parent_data,
+ .num_parents = ARRAY_SIZE(encp_parent_data),
+ },
+};
+
+static struct clk_regmap encp = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VID_CLK_CTRL2,
+ .bit_idx = 2,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "encp",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &encp_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static u32 encl_parent_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
+static const struct clk_parent_data encl_parent_data[] = {
+ { .hw = &video0_div1.hw },
+ { .hw = &video0_div2.hw },
+ { .hw = &video0_div4.hw },
+ { .hw = &video0_div6.hw },
+ { .hw = &video0_div12.hw },
+ { .hw = &video2_div1.hw },
+ { .hw = &video2_div2.hw },
+ { .hw = &video2_div4.hw },
+ { .hw = &video2_div6.hw },
+ { .hw = &video2_div12.hw }
+};
+
+static struct clk_regmap encl_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VIID_CLK_DIV,
+ .mask = 0xf,
+ .shift = 12,
+ .table = encl_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "encl_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = encl_parent_data,
+ .num_parents = ARRAY_SIZE(encl_parent_data),
+ },
+};
+
+static struct clk_regmap encl = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VID_CLK_CTRL2,
+ .bit_idx = 3,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "encl",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &encl_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static u32 vdac_parent_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
+static const struct clk_parent_data vdac_parent_data[] = {
+ { .hw = &video0_div1.hw },
+ { .hw = &video0_div2.hw },
+ { .hw = &video0_div4.hw },
+ { .hw = &video0_div6.hw },
+ { .hw = &video0_div12.hw },
+ { .hw = &video2_div1.hw },
+ { .hw = &video2_div2.hw },
+ { .hw = &video2_div4.hw },
+ { .hw = &video2_div6.hw },
+ { .hw = &video2_div12.hw }
+};
+
+static struct clk_regmap vdac_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VIID_CLK_DIV,
+ .mask = 0xf,
+ .shift = 28,
+ .table = vdac_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vdac_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = vdac_parent_data,
+ .num_parents = ARRAY_SIZE(vdac_parent_data),
+ },
+};
+
+static struct clk_regmap vdac = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VID_CLK_CTRL2,
+ .bit_idx = 4,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vdac",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vdac_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static const struct clk_parent_data mali_01_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .fw_name = "gp1pll" },
+ { .hw = &hifi0_pll.hw },
+ { .hw = &fclk_div2p5.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw }
+};
+
+static struct clk_regmap mali_0_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_MALI_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mali_0_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = mali_01_parent_data,
+ .num_parents = ARRAY_SIZE(mali_01_parent_data),
+ },
+};
+
+static struct clk_regmap mali_0_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_MALI_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mali_0_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &mali_0_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap mali_0 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_MALI_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mali_0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &mali_0_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static struct clk_regmap mali_1_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_MALI_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 25,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mali_1_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = mali_01_parent_data,
+ .num_parents = ARRAY_SIZE(mali_01_parent_data),
+ },
+};
+
+static struct clk_regmap mali_1_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_MALI_CLK_CTRL,
+ .shift = 16,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mali_1_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &mali_1_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap mali_1 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_MALI_CLK_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mali_1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &mali_1_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static const struct clk_parent_data mali_parent_data[] = {
+ { .hw = &mali_0.hw },
+ { .hw = &mali_1.hw }
+};
+
+static struct clk_regmap mali = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_MALI_CLK_CTRL,
+ .mask = 0x1,
+ .shift = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mali",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = mali_parent_data,
+ .num_parents = ARRAY_SIZE(mali_parent_data),
+ },
+};
+
+static const struct clk_parent_data mali_stack_01_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .fw_name = "gp1pll" },
+ { .hw = &hifi0_pll.hw },
+ { .hw = &fclk_div2p5.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw }
+};
+
+static struct clk_regmap mali_stack_0_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_MALI_STACK_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mali_stack_0_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = mali_stack_01_parent_data,
+ .num_parents = ARRAY_SIZE(mali_stack_01_parent_data),
+ },
+};
+
+static struct clk_regmap mali_stack_0_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_MALI_STACK_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mali_stack_0_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &mali_stack_0_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap mali_stack_0 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_MALI_STACK_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mali_stack_0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &mali_stack_0_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static struct clk_regmap mali_stack_1_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_MALI_STACK_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 25,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mali_stack_1_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = mali_stack_01_parent_data,
+ .num_parents = ARRAY_SIZE(mali_stack_01_parent_data),
+ },
+};
+
+static struct clk_regmap mali_stack_1_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_MALI_STACK_CLK_CTRL,
+ .shift = 16,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mali_stack_1_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &mali_stack_1_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap mali_stack_1 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_MALI_STACK_CLK_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mali_stack_1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &mali_stack_1_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static const struct clk_parent_data mali_stack_parent_data[] = {
+ { .hw = &mali_stack_0.hw },
+ { .hw = &mali_stack_1.hw }
+};
+
+static struct clk_regmap mali_stack = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_MALI_STACK_CLK_CTRL,
+ .mask = 0x1,
+ .shift = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mali_stack",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = mali_stack_parent_data,
+ .num_parents = ARRAY_SIZE(mali_stack_parent_data),
+ },
+};
+
+static const struct clk_parent_data vdec_01_parent_data[] = {
+ { .hw = &fclk_div2p5.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw },
+ { .hw = &hifi0_pll.hw },
+ { .fw_name = "gp1pll" },
+ { .fw_name = "xtal" }
+};
+
+static struct clk_regmap vdec_0_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VDEC_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vdec_0_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = vdec_01_parent_data,
+ .num_parents = ARRAY_SIZE(vdec_01_parent_data),
+ },
+};
+
+static struct clk_regmap vdec_0_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_VDEC_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vdec_0_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vdec_0_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap vdec_0 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VDEC_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vdec_0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vdec_0_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static struct clk_regmap vdec_1_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VDEC3_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vdec_1_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = vdec_01_parent_data,
+ .num_parents = ARRAY_SIZE(vdec_01_parent_data),
+ },
+};
+
+static struct clk_regmap vdec_1_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_VDEC3_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vdec_1_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vdec_1_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap vdec_1 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VDEC3_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vdec_1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vdec_1_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static const struct clk_parent_data vdec_parent_data[] = {
+ { .hw = &vdec_0.hw },
+ { .hw = &vdec_1.hw }
+};
+
+static struct clk_regmap vdec = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VDEC3_CLK_CTRL,
+ .mask = 0x1,
+ .shift = 15,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vdec",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = vdec_parent_data,
+ .num_parents = ARRAY_SIZE(vdec_parent_data),
+ },
+};
+
+static const struct clk_parent_data hevcf_01_parent_data[] = {
+ { .hw = &fclk_div2p5.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw },
+ { .hw = &hifi0_pll.hw },
+ { .fw_name = "gp1pll" },
+ { .fw_name = "xtal" }
+};
+
+static struct clk_regmap hevcf_0_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VDEC2_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hevcf_0_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = hevcf_01_parent_data,
+ .num_parents = ARRAY_SIZE(hevcf_01_parent_data),
+ },
+};
+
+static struct clk_regmap hevcf_0_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_VDEC2_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hevcf_0_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &hevcf_0_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap hevcf_0 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VDEC2_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hevcf_0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &hevcf_0_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static struct clk_regmap hevcf_1_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VDEC4_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hevcf_1_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = hevcf_01_parent_data,
+ .num_parents = ARRAY_SIZE(hevcf_01_parent_data),
+ },
+};
+
+static struct clk_regmap hevcf_1_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_VDEC4_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hevcf_1_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &hevcf_1_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap hevcf_1 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VDEC4_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hevcf_1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &hevcf_1_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static const struct clk_parent_data hevcf_parent_data[] = {
+ { .hw = &hevcf_0.hw },
+ { .hw = &hevcf_1.hw }
+};
+
+static struct clk_regmap hevcf = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VDEC4_CLK_CTRL,
+ .mask = 0x1,
+ .shift = 15,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hevcf",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = hevcf_parent_data,
+ .num_parents = ARRAY_SIZE(hevcf_parent_data),
+ },
+};
+
+static u32 vpu_01_parent_table[] = { 0, 1, 2, 3, 4, 6, 7 };
+static const struct clk_parent_data vpu_01_parent_data[] = {
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw },
+ { .hw = &fclk_div2.hw },
+ { .hw = &hifi0_pll.hw },
+ { .fw_name = "gp1pll" }
+};
+
+static struct clk_regmap vpu_0_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VPU_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ .table = vpu_01_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_0_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = vpu_01_parent_data,
+ .num_parents = ARRAY_SIZE(vpu_01_parent_data),
+ },
+};
+
+static struct clk_regmap vpu_0_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_VPU_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_0_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vpu_0_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap vpu_0 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VPU_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vpu_0_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static struct clk_regmap vpu_1_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VPU_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 25,
+ .table = vpu_01_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_1_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = vpu_01_parent_data,
+ .num_parents = ARRAY_SIZE(vpu_01_parent_data),
+ },
+};
+
+static struct clk_regmap vpu_1_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_VPU_CLK_CTRL,
+ .shift = 16,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_1_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vpu_1_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap vpu_1 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VPU_CLK_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vpu_1_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static const struct clk_parent_data vpu_parent_data[] = {
+ { .hw = &vpu_0.hw },
+ { .hw = &vpu_1.hw }
+};
+
+static struct clk_regmap vpu = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VPU_CLK_CTRL,
+ .mask = 0x1,
+ .shift = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = vpu_parent_data,
+ .num_parents = ARRAY_SIZE(vpu_parent_data),
+ },
+};
+
+static const struct clk_parent_data vpu_clkb_tmp_parent_data[] = {
+ { .hw = &vpu.hw },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw }
+};
+
+static struct clk_regmap vpu_clkb_tmp_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VPU_CLKB_CTRL,
+ .mask = 0x3,
+ .shift = 20,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_clkb_tmp_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = vpu_clkb_tmp_parent_data,
+ .num_parents = ARRAY_SIZE(vpu_clkb_tmp_parent_data),
+ },
+};
+
+static struct clk_regmap vpu_clkb_tmp_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_VPU_CLKB_CTRL,
+ .shift = 16,
+ .width = 4,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_clkb_tmp_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vpu_clkb_tmp_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap vpu_clkb_tmp = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VPU_CLKB_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_clkb_tmp",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vpu_clkb_tmp_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap vpu_clkb_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_VPU_CLKB_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_clkb_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vpu_clkb_tmp.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap vpu_clkb = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VPU_CLKB_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_clkb",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vpu_clkb_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static u32 vpu_clkc_01_parent_table[] = { 0, 1, 2, 3, 4, 6, 7 };
+static const struct clk_parent_data vpu_clkc_01_parent_data[] = {
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw },
+ { .hw = &fclk_div2.hw },
+ { .hw = &hifi0_pll.hw },
+ { .fw_name = "gp1pll" }
+};
+
+static struct clk_regmap vpu_clkc_0_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VPU_CLKC_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ .table = vpu_clkc_01_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_clkc_0_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = vpu_clkc_01_parent_data,
+ .num_parents = ARRAY_SIZE(vpu_clkc_01_parent_data),
+ },
+};
+
+static struct clk_regmap vpu_clkc_0_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_VPU_CLKC_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_clkc_0_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vpu_clkc_0_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap vpu_clkc_0 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VPU_CLKC_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_clkc_0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vpu_clkc_0_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static struct clk_regmap vpu_clkc_1_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VPU_CLKC_CTRL,
+ .mask = 0x7,
+ .shift = 25,
+ .table = vpu_clkc_01_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_clkc_1_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = vpu_clkc_01_parent_data,
+ .num_parents = ARRAY_SIZE(vpu_clkc_01_parent_data),
+ },
+};
+
+static struct clk_regmap vpu_clkc_1_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_VPU_CLKC_CTRL,
+ .shift = 16,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_clkc_1_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vpu_clkc_1_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap vpu_clkc_1 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VPU_CLKC_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_clkc_1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vpu_clkc_1_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static const struct clk_parent_data vpu_clkc_parent_data[] = {
+ { .hw = &vpu_clkc_0.hw },
+ { .hw = &vpu_clkc_1.hw }
+};
+
+static struct clk_regmap vpu_clkc = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VPU_CLKC_CTRL,
+ .mask = 0x1,
+ .shift = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vpu_clkc",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = vpu_clkc_parent_data,
+ .num_parents = ARRAY_SIZE(vpu_clkc_parent_data),
+ },
+};
+
+static u32 vapb_01_parent_table[] = { 0, 1, 2, 3, 4, 6, 7 };
+static const struct clk_parent_data vapb_01_parent_data[] = {
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw },
+ { .hw = &fclk_div2.hw },
+ { .hw = &hifi0_pll.hw },
+ { .hw = &fclk_div2p5.hw }
+};
+
+static struct clk_regmap vapb_0_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VAPBCLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ .table = vapb_01_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vapb_0_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = vapb_01_parent_data,
+ .num_parents = ARRAY_SIZE(vapb_01_parent_data),
+ },
+};
+
+static struct clk_regmap vapb_0_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_VAPBCLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vapb_0_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vapb_0_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap vapb_0 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VAPBCLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vapb_0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vapb_0_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static struct clk_regmap vapb_1_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VAPBCLK_CTRL,
+ .mask = 0x7,
+ .shift = 25,
+ .table = vapb_01_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vapb_1_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = vapb_01_parent_data,
+ .num_parents = ARRAY_SIZE(vapb_01_parent_data),
+ },
+};
+
+static struct clk_regmap vapb_1_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_VAPBCLK_CTRL,
+ .shift = 16,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vapb_1_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vapb_1_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap vapb_1 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VAPBCLK_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vapb_1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vapb_1_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static const struct clk_parent_data vapb_parent_data[] = {
+ { .hw = &vapb_0.hw },
+ { .hw = &vapb_1.hw }
+};
+
+static struct clk_regmap vapb = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VAPBCLK_CTRL,
+ .mask = 0x1,
+ .shift = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vapb",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = vapb_parent_data,
+ .num_parents = ARRAY_SIZE(vapb_parent_data),
+ },
+};
+
+static struct clk_regmap ge2d = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VAPBCLK_CTRL,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "ge2d",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vapb.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct clk_parent_data dewarpa_parent_data[] = {
+ { .hw = &fclk_div2p5.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw },
+ { .hw = &gp0_pll.hw },
+ { .hw = &hifi0_pll.hw },
+ { .fw_name = "gp1pll" }
+};
+
+static struct clk_regmap dewarpa_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_DEWARPA_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dewarpa_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = dewarpa_parent_data,
+ .num_parents = ARRAY_SIZE(dewarpa_parent_data),
+ },
+};
+
+static struct clk_regmap dewarpa_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_DEWARPA_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dewarpa_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &dewarpa_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap dewarpa = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_DEWARPA_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dewarpa",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &dewarpa_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data cmpr_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div2p5.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw },
+ { .hw = &hifi0_pll.hw },
+ { .fw_name = "gp1pll" }
+};
+
+static struct clk_regmap cmpr_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_CMPR_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 25,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "cmpr_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = cmpr_parent_data,
+ .num_parents = ARRAY_SIZE(cmpr_parent_data),
+ },
+};
+
+static struct clk_regmap cmpr_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_CMPR_CLK_CTRL,
+ .shift = 16,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "cmpr_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &cmpr_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap cmpr = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_CMPR_CLK_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "cmpr",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &cmpr_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data hdmitx_sys_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div5.hw }
+};
+
+static struct clk_regmap hdmitx_sys_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_HDMI_CLK_CTRL,
+ .mask = 0x3,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hdmitx_sys_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = hdmitx_sys_parent_data,
+ .num_parents = ARRAY_SIZE(hdmitx_sys_parent_data),
+ },
+};
+
+static struct clk_regmap hdmitx_sys_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_HDMI_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hdmitx_sys_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &hdmitx_sys_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap hdmitx_sys = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_HDMI_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hdmitx_sys",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &hdmitx_sys_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static const struct clk_parent_data hdmitx_prif_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div5.hw }
+};
+
+static struct clk_regmap hdmitx_prif_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_HTX_CLK_CTRL0,
+ .mask = 0x3,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hdmitx_prif_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = hdmitx_prif_parent_data,
+ .num_parents = ARRAY_SIZE(hdmitx_prif_parent_data),
+ },
+};
+
+static struct clk_regmap hdmitx_prif_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_HTX_CLK_CTRL0,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hdmitx_prif_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &hdmitx_prif_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap hdmitx_prif = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_HTX_CLK_CTRL0,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hdmitx_prif",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &hdmitx_prif_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static const struct clk_parent_data hdmitx_200m_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div5.hw }
+};
+
+static struct clk_regmap hdmitx_200m_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_HTX_CLK_CTRL0,
+ .mask = 0x3,
+ .shift = 25,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hdmitx_200m_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = hdmitx_200m_parent_data,
+ .num_parents = ARRAY_SIZE(hdmitx_200m_parent_data),
+ },
+};
+
+static struct clk_regmap hdmitx_200m_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_HTX_CLK_CTRL0,
+ .shift = 16,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hdmitx_200m_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &hdmitx_200m_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap hdmitx_200m = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_HTX_CLK_CTRL0,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hdmitx_200m",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &hdmitx_200m_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static const struct clk_parent_data hdmitx_aud_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div5.hw }
+};
+
+static struct clk_regmap hdmitx_aud_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_HTX_CLK_CTRL1,
+ .mask = 0x3,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hdmitx_aud_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = hdmitx_aud_parent_data,
+ .num_parents = ARRAY_SIZE(hdmitx_aud_parent_data),
+ },
+};
+
+static struct clk_regmap hdmitx_aud_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_HTX_CLK_CTRL1,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hdmitx_aud_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &hdmitx_aud_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap hdmitx_aud = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_HTX_CLK_CTRL1,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hdmitx_aud",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &hdmitx_aud_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static u32 pwm_a_parent_table[] = { 0, 2, 3 };
+static const struct clk_parent_data pwm_a_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw }
+};
+
+static struct clk_regmap pwm_a_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_PWM_CLK_AB_CTRL,
+ .mask = 0x3,
+ .shift = 9,
+ .table = pwm_a_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_a_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = pwm_a_parent_data,
+ .num_parents = ARRAY_SIZE(pwm_a_parent_data),
+ },
+};
+
+static struct clk_regmap pwm_a_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_PWM_CLK_AB_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_a_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_a_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap pwm_a = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_PWM_CLK_AB_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_a",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_a_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static u32 pwm_b_parent_table[] = { 0, 2, 3 };
+static const struct clk_parent_data pwm_b_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw }
+};
+
+static struct clk_regmap pwm_b_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_PWM_CLK_AB_CTRL,
+ .mask = 0x3,
+ .shift = 25,
+ .table = pwm_b_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_b_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = pwm_b_parent_data,
+ .num_parents = ARRAY_SIZE(pwm_b_parent_data),
+ },
+};
+
+static struct clk_regmap pwm_b_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_PWM_CLK_AB_CTRL,
+ .shift = 16,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_b_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_b_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap pwm_b = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_PWM_CLK_AB_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_b",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_b_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static u32 pwm_c_parent_table[] = { 0, 2, 3 };
+static const struct clk_parent_data pwm_c_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw }
+};
+
+static struct clk_regmap pwm_c_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_PWM_CLK_CD_CTRL,
+ .mask = 0x3,
+ .shift = 9,
+ .table = pwm_c_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_c_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = pwm_c_parent_data,
+ .num_parents = ARRAY_SIZE(pwm_c_parent_data),
+ },
+};
+
+static struct clk_regmap pwm_c_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_PWM_CLK_CD_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_c_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_c_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap pwm_c = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_PWM_CLK_CD_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_c",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_c_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static u32 pwm_d_parent_table[] = { 0, 2, 3 };
+static const struct clk_parent_data pwm_d_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw }
+};
+
+static struct clk_regmap pwm_d_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_PWM_CLK_CD_CTRL,
+ .mask = 0x3,
+ .shift = 25,
+ .table = pwm_d_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_d_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = pwm_d_parent_data,
+ .num_parents = ARRAY_SIZE(pwm_d_parent_data),
+ },
+};
+
+static struct clk_regmap pwm_d_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_PWM_CLK_CD_CTRL,
+ .shift = 16,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_d_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_d_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap pwm_d = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_PWM_CLK_CD_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_d",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_d_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static u32 pwm_e_parent_table[] = { 0, 2, 3 };
+static const struct clk_parent_data pwm_e_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw }
+};
+
+static struct clk_regmap pwm_e_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_PWM_CLK_EF_CTRL,
+ .mask = 0x3,
+ .shift = 9,
+ .table = pwm_e_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_e_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = pwm_e_parent_data,
+ .num_parents = ARRAY_SIZE(pwm_e_parent_data),
+ },
+};
+
+static struct clk_regmap pwm_e_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_PWM_CLK_EF_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_e_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_e_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap pwm_e = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_PWM_CLK_EF_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_e",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_e_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static u32 pwm_f_parent_table[] = { 0, 2, 3 };
+static const struct clk_parent_data pwm_f_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw }
+};
+
+static struct clk_regmap pwm_f_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_PWM_CLK_EF_CTRL,
+ .mask = 0x3,
+ .shift = 25,
+ .table = pwm_f_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_f_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = pwm_f_parent_data,
+ .num_parents = ARRAY_SIZE(pwm_f_parent_data),
+ },
+};
+
+static struct clk_regmap pwm_f_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_PWM_CLK_EF_CTRL,
+ .shift = 16,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_f_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_f_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap pwm_f = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_PWM_CLK_EF_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_f",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_f_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static u32 pwm_g_parent_table[] = { 0, 2, 3 };
+static const struct clk_parent_data pwm_g_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw }
+};
+
+static struct clk_regmap pwm_g_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_PWM_CLK_GH_CTRL,
+ .mask = 0x3,
+ .shift = 9,
+ .table = pwm_g_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_g_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = pwm_g_parent_data,
+ .num_parents = ARRAY_SIZE(pwm_g_parent_data),
+ },
+};
+
+static struct clk_regmap pwm_g_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_PWM_CLK_GH_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_g_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_g_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap pwm_g = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_PWM_CLK_GH_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_g",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_g_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static u32 pwm_h_parent_table[] = { 0, 2, 3 };
+static const struct clk_parent_data pwm_h_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw }
+};
+
+static struct clk_regmap pwm_h_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_PWM_CLK_GH_CTRL,
+ .mask = 0x3,
+ .shift = 25,
+ .table = pwm_h_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_h_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = pwm_h_parent_data,
+ .num_parents = ARRAY_SIZE(pwm_h_parent_data),
+ },
+};
+
+static struct clk_regmap pwm_h_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_PWM_CLK_GH_CTRL,
+ .shift = 16,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_h_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_h_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap pwm_h = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_PWM_CLK_GH_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_h",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_h_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static u32 pwm_i_parent_table[] = { 0, 2, 3 };
+static const struct clk_parent_data pwm_i_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw }
+};
+
+static struct clk_regmap pwm_i_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_PWM_CLK_IJ_CTRL,
+ .mask = 0x3,
+ .shift = 9,
+ .table = pwm_i_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_i_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = pwm_i_parent_data,
+ .num_parents = ARRAY_SIZE(pwm_i_parent_data),
+ },
+};
+
+static struct clk_regmap pwm_i_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_PWM_CLK_IJ_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_i_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_i_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap pwm_i = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_PWM_CLK_IJ_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_i",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_i_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static u32 pwm_j_parent_table[] = { 0, 2, 3 };
+static const struct clk_parent_data pwm_j_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw }
+};
+
+static struct clk_regmap pwm_j_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_PWM_CLK_IJ_CTRL,
+ .mask = 0x3,
+ .shift = 25,
+ .table = pwm_j_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_j_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = pwm_j_parent_data,
+ .num_parents = ARRAY_SIZE(pwm_j_parent_data),
+ },
+};
+
+static struct clk_regmap pwm_j_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_PWM_CLK_IJ_CTRL,
+ .shift = 16,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_j_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_j_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap pwm_j = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_PWM_CLK_IJ_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_j",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pwm_j_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data spicc0_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &sys_clk.hw },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div2.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw },
+ { .fw_name = "gp1pll" }
+};
+
+static struct clk_regmap spicc0_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_SPICC_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "spicc0_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = spicc0_parent_data,
+ .num_parents = ARRAY_SIZE(spicc0_parent_data),
+ },
+};
+
+static struct clk_regmap spicc0_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_SPICC_CLK_CTRL,
+ .shift = 0,
+ .width = 6,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "spicc0_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &spicc0_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap spicc0 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_SPICC_CLK_CTRL,
+ .bit_idx = 6,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "spicc0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &spicc0_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static u32 sd_emmc_a_parent_table[] = { 0, 1, 2, 3, 4, 6, 7 };
+static const struct clk_parent_data sd_emmc_a_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div2.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &hifi0_pll.hw },
+ { .hw = &fclk_div2p5.hw },
+ { .fw_name = "gp1pll" },
+ { .hw = &gp0_pll.hw }
+};
+
+static struct clk_regmap sd_emmc_a_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_SD_EMMC_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ .table = sd_emmc_a_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sd_emmc_a_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = sd_emmc_a_parent_data,
+ .num_parents = ARRAY_SIZE(sd_emmc_a_parent_data),
+ },
+};
+
+static struct clk_regmap sd_emmc_a_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_SD_EMMC_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sd_emmc_a_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sd_emmc_a_mux.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap sd_emmc_a = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_SD_EMMC_CLK_CTRL,
+ .bit_idx = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sd_emmc_a",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sd_emmc_a_div.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static u32 sd_emmc_b_parent_table[] = { 0, 1, 2, 3, 4, 6, 7 };
+static const struct clk_parent_data sd_emmc_b_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div2.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &hifi0_pll.hw },
+ { .hw = &fclk_div2p5.hw },
+ { .fw_name = "gp1pll" },
+ { .hw = &gp0_pll.hw }
+};
+
+static struct clk_regmap sd_emmc_b_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_SD_EMMC_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 25,
+ .table = sd_emmc_b_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sd_emmc_b_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = sd_emmc_b_parent_data,
+ .num_parents = ARRAY_SIZE(sd_emmc_b_parent_data),
+ },
+};
+
+static struct clk_regmap sd_emmc_b_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_SD_EMMC_CLK_CTRL,
+ .shift = 16,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sd_emmc_b_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sd_emmc_b_mux.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap sd_emmc_b = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_SD_EMMC_CLK_CTRL,
+ .bit_idx = 23,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sd_emmc_b",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sd_emmc_b_div.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static u32 sd_emmc_c_parent_table[] = { 0, 1, 2, 3, 4, 6, 7 };
+static const struct clk_parent_data sd_emmc_c_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div2.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &hifi0_pll.hw },
+ { .hw = &fclk_div2p5.hw },
+ { .fw_name = "gp1pll" },
+ { .hw = &gp0_pll.hw }
+};
+
+static struct clk_regmap sd_emmc_c_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_NAND_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ .table = sd_emmc_c_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sd_emmc_c_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = sd_emmc_c_parent_data,
+ .num_parents = ARRAY_SIZE(sd_emmc_c_parent_data),
+ },
+};
+
+static struct clk_regmap sd_emmc_c_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_NAND_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sd_emmc_c_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sd_emmc_c_mux.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap sd_emmc_c = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_NAND_CLK_CTRL,
+ .bit_idx = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sd_emmc_c",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sd_emmc_c_div.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct clk_parent_data vdin_meas_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div5.hw }
+};
+
+static struct clk_regmap vdin_meas_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vdin_meas_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = vdin_meas_parent_data,
+ .num_parents = ARRAY_SIZE(vdin_meas_parent_data),
+ },
+};
+
+static struct clk_regmap vdin_meas_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vdin_meas_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vdin_meas_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap vdin_meas = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vdin_meas",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vdin_meas_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data vid_lock_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &encl.hw },
+ { .hw = &enci.hw },
+ { .hw = &encp.hw }
+};
+
+static struct clk_regmap vid_lock_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VID_LOCK_CLK_CTRL,
+ .mask = 0x3,
+ .shift = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vid_lock_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = vid_lock_parent_data,
+ .num_parents = ARRAY_SIZE(vid_lock_parent_data),
+ },
+};
+
+static struct clk_regmap vid_lock_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_VID_LOCK_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vid_lock_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vid_lock_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap vid_lock = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VID_LOCK_CLK_CTRL,
+ .bit_idx = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vid_lock",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vid_lock_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data eth_clk_rmii_parent_data[] = {
+ { .hw = &fclk_div2.hw }
+};
+
+static struct clk_regmap eth_clk_rmii_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_ETH_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "eth_clk_rmii_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = eth_clk_rmii_parent_data,
+ .num_parents = ARRAY_SIZE(eth_clk_rmii_parent_data),
+ },
+};
+
+static struct clk_regmap eth_clk_rmii_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_ETH_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "eth_clk_rmii_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ ð_clk_rmii_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap eth_clk_rmii = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_ETH_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "eth_clk_rmii",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ ð_clk_rmii_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_fixed_factor eth_clk125M_div = {
+ .mult = 1,
+ .div = 8,
+ .hw.init = &(struct clk_init_data) {
+ .name = "eth_clk125M_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &fclk_div2.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap eth_clk125M = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_ETH_CLK_CTRL,
+ .bit_idx = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "eth_clk125M",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ ð_clk125M_div.hw,
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct clk_parent_data ts_parent_data[] = {
+ { .fw_name = "xtal" }
+};
+
+static struct clk_regmap ts_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_TS_CLK_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "ts_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_data = ts_parent_data,
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap ts = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_TS_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "ts",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &ts_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data amfc_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &sys_clk.hw },
+ { .hw = &fclk_div2.hw },
+ { .hw = &fclk_div2p5.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw }
+};
+
+static struct clk_regmap amfc_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_AMFC_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "amfc_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = amfc_parent_data,
+ .num_parents = ARRAY_SIZE(amfc_parent_data),
+ },
+};
+
+static struct clk_regmap amfc_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_AMFC_CLK_CTRL,
+ .shift = 0,
+ .width = 6,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "amfc_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &amfc_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap amfc = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_AMFC_CLK_CTRL,
+ .bit_idx = 6,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "amfc",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &amfc_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data csi2_adapt_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw },
+ { .fw_name = "gp1pll" },
+ { .hw = &hifi0_pll.hw },
+ { .hw = &gp0_pll.hw }
+};
+
+static struct clk_regmap csi2_adapt_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_CSI2_ADAPT_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "csi2_adapt_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = csi2_adapt_parent_data,
+ .num_parents = ARRAY_SIZE(csi2_adapt_parent_data),
+ },
+};
+
+static struct clk_regmap csi2_adapt_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_CSI2_ADAPT_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "csi2_adapt_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &csi2_adapt_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap csi2_adapt = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_CSI2_ADAPT_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "csi2_adapt",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &csi2_adapt_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data mipi_csi_phy_01_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &gp0_pll.hw },
+ { .fw_name = "gp1pll" },
+ { .hw = &hifi0_pll.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw }
+};
+
+static struct clk_regmap mipi_csi_phy_0_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mipi_csi_phy_0_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = mipi_csi_phy_01_parent_data,
+ .num_parents = ARRAY_SIZE(mipi_csi_phy_01_parent_data),
+ },
+};
+
+static struct clk_regmap mipi_csi_phy_0_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mipi_csi_phy_0_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &mipi_csi_phy_0_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap mipi_csi_phy_0 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mipi_csi_phy_0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &mipi_csi_phy_0_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static struct clk_regmap mipi_csi_phy_1_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 25,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mipi_csi_phy_1_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = mipi_csi_phy_01_parent_data,
+ .num_parents = ARRAY_SIZE(mipi_csi_phy_01_parent_data),
+ },
+};
+
+static struct clk_regmap mipi_csi_phy_1_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL,
+ .shift = 16,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mipi_csi_phy_1_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &mipi_csi_phy_1_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap mipi_csi_phy_1 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mipi_csi_phy_1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &mipi_csi_phy_1_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static const struct clk_parent_data mipi_csi_phy_parent_data[] = {
+ { .hw = &mipi_csi_phy_0.hw },
+ { .hw = &mipi_csi_phy_1.hw }
+};
+
+static struct clk_regmap mipi_csi_phy = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL,
+ .mask = 0x1,
+ .shift = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mipi_csi_phy",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = mipi_csi_phy_parent_data,
+ .num_parents = ARRAY_SIZE(mipi_csi_phy_parent_data),
+ },
+};
+
+static u32 mipi_dsi_phy_parent_table[] = { 0, 1, 2, 4, 5, 6, 7 };
+static const struct clk_parent_data mipi_dsi_phy_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &gp0_pll.hw },
+ { .hw = &hifi0_pll.hw },
+ { .hw = &fclk_div2.hw },
+ { .hw = &fclk_div2p5.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div7.hw }
+};
+
+static struct clk_regmap mipi_dsi_phy_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_MIPIDSI_PHY_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 12,
+ .table = mipi_dsi_phy_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mipi_dsi_phy_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = mipi_dsi_phy_parent_data,
+ .num_parents = ARRAY_SIZE(mipi_dsi_phy_parent_data),
+ },
+};
+
+static struct clk_regmap mipi_dsi_phy_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_MIPIDSI_PHY_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mipi_dsi_phy_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &mipi_dsi_phy_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap mipi_dsi_phy = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_MIPIDSI_PHY_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mipi_dsi_phy",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &mipi_dsi_phy_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static u32 mipi_dsi_meas_parent_table[] = { 0, 1, 2, 4, 5, 6, 7 };
+static const struct clk_parent_data mipi_dsi_meas_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &gp0_pll.hw },
+ { .hw = &hifi0_pll.hw },
+ { .hw = &fclk_div2.hw },
+ { .hw = &fclk_div2p5.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div7.hw }
+};
+
+static struct clk_regmap mipi_dsi_meas_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_MIPIDSI_PHY_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 12,
+ .table = mipi_dsi_meas_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mipi_dsi_meas_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = mipi_dsi_meas_parent_data,
+ .num_parents = ARRAY_SIZE(mipi_dsi_meas_parent_data),
+ },
+};
+
+static struct clk_regmap mipi_dsi_meas_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_MIPIDSI_PHY_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mipi_dsi_meas_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &mipi_dsi_meas_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap mipi_dsi_meas = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
+ .bit_idx = 20,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mipi_dsi_meas",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &mipi_dsi_meas_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data nna_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div2p5.hw },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div2.hw },
+ { .fw_name = "gp1pll" },
+ { .hw = &hifi0_pll.hw }
+};
+
+static struct clk_regmap nna_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_NNA_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "nna_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = nna_parent_data,
+ .num_parents = ARRAY_SIZE(nna_parent_data),
+ },
+};
+
+static struct clk_regmap nna_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_NNA_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "nna_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &nna_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap nna = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_NNA_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "nna",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &nna_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data vc9000e_aclk_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw },
+ { .hw = &fclk_div2p5.hw },
+ { .hw = &hifi0_pll.hw },
+ { .hw = &gp0_pll.hw }
+};
+
+static struct clk_regmap vc9000e_aclk_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VC9000E_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vc9000e_aclk_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = vc9000e_aclk_parent_data,
+ .num_parents = ARRAY_SIZE(vc9000e_aclk_parent_data),
+ },
+};
+
+static struct clk_regmap vc9000e_aclk_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_VC9000E_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vc9000e_aclk_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vc9000e_aclk_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap vc9000e_aclk = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VC9000E_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vc9000e_aclk",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vc9000e_aclk_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data vc9000e_core_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div7.hw },
+ { .hw = &fclk_div2p5.hw },
+ { .hw = &hifi0_pll.hw },
+ { .hw = &gp0_pll.hw }
+};
+
+static struct clk_regmap vc9000e_core_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_VC9000E_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 25,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vc9000e_core_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = vc9000e_core_parent_data,
+ .num_parents = ARRAY_SIZE(vc9000e_core_parent_data),
+ },
+};
+
+static struct clk_regmap vc9000e_core_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_VC9000E_CLK_CTRL,
+ .shift = 16,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vc9000e_core_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vc9000e_core_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap vc9000e_core = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_VC9000E_CLK_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vc9000e_core",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &vc9000e_core_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data dspa_01_parent_data[] = {
+ { .fw_name = "xtal" },
+ { .hw = &fclk_div2p5.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div5.hw },
+ { .fw_name = "gp2pll" },
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div7.hw },
+ { .hw = &rtc_clk.hw }
+};
+
+static struct clk_regmap dspa_0_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_DSPA_CLK_CTRL0,
+ .mask = 0x7,
+ .shift = 10,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa_0_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = dspa_01_parent_data,
+ .num_parents = ARRAY_SIZE(dspa_01_parent_data),
+ },
+};
+
+static struct clk_regmap dspa_0_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_DSPA_CLK_CTRL0,
+ .shift = 0,
+ .width = 10,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa_0_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &dspa_0_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap dspa_0 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_DSPA_CLK_CTRL0,
+ .bit_idx = 13,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa_0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &dspa_0_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static struct clk_regmap dspa_1_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_DSPA_CLK_CTRL0,
+ .mask = 0x7,
+ .shift = 26,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa_1_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = dspa_01_parent_data,
+ .num_parents = ARRAY_SIZE(dspa_01_parent_data),
+ },
+};
+
+static struct clk_regmap dspa_1_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_DSPA_CLK_CTRL0,
+ .shift = 16,
+ .width = 10,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa_1_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &dspa_1_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap dspa_1 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_DSPA_CLK_CTRL0,
+ .bit_idx = 29,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa_1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &dspa_1_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ },
+};
+
+static const struct clk_parent_data dspa_parent_data[] = {
+ { .hw = &dspa_0.hw },
+ { .hw = &dspa_1.hw }
+};
+
+static struct clk_regmap dspa = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_DSPA_CLK_CTRL0,
+ .mask = 0x1,
+ .shift = 15,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = dspa_parent_data,
+ .num_parents = ARRAY_SIZE(dspa_parent_data),
+ },
+};
+
+static const struct clk_parent_data pcie_tl_parent_data[] = {
+ { .hw = &fclk_div4.hw },
+ { .hw = &fclk_div3.hw },
+ { .hw = &fclk_div5.hw },
+ { .hw = &fclk_div2.hw },
+ { .hw = &fclk_div2p5.hw },
+ { .hw = &gp0_pll.hw },
+ { .hw = &hifi0_pll.hw },
+ { .fw_name = "xtal" }
+};
+
+static struct clk_regmap pcie_tl_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_PCIE_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 25,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pcie_tl_mux",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = pcie_tl_parent_data,
+ .num_parents = ARRAY_SIZE(pcie_tl_parent_data),
+ },
+};
+
+static struct clk_regmap pcie_tl_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_PCIE_CLK_CTRL,
+ .shift = 16,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pcie_tl_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie_tl_mux.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap pcie_tl = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_PCIE_CLK_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pcie_tl",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie_tl_div.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+#define MESON_CLK_GATE_SYS_CLK(_name, _reg, _bit) \
+struct clk_regmap _name = { \
+ .data = &(struct clk_regmap_gate_data) { \
+ .offset = (_reg), \
+ .bit_idx = (_bit), \
+ }, \
+ .hw.init = &(struct clk_init_data) { \
+ .name = #_name, \
+ .ops = &clk_regmap_gate_ops, \
+ .parent_hws = (const struct clk_hw *[]) { \
+ &sys_clk.hw \
+ }, \
+ .num_parents = 1, \
+ .flags = CLK_IGNORE_UNUSED, \
+ }, \
+}
+
+#define MESON_CLK_GATE_AXI_CLK(_name, _reg, _bit) \
+struct clk_regmap _name = { \
+ .data = &(struct clk_regmap_gate_data) { \
+ .offset = (_reg), \
+ .bit_idx = (_bit), \
+ }, \
+ .hw.init = &(struct clk_init_data) { \
+ .name = #_name, \
+ .ops = &clk_regmap_gate_ops, \
+ .parent_hws = (const struct clk_hw *[]) { \
+ &axi_clk.hw \
+ }, \
+ .num_parents = 1, \
+ .flags = CLK_IGNORE_UNUSED, \
+ }, \
+}
+
+MESON_CLK_GATE_SYS_CLK(sys_am_axi, CLKCTRL_SYS_CLK_EN0_REG0, 0);
+MESON_CLK_GATE_SYS_CLK(sys_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1);
+MESON_CLK_GATE_SYS_CLK(sys_vc9000e, CLKCTRL_SYS_CLK_EN0_REG0, 2);
+MESON_CLK_GATE_SYS_CLK(sys_mipi_dsi, CLKCTRL_SYS_CLK_EN0_REG0, 3);
+MESON_CLK_GATE_SYS_CLK(sys_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4);
+MESON_CLK_GATE_SYS_CLK(sys_amfc, CLKCTRL_SYS_CLK_EN0_REG0, 5);
+MESON_CLK_GATE_SYS_CLK(sys_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6);
+MESON_CLK_GATE_SYS_CLK(sys_nna, CLKCTRL_SYS_CLK_EN0_REG0, 7);
+MESON_CLK_GATE_SYS_CLK(sys_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13);
+MESON_CLK_GATE_SYS_CLK(sys_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14);
+MESON_CLK_GATE_SYS_CLK(sys_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16);
+MESON_CLK_GATE_SYS_CLK(sys_mipi_dsi_phy, CLKCTRL_SYS_CLK_EN0_REG0, 20);
+MESON_CLK_GATE_SYS_CLK(sys_sd_emmc_a, CLKCTRL_SYS_CLK_EN0_REG0, 24);
+MESON_CLK_GATE_SYS_CLK(sys_sd_emmc_b, CLKCTRL_SYS_CLK_EN0_REG0, 25);
+MESON_CLK_GATE_SYS_CLK(sys_sd_emmc_c, CLKCTRL_SYS_CLK_EN0_REG0, 26);
+MESON_CLK_GATE_SYS_CLK(sys_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27);
+MESON_CLK_GATE_SYS_CLK(sys_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28);
+MESON_CLK_GATE_SYS_CLK(sys_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30);
+MESON_CLK_GATE_SYS_CLK(sys_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31);
+MESON_CLK_GATE_SYS_CLK(sys_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0);
+MESON_CLK_GATE_SYS_CLK(sys_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3);
+MESON_CLK_GATE_SYS_CLK(sys_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5);
+MESON_CLK_GATE_SYS_CLK(sys_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6);
+MESON_CLK_GATE_SYS_CLK(sys_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7);
+MESON_CLK_GATE_SYS_CLK(sys_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8);
+MESON_CLK_GATE_SYS_CLK(sys_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9);
+MESON_CLK_GATE_SYS_CLK(sys_ts_pll, CLKCTRL_SYS_CLK_EN0_REG1, 16);
+MESON_CLK_GATE_SYS_CLK(sys_csi_dig_clkin, CLKCTRL_SYS_CLK_EN0_REG1, 18);
+MESON_CLK_GATE_SYS_CLK(sys_ge2d, CLKCTRL_SYS_CLK_EN0_REG1, 20);
+MESON_CLK_GATE_SYS_CLK(sys_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21);
+MESON_CLK_GATE_SYS_CLK(sys_pcie, CLKCTRL_SYS_CLK_EN0_REG1, 24);
+MESON_CLK_GATE_SYS_CLK(sys_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26);
+MESON_CLK_GATE_SYS_CLK(sys_pcie_phy, CLKCTRL_SYS_CLK_EN0_REG1, 27);
+MESON_CLK_GATE_SYS_CLK(sys_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30);
+MESON_CLK_GATE_SYS_CLK(sys_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31);
+MESON_CLK_GATE_SYS_CLK(sys_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0);
+MESON_CLK_GATE_SYS_CLK(sys_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1);
+MESON_CLK_GATE_SYS_CLK(sys_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2);
+MESON_CLK_GATE_SYS_CLK(sys_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4);
+MESON_CLK_GATE_SYS_CLK(sys_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5);
+MESON_CLK_GATE_SYS_CLK(sys_hdmi20_aes, CLKCTRL_SYS_CLK_EN0_REG2, 9);
+MESON_CLK_GATE_SYS_CLK(sys_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11);
+MESON_CLK_GATE_SYS_CLK(sys_csi2_host, CLKCTRL_SYS_CLK_EN0_REG2, 16);
+MESON_CLK_GATE_SYS_CLK(sys_csi2_adapt, CLKCTRL_SYS_CLK_EN0_REG2, 17);
+MESON_CLK_GATE_SYS_CLK(sys_cpu_apb, CLKCTRL_SYS_CLK_EN0_REG2, 19);
+MESON_CLK_GATE_SYS_CLK(sys_dspa, CLKCTRL_SYS_CLK_EN0_REG2, 21);
+MESON_CLK_GATE_SYS_CLK(sys_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25);
+MESON_CLK_GATE_SYS_CLK(sys_csi2_phy0, CLKCTRL_SYS_CLK_EN0_REG2, 27);
+MESON_CLK_GATE_SYS_CLK(sys_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28);
+MESON_CLK_GATE_SYS_CLK(sys_pwm_j, CLKCTRL_SYS_CLK_EN0_REG2, 29);
+MESON_CLK_GATE_SYS_CLK(sys_gic, CLKCTRL_SYS_CLK_EN0_REG2, 30);
+MESON_CLK_GATE_SYS_CLK(sys_pwm_i, CLKCTRL_SYS_CLK_EN0_REG2, 31);
+MESON_CLK_GATE_SYS_CLK(sys_pwm_h, CLKCTRL_SYS_CLK_EN0_REG3, 0);
+MESON_CLK_GATE_SYS_CLK(sys_pwm_g, CLKCTRL_SYS_CLK_EN0_REG3, 1);
+MESON_CLK_GATE_SYS_CLK(sys_pwm_f, CLKCTRL_SYS_CLK_EN0_REG3, 2);
+MESON_CLK_GATE_SYS_CLK(sys_pwm_e, CLKCTRL_SYS_CLK_EN0_REG3, 3);
+MESON_CLK_GATE_SYS_CLK(sys_pwm_d, CLKCTRL_SYS_CLK_EN0_REG3, 4);
+MESON_CLK_GATE_SYS_CLK(sys_pwm_c, CLKCTRL_SYS_CLK_EN0_REG3, 5);
+MESON_CLK_GATE_SYS_CLK(sys_pwm_b, CLKCTRL_SYS_CLK_EN0_REG3, 6);
+MESON_CLK_GATE_SYS_CLK(sys_pwm_a, CLKCTRL_SYS_CLK_EN0_REG3, 7);
+
+MESON_CLK_GATE_AXI_CLK(axi_ao_nic, CLKCTRL_AXI_CLK_EN0, 0);
+MESON_CLK_GATE_AXI_CLK(axi_dev0_mmc, CLKCTRL_AXI_CLK_EN0, 1);
+MESON_CLK_GATE_AXI_CLK(axi_cpu_sram, CLKCTRL_AXI_CLK_EN0, 2);
+
+static struct clk_regmap *const pll_regmaps[] = {
+ &fixed_pll_vco,
+ &fixed_pll,
+ &gp0_pll_vco,
+ &gp0_pll,
+ &hifi0_pll_vco,
+ &hifi0_pll,
+ &hifi1_pll_vco,
+ &hifi1_pll,
+ &fclk50m,
+ &fclk_div2,
+ &fclk_div2p5,
+ &fclk_div3,
+ &fclk_div4,
+ &fclk_div5,
+ &fclk_div7,
+};
+
+static struct clk_regmap *const clk_regmaps[] = {
+ &rtc_dual_clkin,
+ &rtc_dual_div,
+ &rtc_dual_mux,
+ &rtc_dual,
+ &rtc_clk,
+ &sys_clk_0_mux,
+ &sys_clk_0_div,
+ &sys_clk_0,
+ &sys_clk_1_mux,
+ &sys_clk_1_div,
+ &sys_clk_1,
+ &sys_clk,
+ &clk_24m_in,
+ &clk_12m,
+ &axi_clk_0_mux,
+ &axi_clk_0_div,
+ &axi_clk_0,
+ &axi_clk_1_mux,
+ &axi_clk_1_div,
+ &axi_clk_1,
+ &axi_clk,
+ &sar_adc_mux,
+ &sar_adc_div,
+ &sar_adc,
+ &cecb_dual_clkin,
+ &cecb_dual_div,
+ &cecb_dual_mux,
+ &cecb_dual,
+ &cecb_clk,
+ &sc_pre_mux,
+ &sc_pre_div,
+ &sc_pre,
+ &sc_div,
+ &cdac_mux,
+ &cdac_div,
+ &cdac,
+ &hdmitx_pixel_mux,
+ &hdmitx_pixel,
+ &hdmitx_fe_mux,
+ &hdmitx_fe,
+ &video_src0_mux,
+ &video_src0_div,
+ &video_src0,
+ &video_src1_mux,
+ &video_src1_div,
+ &video_src1,
+ &video0_div1,
+ &video0_div2_gate,
+ &video0_div4_gate,
+ &video0_div6_gate,
+ &video0_div12_gate,
+ &video2_div1,
+ &video2_div2_gate,
+ &video2_div4_gate,
+ &video2_div6_gate,
+ &video2_div12_gate,
+ &lcd_an_mux,
+ &lcd_an_ph2,
+ &lcd_an_ph3,
+ &enci_mux,
+ &enci,
+ &encp_mux,
+ &encp,
+ &encl_mux,
+ &encl,
+ &vdac_mux,
+ &vdac,
+ &mali_0_mux,
+ &mali_0_div,
+ &mali_0,
+ &mali_1_mux,
+ &mali_1_div,
+ &mali_1,
+ &mali,
+ &mali_stack_0_mux,
+ &mali_stack_0_div,
+ &mali_stack_0,
+ &mali_stack_1_mux,
+ &mali_stack_1_div,
+ &mali_stack_1,
+ &mali_stack,
+ &vdec_0_mux,
+ &vdec_0_div,
+ &vdec_0,
+ &vdec_1_mux,
+ &vdec_1_div,
+ &vdec_1,
+ &vdec,
+ &hevcf_0_mux,
+ &hevcf_0_div,
+ &hevcf_0,
+ &hevcf_1_mux,
+ &hevcf_1_div,
+ &hevcf_1,
+ &hevcf,
+ &vpu_0_mux,
+ &vpu_0_div,
+ &vpu_0,
+ &vpu_1_mux,
+ &vpu_1_div,
+ &vpu_1,
+ &vpu,
+ &vpu_clkb_tmp_mux,
+ &vpu_clkb_tmp_div,
+ &vpu_clkb_tmp,
+ &vpu_clkb_div,
+ &vpu_clkb,
+ &vpu_clkc_0_mux,
+ &vpu_clkc_0_div,
+ &vpu_clkc_0,
+ &vpu_clkc_1_mux,
+ &vpu_clkc_1_div,
+ &vpu_clkc_1,
+ &vpu_clkc,
+ &vapb_0_mux,
+ &vapb_0_div,
+ &vapb_0,
+ &vapb_1_mux,
+ &vapb_1_div,
+ &vapb_1,
+ &vapb,
+ &ge2d,
+ &dewarpa_mux,
+ &dewarpa_div,
+ &dewarpa,
+ &cmpr_mux,
+ &cmpr_div,
+ &cmpr,
+ &hdmitx_sys_mux,
+ &hdmitx_sys_div,
+ &hdmitx_sys,
+ &hdmitx_prif_mux,
+ &hdmitx_prif_div,
+ &hdmitx_prif,
+ &hdmitx_200m_mux,
+ &hdmitx_200m_div,
+ &hdmitx_200m,
+ &hdmitx_aud_mux,
+ &hdmitx_aud_div,
+ &hdmitx_aud,
+ &pwm_a_mux,
+ &pwm_a_div,
+ &pwm_a,
+ &pwm_b_mux,
+ &pwm_b_div,
+ &pwm_b,
+ &pwm_c_mux,
+ &pwm_c_div,
+ &pwm_c,
+ &pwm_d_mux,
+ &pwm_d_div,
+ &pwm_d,
+ &pwm_e_mux,
+ &pwm_e_div,
+ &pwm_e,
+ &pwm_f_mux,
+ &pwm_f_div,
+ &pwm_f,
+ &pwm_g_mux,
+ &pwm_g_div,
+ &pwm_g,
+ &pwm_h_mux,
+ &pwm_h_div,
+ &pwm_h,
+ &pwm_i_mux,
+ &pwm_i_div,
+ &pwm_i,
+ &pwm_j_mux,
+ &pwm_j_div,
+ &pwm_j,
+ &spicc0_mux,
+ &spicc0_div,
+ &spicc0,
+ &sd_emmc_a_mux,
+ &sd_emmc_a_div,
+ &sd_emmc_a,
+ &sd_emmc_b_mux,
+ &sd_emmc_b_div,
+ &sd_emmc_b,
+ &sd_emmc_c_mux,
+ &sd_emmc_c_div,
+ &sd_emmc_c,
+ &vdin_meas_mux,
+ &vdin_meas_div,
+ &vdin_meas,
+ &vid_lock_mux,
+ &vid_lock_div,
+ &vid_lock,
+ ð_clk_rmii_mux,
+ ð_clk_rmii_div,
+ ð_clk_rmii,
+ ð_clk125M,
+ &ts_div,
+ &ts,
+ &amfc_mux,
+ &amfc_div,
+ &amfc,
+ &csi2_adapt_mux,
+ &csi2_adapt_div,
+ &csi2_adapt,
+ &mipi_csi_phy_0_mux,
+ &mipi_csi_phy_0_div,
+ &mipi_csi_phy_0,
+ &mipi_csi_phy_1_mux,
+ &mipi_csi_phy_1_div,
+ &mipi_csi_phy_1,
+ &mipi_csi_phy,
+ &mipi_dsi_phy_mux,
+ &mipi_dsi_phy_div,
+ &mipi_dsi_phy,
+ &mipi_dsi_meas_mux,
+ &mipi_dsi_meas_div,
+ &mipi_dsi_meas,
+ &nna_mux,
+ &nna_div,
+ &nna,
+ &vc9000e_aclk_mux,
+ &vc9000e_aclk_div,
+ &vc9000e_aclk,
+ &vc9000e_core_mux,
+ &vc9000e_core_div,
+ &vc9000e_core,
+ &dspa_0_mux,
+ &dspa_0_div,
+ &dspa_0,
+ &dspa_1_mux,
+ &dspa_1_div,
+ &dspa_1,
+ &dspa,
+ &pcie_tl_mux,
+ &pcie_tl_div,
+ &pcie_tl,
+ &sys_am_axi,
+ &sys_dos,
+ &sys_vc9000e,
+ &sys_mipi_dsi,
+ &sys_ethphy,
+ &sys_amfc,
+ &sys_mali,
+ &sys_nna,
+ &sys_aocpu,
+ &sys_aucpu,
+ &sys_cec,
+ &sys_mipi_dsi_phy,
+ &sys_sd_emmc_a,
+ &sys_sd_emmc_b,
+ &sys_sd_emmc_c,
+ &sys_smartcard,
+ &sys_acodec,
+ &sys_msr_clk,
+ &sys_ir_ctrl,
+ &sys_audio,
+ &sys_eth,
+ &sys_uart_a,
+ &sys_uart_b,
+ &sys_uart_c,
+ &sys_uart_d,
+ &sys_uart_e,
+ &sys_ts_pll,
+ &sys_csi_dig_clkin,
+ &sys_ge2d,
+ &sys_spicc0,
+ &sys_pcie,
+ &sys_usb,
+ &sys_pcie_phy,
+ &sys_i2c_m_a,
+ &sys_i2c_m_b,
+ &sys_i2c_m_c,
+ &sys_i2c_m_d,
+ &sys_i2c_m_e,
+ &sys_hdmitx_apb,
+ &sys_i2c_s_a,
+ &sys_hdmi20_aes,
+ &sys_mmc_apb,
+ &sys_csi2_host,
+ &sys_csi2_adapt,
+ &sys_cpu_apb,
+ &sys_dspa,
+ &sys_vpu_intr,
+ &sys_csi2_phy0,
+ &sys_sar_adc,
+ &sys_pwm_j,
+ &sys_gic,
+ &sys_pwm_i,
+ &sys_pwm_h,
+ &sys_pwm_g,
+ &sys_pwm_f,
+ &sys_pwm_e,
+ &sys_pwm_d,
+ &sys_pwm_c,
+ &sys_pwm_b,
+ &sys_pwm_a,
+ &axi_ao_nic,
+ &axi_dev0_mmc,
+ &axi_cpu_sram,
+};
+
+static struct clk_hw_onecell_data hw_onecell_data = {
+ .hws = {
+ [CLKID_FIXED_PLL_VCO] = &fixed_pll_vco.hw,
+ [CLKID_FIXED_PLL] = &fixed_pll.hw,
+ [CLKID_GP0_PLL_VCO] = &gp0_pll_vco.hw,
+ [CLKID_GP0_PLL] = &gp0_pll.hw,
+ [CLKID_HIFI0_PLL_VCO] = &hifi0_pll_vco.hw,
+ [CLKID_HIFI0_PLL] = &hifi0_pll.hw,
+ [CLKID_HIFI1_PLL_VCO] = &hifi1_pll_vco.hw,
+ [CLKID_HIFI1_PLL] = &hifi1_pll.hw,
+ [CLKID_FCLK50M_DIV] = &fclk50m_div.hw,
+ [CLKID_FCLK50M] = &fclk50m.hw,
+ [CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw,
+ [CLKID_FCLK_DIV2] = &fclk_div2.hw,
+ [CLKID_FCLK_DIV2P5_DIV] = &fclk_div2p5_div.hw,
+ [CLKID_FCLK_DIV2P5] = &fclk_div2p5.hw,
+ [CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw,
+ [CLKID_FCLK_DIV3] = &fclk_div3.hw,
+ [CLKID_FCLK_DIV4_DIV] = &fclk_div4_div.hw,
+ [CLKID_FCLK_DIV4] = &fclk_div4.hw,
+ [CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw,
+ [CLKID_FCLK_DIV5] = &fclk_div5.hw,
+ [CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw,
+ [CLKID_FCLK_DIV7] = &fclk_div7.hw,
+ [CLKID_RTC_DUAL_CLKIN] = &rtc_dual_clkin.hw,
+ [CLKID_RTC_DUAL_DIV] = &rtc_dual_div.hw,
+ [CLKID_RTC_DUAL_MUX] = &rtc_dual_mux.hw,
+ [CLKID_RTC_DUAL] = &rtc_dual.hw,
+ [CLKID_RTC_CLK] = &rtc_clk.hw,
+ [CLKID_SYS_CLK_0_MUX] = &sys_clk_0_mux.hw,
+ [CLKID_SYS_CLK_0_DIV] = &sys_clk_0_div.hw,
+ [CLKID_SYS_CLK_0] = &sys_clk_0.hw,
+ [CLKID_SYS_CLK_1_MUX] = &sys_clk_1_mux.hw,
+ [CLKID_SYS_CLK_1_DIV] = &sys_clk_1_div.hw,
+ [CLKID_SYS_CLK_1] = &sys_clk_1.hw,
+ [CLKID_SYS_CLK] = &sys_clk.hw,
+ [CLKID_CLK_24M_IN] = &clk_24m_in.hw,
+ [CLKID_CLK_12M_DIV] = &clk_12m_div.hw,
+ [CLKID_CLK_12M] = &clk_12m.hw,
+ [CLKID_AXI_CLK_0_MUX] = &axi_clk_0_mux.hw,
+ [CLKID_AXI_CLK_0_DIV] = &axi_clk_0_div.hw,
+ [CLKID_AXI_CLK_0] = &axi_clk_0.hw,
+ [CLKID_AXI_CLK_1_MUX] = &axi_clk_1_mux.hw,
+ [CLKID_AXI_CLK_1_DIV] = &axi_clk_1_div.hw,
+ [CLKID_AXI_CLK_1] = &axi_clk_1.hw,
+ [CLKID_AXI_CLK] = &axi_clk.hw,
+ [CLKID_SAR_ADC_MUX] = &sar_adc_mux.hw,
+ [CLKID_SAR_ADC_DIV] = &sar_adc_div.hw,
+ [CLKID_SAR_ADC] = &sar_adc.hw,
+ [CLKID_CECB_DUAL_CLKIN] = &cecb_dual_clkin.hw,
+ [CLKID_CECB_DUAL_DIV] = &cecb_dual_div.hw,
+ [CLKID_CECB_DUAL_MUX] = &cecb_dual_mux.hw,
+ [CLKID_CECB_DUAL] = &cecb_dual.hw,
+ [CLKID_CECB_CLK] = &cecb_clk.hw,
+ [CLKID_SC_PRE_MUX] = &sc_pre_mux.hw,
+ [CLKID_SC_PRE_DIV] = &sc_pre_div.hw,
+ [CLKID_SC_PRE] = &sc_pre.hw,
+ [CLKID_SC_DIV] = &sc_div.hw,
+ [CLKID_CDAC_MUX] = &cdac_mux.hw,
+ [CLKID_CDAC_DIV] = &cdac_div.hw,
+ [CLKID_CDAC] = &cdac.hw,
+ [CLKID_HDMITX_PIXEL_MUX] = &hdmitx_pixel_mux.hw,
+ [CLKID_HDMITX_PIXEL] = &hdmitx_pixel.hw,
+ [CLKID_HDMITX_FE_MUX] = &hdmitx_fe_mux.hw,
+ [CLKID_HDMITX_FE] = &hdmitx_fe.hw,
+ [CLKID_VIDEO_SRC0_MUX] = &video_src0_mux.hw,
+ [CLKID_VIDEO_SRC0_DIV] = &video_src0_div.hw,
+ [CLKID_VIDEO_SRC0] = &video_src0.hw,
+ [CLKID_VIDEO_SRC1_MUX] = &video_src1_mux.hw,
+ [CLKID_VIDEO_SRC1_DIV] = &video_src1_div.hw,
+ [CLKID_VIDEO_SRC1] = &video_src1.hw,
+ [CLKID_VIDEO0_DIV1] = &video0_div1.hw,
+ [CLKID_VIDEO0_DIV2_GATE] = &video0_div2_gate.hw,
+ [CLKID_VIDEO0_DIV2] = &video0_div2.hw,
+ [CLKID_VIDEO0_DIV4_GATE] = &video0_div4_gate.hw,
+ [CLKID_VIDEO0_DIV4] = &video0_div4.hw,
+ [CLKID_VIDEO0_DIV6_GATE] = &video0_div6_gate.hw,
+ [CLKID_VIDEO0_DIV6] = &video0_div6.hw,
+ [CLKID_VIDEO0_DIV12_GATE] = &video0_div12_gate.hw,
+ [CLKID_VIDEO0_DIV12] = &video0_div12.hw,
+ [CLKID_VIDEO2_DIV1] = &video2_div1.hw,
+ [CLKID_VIDEO2_DIV2_GATE] = &video2_div2_gate.hw,
+ [CLKID_VIDEO2_DIV2] = &video2_div2.hw,
+ [CLKID_VIDEO2_DIV4_GATE] = &video2_div4_gate.hw,
+ [CLKID_VIDEO2_DIV4] = &video2_div4.hw,
+ [CLKID_VIDEO2_DIV6_GATE] = &video2_div6_gate.hw,
+ [CLKID_VIDEO2_DIV6] = &video2_div6.hw,
+ [CLKID_VIDEO2_DIV12_GATE] = &video2_div12_gate.hw,
+ [CLKID_VIDEO2_DIV12] = &video2_div12.hw,
+ [CLKID_LCD_AN_MUX] = &lcd_an_mux.hw,
+ [CLKID_LCD_AN_PH2] = &lcd_an_ph2.hw,
+ [CLKID_LCD_AN_PH3] = &lcd_an_ph3.hw,
+ [CLKID_ENCI_MUX] = &enci_mux.hw,
+ [CLKID_ENCI] = &enci.hw,
+ [CLKID_ENCP_MUX] = &encp_mux.hw,
+ [CLKID_ENCP] = &encp.hw,
+ [CLKID_ENCL_MUX] = &encl_mux.hw,
+ [CLKID_ENCL] = &encl.hw,
+ [CLKID_VDAC_MUX] = &vdac_mux.hw,
+ [CLKID_VDAC] = &vdac.hw,
+ [CLKID_MALI_0_MUX] = &mali_0_mux.hw,
+ [CLKID_MALI_0_DIV] = &mali_0_div.hw,
+ [CLKID_MALI_0] = &mali_0.hw,
+ [CLKID_MALI_1_MUX] = &mali_1_mux.hw,
+ [CLKID_MALI_1_DIV] = &mali_1_div.hw,
+ [CLKID_MALI_1] = &mali_1.hw,
+ [CLKID_MALI] = &mali.hw,
+ [CLKID_MALI_STACK_0_MUX] = &mali_stack_0_mux.hw,
+ [CLKID_MALI_STACK_0_DIV] = &mali_stack_0_div.hw,
+ [CLKID_MALI_STACK_0] = &mali_stack_0.hw,
+ [CLKID_MALI_STACK_1_MUX] = &mali_stack_1_mux.hw,
+ [CLKID_MALI_STACK_1_DIV] = &mali_stack_1_div.hw,
+ [CLKID_MALI_STACK_1] = &mali_stack_1.hw,
+ [CLKID_MALI_STACK] = &mali_stack.hw,
+ [CLKID_VDEC_0_MUX] = &vdec_0_mux.hw,
+ [CLKID_VDEC_0_DIV] = &vdec_0_div.hw,
+ [CLKID_VDEC_0] = &vdec_0.hw,
+ [CLKID_VDEC_1_MUX] = &vdec_1_mux.hw,
+ [CLKID_VDEC_1_DIV] = &vdec_1_div.hw,
+ [CLKID_VDEC_1] = &vdec_1.hw,
+ [CLKID_VDEC] = &vdec.hw,
+ [CLKID_HEVCF_0_MUX] = &hevcf_0_mux.hw,
+ [CLKID_HEVCF_0_DIV] = &hevcf_0_div.hw,
+ [CLKID_HEVCF_0] = &hevcf_0.hw,
+ [CLKID_HEVCF_1_MUX] = &hevcf_1_mux.hw,
+ [CLKID_HEVCF_1_DIV] = &hevcf_1_div.hw,
+ [CLKID_HEVCF_1] = &hevcf_1.hw,
+ [CLKID_HEVCF] = &hevcf.hw,
+ [CLKID_VPU_0_MUX] = &vpu_0_mux.hw,
+ [CLKID_VPU_0_DIV] = &vpu_0_div.hw,
+ [CLKID_VPU_0] = &vpu_0.hw,
+ [CLKID_VPU_1_MUX] = &vpu_1_mux.hw,
+ [CLKID_VPU_1_DIV] = &vpu_1_div.hw,
+ [CLKID_VPU_1] = &vpu_1.hw,
+ [CLKID_VPU] = &vpu.hw,
+ [CLKID_VPU_CLKB_TMP_MUX] = &vpu_clkb_tmp_mux.hw,
+ [CLKID_VPU_CLKB_TMP_DIV] = &vpu_clkb_tmp_div.hw,
+ [CLKID_VPU_CLKB_TMP] = &vpu_clkb_tmp.hw,
+ [CLKID_VPU_CLKB_DIV] = &vpu_clkb_div.hw,
+ [CLKID_VPU_CLKB] = &vpu_clkb.hw,
+ [CLKID_VPU_CLKC_0_MUX] = &vpu_clkc_0_mux.hw,
+ [CLKID_VPU_CLKC_0_DIV] = &vpu_clkc_0_div.hw,
+ [CLKID_VPU_CLKC_0] = &vpu_clkc_0.hw,
+ [CLKID_VPU_CLKC_1_MUX] = &vpu_clkc_1_mux.hw,
+ [CLKID_VPU_CLKC_1_DIV] = &vpu_clkc_1_div.hw,
+ [CLKID_VPU_CLKC_1] = &vpu_clkc_1.hw,
+ [CLKID_VPU_CLKC] = &vpu_clkc.hw,
+ [CLKID_VAPB_0_MUX] = &vapb_0_mux.hw,
+ [CLKID_VAPB_0_DIV] = &vapb_0_div.hw,
+ [CLKID_VAPB_0] = &vapb_0.hw,
+ [CLKID_VAPB_1_MUX] = &vapb_1_mux.hw,
+ [CLKID_VAPB_1_DIV] = &vapb_1_div.hw,
+ [CLKID_VAPB_1] = &vapb_1.hw,
+ [CLKID_VAPB] = &vapb.hw,
+ [CLKID_GE2D] = &ge2d.hw,
+ [CLKID_DEWARPA_MUX] = &dewarpa_mux.hw,
+ [CLKID_DEWARPA_DIV] = &dewarpa_div.hw,
+ [CLKID_DEWARPA] = &dewarpa.hw,
+ [CLKID_CMPR_MUX] = &cmpr_mux.hw,
+ [CLKID_CMPR_DIV] = &cmpr_div.hw,
+ [CLKID_CMPR] = &cmpr.hw,
+ [CLKID_HDMITX_SYS_MUX] = &hdmitx_sys_mux.hw,
+ [CLKID_HDMITX_SYS_DIV] = &hdmitx_sys_div.hw,
+ [CLKID_HDMITX_SYS] = &hdmitx_sys.hw,
+ [CLKID_HDMITX_PRIF_MUX] = &hdmitx_prif_mux.hw,
+ [CLKID_HDMITX_PRIF_DIV] = &hdmitx_prif_div.hw,
+ [CLKID_HDMITX_PRIF] = &hdmitx_prif.hw,
+ [CLKID_HDMITX_200M_MUX] = &hdmitx_200m_mux.hw,
+ [CLKID_HDMITX_200M_DIV] = &hdmitx_200m_div.hw,
+ [CLKID_HDMITX_200M] = &hdmitx_200m.hw,
+ [CLKID_HDMITX_AUD_MUX] = &hdmitx_aud_mux.hw,
+ [CLKID_HDMITX_AUD_DIV] = &hdmitx_aud_div.hw,
+ [CLKID_HDMITX_AUD] = &hdmitx_aud.hw,
+ [CLKID_PWM_A_MUX] = &pwm_a_mux.hw,
+ [CLKID_PWM_A_DIV] = &pwm_a_div.hw,
+ [CLKID_PWM_A] = &pwm_a.hw,
+ [CLKID_PWM_B_MUX] = &pwm_b_mux.hw,
+ [CLKID_PWM_B_DIV] = &pwm_b_div.hw,
+ [CLKID_PWM_B] = &pwm_b.hw,
+ [CLKID_PWM_C_MUX] = &pwm_c_mux.hw,
+ [CLKID_PWM_C_DIV] = &pwm_c_div.hw,
+ [CLKID_PWM_C] = &pwm_c.hw,
+ [CLKID_PWM_D_MUX] = &pwm_d_mux.hw,
+ [CLKID_PWM_D_DIV] = &pwm_d_div.hw,
+ [CLKID_PWM_D] = &pwm_d.hw,
+ [CLKID_PWM_E_MUX] = &pwm_e_mux.hw,
+ [CLKID_PWM_E_DIV] = &pwm_e_div.hw,
+ [CLKID_PWM_E] = &pwm_e.hw,
+ [CLKID_PWM_F_MUX] = &pwm_f_mux.hw,
+ [CLKID_PWM_F_DIV] = &pwm_f_div.hw,
+ [CLKID_PWM_F] = &pwm_f.hw,
+ [CLKID_PWM_G_MUX] = &pwm_g_mux.hw,
+ [CLKID_PWM_G_DIV] = &pwm_g_div.hw,
+ [CLKID_PWM_G] = &pwm_g.hw,
+ [CLKID_PWM_H_MUX] = &pwm_h_mux.hw,
+ [CLKID_PWM_H_DIV] = &pwm_h_div.hw,
+ [CLKID_PWM_H] = &pwm_h.hw,
+ [CLKID_PWM_I_MUX] = &pwm_i_mux.hw,
+ [CLKID_PWM_I_DIV] = &pwm_i_div.hw,
+ [CLKID_PWM_I] = &pwm_i.hw,
+ [CLKID_PWM_J_MUX] = &pwm_j_mux.hw,
+ [CLKID_PWM_J_DIV] = &pwm_j_div.hw,
+ [CLKID_PWM_J] = &pwm_j.hw,
+ [CLKID_SPICC0_MUX] = &spicc0_mux.hw,
+ [CLKID_SPICC0_DIV] = &spicc0_div.hw,
+ [CLKID_SPICC0] = &spicc0.hw,
+ [CLKID_SD_EMMC_A_MUX] = &sd_emmc_a_mux.hw,
+ [CLKID_SD_EMMC_A_DIV] = &sd_emmc_a_div.hw,
+ [CLKID_SD_EMMC_A] = &sd_emmc_a.hw,
+ [CLKID_SD_EMMC_B_MUX] = &sd_emmc_b_mux.hw,
+ [CLKID_SD_EMMC_B_DIV] = &sd_emmc_b_div.hw,
+ [CLKID_SD_EMMC_B] = &sd_emmc_b.hw,
+ [CLKID_SD_EMMC_C_MUX] = &sd_emmc_c_mux.hw,
+ [CLKID_SD_EMMC_C_DIV] = &sd_emmc_c_div.hw,
+ [CLKID_SD_EMMC_C] = &sd_emmc_c.hw,
+ [CLKID_VDIN_MEAS_MUX] = &vdin_meas_mux.hw,
+ [CLKID_VDIN_MEAS_DIV] = &vdin_meas_div.hw,
+ [CLKID_VDIN_MEAS] = &vdin_meas.hw,
+ [CLKID_VID_LOCK_MUX] = &vid_lock_mux.hw,
+ [CLKID_VID_LOCK_DIV] = &vid_lock_div.hw,
+ [CLKID_VID_LOCK] = &vid_lock.hw,
+ [CLKID_ETH_CLK_RMII_MUX] = ð_clk_rmii_mux.hw,
+ [CLKID_ETH_CLK_RMII_DIV] = ð_clk_rmii_div.hw,
+ [CLKID_ETH_CLK_RMII] = ð_clk_rmii.hw,
+ [CLKID_ETH_CLK125M_DIV] = ð_clk125M_div.hw,
+ [CLKID_ETH_CLK125M] = ð_clk125M.hw,
+ [CLKID_TS_DIV] = &ts_div.hw,
+ [CLKID_TS] = &ts.hw,
+ [CLKID_AMFC_MUX] = &amfc_mux.hw,
+ [CLKID_AMFC_DIV] = &amfc_div.hw,
+ [CLKID_AMFC] = &amfc.hw,
+ [CLKID_CSI2_ADAPT_MUX] = &csi2_adapt_mux.hw,
+ [CLKID_CSI2_ADAPT_DIV] = &csi2_adapt_div.hw,
+ [CLKID_CSI2_ADAPT] = &csi2_adapt.hw,
+ [CLKID_MIPI_CSI_PHY_0_MUX] = &mipi_csi_phy_0_mux.hw,
+ [CLKID_MIPI_CSI_PHY_0_DIV] = &mipi_csi_phy_0_div.hw,
+ [CLKID_MIPI_CSI_PHY_0] = &mipi_csi_phy_0.hw,
+ [CLKID_MIPI_CSI_PHY_1_MUX] = &mipi_csi_phy_1_mux.hw,
+ [CLKID_MIPI_CSI_PHY_1_DIV] = &mipi_csi_phy_1_div.hw,
+ [CLKID_MIPI_CSI_PHY_1] = &mipi_csi_phy_1.hw,
+ [CLKID_MIPI_CSI_PHY] = &mipi_csi_phy.hw,
+ [CLKID_MIPI_DSI_PHY_MUX] = &mipi_dsi_phy_mux.hw,
+ [CLKID_MIPI_DSI_PHY_DIV] = &mipi_dsi_phy_div.hw,
+ [CLKID_MIPI_DSI_PHY] = &mipi_dsi_phy.hw,
+ [CLKID_MIPI_DSI_MEAS_MUX] = &mipi_dsi_meas_mux.hw,
+ [CLKID_MIPI_DSI_MEAS_DIV] = &mipi_dsi_meas_div.hw,
+ [CLKID_MIPI_DSI_MEAS] = &mipi_dsi_meas.hw,
+ [CLKID_NNA_MUX] = &nna_mux.hw,
+ [CLKID_NNA_DIV] = &nna_div.hw,
+ [CLKID_NNA] = &nna.hw,
+ [CLKID_VC9000E_ACLK_MUX] = &vc9000e_aclk_mux.hw,
+ [CLKID_VC9000E_ACLK_DIV] = &vc9000e_aclk_div.hw,
+ [CLKID_VC9000E_ACLK] = &vc9000e_aclk.hw,
+ [CLKID_VC9000E_CORE_MUX] = &vc9000e_core_mux.hw,
+ [CLKID_VC9000E_CORE_DIV] = &vc9000e_core_div.hw,
+ [CLKID_VC9000E_CORE] = &vc9000e_core.hw,
+ [CLKID_DSPA_0_MUX] = &dspa_0_mux.hw,
+ [CLKID_DSPA_0_DIV] = &dspa_0_div.hw,
+ [CLKID_DSPA_0] = &dspa_0.hw,
+ [CLKID_DSPA_1_MUX] = &dspa_1_mux.hw,
+ [CLKID_DSPA_1_DIV] = &dspa_1_div.hw,
+ [CLKID_DSPA_1] = &dspa_1.hw,
+ [CLKID_DSPA] = &dspa.hw,
+ [CLKID_PCIE_TL_MUX] = &pcie_tl_mux.hw,
+ [CLKID_PCIE_TL_DIV] = &pcie_tl_div.hw,
+ [CLKID_PCIE_TL] = &pcie_tl.hw,
+ [CLKID_SYS_AM_AXI] = &sys_am_axi.hw,
+ [CLKID_SYS_DOS] = &sys_dos.hw,
+ [CLKID_SYS_VC9000E] = &sys_vc9000e.hw,
+ [CLKID_SYS_MIPI_DSI] = &sys_mipi_dsi.hw,
+ [CLKID_SYS_ETHPHY] = &sys_ethphy.hw,
+ [CLKID_SYS_AMFC] = &sys_amfc.hw,
+ [CLKID_SYS_MALI] = &sys_mali.hw,
+ [CLKID_SYS_NNA] = &sys_nna.hw,
+ [CLKID_SYS_AOCPU] = &sys_aocpu.hw,
+ [CLKID_SYS_AUCPU] = &sys_aucpu.hw,
+ [CLKID_SYS_CEC] = &sys_cec.hw,
+ [CLKID_SYS_MIPI_DSI_PHY] = &sys_mipi_dsi_phy.hw,
+ [CLKID_SYS_SD_EMMC_A] = &sys_sd_emmc_a.hw,
+ [CLKID_SYS_SD_EMMC_B] = &sys_sd_emmc_b.hw,
+ [CLKID_SYS_SD_EMMC_C] = &sys_sd_emmc_c.hw,
+ [CLKID_SYS_SMARTCARD] = &sys_smartcard.hw,
+ [CLKID_SYS_ACODEC] = &sys_acodec.hw,
+ [CLKID_SYS_MSR_CLK] = &sys_msr_clk.hw,
+ [CLKID_SYS_IR_CTRL] = &sys_ir_ctrl.hw,
+ [CLKID_SYS_AUDIO] = &sys_audio.hw,
+ [CLKID_SYS_ETH] = &sys_eth.hw,
+ [CLKID_SYS_UART_A] = &sys_uart_a.hw,
+ [CLKID_SYS_UART_B] = &sys_uart_b.hw,
+ [CLKID_SYS_UART_C] = &sys_uart_c.hw,
+ [CLKID_SYS_UART_D] = &sys_uart_d.hw,
+ [CLKID_SYS_UART_E] = &sys_uart_e.hw,
+ [CLKID_SYS_TS_PLL] = &sys_ts_pll.hw,
+ [CLKID_SYS_CSI_DIG_CLKIN] = &sys_csi_dig_clkin.hw,
+ [CLKID_SYS_GE2D] = &sys_ge2d.hw,
+ [CLKID_SYS_SPICC0] = &sys_spicc0.hw,
+ [CLKID_SYS_PCIE] = &sys_pcie.hw,
+ [CLKID_SYS_USB] = &sys_usb.hw,
+ [CLKID_SYS_PCIE_PHY] = &sys_pcie_phy.hw,
+ [CLKID_SYS_I2C_M_A] = &sys_i2c_m_a.hw,
+ [CLKID_SYS_I2C_M_B] = &sys_i2c_m_b.hw,
+ [CLKID_SYS_I2C_M_C] = &sys_i2c_m_c.hw,
+ [CLKID_SYS_I2C_M_D] = &sys_i2c_m_d.hw,
+ [CLKID_SYS_I2C_M_E] = &sys_i2c_m_e.hw,
+ [CLKID_SYS_HDMITX_APB] = &sys_hdmitx_apb.hw,
+ [CLKID_SYS_I2C_S_A] = &sys_i2c_s_a.hw,
+ [CLKID_SYS_HDMI20_AES] = &sys_hdmi20_aes.hw,
+ [CLKID_SYS_MMC_APB] = &sys_mmc_apb.hw,
+ [CLKID_SYS_CSI2_HOST] = &sys_csi2_host.hw,
+ [CLKID_SYS_CSI2_ADAPT] = &sys_csi2_adapt.hw,
+ [CLKID_SYS_CPU_APB] = &sys_cpu_apb.hw,
+ [CLKID_SYS_DSPA] = &sys_dspa.hw,
+ [CLKID_SYS_VPU_INTR] = &sys_vpu_intr.hw,
+ [CLKID_SYS_CSI2_PHY0] = &sys_csi2_phy0.hw,
+ [CLKID_SYS_SAR_ADC] = &sys_sar_adc.hw,
+ [CLKID_SYS_PWM_J] = &sys_pwm_j.hw,
+ [CLKID_SYS_GIC] = &sys_gic.hw,
+ [CLKID_SYS_PWM_I] = &sys_pwm_i.hw,
+ [CLKID_SYS_PWM_H] = &sys_pwm_h.hw,
+ [CLKID_SYS_PWM_G] = &sys_pwm_g.hw,
+ [CLKID_SYS_PWM_F] = &sys_pwm_f.hw,
+ [CLKID_SYS_PWM_E] = &sys_pwm_e.hw,
+ [CLKID_SYS_PWM_D] = &sys_pwm_d.hw,
+ [CLKID_SYS_PWM_C] = &sys_pwm_c.hw,
+ [CLKID_SYS_PWM_B] = &sys_pwm_b.hw,
+ [CLKID_SYS_PWM_A] = &sys_pwm_a.hw,
+ [CLKID_AXI_AO_NIC] = &axi_ao_nic.hw,
+ [CLKID_AXI_DEV0_MMC] = &axi_dev0_mmc.hw,
+ [CLKID_AXI_CPU_SRAM] = &axi_cpu_sram.hw,
+ [NR_CLKS] = NULL
+ },
+ .num = NR_CLKS,
+};
+
+static int meson_s6_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct regmap *basic_map;
+ struct regmap *pll_map;
+ const struct clk_hw_onecell_data *hw_onecell_data;
+ struct clk *clk;
+ int ret, i;
+
+ hw_onecell_data = of_device_get_match_data(&pdev->dev);
+ if (!hw_onecell_data)
+ return -EINVAL;
+ pr_info("");
+ clk = devm_clk_get(dev, "xtal");
+ if (IS_ERR(clk)) {
+ pr_err("%s: clock source xtal not found\n", dev_name(&pdev->dev));
+ return PTR_ERR(clk);
+ }
+
+#ifdef CONFIG_AMLOGIC_CLK_DEBUG
+ ret = devm_clk_hw_register_clkdev(dev, __clk_get_hw(clk),
+ NULL,
+ __clk_get_name(clk));
+ if (ret < 0) {
+ dev_err(dev, "Failed to clkdev register: %d\n", ret);
+ return ret;
+ }
+#endif
+
+ basic_map = meson_clk_regmap_resource(pdev, dev, 0);
+ if (IS_ERR(basic_map)) {
+ dev_err(dev, "basic clk registers not found\n");
+ return PTR_ERR(basic_map);
+ }
+
+ pll_map = meson_clk_regmap_resource(pdev, dev, 1);
+ if (IS_ERR(pll_map)) {
+ dev_err(dev, "pll clk registers not found\n");
+ return PTR_ERR(pll_map);
+ }
+
+ /* Populate regmap for the regmap backed clocks */
+ for (i = 0; i < ARRAY_SIZE(clk_regmaps); i++)
+ clk_regmaps[i]->map = basic_map;
+
+ for (i = 0; i < ARRAY_SIZE(pll_regmaps); i++)
+ pll_regmaps[i]->map = pll_map;
+
+ for (i = 0; i < hw_onecell_data->num; i++) {
+ /* array might be sparse */
+ if (!hw_onecell_data->hws[i])
+ continue;
+
+ //dev_err(dev, "register %d %s\n", i,
+ // hw_onecell_data->hws[i]->init->name);
+
+ ret = devm_clk_hw_register(dev, hw_onecell_data->hws[i]);
+ if (ret) {
+ dev_err(dev, "Clock registration failed\n");
+ return ret;
+ }
+
+#ifdef CONFIG_AMLOGIC_CLK_DEBUG
+ ret = devm_clk_hw_register_clkdev(dev, hw_onecell_data->hws[i],
+ NULL,
+ clk_hw_get_name(hw_onecell_data->hws[i]));
+ if (ret < 0) {
+ dev_err(dev, "Failed to clkdev register: %d\n", ret);
+ return ret;
+ }
+#endif
+ }
+
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+ (void *)hw_onecell_data);
+}
+
+static const struct of_device_id clkc_match_table[] = {
+ {
+ .compatible = "amlogic,s6-clkc",
+ .data = &hw_onecell_data
+ },
+ {}
+};
+
+static struct platform_driver s6_driver = {
+ .probe = meson_s6_probe,
+ .driver = {
+ .name = "s6-clkc",
+ .of_match_table = clkc_match_table,
+ },
+};
+
+builtin_platform_driver(s6_driver);
+
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/meson/s6.h b/drivers/clk/meson/s6.h
new file mode 100644
index 0000000..40a091d
--- /dev/null
+++ b/drivers/clk/meson/s6.h
@@ -0,0 +1,200 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __S6_H
+#define __S6_H
+
+/*
+ * Clock controller register offsets
+ * REG_BASE: REGISTER_BASE_ADDR = 0xfe000000
+ */
+#define CLKCTRL_OSCIN_CTRL (0x0001 << 2)
+#define CLKCTRL_RTC_BY_OSCIN_CTRL0 (0x0002 << 2)
+#define CLKCTRL_RTC_BY_OSCIN_CTRL1 (0x0003 << 2)
+#define CLKCTRL_RTC_CTRL (0x0004 << 2)
+#define CLKCTRL_CHECK_CLK_RESULT (0x0005 << 2)
+#define CLKCTRL_MBIST_ATSPEED_CTRL (0x0006 << 2)
+#define CLKCTRL_LOCK_BIT_REG0 (0x0008 << 2)
+#define CLKCTRL_LOCK_BIT_REG1 (0x0009 << 2)
+#define CLKCTRL_LOCK_BIT_REG2 (0x000a << 2)
+#define CLKCTRL_LOCK_BIT_REG3 (0x000b << 2)
+#define CLKCTRL_PROT_BIT_REG0 (0x000c << 2)
+#define CLKCTRL_PROT_BIT_REG1 (0x000d << 2)
+#define CLKCTRL_PROT_BIT_REG2 (0x000e << 2)
+#define CLKCTRL_PROT_BIT_REG3 (0x000f << 2)
+#define CLKCTRL_SYS_CLK_CTRL0 (0x0010 << 2)
+#define CLKCTRL_SYS_CLK_EN0_REG0 (0x0011 << 2)
+#define CLKCTRL_SYS_CLK_EN0_REG1 (0x0012 << 2)
+#define CLKCTRL_SYS_CLK_EN0_REG2 (0x0013 << 2)
+#define CLKCTRL_SYS_CLK_EN0_REG3 (0x0014 << 2)
+#define CLKCTRL_SYS_CLK_EN1_REG0 (0x0015 << 2)
+#define CLKCTRL_SYS_CLK_EN1_REG1 (0x0016 << 2)
+#define CLKCTRL_SYS_CLK_EN1_REG2 (0x0017 << 2)
+#define CLKCTRL_SYS_CLK_EN1_REG3 (0x0018 << 2)
+#define CLKCTRL_SYS_CLK_VPU_EN0 (0x0019 << 2)
+#define CLKCTRL_SYS_CLK_VPU_EN1 (0x001a << 2)
+#define CLKCTRL_AXI_CLK_CTRL0 (0x001b << 2)
+#define CLKCTRL_TST_CTRL0 (0x0020 << 2)
+#define CLKCTRL_TST_CTRL1 (0x0021 << 2)
+#define CLKCTRL_CECB_CTRL0 (0x0024 << 2)
+#define CLKCTRL_CECB_CTRL1 (0x0025 << 2)
+#define CLKCTRL_SC_CLK_CTRL (0x0026 << 2)
+#define CLKCTRL_DSPA_CLK_CTRL0 (0x0027 << 2)
+#define CLKCTRL_RAMA_CLK_CTRL0 (0x0029 << 2)
+#define CLKCTRL_CLK12_24_CTRL (0x002a << 2)
+#define CLKCTRL_AXI_CLK_EN0 (0x002b << 2)
+#define CLKCTRL_AXI_CLK_EN1 (0x002c << 2)
+#define CLKCTRL_VID_CLK_CTRL (0x0030 << 2)
+#define CLKCTRL_VID_CLK_CTRL2 (0x0031 << 2)
+#define CLKCTRL_VID_CLK_DIV (0x0032 << 2)
+#define CLKCTRL_VIID_CLK_DIV (0x0033 << 2)
+#define CLKCTRL_VIID_CLK_CTRL (0x0034 << 2)
+#define CLKCTRL_HDMI_CLK_CTRL (0x0038 << 2)
+#define CLKCTRL_VID_PLL_CLK_DIV (0x0039 << 2)
+#define CLKCTRL_VPU_CLK_CTRL (0x003a << 2)
+#define CLKCTRL_VPU_CLKB_CTRL (0x003b << 2)
+#define CLKCTRL_VPU_CLKC_CTRL (0x003c << 2)
+#define CLKCTRL_VID_LOCK_CLK_CTRL (0x003d << 2)
+#define CLKCTRL_VDIN_MEAS_CLK_CTRL (0x003e << 2)
+#define CLKCTRL_VAPBCLK_CTRL (0x003f << 2)
+#define CLKCTRL_MIPIDSI_PHY_CLK_CTRL (0x0041 << 2)
+#define CLKCTRL_CDAC_CLK_CTRL (0x0042 << 2)
+#define CLKCTRL_MIPI_CSI_PHY_CLK_CTRL (0x0043 << 2)
+#define CLKCTRL_CSI2_ADAPT_CLK_CTRL (0x0044 << 2)
+#define CLKCTRL_DSI_PLL_CLK_DIV (0x0045 << 2)
+#define CLKCTRL_HTX_CLK_CTRL0 (0x0047 << 2)
+#define CLKCTRL_HTX_CLK_CTRL1 (0x0048 << 2)
+#define CLKCTRL_VDEC_CLK_CTRL (0x0050 << 2)
+#define CLKCTRL_VDEC2_CLK_CTRL (0x0051 << 2)
+#define CLKCTRL_VDEC3_CLK_CTRL (0x0052 << 2)
+#define CLKCTRL_VDEC4_CLK_CTRL (0x0053 << 2)
+#define CLKCTRL_TS_CLK_CTRL (0x0056 << 2)
+#define CLKCTRL_MALI_CLK_CTRL (0x0057 << 2)
+#define CLKCTRL_MALI_STACK_CLK_CTRL (0x0058 << 2)
+#define CLKCTRL_ETH_CLK_CTRL (0x0059 << 2)
+#define CLKCTRL_NAND_CLK_CTRL (0x005a << 2)
+#define CLKCTRL_SD_EMMC_CLK_CTRL (0x005b << 2)
+#define CLKCTRL_SPICC_CLK_CTRL (0x005d << 2)
+#define CLKCTRL_GEN_CLK_CTRL (0x005e << 2)
+#define CLKCTRL_SAR_CLK_CTRL0 (0x005f << 2)
+#define CLKCTRL_PWM_CLK_AB_CTRL (0x0060 << 2)
+#define CLKCTRL_PWM_CLK_CD_CTRL (0x0061 << 2)
+#define CLKCTRL_PWM_CLK_EF_CTRL (0x0062 << 2)
+#define CLKCTRL_PWM_CLK_GH_CTRL (0x0063 << 2)
+#define CLKCTRL_PWM_CLK_IJ_CTRL (0x0064 << 2)
+#define CLKCTRL_AMFC_CLK_CTRL (0x0065 << 2)
+#define CLKCTRL_VC9000E_CLK_CTRL (0x0066 << 2)
+#define CLKCTRL_NNA_CLK_CTRL (0x0067 << 2)
+#define CLKCTRL_USB_CLK_CTRL (0x0068 << 2)
+#define CLKCTRL_PCIE_CLK_CTRL (0x0069 << 2)
+#define CLKCTRL_CMPR_CLK_CTRL (0x006a << 2)
+#define CLKCTRL_DEWARPA_CLK_CTRL (0x006b << 2)
+#define CLKCTRL_TIMESTAMP_CTRL (0x0100 << 2)
+#define CLKCTRL_TIMESTAMP_CTRL1 (0x0101 << 2)
+#define CLKCTRL_TIMESTAMP_CTRL2 (0x0103 << 2)
+#define CLKCTRL_TIMESTAMP_RD0 (0x0104 << 2)
+#define CLKCTRL_TIMESTAMP_RD1 (0x0105 << 2)
+#define CLKCTRL_TIMEBASE_CTRL0 (0x0106 << 2)
+#define CLKCTRL_TIMEBASE_CTRL1 (0x0107 << 2)
+#define CLKCTRL_EFUSE_CPU_CFG01 (0x0120 << 2)
+#define CLKCTRL_EFUSE_CPU_CFG2 (0x0121 << 2)
+#define CLKCTRL_EFUSE_ENCP_CFG0 (0x0122 << 2)
+#define CLKCTRL_EFUSE_MALI_CFG01 (0x0123 << 2)
+#define CLKCTRL_EFUSE_HEVCB_CFG01 (0x0124 << 2)
+#define CLKCTRL_EFUSE_HEVCB_CFG2 (0x0125 << 2)
+#define CLKCTRL_EFUSE_LOCK (0x0126 << 2)
+#define CLKCTRL_EFUSE_MALI_STACK_CFG01 (0x0127 << 2)
+
+/* ANA_CTRL - Registers
+ *REG_BASE: REGISTER_BASE_ADDR = 0xfe008000
+ */
+#define ANACTRL_SYS0PLL_CTRL0 (0x0000 << 2)
+#define ANACTRL_SYS0PLL_CTRL1 (0x0001 << 2)
+#define ANACTRL_SYS0PLL_CTRL2 (0x0002 << 2)
+#define ANACTRL_SYS0PLL_CTRL3 (0x0003 << 2)
+#define ANACTRL_SYS1PLL_CTRL0 (0x0004 << 2)
+#define ANACTRL_SYS1PLL_CTRL1 (0x0005 << 2)
+#define ANACTRL_SYS1PLL_CTRL2 (0x0006 << 2)
+#define ANACTRL_SYS1PLL_CTRL3 (0x0007 << 2)
+#define ANACTRL_SYS0PLL_STS (0x0008 << 2)
+#define ANACTRL_SYS1PLL_STS (0x0009 << 2)
+#define ANACTRL_FIXPLL_CTRL0 (0x0010 << 2)
+#define ANACTRL_FIXPLL_CTRL1 (0x0011 << 2)
+#define ANACTRL_FIXPLL_CTRL2 (0x0012 << 2)
+#define ANACTRL_FIXPLL_CTRL3 (0x0013 << 2)
+#define ANACTRL_FIXPLL_CTRL4 (0x0014 << 2)
+#define ANACTRL_FIXPLL_STS (0x0017 << 2)
+#define ANACTRL_GP0PLL_CTRL0 (0x0020 << 2)
+#define ANACTRL_GP0PLL_CTRL1 (0x0021 << 2)
+#define ANACTRL_GP0PLL_CTRL2 (0x0022 << 2)
+#define ANACTRL_GP0PLL_CTRL3 (0x0023 << 2)
+#define ANACTRL_GP0PLL_CTRL4 (0x0024 << 2)
+#define ANACTRL_GP0PLL_STS (0x0027 << 2)
+#define ANACTRL_GP1PLL_CTRL0 (0x0030 << 2)
+#define ANACTRL_GP1PLL_CTRL1 (0x0031 << 2)
+#define ANACTRL_GP1PLL_CTRL2 (0x0032 << 2)
+#define ANACTRL_GP1PLL_CTRL3 (0x0033 << 2)
+#define ANACTRL_GP1PLL_STS (0x0037 << 2)
+#define ANACTRL_GP2PLL_CTRL0 (0x0050 << 2)
+#define ANACTRL_GP2PLL_CTRL1 (0x0051 << 2)
+#define ANACTRL_GP2PLL_CTRL2 (0x0052 << 2)
+#define ANACTRL_GP2PLL_CTRL3 (0x0053 << 2)
+#define ANACTRL_GP2PLL_STS (0x0057 << 2)
+#define ANACTRL_HIFI0PLL_CTRL0 (0x0040 << 2)
+#define ANACTRL_HIFI0PLL_CTRL1 (0x0041 << 2)
+#define ANACTRL_HIFI0PLL_CTRL2 (0x0042 << 2)
+#define ANACTRL_HIFI0PLL_CTRL3 (0x0043 << 2)
+#define ANACTRL_HIFI0PLL_CTRL4 (0x0044 << 2)
+#define ANACTRL_HIFI1PLL_CTRL0 (0x0045 << 2)
+#define ANACTRL_HIFI1PLL_CTRL1 (0x0046 << 2)
+#define ANACTRL_HIFI1PLL_CTRL2 (0x0047 << 2)
+#define ANACTRL_HIFI1PLL_CTRL3 (0x0048 << 2)
+#define ANACTRL_HIFI1PLL_CTRL4 (0x0049 << 2)
+#define ANACTRL_HIFI0PLL_STS (0x004a << 2)
+#define ANACTRL_HIFI1PLL_STS (0x004b << 2)
+#define ANACTRL_HDMIPLL_CTRL0 (0x0070 << 2)
+#define ANACTRL_HDMIPLL_CTRL1 (0x0071 << 2)
+#define ANACTRL_HDMIPLL_CTRL2 (0x0072 << 2)
+#define ANACTRL_HDMIPLL_CTRL3 (0x0073 << 2)
+#define ANACTRL_HDMIPLL_STS (0x0077 << 2)
+#define ANACTRL_HDMIPLL_VLOCK (0x0079 << 2)
+#define ANACTRL_HDMIPHY_CTRL0 (0x0080 << 2)
+#define ANACTRL_HDMIPHY_CTRL1 (0x0081 << 2)
+#define ANACTRL_HDMIPHY_CTRL2 (0x0082 << 2)
+#define ANACTRL_HDMIPHY_CTRL3 (0x0083 << 2)
+#define ANACTRL_HDMIPHY_CTRL4 (0x0084 << 2)
+#define ANACTRL_HDMIPHY_CTRL5 (0x0085 << 2)
+#define ANACTRL_HDMIPHY_STS (0x0086 << 2)
+#define ANACTRL_MIPICSI_CTRL0 (0x0090 << 2)
+#define ANACTRL_MIPICSI_CTRL1 (0x0091 << 2)
+#define ANACTRL_MIPICSI_CTRL2 (0x0092 << 2)
+#define ANACTRL_MIPICSI_CTRL3 (0x0093 << 2)
+#define ANACTRL_MIPICSI_CTRL4 (0x0094 << 2)
+#define ANACTRL_MIPICSI_CTRL5 (0x0095 << 2)
+#define ANACTRL_MIPICSI_CTRL6 (0x0096 << 2)
+#define ANACTRL_MIPICSI_CTRL7 (0x0097 << 2)
+#define ANACTRL_CSIPLL_CTRL0 (0x0098 << 2)
+#define ANACTRL_CSIPLL_CTRL1 (0x0099 << 2)
+#define ANACTRL_CSIPLL_CTRL2 (0x009a << 2)
+#define ANACTRL_CSIPLL_CTRL3 (0x009b << 2)
+#define ANACTRL_CSIPLL_STS (0x009c << 2)
+#define ANACTRL_VDAC_CTRL0 (0x00b0 << 2)
+#define ANACTRL_VDAC_CTRL1 (0x00b1 << 2)
+#define ANACTRL_POR_CTRL (0x00b6 << 2)
+#define ANACTRL_LOCK_BIT (0x00b8 << 2)
+#define ANACTRL_PROT_BIT (0x00b9 << 2)
+#define ANACTRL_DDR_LDO_CTRL (0x00d3 << 2)
+#define ANACTRL_MISC_PZQ_CTRL (0x00d4 << 2)
+#define ANACTRL_CHIP_TEST_STS0 (0x00e0 << 2)
+#define ANACTRL_CHIP_TEST_STS1 (0x00e1 << 2)
+#define ANACTRL_DSIPLL_CTRL0 (0x00f0 << 2)
+#define ANACTRL_DSIPLL_CTRL1 (0x00f1 << 2)
+#define ANACTRL_DSIPLL_CTRL2 (0x00f2 << 2)
+#define ANACTRL_DSIPLL_CTRL3 (0x00f3 << 2)
+#define ANACTRL_DSIPLL_STS (0x00f4 << 2)
+#define ANACTRL_MIPIDSI_CTRL0 (0x00f5 << 2)
+#define ANACTRL_MIPIDSI_CTRL1 (0x00f6 << 2)
+
+#endif /* __S6_H */
diff --git a/include/dt-bindings/clock/s6-clkc.h b/include/dt-bindings/clock/s6-clkc.h
index 3c505ea..d88b588 100644
--- a/include/dt-bindings/clock/s6-clkc.h
+++ b/include/dt-bindings/clock/s6-clkc.h
@@ -3,306 +3,337 @@
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
-#ifndef __S7D_CLKC_H
-#define __S7D_CLKC_H
+#ifndef __S6_CLKC_H
+#define __S6_CLKC_H
-/*
- * CLKID index values
- */
-#define CLKID_PLL_BASE 0
-#define CLKID_FIXED_PLL_DCO (CLKID_PLL_BASE + 0)
-#define CLKID_FIXED_PLL (CLKID_PLL_BASE + 1)
-#define CLKID_FCLK_DIV2_DIV (CLKID_PLL_BASE + 2)
-#define CLKID_FCLK_DIV2 (CLKID_PLL_BASE + 3)
-#define CLKID_FCLK_DIV3_DIV (CLKID_PLL_BASE + 4)
-#define CLKID_FCLK_DIV3 (CLKID_PLL_BASE + 5)
-#define CLKID_FCLK_DIV4_DIV (CLKID_PLL_BASE + 6)
-#define CLKID_FCLK_DIV4 (CLKID_PLL_BASE + 7)
-#define CLKID_FCLK_DIV5_DIV (CLKID_PLL_BASE + 8)
-#define CLKID_FCLK_DIV5 (CLKID_PLL_BASE + 9)
-#define CLKID_FCLK_DIV7_DIV (CLKID_PLL_BASE + 10)
-#define CLKID_FCLK_DIV7 (CLKID_PLL_BASE + 11)
-#define CLKID_FCLK_DIV2P5_DIV (CLKID_PLL_BASE + 12)
-#define CLKID_FCLK_DIV2P5 (CLKID_PLL_BASE + 13)
-#define CLKID_FCLK_CLK50M_DIV (CLKID_PLL_BASE + 14)
-#define CLKID_FCLK_CLK50M (CLKID_PLL_BASE + 15)
-#define CLKID_GP0_PLL_DCO (CLKID_PLL_BASE + 16)
-#define CLKID_GP0_PLL (CLKID_PLL_BASE + 17)
-#define CLKID_GP1_PLL_DCO (CLKID_PLL_BASE + 18)
-#define CLKID_GP1_PLL (CLKID_PLL_BASE + 19)
-#define CLKID_HIFI_PLL_DCO (CLKID_PLL_BASE + 20)
-#define CLKID_HIFI_PLL (CLKID_PLL_BASE + 21)
-#define CLKID_HIFI1_PLL_DCO (CLKID_PLL_BASE + 22)
-#define CLKID_HIFI1_PLL (CLKID_PLL_BASE + 23)
+#define CLKID_FIXED_PLL_VCO 0
+#define CLKID_FIXED_PLL 1
+#define CLKID_GP0_PLL_VCO 2
+#define CLKID_GP0_PLL 3
+#define CLKID_HIFI0_PLL_VCO 4
+#define CLKID_HIFI0_PLL 5
+#define CLKID_HIFI1_PLL_VCO 6
+#define CLKID_HIFI1_PLL 7
+#define CLKID_FCLK50M_DIV 8
+#define CLKID_FCLK50M 9
+#define CLKID_FCLK_DIV2_DIV 10
+#define CLKID_FCLK_DIV2 11
+#define CLKID_FCLK_DIV2P5_DIV 12
+#define CLKID_FCLK_DIV2P5 13
+#define CLKID_FCLK_DIV3_DIV 14
+#define CLKID_FCLK_DIV3 15
+#define CLKID_FCLK_DIV4_DIV 16
+#define CLKID_FCLK_DIV4 17
+#define CLKID_FCLK_DIV5_DIV 18
+#define CLKID_FCLK_DIV5 19
+#define CLKID_FCLK_DIV7_DIV 20
+#define CLKID_FCLK_DIV7 21
+#define CLKID_RTC_DUAL_CLKIN 22
+#define CLKID_RTC_DUAL_DIV 23
+#define CLKID_RTC_DUAL_MUX 24
+#define CLKID_RTC_DUAL 25
+#define CLKID_RTC_CLK 26
+#define CLKID_SYS_CLK_0_MUX 27
+#define CLKID_SYS_CLK_0_DIV 28
+#define CLKID_SYS_CLK_0 29
+#define CLKID_SYS_CLK_1_MUX 30
+#define CLKID_SYS_CLK_1_DIV 31
+#define CLKID_SYS_CLK_1 32
+#define CLKID_SYS_CLK 33
+#define CLKID_CLK_24M_IN 34
+#define CLKID_CLK_12M_DIV 35
+#define CLKID_CLK_12M 36
+#define CLKID_AXI_CLK_0_MUX 37
+#define CLKID_AXI_CLK_0_DIV 38
+#define CLKID_AXI_CLK_0 39
+#define CLKID_AXI_CLK_1_MUX 40
+#define CLKID_AXI_CLK_1_DIV 41
+#define CLKID_AXI_CLK_1 42
+#define CLKID_AXI_CLK 43
+#define CLKID_SAR_ADC_MUX 44
+#define CLKID_SAR_ADC_DIV 45
+#define CLKID_SAR_ADC 46
+#define CLKID_CECB_DUAL_CLKIN 47
+#define CLKID_CECB_DUAL_DIV 48
+#define CLKID_CECB_DUAL_MUX 49
+#define CLKID_CECB_DUAL 50
+#define CLKID_CECB_CLK 51
+#define CLKID_SC_PRE_MUX 52
+#define CLKID_SC_PRE_DIV 53
+#define CLKID_SC_PRE 54
+#define CLKID_SC_DIV 55
+#define CLKID_CDAC_MUX 56
+#define CLKID_CDAC_DIV 57
+#define CLKID_CDAC 58
+#define CLKID_HDMITX_PIXEL_MUX 59
+#define CLKID_HDMITX_PIXEL 60
+#define CLKID_HDMITX_FE_MUX 61
+#define CLKID_HDMITX_FE 62
+#define CLKID_VIDEO_SRC0_MUX 63
+#define CLKID_VIDEO_SRC0_DIV 64
+#define CLKID_VIDEO_SRC0 65
+#define CLKID_VIDEO_SRC1_MUX 66
+#define CLKID_VIDEO_SRC1_DIV 67
+#define CLKID_VIDEO_SRC1 68
+#define CLKID_VIDEO0_DIV1 69
+#define CLKID_VIDEO0_DIV2_GATE 70
+#define CLKID_VIDEO0_DIV2 71
+#define CLKID_VIDEO0_DIV4_GATE 72
+#define CLKID_VIDEO0_DIV4 73
+#define CLKID_VIDEO0_DIV6_GATE 74
+#define CLKID_VIDEO0_DIV6 75
+#define CLKID_VIDEO0_DIV12_GATE 76
+#define CLKID_VIDEO0_DIV12 77
+#define CLKID_VIDEO2_DIV1 78
+#define CLKID_VIDEO2_DIV2_GATE 79
+#define CLKID_VIDEO2_DIV2 80
+#define CLKID_VIDEO2_DIV4_GATE 81
+#define CLKID_VIDEO2_DIV4 82
+#define CLKID_VIDEO2_DIV6_GATE 83
+#define CLKID_VIDEO2_DIV6 84
+#define CLKID_VIDEO2_DIV12_GATE 85
+#define CLKID_VIDEO2_DIV12 86
+#define CLKID_LCD_AN_MUX 87
+#define CLKID_LCD_AN_PH2 88
+#define CLKID_LCD_AN_PH3 89
+#define CLKID_ENCI_MUX 90
+#define CLKID_ENCI 91
+#define CLKID_ENCP_MUX 92
+#define CLKID_ENCP 93
+#define CLKID_ENCL_MUX 94
+#define CLKID_ENCL 95
+#define CLKID_VDAC_MUX 96
+#define CLKID_VDAC 97
+#define CLKID_MALI_0_MUX 98
+#define CLKID_MALI_0_DIV 99
+#define CLKID_MALI_0 100
+#define CLKID_MALI_1_MUX 101
+#define CLKID_MALI_1_DIV 102
+#define CLKID_MALI_1 103
+#define CLKID_MALI 104
+#define CLKID_MALI_STACK_0_MUX 105
+#define CLKID_MALI_STACK_0_DIV 106
+#define CLKID_MALI_STACK_0 107
+#define CLKID_MALI_STACK_1_MUX 108
+#define CLKID_MALI_STACK_1_DIV 109
+#define CLKID_MALI_STACK_1 110
+#define CLKID_MALI_STACK 111
+#define CLKID_VDEC_0_MUX 112
+#define CLKID_VDEC_0_DIV 113
+#define CLKID_VDEC_0 114
+#define CLKID_VDEC_1_MUX 115
+#define CLKID_VDEC_1_DIV 116
+#define CLKID_VDEC_1 117
+#define CLKID_VDEC 118
+#define CLKID_HEVCF_0_MUX 119
+#define CLKID_HEVCF_0_DIV 120
+#define CLKID_HEVCF_0 121
+#define CLKID_HEVCF_1_MUX 122
+#define CLKID_HEVCF_1_DIV 123
+#define CLKID_HEVCF_1 124
+#define CLKID_HEVCF 125
+#define CLKID_VPU_0_MUX 126
+#define CLKID_VPU_0_DIV 127
+#define CLKID_VPU_0 128
+#define CLKID_VPU_1_MUX 129
+#define CLKID_VPU_1_DIV 130
+#define CLKID_VPU_1 131
+#define CLKID_VPU 132
+#define CLKID_VPU_CLKB_TMP_MUX 133
+#define CLKID_VPU_CLKB_TMP_DIV 134
+#define CLKID_VPU_CLKB_TMP 135
+#define CLKID_VPU_CLKB_DIV 136
+#define CLKID_VPU_CLKB 137
+#define CLKID_VPU_CLKC_0_MUX 138
+#define CLKID_VPU_CLKC_0_DIV 139
+#define CLKID_VPU_CLKC_0 140
+#define CLKID_VPU_CLKC_1_MUX 141
+#define CLKID_VPU_CLKC_1_DIV 142
+#define CLKID_VPU_CLKC_1 143
+#define CLKID_VPU_CLKC 144
+#define CLKID_VAPB_0_MUX 145
+#define CLKID_VAPB_0_DIV 146
+#define CLKID_VAPB_0 147
+#define CLKID_VAPB_1_MUX 148
+#define CLKID_VAPB_1_DIV 149
+#define CLKID_VAPB_1 150
+#define CLKID_VAPB 151
+#define CLKID_GE2D 152
+#define CLKID_DEWARPA_MUX 153
+#define CLKID_DEWARPA_DIV 154
+#define CLKID_DEWARPA 155
+#define CLKID_CMPR_MUX 156
+#define CLKID_CMPR_DIV 157
+#define CLKID_CMPR 158
+#define CLKID_HDMITX_SYS_MUX 159
+#define CLKID_HDMITX_SYS_DIV 160
+#define CLKID_HDMITX_SYS 161
+#define CLKID_HDMITX_PRIF_MUX 162
+#define CLKID_HDMITX_PRIF_DIV 163
+#define CLKID_HDMITX_PRIF 164
+#define CLKID_HDMITX_200M_MUX 165
+#define CLKID_HDMITX_200M_DIV 166
+#define CLKID_HDMITX_200M 167
+#define CLKID_HDMITX_AUD_MUX 168
+#define CLKID_HDMITX_AUD_DIV 169
+#define CLKID_HDMITX_AUD 170
+#define CLKID_PWM_A_MUX 171
+#define CLKID_PWM_A_DIV 172
+#define CLKID_PWM_A 173
+#define CLKID_PWM_B_MUX 174
+#define CLKID_PWM_B_DIV 175
+#define CLKID_PWM_B 176
+#define CLKID_PWM_C_MUX 177
+#define CLKID_PWM_C_DIV 178
+#define CLKID_PWM_C 179
+#define CLKID_PWM_D_MUX 180
+#define CLKID_PWM_D_DIV 181
+#define CLKID_PWM_D 182
+#define CLKID_PWM_E_MUX 183
+#define CLKID_PWM_E_DIV 184
+#define CLKID_PWM_E 185
+#define CLKID_PWM_F_MUX 186
+#define CLKID_PWM_F_DIV 187
+#define CLKID_PWM_F 188
+#define CLKID_PWM_G_MUX 189
+#define CLKID_PWM_G_DIV 190
+#define CLKID_PWM_G 191
+#define CLKID_PWM_H_MUX 192
+#define CLKID_PWM_H_DIV 193
+#define CLKID_PWM_H 194
+#define CLKID_PWM_I_MUX 195
+#define CLKID_PWM_I_DIV 196
+#define CLKID_PWM_I 197
+#define CLKID_PWM_J_MUX 198
+#define CLKID_PWM_J_DIV 199
+#define CLKID_PWM_J 200
+#define CLKID_SPICC0_MUX 201
+#define CLKID_SPICC0_DIV 202
+#define CLKID_SPICC0 203
+#define CLKID_SD_EMMC_A_MUX 204
+#define CLKID_SD_EMMC_A_DIV 205
+#define CLKID_SD_EMMC_A 206
+#define CLKID_SD_EMMC_B_MUX 207
+#define CLKID_SD_EMMC_B_DIV 208
+#define CLKID_SD_EMMC_B 209
+#define CLKID_SD_EMMC_C_MUX 210
+#define CLKID_SD_EMMC_C_DIV 211
+#define CLKID_SD_EMMC_C 212
+#define CLKID_VDIN_MEAS_MUX 213
+#define CLKID_VDIN_MEAS_DIV 214
+#define CLKID_VDIN_MEAS 215
+#define CLKID_VID_LOCK_MUX 216
+#define CLKID_VID_LOCK_DIV 217
+#define CLKID_VID_LOCK 218
+#define CLKID_ETH_CLK_RMII_MUX 219
+#define CLKID_ETH_CLK_RMII_DIV 220
+#define CLKID_ETH_CLK_RMII 221
+#define CLKID_ETH_CLK125M_DIV 222
+#define CLKID_ETH_CLK125M 223
+#define CLKID_TS_DIV 224
+#define CLKID_TS 225
+#define CLKID_AMFC_MUX 226
+#define CLKID_AMFC_DIV 227
+#define CLKID_AMFC 228
+#define CLKID_CSI2_ADAPT_MUX 229
+#define CLKID_CSI2_ADAPT_DIV 230
+#define CLKID_CSI2_ADAPT 231
+#define CLKID_MIPI_CSI_PHY_0_MUX 232
+#define CLKID_MIPI_CSI_PHY_0_DIV 233
+#define CLKID_MIPI_CSI_PHY_0 234
+#define CLKID_MIPI_CSI_PHY_1_MUX 235
+#define CLKID_MIPI_CSI_PHY_1_DIV 236
+#define CLKID_MIPI_CSI_PHY_1 237
+#define CLKID_MIPI_CSI_PHY 238
+#define CLKID_MIPI_DSI_PHY_MUX 239
+#define CLKID_MIPI_DSI_PHY_DIV 240
+#define CLKID_MIPI_DSI_PHY 241
+#define CLKID_MIPI_DSI_MEAS_MUX 242
+#define CLKID_MIPI_DSI_MEAS_DIV 243
+#define CLKID_MIPI_DSI_MEAS 244
+#define CLKID_NNA_MUX 245
+#define CLKID_NNA_DIV 246
+#define CLKID_NNA 247
+#define CLKID_VC9000E_ACLK_MUX 248
+#define CLKID_VC9000E_ACLK_DIV 249
+#define CLKID_VC9000E_ACLK 250
+#define CLKID_VC9000E_CORE_MUX 251
+#define CLKID_VC9000E_CORE_DIV 252
+#define CLKID_VC9000E_CORE 253
+#define CLKID_DSPA_0_MUX 254
+#define CLKID_DSPA_0_DIV 255
+#define CLKID_DSPA_0 256
+#define CLKID_DSPA_1_MUX 257
+#define CLKID_DSPA_1_DIV 258
+#define CLKID_DSPA_1 259
+#define CLKID_DSPA 260
+#define CLKID_PCIE_TL_MUX 261
+#define CLKID_PCIE_TL_DIV 262
+#define CLKID_PCIE_TL 263
+#define CLKID_SYS_AM_AXI 264
+#define CLKID_SYS_DOS 265
+#define CLKID_SYS_VC9000E 266
+#define CLKID_SYS_MIPI_DSI 267
+#define CLKID_SYS_ETHPHY 268
+#define CLKID_SYS_AMFC 269
+#define CLKID_SYS_MALI 270
+#define CLKID_SYS_NNA 271
+#define CLKID_SYS_AOCPU 272
+#define CLKID_SYS_AUCPU 273
+#define CLKID_SYS_CEC 274
+#define CLKID_SYS_MIPI_DSI_PHY 275
+#define CLKID_SYS_SD_EMMC_A 276
+#define CLKID_SYS_SD_EMMC_B 277
+#define CLKID_SYS_SD_EMMC_C 278
+#define CLKID_SYS_SMARTCARD 279
+#define CLKID_SYS_ACODEC 280
+#define CLKID_SYS_MSR_CLK 281
+#define CLKID_SYS_IR_CTRL 282
+#define CLKID_SYS_AUDIO 283
+#define CLKID_SYS_ETH 284
+#define CLKID_SYS_UART_A 285
+#define CLKID_SYS_UART_B 286
+#define CLKID_SYS_UART_C 287
+#define CLKID_SYS_UART_D 288
+#define CLKID_SYS_UART_E 289
+#define CLKID_SYS_TS_PLL 290
+#define CLKID_SYS_CSI_DIG_CLKIN 291
+#define CLKID_SYS_GE2D 292
+#define CLKID_SYS_SPICC0 293
+#define CLKID_SYS_PCIE 294
+#define CLKID_SYS_USB 295
+#define CLKID_SYS_PCIE_PHY 296
+#define CLKID_SYS_I2C_M_A 297
+#define CLKID_SYS_I2C_M_B 298
+#define CLKID_SYS_I2C_M_C 299
+#define CLKID_SYS_I2C_M_D 300
+#define CLKID_SYS_I2C_M_E 301
+#define CLKID_SYS_HDMITX_APB 302
+#define CLKID_SYS_I2C_S_A 303
+#define CLKID_SYS_HDMI20_AES 304
+#define CLKID_SYS_MMC_APB 305
+#define CLKID_SYS_CSI2_HOST 306
+#define CLKID_SYS_CSI2_ADAPT 307
+#define CLKID_SYS_CPU_APB 308
+#define CLKID_SYS_DSPA 309
+#define CLKID_SYS_VPU_INTR 310
+#define CLKID_SYS_CSI2_PHY0 311
+#define CLKID_SYS_SAR_ADC 312
+#define CLKID_SYS_PWM_J 313
+#define CLKID_SYS_GIC 314
+#define CLKID_SYS_PWM_I 315
+#define CLKID_SYS_PWM_H 316
+#define CLKID_SYS_PWM_G 317
+#define CLKID_SYS_PWM_F 318
+#define CLKID_SYS_PWM_E 319
+#define CLKID_SYS_PWM_D 320
+#define CLKID_SYS_PWM_C 321
+#define CLKID_SYS_PWM_B 322
+#define CLKID_SYS_PWM_A 323
+#define CLKID_AXI_AO_NIC 324
+#define CLKID_AXI_DEV0_MMC 325
+#define CLKID_AXI_CPU_SRAM 326
-#define CLKID_CPU_BASE (CLKID_PLL_BASE + 24)
-#define CLKID_CPU_CLK (CLKID_CPU_BASE + 0)
-#define CLKID_DSU_CLK (CLKID_CPU_BASE + 1)
+#define NR_CLKS 327
-#define CLKID_BASE (CLKID_CPU_BASE + 2)
-#define CLKID_RTC_DUAL_CLKIN (CLKID_BASE + 0)
-#define CLKID_RTC_DUAL_DIV (CLKID_BASE + 1)
-#define CLKID_RTC_DUAL_SEL (CLKID_BASE + 2)
-#define CLKID_RTC_DUAL_CLKOUT (CLKID_BASE + 3)
-#define CLKID_RTC_CLK (CLKID_BASE + 4)
-#define CLKID_SYS_CLK_0_SEL (CLKID_BASE + 5)
-#define CLKID_SYS_CLK_0_DIV (CLKID_BASE + 6)
-#define CLKID_SYS_CLK_0 (CLKID_BASE + 7)
-#define CLKID_SYS_CLK_1_SEL (CLKID_BASE + 8)
-#define CLKID_SYS_CLK_1_DIV (CLKID_BASE + 9)
-#define CLKID_SYS_CLK_1 (CLKID_BASE + 10)
-#define CLKID_SYS_CLK (CLKID_BASE + 11)
-#define CLKID_AXI_CLK_0_SEL (CLKID_BASE + 12)
-#define CLKID_AXI_CLK_0_DIV (CLKID_BASE + 13)
-#define CLKID_AXI_CLK_0 (CLKID_BASE + 14)
-#define CLKID_AXI_CLK_1_SEL (CLKID_BASE + 15)
-#define CLKID_AXI_CLK_1_DIV (CLKID_BASE + 16)
-#define CLKID_AXI_CLK_1 (CLKID_BASE + 17)
-#define CLKID_AXI_CLK (CLKID_BASE + 18)
-#define CLKID_SAR_ADC_SEL (CLKID_BASE + 19)
-#define CLKID_SAR_ADC_DIV (CLKID_BASE + 20)
-#define CLKID_SAR_ADC (CLKID_BASE + 21)
-#define CLKID_CECB_DUAL_CLKIN (CLKID_BASE + 22)
-#define CLKID_CECB_DUAL_DIV (CLKID_BASE + 23)
-#define CLKID_CECB_DUAL_SEL (CLKID_BASE + 24)
-#define CLKID_CECB_DUAL_CLKOUT (CLKID_BASE + 25)
-#define CLKID_CECB_CLK (CLKID_BASE + 26)
-#define CLKID_SC_SEL (CLKID_BASE + 27)
-#define CLKID_SC_DIV (CLKID_BASE + 28)
-#define CLKID_SC (CLKID_BASE + 29)
-#define CLKID_CDAC_SEL (CLKID_BASE + 30)
-#define CLKID_CDAC_DIV (CLKID_BASE + 31)
-#define CLKID_CDAC (CLKID_BASE + 32)
-#define CLKID_12_24M_IN (CLKID_BASE + 33)
-#define CLKID_12_24M (CLKID_BASE + 34)
-#define CLKID_VCLK_SEL (CLKID_BASE + 35)
-#define CLKID_VCLK2_SEL (CLKID_BASE + 36)
-#define CLKID_VCLK_INPUT (CLKID_BASE + 37)
-#define CLKID_VCLK2_INPUT (CLKID_BASE + 38)
-#define CLKID_VCLK_DIV (CLKID_BASE + 39)
-#define CLKID_VCLK2_DIV (CLKID_BASE + 40)
-#define CLKID_VCLK (CLKID_BASE + 41)
-#define CLKID_VCLK2 (CLKID_BASE + 42)
-#define CLKID_VCLK_DIV1 (CLKID_BASE + 43)
-#define CLKID_VCLK_DIV2_EN (CLKID_BASE + 44)
-#define CLKID_VCLK_DIV4_EN (CLKID_BASE + 45)
-#define CLKID_VCLK_DIV6_EN (CLKID_BASE + 46)
-#define CLKID_VCLK_DIV12_EN (CLKID_BASE + 47)
-#define CLKID_VCLK2_DIV1 (CLKID_BASE + 48)
-#define CLKID_VCLK2_DIV2_EN (CLKID_BASE + 49)
-#define CLKID_VCLK2_DIV4_EN (CLKID_BASE + 50)
-#define CLKID_VCLK2_DIV6_EN (CLKID_BASE + 51)
-#define CLKID_VCLK2_DIV12_EN (CLKID_BASE + 52)
-#define CLKID_VCLK_DIV2 (CLKID_BASE + 53)
-#define CLKID_VCLK_DIV4 (CLKID_BASE + 54)
-#define CLKID_VCLK_DIV6 (CLKID_BASE + 55)
-#define CLKID_VCLK_DIV12 (CLKID_BASE + 56)
-#define CLKID_VCLK2_DIV2 (CLKID_BASE + 57)
-#define CLKID_VCLK2_DIV4 (CLKID_BASE + 58)
-#define CLKID_VCLK2_DIV6 (CLKID_BASE + 59)
-#define CLKID_VCLK2_DIV12 (CLKID_BASE + 60)
-#define CLKID_ENCI_SEL (CLKID_BASE + 61)
-#define CLKID_ENCL_SEL (CLKID_BASE + 62)
-#define CLKID_ENCP_SEL (CLKID_BASE + 63)
-#define CLKID_VDAC_SEL (CLKID_BASE + 64)
-#define CLKID_HDMI_TX_PIXEL_SEL (CLKID_BASE + 65)
-#define CLKID_HDMI_TX_FE_SEL (CLKID_BASE + 66)
-#define CLKID_ENCI (CLKID_BASE + 67)
-#define CLKID_ENCL (CLKID_BASE + 68)
-#define CLKID_ENCP (CLKID_BASE + 69)
-#define CLKID_VDAC (CLKID_BASE + 70)
-#define CLKID_HDMI_TX_PIXEL (CLKID_BASE + 71)
-#define CLKID_HDMI_TX_FE (CLKID_BASE + 72)
-#define CLKID_LCD_AN_CLK_PH23_SEL (CLKID_BASE + 73)
-#define CLKID_LCD_AN_CLK_PH23 (CLKID_BASE + 74)
-#define CLKID_LCD_AN_CLK_PH2 (CLKID_BASE + 75)
-#define CLKID_LCD_AN_CLK_PH3 (CLKID_BASE + 76)
-#define CLKID_HDMI_TX_SYS_SEL (CLKID_BASE + 77)
-#define CLKID_HDMI_TX_SYS_DIV (CLKID_BASE + 78)
-#define CLKID_HDMI_TX_SYS (CLKID_BASE + 79)
-#define CLKID_HDMI_TX_PRIF_SEL (CLKID_BASE + 80)
-#define CLKID_HDMI_TX_PRIF_DIV (CLKID_BASE + 81)
-#define CLKID_HDMI_TX_PRIF (CLKID_BASE + 82)
-#define CLKID_HDMI_TX_200M_SEL (CLKID_BASE + 83)
-#define CLKID_HDMI_TX_200M_DIV (CLKID_BASE + 84)
-#define CLKID_HDMI_TX_200M (CLKID_BASE + 85)
-#define CLKID_HDMI_TX_AUD_SEL (CLKID_BASE + 86)
-#define CLKID_HDMI_TX_AUD_DIV (CLKID_BASE + 87)
-#define CLKID_HDMI_TX_AUD (CLKID_BASE + 88)
-#define CLKID_VID_LOCK_SEL (CLKID_BASE + 89)
-#define CLKID_VID_LOCK_DIV (CLKID_BASE + 90)
-#define CLKID_VID_LOCK (CLKID_BASE + 91)
-#define CLKID_VDIN_MEAS_SEL (CLKID_BASE + 92)
-#define CLKID_VDIN_MEAS_DIV (CLKID_BASE + 93)
-#define CLKID_VDIN_MEAS (CLKID_BASE + 94)
-#define CLKID_ETH_RMII_DIV (CLKID_BASE + 95)
-#define CLKID_ETH_RMII (CLKID_BASE + 96)
-#define CLKID_ETH_125M_DIV8 (CLKID_BASE + 97)
-#define CLKID_ETH_125M (CLKID_BASE + 98)
-#define CLKID_TS_DIV (CLKID_BASE + 99)
-#define CLKID_TS (CLKID_BASE + 100)
-#define CLKID_AMFC_SEL (CLKID_BASE + 101)
-#define CLKID_AMFC_DIV (CLKID_BASE + 102)
-#define CLKID_AMFC (CLKID_BASE + 103)
-#define CLKID_MALI_0_SEL (CLKID_BASE + 104)
-#define CLKID_MALI_0_DIV (CLKID_BASE + 105)
-#define CLKID_MALI_0 (CLKID_BASE + 106)
-#define CLKID_MALI_1_SEL (CLKID_BASE + 107)
-#define CLKID_MALI_1_DIV (CLKID_BASE + 108)
-#define CLKID_MALI_1 (CLKID_BASE + 109)
-#define CLKID_MALI (CLKID_BASE + 110)
-#define CLKID_MALI_STACK_0_SEL (CLKID_BASE + 111)
-#define CLKID_MALI_STACK_0_DIV (CLKID_BASE + 112)
-#define CLKID_MALI_STACK_0 (CLKID_BASE + 113)
-#define CLKID_MALI_STACK_1_SEL (CLKID_BASE + 114)
-#define CLKID_MALI_STACK_1_DIV (CLKID_BASE + 115)
-#define CLKID_MALI_STACK_1 (CLKID_BASE + 116)
-#define CLKID_MALI_STACK (CLKID_BASE + 117)
-#define CLKID_VDEC_0_SEL (CLKID_BASE + 118)
-#define CLKID_VDEC_0_DIV (CLKID_BASE + 119)
-#define CLKID_VDEC_0 (CLKID_BASE + 120)
-#define CLKID_VDEC_1_SEL (CLKID_BASE + 121)
-#define CLKID_VDEC_1_DIV (CLKID_BASE + 122)
-#define CLKID_VDEC_1 (CLKID_BASE + 123)
-#define CLKID_VDEC (CLKID_BASE + 124)
-#define CLKID_HEVCF_0_SEL (CLKID_BASE + 125)
-#define CLKID_HEVCF_0_DIV (CLKID_BASE + 126)
-#define CLKID_HEVCF_0 (CLKID_BASE + 127)
-#define CLKID_HEVCF_1_SEL (CLKID_BASE + 128)
-#define CLKID_HEVCF_1_DIV (CLKID_BASE + 129)
-#define CLKID_HEVCF_1 (CLKID_BASE + 130)
-#define CLKID_HEVCF (CLKID_BASE + 131)
-#define CLKID_HCODEC_0_SEL (CLKID_BASE + 132)
-#define CLKID_HCODEC_0_DIV (CLKID_BASE + 133)
-#define CLKID_HCODEC_0 (CLKID_BASE + 134)
-#define CLKID_HCODEC_1_SEL (CLKID_BASE + 135)
-#define CLKID_HCODEC_1_DIV (CLKID_BASE + 136)
-#define CLKID_HCODEC_1 (CLKID_BASE + 137)
-#define CLKID_HCODEC (CLKID_BASE + 138)
-#define CLKID_VPU_0_SEL (CLKID_BASE + 139)
-#define CLKID_VPU_0_DIV (CLKID_BASE + 140)
-#define CLKID_VPU_0 (CLKID_BASE + 141)
-#define CLKID_VPU_1_SEL (CLKID_BASE + 142)
-#define CLKID_VPU_1_DIV (CLKID_BASE + 143)
-#define CLKID_VPU_1 (CLKID_BASE + 144)
-#define CLKID_VPU (CLKID_BASE + 145)
-#define CLKID_VPU_CLKB_TMP_SEL (CLKID_BASE + 146)
-#define CLKID_VPU_CLKB_TMP_DIV (CLKID_BASE + 147)
-#define CLKID_VPU_CLKB_TMP (CLKID_BASE + 148)
-#define CLKID_VPU_CLKB_DIV (CLKID_BASE + 149)
-#define CLKID_VPU_CLKB (CLKID_BASE + 150)
-#define CLKID_VPU_CLKC_0_SEL (CLKID_BASE + 151)
-#define CLKID_VPU_CLKC_0_DIV (CLKID_BASE + 152)
-#define CLKID_VPU_CLKC_0 (CLKID_BASE + 153)
-#define CLKID_VPU_CLKC_1_SEL (CLKID_BASE + 154)
-#define CLKID_VPU_CLKC_1_DIV (CLKID_BASE + 155)
-#define CLKID_VPU_CLKC_1 (CLKID_BASE + 156)
-#define CLKID_VPU_CLKC (CLKID_BASE + 157)
-#define CLKID_VAPB_0_SEL (CLKID_BASE + 158)
-#define CLKID_VAPB_0_DIV (CLKID_BASE + 159)
-#define CLKID_VAPB_0 (CLKID_BASE + 160)
-#define CLKID_VAPB_1_SEL (CLKID_BASE + 161)
-#define CLKID_VAPB_1_DIV (CLKID_BASE + 162)
-#define CLKID_VAPB_1 (CLKID_BASE + 163)
-#define CLKID_VAPB (CLKID_BASE + 164)
-#define CLKID_GE2D (CLKID_BASE + 165)
-#define CLKID_PWM_A_SEL (CLKID_BASE + 166)
-#define CLKID_PWM_A_DIV (CLKID_BASE + 167)
-#define CLKID_PWM_A (CLKID_BASE + 168)
-#define CLKID_PWM_B_SEL (CLKID_BASE + 169)
-#define CLKID_PWM_B_DIV (CLKID_BASE + 170)
-#define CLKID_PWM_B (CLKID_BASE + 171)
-#define CLKID_PWM_C_SEL (CLKID_BASE + 172)
-#define CLKID_PWM_C_DIV (CLKID_BASE + 173)
-#define CLKID_PWM_C (CLKID_BASE + 174)
-#define CLKID_PWM_D_SEL (CLKID_BASE + 175)
-#define CLKID_PWM_D_DIV (CLKID_BASE + 176)
-#define CLKID_PWM_D (CLKID_BASE + 177)
-#define CLKID_PWM_E_SEL (CLKID_BASE + 178)
-#define CLKID_PWM_E_DIV (CLKID_BASE + 179)
-#define CLKID_PWM_E (CLKID_BASE + 180)
-#define CLKID_PWM_F_SEL (CLKID_BASE + 181)
-#define CLKID_PWM_F_DIV (CLKID_BASE + 182)
-#define CLKID_PWM_F (CLKID_BASE + 183)
-#define CLKID_PWM_G_SEL (CLKID_BASE + 184)
-#define CLKID_PWM_G_DIV (CLKID_BASE + 185)
-#define CLKID_PWM_G (CLKID_BASE + 186)
-#define CLKID_PWM_H_SEL (CLKID_BASE + 187)
-#define CLKID_PWM_H_DIV (CLKID_BASE + 188)
-#define CLKID_PWM_H (CLKID_BASE + 189)
-#define CLKID_PWM_I_SEL (CLKID_BASE + 190)
-#define CLKID_PWM_I_DIV (CLKID_BASE + 191)
-#define CLKID_PWM_I (CLKID_BASE + 192)
-#define CLKID_PWM_J_SEL (CLKID_BASE + 193)
-#define CLKID_PWM_J_DIV (CLKID_BASE + 194)
-#define CLKID_PWM_J (CLKID_BASE + 195)
-#define CLKID_SPICC_SEL (CLKID_BASE + 196)
-#define CLKID_SPICC_DIV (CLKID_BASE + 197)
-#define CLKID_SPICC (CLKID_BASE + 198)
-#define CLKID_SD_EMMC_A_SEL (CLKID_BASE + 199)
-#define CLKID_SD_EMMC_A_DIV (CLKID_BASE + 200)
-#define CLKID_SD_EMMC_A (CLKID_BASE + 201)
-#define CLKID_SD_EMMC_B_SEL (CLKID_BASE + 202)
-#define CLKID_SD_EMMC_B_DIV (CLKID_BASE + 203)
-#define CLKID_SD_EMMC_B (CLKID_BASE + 204)
-#define CLKID_SD_EMMC_C_SEL (CLKID_BASE + 205)
-#define CLKID_SD_EMMC_C_DIV (CLKID_BASE + 206)
-#define CLKID_SD_EMMC_C (CLKID_BASE + 207)
-#define CLKID_GEN_SEL (CLKID_BASE + 208)
-#define CLKID_GEN_DIV (CLKID_BASE + 209)
-#define CLKID_GEN (CLKID_BASE + 210)
-#define CLKID_SYS_AM_AXI (CLKID_BASE + 211)
-#define CLKID_SYS_DOS (CLKID_BASE + 212)
-#define CLKID_SYS_ETHPHY (CLKID_BASE + 213)
-#define CLKID_SYS_MALI_GATE (CLKID_BASE + 214)
-#define CLKID_SYS_AOCPU (CLKID_BASE + 215)
-#define CLKID_SYS_AUCPU (CLKID_BASE + 216)
-#define CLKID_SYS_CEC (CLKID_BASE + 217)
-#define CLKID_SYS_SD_EMMC_A (CLKID_BASE + 218)
-#define CLKID_SYS_SD_EMMC_B (CLKID_BASE + 219)
-#define CLKID_SYS_SD_EMMC_C (CLKID_BASE + 220)
-#define CLKID_SYS_SMARTCARD (CLKID_BASE + 221)
-#define CLKID_SYS_ACODEC (CLKID_BASE + 222)
-#define CLKID_SYS_MSR_CLK (CLKID_BASE + 223)
-#define CLKID_SYS_IR_CTRL (CLKID_BASE + 224)
-#define CLKID_SYS_AUDIO (CLKID_BASE + 225)
-#define CLKID_SYS_ETH (CLKID_BASE + 226)
-#define CLKID_SYS_UART_A (CLKID_BASE + 227)
-#define CLKID_SYS_UART_B (CLKID_BASE + 228)
-#define CLKID_SYS_UART_C (CLKID_BASE + 229)
-#define CLKID_SYS_UART_D (CLKID_BASE + 230)
-#define CLKID_SYS_UART_E (CLKID_BASE + 231)
-#define CLKID_SYS_TS_PLL (CLKID_BASE + 232)
-#define CLKID_SYS_GE2D (CLKID_BASE + 233)
-#define CLKID_SYS_SPICC0 (CLKID_BASE + 234)
-#define CLKID_SYS_USB (CLKID_BASE + 235)
-#define CLKID_SYS_I2C_M_A (CLKID_BASE + 236)
-#define CLKID_SYS_I2C_M_B (CLKID_BASE + 237)
-#define CLKID_SYS_I2C_M_C (CLKID_BASE + 238)
-#define CLKID_SYS_I2C_M_D (CLKID_BASE + 239)
-#define CLKID_SYS_I2C_M_E (CLKID_BASE + 240)
-#define CLKID_SYS_HDMITX_APB (CLKID_BASE + 241)
-#define CLKID_SYS_I2C_S_A (CLKID_BASE + 242)
-#define CLKID_SYS_HDMI20_AES (CLKID_BASE + 243)
-#define CLKID_SYS_MMC_APB (CLKID_BASE + 244)
-#define CLKID_SYS_CPU_APB (CLKID_BASE + 245)
-#define CLKID_SYS_VPU_INTR (CLKID_BASE + 246)
-#define CLKID_SYS_SAR_ADC (CLKID_BASE + 247)
-#define CLKID_SYS_PWM_J (CLKID_BASE + 248)
-#define CLKID_SYS_GIC (CLKID_BASE + 249)
-#define CLKID_SYS_PWM_I (CLKID_BASE + 250)
-#define CLKID_SYS_PWM_H (CLKID_BASE + 251)
-#define CLKID_SYS_PWM_G (CLKID_BASE + 252)
-#define CLKID_SYS_PWM_F (CLKID_BASE + 253)
-#define CLKID_SYS_PWM_E (CLKID_BASE + 254)
-#define CLKID_SYS_PWM_D (CLKID_BASE + 255)
-#define CLKID_SYS_PWM_C (CLKID_BASE + 256)
-#define CLKID_SYS_PWM_B (CLKID_BASE + 257)
-#define CLKID_SYS_PWM_A (CLKID_BASE + 258)
-#define CLKID_AXI_SYS_NIC (CLKID_BASE + 259)
-#define CLKID_AXI_RAMA (CLKID_BASE + 260)
-#define CLKID_AXI_DEV0_MMC (CLKID_BASE + 261)
-
-#define NR_CLKS (CLKID_BASE + 262)
-
-#endif /* __S7D_CLKC_H */
+#endif /* __S6_CLKC_H */
diff --git a/include/dt-bindings/clock/s6-secure-clk.h b/include/dt-bindings/clock/s6-secure-clk.h
new file mode 100644
index 0000000..402d02f
--- /dev/null
+++ b/include/dt-bindings/clock/s6-secure-clk.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __S6_SECURE_CLK_H
+#define __S6_SECURE_CLK_H
+
+/*
+ * CLKID index values
+ */
+#define CLKID_SYS0PLL_IN 0
+#define CLKID_DDRPHY 1
+#define CLKID_SYS1PLL_IN 2
+#define CLKID_PCIEPLL_IN 3
+#define CLKID_GP0PLL_IN 4
+#define CLKID_OTHERPLL_IN 5
+#define CLKID_USB0PHYPLL_IN 6
+#define CLKID_USB3PHY20PLL_IN 7
+#define CLKID_HIFI0PLL_IN 8
+#define CLKID_DSIPLL_IN 9
+#define CLKID_ETH_HIFI1PLL_IN 10
+#define CLKID_ADCPLL_IN 11
+#define CLKID_FIXEDPLL_IN 12
+#define CLKID_MCLKPLL_IN 13
+
+#define CLKID_CPUCLK 14
+#define CLKID_DSUCLK 15
+
+#define CLKID_GP1PLL 16
+#define CLKID_GP2PLL 17
+
+#endif /* __S6_SECURE_CLK_H */
diff --git a/modules.bzl b/modules.bzl
index 3b0c451..d2a02a2 100644
--- a/modules.bzl
+++ b/modules.bzl
@@ -34,6 +34,7 @@
"common_drivers/drivers/clk/meson/amlogic-clk-soc-g12a.ko",
"common_drivers/drivers/clk/meson/amlogic-clk-soc-s4.ko",
"common_drivers/drivers/clk/meson/amlogic-clk-soc-s5.ko",
+ "common_drivers/drivers/clk/meson/amlogic-clk-soc-s6.ko",
"common_drivers/drivers/clk/meson/amlogic-clk-soc-sc2.ko",
"common_drivers/drivers/clk/meson/amlogic-clk-soc-t3.ko",
"common_drivers/drivers/clk/meson/amlogic-clk-soc-t3x.ko",