| commit | 5fccce2653f8d7d8f20c75027c02d02ae943cdff | [log] [tgz] |
|---|---|---|
| author | xuesong.jiang <xuesong.jiang@amlogic.com> | Tue Oct 22 20:28:50 2024 +0800 |
| committer | xuesong.jiang <xuesong.jiang@amlogic.com> | Tue Oct 22 20:31:30 2024 +0800 |
| tree | d1732dc472cb26fae85418e9fd137daee30883a3 | |
| parent | f61afd28294c22acc40c100a671e365e9d1a2a68 [diff] |
amlv4l2dec: CF2 refine log output [1/1] PD#SWPL-185270 Problem: refine log output Solution: refine log output Verify: (detail info) Change-Id: Iba3a1b0a85d521129ceb3023ab7c047ba1ad5826 Signed-off-by: xuesong.jiang <xuesong.jiang@amlogic.com>