commit 7765f173f34faa89ad5a3f09144460cfa4d8e1cf
author hanghang.luo <hanghang.luo@amlogic.com> Thu Dec 19 17:07:09 2024 +0800
committer hanghang.luo <hanghang.luo@amlogic.com> Thu Dec 19 17:09:13 2024 +0800
tree 9a383b1d2ca075b478cd3af56f9d6c2e7cdac5dc
parent 53c47337d2dc2d661e19765e98a4da12e12cdfb9

v4l2dec: CB0 set dw for h265 [1/1]

PD#SWPL-197002

Problem:
set dw for h265

Solution:
set dw for h265

Verify:
bp201

Change-Id: I45dc0cea86cfee96fb20c137a8c4450c2243fd15
Signed-off-by: hanghang.luo <hanghang.luo@amlogic.com>

src/gstamlv4l2object.c

diff --git a/src/gstamlv4l2object.c b/src/gstamlv4l2object.c
index 75aff50..0d1da57 100644
--- a/src/gstamlv4l2object.c
+++ b/src/gstamlv4l2object.c
@@ -3654,7 +3654,7 @@
     return FALSE;
 }
 
-static int gst_aml_config_dw_for_hevc_core (gboolean low_mem, gboolean interlace, gboolean pip)
+static int gst_aml_config_dw_for_hevc_core (gboolean low_mem, gboolean interlace, gboolean pip, guint32 pixFormat)
 {
   const char *env_4k;
   const char *env_de_counter;
@@ -3663,15 +3663,23 @@
 
   if (interlace)
   {
-      double_write = VDEC_DW_NO_AFBC;
-      GST_DEBUG("interlace set DW=%d for hevc core", double_write);
+      if (V4L2_PIX_FMT_HEVC == pixFormat)
+      {
+          double_write = VDEC_DW_AFBC_1_1_DW;
+          //need to cfg according to 8bit or 10bit in the future
+      }
+      else
+      {
+          double_write = VDEC_DW_NO_AFBC;
+      }
+      GST_DEBUG ("interlace set DW=%d for hevc core", double_write);
       return double_write;
   }
 
   if (low_mem)
   {
       double_write = VDEC_DW_AFBC_ONLY;
-      GST_DEBUG("low mem set DW=%d for hevc core", double_write);
+      GST_DEBUG ("low mem set DW=%d for hevc core", double_write);
       return double_write;
   }
 
@@ -3682,7 +3690,7 @@
   if (!check_env_valid(env_4k) && !check_env_valid(env_de_counter) && !check_env_valid (env_ai_pq) && !pip)
       double_write = VDEC_DW_AFBC_x2_1_4_DW;
 
-  GST_DEBUG("default set DW=%d for hevc core", double_write);
+  GST_DEBUG ("default set DW=%d for hevc core", double_write);
   return double_write;
 }
 
@@ -3702,14 +3710,14 @@
           if (v4l2object->low_memory_mode && !interlace)
               double_write = VDEC_DW_AFBC_ONLY;
           break;
-      // for hevc core, refer to gst_aml_config_dw__for_hevc_core
+      // for hevc core, refer to gst_aml_config_dw_for_hevc_core
       case V4L2_PIX_FMT_H264:
       case V4L2_PIX_FMT_HEVC:
       case V4L2_PIX_FMT_VP9:
       case V4L2_PIX_FMT_AV1:
       case V4L2_PIX_FMT_AVS2:
       case V4L2_PIX_FMT_AVS3:
-          double_write = gst_aml_config_dw_for_hevc_core (v4l2object->low_memory_mode, interlace, v4l2object->pip);
+          double_write = gst_aml_config_dw_for_hevc_core (v4l2object->low_memory_mode, interlace, v4l2object->pip, pixFormat);
           break;
       default:
           GST_WARNING("unknown video format %d", pixFormat);