HEVC: CB1 Fix HEVC decoder working abnormality. [1/1]
PD#SWPL-191222
Problem:
S6 did not disable axi arb before reset, which
caused a new axi cmd to be issued after the axi
cmd ended, causing the decoder to work abnormally.
Solution:
Disable axi arb before resetting S6 HEVC related
decoding, and enable axi arb after reset.
Verify:
S6
Change-Id: Iebd31f6133ffba579c36cc239056ef0408122f25
Signed-off-by: kuan.hu <kuan.hu@amlogic.com>
diff --git a/drivers/common/chips/decoder_cpu_ver_info.c b/drivers/common/chips/decoder_cpu_ver_info.c
index 249ef10..3324a81 100644
--- a/drivers/common/chips/decoder_cpu_ver_info.c
+++ b/drivers/common/chips/decoder_cpu_ver_info.c
@@ -489,7 +489,7 @@
.is_support_h264_mmu = true,
.is_support_dual_core = false,
.is_support_rdma = false,
- .is_support_axi_ctrl = false,
+ .is_support_axi_ctrl = true,
.is_mjpeg_endian_rematch = true,
.is_vcpu_clk_set = true,
.is_vp9_adapt_prob_hw_mode = true,
diff --git a/drivers/frame_provider/decoder/utils/vdec.c b/drivers/frame_provider/decoder/utils/vdec.c
index 180a7d3..0807780 100644
--- a/drivers/frame_provider/decoder/utils/vdec.c
+++ b/drivers/frame_provider/decoder/utils/vdec.c
@@ -1060,6 +1060,27 @@
}
}
+static void arb_dmc_ctrl(bool enable, u32 target)
+{
+ if (target == VDEC_INPUT_TARGET_VLD) {
+ dec_dmc_port_ctrl(enable, target);
+ } else if (target == VDEC_INPUT_TARGET_HEVC) {
+ if (enable) {
+ CLEAR_VREG_MASK(HEVC_ASSIST_AXI_CTRL, ((1 << 6 ) | (1 << 14)));
+ } else {
+ unsigned int mask = (1 << 6) | (1 << 7);
+ unsigned int sts_reg_addr = 0xd8;
+
+ SET_VREG_MASK(HEVC_ASSIST_AXI_CTRL, ((1 << 6 ) | (1 << 14)));
+ dos_wait_status(HEVC_ASSIST_AFIFO_CTRL, (0x3 << 27), 0);
+
+ while (!(codec_dmcbus_read(sts_reg_addr)
+ & mask))
+ ;
+ }
+ }
+}
+
void arb_ctrl_wait_idle(int enable)
{
#define T6D_SYSCTRL_AXI_PIPE_CTRL0 0x55
@@ -1089,7 +1110,9 @@
arb_ctrl_wait_idle(enable);
} else {
if (is_support_axi_ctrl()) {
- if (target == VDEC_INPUT_TARGET_VLD)
+ if (get_cpu_major_id() == AM_MESON_CPU_MAJOR_ID_S6)
+ arb_dmc_ctrl(enable, target);
+ else if (target == VDEC_INPUT_TARGET_VLD)
vdec_dbus_ctrl(enable);
else if (target == VDEC_INPUT_TARGET_HEVC)
hevc_arb_ctrl(enable, 0);
@@ -1140,7 +1163,9 @@
arb_ctrl_wait_idle(1);
} else {
if (is_support_axi_ctrl()) {
- if (input->target == VDEC_INPUT_TARGET_VLD) {
+ if (get_cpu_major_id() == AM_MESON_CPU_MAJOR_ID_S6)
+ arb_dmc_ctrl(0, input->target);
+ else if (input->target == VDEC_INPUT_TARGET_VLD) {
if (!vdec_on(VDEC_1))
return;
vdec_dbus_ctrl(0);
@@ -1165,7 +1190,9 @@
arb_ctrl_wait_idle(1);
} else {
if (is_support_axi_ctrl()) {
- if (input->target == VDEC_INPUT_TARGET_VLD)
+ if (get_cpu_major_id() == AM_MESON_CPU_MAJOR_ID_S6)
+ arb_dmc_ctrl(1, input->target);
+ else if (input->target == VDEC_INPUT_TARGET_VLD)
vdec_dbus_ctrl(1);
else if (input->target == VDEC_INPUT_TARGET_HEVC)
hevc_arb_ctrl(1, 0);