SoC common: aocpu add detection for no access permission [1/3]

PD#SWPL-174194

Problem:
aocpu access addr with no permission would not read or
write successfully, and no exception occurs.

Solution:
aocpu add detection for no access permission.

Verify:
s6_bl201

Change-Id: I2bbae898a20bec9f9a01a8ff34805481b39165c6
Signed-off-by: bangzheng.liu <bangzheng.liu@amlogic.com>
diff --git a/GCC/AML_RISC-V/aocpu/port.c b/GCC/AML_RISC-V/aocpu/port.c
index 55972ed..b9da957 100644
--- a/GCC/AML_RISC-V/aocpu/port.c
+++ b/GCC/AML_RISC-V/aocpu/port.c
@@ -421,6 +421,16 @@
 }
 /*-----------------------------------------------------------*/
 
+#ifdef CONFIG_AOCPU_BUSRESPERR_DETECTION
+void vBusRespERRHandler(void)
+{
+	printf("bl30 bus response error: no access permission, stop here!\n");
+	printf("The instruction addr is 0x%lx\n", read_csr(mepc));
+	printf("The accessd     addr is 0x%lx\n", read_csr(mbadaddr));
+	do {} while (1);
+}
+#endif
+
 /* Replace yield with generating soft interrupt pending instead
  * of ECALL, which causing IRQ interrupted by task switch.
  */
diff --git a/GCC/AML_RISC-V/aocpu/portASM.S b/GCC/AML_RISC-V/aocpu/portASM.S
index 8680aff..1415bf3 100644
--- a/GCC/AML_RISC-V/aocpu/portASM.S
+++ b/GCC/AML_RISC-V/aocpu/portASM.S
@@ -561,6 +561,16 @@
 	mret
 #endif
 
+#ifdef CONFIG_AOCPU_BUSRESPERR_DETECTION
+.align 4
+.globl BUS_RESP_ERR_HANDLER
+BUS_RESP_ERR_HANDLER:
+	jal 	vBusRespERRHandler
+	//never return
+
+	mret
+#endif
+
 xPortStartScheduler:
 	jal		vPortSetup
 	portRESTORE_CONTEXT_EXCP_2
diff --git a/Kconfig b/Kconfig
index 6a13094..72425ce 100644
--- a/Kconfig
+++ b/Kconfig
@@ -20,6 +20,11 @@
 	help
 	  Record AOCPU tickcount to register.
 
+config AOCPU_BUSRESPERR_DETECTION
+	bool "AOCPU bus response error detection mechanism"
+	help
+	  Generate irq and show error pc and address.
+
 config RISCV_WCN
 	bool "RISCV for WCN"
 	help
diff --git a/vtable.S b/vtable.S
index cf8abd0..d1dd755 100644
--- a/vtable.S
+++ b/vtable.S
@@ -12,6 +12,8 @@
 
 	.weak  eclic_meip_handler
 
+	.weak  eclic_inner_irq17_handler
+
 	.weak  eclic_irq19_handler
 
 	.weak  eclic_irq20_handler
@@ -76,7 +78,7 @@
 	.word  0
 
 	.word  0
-	.word  0
+	.word  eclic_inner_irq17_handler
 	.word  0
 	.word  eclic_irq19_handler