| commit | 0d1ed95fd8a77bf1db5279a13860e4c9ba39bfbd | [log] [tgz] |
|---|---|---|
| author | Jianyi Shi <jianyi.shi@amlogic.com> | Thu Jul 28 17:54:11 2022 +0800 |
| committer | Jianyi Shi <jianyi.shi@amlogic.com> | Thu Aug 04 02:11:57 2022 -0700 |
| tree | 346493d6a9036f44d740dbc3cfccf5cdb4bf8b01 | |
| parent | 1171aa3caef7e655c36ddad9aca8ad8fdf897994 [diff] |
a5: A5 uart need work at RTC PLL in bl30 during deep sleep mode [3/3] PD#SWPL-73981 Problem: A5 uart need work at rtc pll mode,now sys_clk is 11.171MHz. Solution: Modify code. Verify: a5_av409 Change-Id: I8c2a804717ec5c7363ca6105620e794df8afe3ec Signed-off-by: Jianyi Shi <jianyi.shi@amlogic.com>