| commit | c204bf76ac5e8f02e8f6b48349a89d546d0af399 | [log] [tgz] |
|---|---|---|
| author | Jianyi Shi <jianyi.shi@amlogic.com> | Fri Sep 15 18:36:42 2023 +0800 |
| committer | gerrit autosubmit <gerrit.autosubmit@amlogic.com> | Thu Sep 21 02:08:52 2023 -0700 |
| tree | b0522bc9cb5fdfd47caf78f641450a95402e3f43 | |
| parent | 70557e87ee2f2467ad31469909b9151bcb5d3aeb [diff] |
All_soc: BL30: delay 20ms after vddcpu poweron [1/1] PD#SWPL-140175 Problem: Need to set delay time to 20ms. Solution: Change code. Verify: All_soc pass Change-Id: If3c07a4f43a593200908452bcaec6f1225687aff Signed-off-by: Jianyi Shi <jianyi.shi@amlogic.com>