blob: 7c4fb9fec75b39b6fe96039ee5659040e31a330b [file] [log] [blame]
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +08001/*
yang.li24770372022-01-11 15:21:49 +08002 * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved.
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +08003 *
yang.li24770372022-01-11 15:21:49 +08004 * SPDX-License-Identifier: MIT
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +08005 */
yang.li24770372022-01-11 15:21:49 +08006
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +08007#include "ddr.h"
8#include "common.h"
9#include "register.h"
10#include "FreeRTOS.h"
11#include "task.h"
12#include "soc.h"
13
14/* io defines */
15#define wr_reg(addr, val) (*((volatile uint32_t *)(addr))) = (val)
16#define rd_reg(addr) (*((volatile uint32_t *)(addr)))
17
18/*clear [mask] 0 bits in [addr], set these 0 bits with [value] corresponding bits*/
19#define modify_reg(addr, value, mask) wr_reg(addr, ((rd_reg(addr) & (mask)) | (value)))
20#define wait_set(addr, loc) do {} while (0 == (rd_reg(addr) & (1 << loc)));
21#define wait_clr(addr, loc) do {} while (1 == (rd_reg(addr) & (1 << loc)));
22#define wait_equal(addr, data) do {} while (data != (rd_reg(addr)));
23
24#define _udelay(tim) vTaskDelay(tim)
25
26unsigned int g_nAPDSet = 0;
27#if 0
28void vDDR_suspend(uint32_t st_f)
29{
30 //printf("aml log : DDR suspend...dummy\n");
31 //return;
32
33 printf("aml log : DDR suspend...1");
34
35 g_nAPDSet = rd_reg(DMC_DRAM_APD_CTRL);
36 wr_reg(DMC_DRAM_APD_CTRL,0);
37
38#ifdef CHECK_DMC_IDLE
39 while ((((rd_reg(DMC_DRAM_STAT)) & 0xf0) != 0) &&
40 (((rd_reg(DMC_DRAM_STAT)) & 0xf0) != 0x40)) {
41 }
42#endif
43
44#if 0
45 wr_reg(DMC_DRAM_SCFG, 2);
46 vTaskDelay(pdMS_TO_TICKS(1));
47 while (((((rd_reg(DMC_DRAM_STAT)) >> 4) & 0xf) != 3)) {
48 }
49#endif
50
51 wr_reg(DMC_DRAM_DFIINITCFG, (1 | (1 << 8)));
52
53 wait_clr(DMC_DRAM_DFIINITCFG, 31);
54
55 vTaskDelay(pdMS_TO_TICKS(1));
56 //wr_reg(AM_DDR_PLL_CNTL0,
57 // (rd_reg(AM_DDR_PLL_CNTL0) & (~(0xf << 28))) | (1 << 29));
58
59 printf("done!!\n");
60
61 vTaskDelay(pdMS_TO_TICKS(1000));
62
63 //vDDR_resume(0);
64
65 printf("\naml log : DMC_DRAM_STAT=0x%x",rd_reg(DMC_DRAM_STAT));
66 printf("\naml log : DMC_DRAM_DFIINITCFG=0x%x\n",rd_reg(DMC_DRAM_DFIINITCFG));
67
68}
69
70void vDDR_resume(uint32_t st_f)
71{
72 printf("aml log : DDR resume...2");
73
74 //printf("aml log : DDR resume...dummy\n");
75 //return;
76
77 #if 0
78 do {
79 wr_reg(AM_DDR_PLL_CNTL0, (rd_reg(AM_DDR_PLL_CNTL0) & (~(0xf << 28))) | (0xc << 28));
80 vTaskDelay(pdMS_TO_TICKS(1));
81 wr_reg(AM_DDR_PLL_CNTL0, (rd_reg(AM_DDR_PLL_CNTL0) & (~(0xf << 28))) | (0xd << 28));
82 vTaskDelay(pdMS_TO_TICKS(5));
83 wr_reg(AM_DDR_PLL_CNTL0, (rd_reg(AM_DDR_PLL_CNTL0) & (~(0xf << 28))) | (0x5 << 28));
84 vTaskDelay(pdMS_TO_TICKS(10));
85 wr_reg(AM_DDR_PLL_CNTL0, (rd_reg(AM_DDR_PLL_CNTL0) & (~(0xf << 28))) | (0x7 << 28));
86 vTaskDelay(pdMS_TO_TICKS(100));
87 } while ((0 == ((rd_reg(AM_DDR_PLL_STS) >> 31) & 0x1)));
88 wr_reg(DDR_CLK_CNTL, 0x10000000);
89 wr_reg(DDR_CLK_CNTL, 0xb0000007);
90
91 vTaskDelay(pdMS_TO_TICKS(1));
92 #endif
93
94
95 wr_reg(DMC_DRAM_DFIINITCFG, (0 | (1 << 8)));
96 vTaskDelay(pdMS_TO_TICKS(1));
97
98 printf("-1");
99
100 wait_set(DMC_DRAM_DFIINITCFG, 31);
101 vTaskDelay(pdMS_TO_TICKS(10)); //extra 10us for vt
102#if 0
103 wr_reg(DMC_DRAM_SCFG, 4);
104#endif
105 vTaskDelay(pdMS_TO_TICKS(1));
106
107 printf("-2");
108
109 int nLoopFlag = 1;
110 do {
111
112 switch ((rd_reg(DMC_DRAM_STAT)) & 0xf0)
113 {
114 case 0: //DRAM IDLE
115 case 0x20: //DRAM ACCESS
116 case 0x40: //DRAM APD
117 nLoopFlag = 0;
118 break;
119 default: break;
120 }
121 } while(nLoopFlag);
122
123 vTaskDelay(pdMS_TO_TICKS(30));
124
125 printf("-3");
126
127 printf("done\n");
128
129 printf("\naml log : DMC_DRAM_STAT=0x%x",rd_reg(DMC_DRAM_STAT));
130 printf("\naml log : DMC_DRAM_DFIINITCFG=0x%x\n",rd_reg(DMC_DRAM_DFIINITCFG));
131
132}
133#endif
134
135/*
136#define PATTERN_MATRIX_X (3 + 32 + 16 + 17) //68*32==2176 ///2.2k -0x880-1 loop
137#define PATTERN_MATRIX_Y (32)
138#define PATTERN_MATRIX_LOOP_SIZE ((PATTERN_MATRIX_X)*(PATTERN_MATRIX_Y) * 4)
139unsigned int cpu_ddr_test_init_pattern_generater(uint32_t martix_x_select, uint32_t martix_y_select)
140{
141 unsigned int pattern_value = 0;
142 unsigned int pattern_value_temp_16 = 0;
143
144 martix_x_select = (martix_x_select % PATTERN_MATRIX_X);
145 {
146 {
147 {
148 if (martix_x_select == 0)
149 pattern_value = 0xaaaa5555; //for 16 bit bus pattern
150
151 if (martix_x_select == 1)
152 pattern_value = 0x0000ffff; //for 16 bit bus pattern
153
154 if (martix_x_select == 2)
155 pattern_value = 0;
156
157 if ((martix_x_select > 2) && (martix_x_select < (3 + 32)))
158 pattern_value = 1 << (martix_x_select - 3);
159 if ((martix_x_select > (2 + 32)) && (martix_x_select < (3 + 32 + 16))) { //for 16 bit bus pattern
160 pattern_value_temp_16 = (1 << (martix_x_select - 3 - 32));
161 pattern_value = pattern_value_temp_16 | ((~pattern_value_temp_16) << 16);
162 }
163 if ((martix_x_select > (2 + 32 + 16)) && (martix_x_select < (3 + 32 + 16 + 17))) { //for dbi bus pattern 17 group
164 pattern_value_temp_16 = (0x0f0f + 0xf0f * (martix_x_select - 3 - 32 - 16));
165 pattern_value = pattern_value_temp_16 | ((~pattern_value_temp_16) << 16);
166 }
167 }
168 if ((martix_y_select % 2))
169 pattern_value = ~pattern_value;
170 if ((martix_y_select % ((PATTERN_MATRIX_Y) / 2)) == (((PATTERN_MATRIX_Y * 1) / 8) - 1)) //for dbi pattern walk 0 and walk 1
171 pattern_value = 0; //insert for dbi pattern jiaxing 20190117
172 if ((martix_y_select % ((PATTERN_MATRIX_Y) / 2)) == (((PATTERN_MATRIX_Y * 3) / 8) - 1)) //for dbi pattern walk 0 and walk 1
173 pattern_value = ~0; //insert for dbi pattern jiaxing 20190117
174 }
175 }
176 return pattern_value;
177}
178*/
179#if 0
180static unsigned int dmc_ddr_test(unsigned int start_add, unsigned int write_enable, unsigned int read_enable, unsigned int read_compare, unsigned int test_end_add, unsigned int pattern, unsigned int seed)
181{
182 seed=2;
183#define DATA_LOOP_PATTERN_INDEX 4 + 32 //0xff
184 unsigned int dmc_test_sts = 0;
185 unsigned int dmc_error = 0;
186 //unsigned int pattern_select = 0;
187 unsigned int pattern_value = 0;
188 unsigned int pattern_inv_value = 0;
189
190 dmc_error = 0;
191 {
192 test_end_add = test_end_add - 4; //sha must bit 0-6 ==ff;
193 }
194 wr_reg(DMC_TEST_STA, start_add); // RESET FIFOS //0x03d81e3f
195 wr_reg(DMC_TEST_EDA, test_end_add); //0x07d81e3f
196 if (pattern == 0) {
197 wr_reg(DMC_TEST_WD0, 0xaa5555aa);
198 wr_reg(DMC_TEST_WD1, 0x55aaaa55);
199 wr_reg(DMC_TEST_WD2, 0);
200 wr_reg(DMC_TEST_WD3, 0xffffffff);
201 wr_reg(DMC_TEST_WD4, 0);
202 wr_reg(DMC_TEST_WD5, 0x0000ffff);
203 wr_reg(DMC_TEST_WD6, 0xffff0000);
204 wr_reg(DMC_TEST_WD7, 0x33cccc33);
205 wr_reg(DMC_TEST_WD0 + 32, 0xaa5555aa);
206 wr_reg(DMC_TEST_WD1 + 32, 0x55aaaa55);
207 wr_reg(DMC_TEST_WD2 + 32, 0);
208 wr_reg(DMC_TEST_WD3 + 32, 0xffffffff);
209 wr_reg(DMC_TEST_WD4 + 32, 0);
210 wr_reg(DMC_TEST_WD5 + 32, 0x0000ffff);
211 wr_reg(DMC_TEST_WD6 + 32, 0xffff0000);
212 wr_reg(DMC_TEST_WD7 + 32, 0x33cccc33);
213 } else if (pattern < 33) {
214 wr_reg(DMC_TEST_WD0, ((1 << (pattern - 1)) + seed));
215 wr_reg(DMC_TEST_WD1, ((2 << (pattern - 1)) + seed));
216 wr_reg(DMC_TEST_WD2, ((3 << (pattern - 1)) + seed));
217 wr_reg(DMC_TEST_WD3, ((4 << (pattern - 1)) + seed));
218 wr_reg(DMC_TEST_WD4, ((4 << (pattern - 1))));
219 wr_reg(DMC_TEST_WD5, ((4 << (pattern - 1))));
220 wr_reg(DMC_TEST_WD6, ((4 << (pattern - 1))));
221 wr_reg(DMC_TEST_WD7, ((4 << (pattern - 1))));
222 if (pattern > 16) {
223 wr_reg(DMC_TEST_WD4, ((4 << (pattern - 1)) + 0x01010101));
224 wr_reg(DMC_TEST_WD5, ((4 << (pattern - 1)) + 0x01010101));
225 wr_reg(DMC_TEST_WD6, ((4 << (pattern - 1)) + 0x01010101));
226 wr_reg(DMC_TEST_WD7, ((4 << (pattern - 1)) + 0x01010101));
227 } else if (pattern > 1) {
228 wr_reg(DMC_TEST_WD4, ((4 << (pattern - 1)) + 0x01010101));
229 wr_reg(DMC_TEST_WD5, ((4 << (pattern - 1)) + 0x01010101));
230 wr_reg(DMC_TEST_WD6, ((4 << (pattern - 1)) + 0x01010101));
231 wr_reg(DMC_TEST_WD7, ((4 << (pattern - 1)) + 0x01010101));
232 }
233 } else {
234 //pattern_select = pattern - 33;
235 pattern_value =1;// cpu_ddr_test_init_pattern_generater(pattern_select, 0);
236 pattern_inv_value = ~pattern_value;
237 for (char counter = 0; counter < 32; ) {
238 wr_reg((DMC_TEST_WD0 + counter), pattern_value);
239 counter = counter + 4;
240 wr_reg((DMC_TEST_WD0 + counter), pattern_inv_value);
241 if (counter == 16)
242 wr_reg((DMC_TEST_WD0 + counter), 0);
243 counter = counter + 4;
244 }
245 for (char counter = 0; counter < 32; ) { //for g12b-revb register not continuous
246 wr_reg((DMC_TEST_WD8 + counter), pattern_value);
247 counter = counter + 4;
248 wr_reg((DMC_TEST_WD8 + counter), pattern_inv_value);
249 if (counter == 16)
250 wr_reg((DMC_TEST_WD0 + counter), ~0);
251 counter = counter + 4;
252 }
253 }
254
255
256 wr_reg(DMC_TEST_STS, 0x8000001f); //must clear watchdog and done flag jiaxing debug 2016_12_07
257 wr_reg(DMC_TEST_WDG, 0xf000f000); //wdg should >rfc value ,use dmc clk count.
258 if ((pattern == 1) || ((pattern < 33) && pattern)) //should repeat 1 times for read ,all will fail when data increase jiaxing debug 20180322
259 wr_reg(DMC_TEST_CTRL, (1 << 31) | (read_compare << 27) | (0 << 28) | (0 << 25) | (1 << 24) | (0 << 20) | (1 << 23) | (0x0 << 16) | (0 << 8) | (0x428) | (3 << 18) | (write_enable << 30) | (read_enable << 29));
260 else
261 wr_reg(DMC_TEST_CTRL, (1 << 31) | (read_compare << 27) | (0 << 28) | (1 << 24) | (0x0 << 16) | (0 << 18) | (0x0 << 0) | (0 << 8) | (0x428) | (3 << 18) | (write_enable << 30) | (read_enable << 29));
262
263 do
264 //_udelay(1);
265 dmc_test_sts = (rd_reg(DMC_TEST_STS));
266 while (!(dmc_test_sts & 0xc0000000));
267
268 wr_reg(DMC_TEST_CTRL, 0x00000000);
269
270 if ((dmc_test_sts & 0x40000000))
271 dmc_error = 1;
272 else
273 if (dmc_test_sts & 0x40000001) //can not deter write triger ,or can not guickly recover dmc with phy? 2016_12_12
274 dmc_error = 1;
275
276 dmc_error = dmc_error + (rd_reg(DMC_TEST_ERR_CNT));
277 wr_reg(DMC_TEST_STS, 0x8000001f); //must clear watchdog and done flag jiaxing debug 2016_12_07
278
279 if (dmc_error) {
280 for (unsigned int counter1 = 0; counter1 < (DMC_TEST_RDRSP_ADDR+4-DMC_TEST_STA); )
281 {
282 printf( "\ncounter %08x %08x",counter1,(rd_reg(DMC_TEST_STA+(counter1))));
283 counter1=counter1+4;
284 }
285 wr_reg(DMC_SOFT_RST, (rd_reg(DMC_SOFT_RST)) & (~((1 << 29) | (1 << 24)))); //clear read buffer dmc test reset
286 vTaskDelay(pdMS_TO_TICKS(1));
287 wr_reg(DMC_SOFT_RST, (rd_reg(DMC_SOFT_RST)) | ((1 << 29)) | (1 << 24));
288 vTaskDelay(pdMS_TO_TICKS(1));
289 }
290 return dmc_error;
291}
292
293unsigned int apb_sec_ctrl = 0;
294#define DDR_APB_SEC_CTRL ((0x00f0 << 2) + 0xff639000)
295#endif
296#if 0 //def CFG_ENABLE_DDR_SUSPEND_TEST
297static void ddr_suspend_resume_test(uint32_t test_size, uint32_t test_delay_time_ms, uint32_t test_write_loops, uint32_t test_read_loops, uint32_t test_skip_suspend, uint32_t p_dev)
298{
299 //return;
300 uint32_t lock_cnt = 100;
301 uint32_t apd_value = 0;
302 p_dev = p_dev;
303 printf( "enter suspend_n_debug\n");
304 apd_value = rd_reg(DMC_DRAM_APD_CTRL);
305 wr_reg(DMC_DRAM_APD_CTRL, 0);
306
307 //watchdog_disable();
308 printf( "test_size=%08x test_delay_time_ms=%d test_write_loops=%d test_read_loops=%d", \
309 test_size, test_delay_time_ms, test_write_loops, test_read_loops);
310 printf( "enter suspend111\n");
311
312#if 1 //def CFG_ENABLE_DDR_DMC_TEST
313 uint64_t dram_size = 0, dram_base = 0;
314 dram_base = 0x0000000; // p_ddrs->ddr_base_addr;
315 //dram_size = 1024;//p_ddrs->cfg_board_common_setting.dram_cs0_size_MB + p_ddrs->cfg_board_common_setting.dram_cs1_size_MB;
316 dram_size =1024;
317
318 if (!test_size)
319 test_size = (dram_size << 20) - 4;
320
321 //if (!test_delay_time_ms)
322 // test_delay_time_ms = 3000;
323
324 if (!test_write_loops)
325 test_write_loops = 1;
326
327 if (!test_read_loops)
328 test_read_loops = 1;
329 uint32_t ddr_bist_test_error = 0;
330#endif
331
332 while ((test_write_loops) || (test_read_loops)) {
333 if (test_write_loops)
334 ddr_bist_test_error = dmc_ddr_test(dram_base, 1, 0, 0, test_size, 1, 0) + ddr_bist_test_error;
335printf( "enter suspend113\n");
336 if (!test_skip_suspend) {
337#if 0 //def CHECK_DMC_IDLE
338 while ((((rd_reg(DMC_DRAM_STAT)) & 0xf0) != 0) && (((rd_reg(DMC_DRAM_STAT)) & 0xf0) != 0x40)) {
339 }
340#endif
341#if 0
342 wr_reg(DMC_DRAM_SCFG, 2);
343 vTaskDelay(pdMS_TO_TICKS(1));
344
345 while (((((rd_reg(DMC_DRAM_STAT)) >> 4) & 0xf) != 3)) {
346 }
347#endif
348//printf( "enter suspend114\n");
349 wr_reg(DMC_DRAM_DFIINITCFG, (1 | (0 << 1) | (0 << 6) | (0 << 14) | (1 << 8)));
350 vTaskDelay(pdMS_TO_TICKS(1));
351 wait_clr(DMC_DRAM_DFIINITCFG, 31); //final version, wait_clr
352 vTaskDelay(pdMS_TO_TICKS(3));
353 // printf( "enter suspend115\n");
354 wr_reg(AM_DDR_PLL_CNTL0, (rd_reg(AM_DDR_PLL_CNTL0) & (~(0xf << 28))) | (1 << 29));
355 }
356 //_udelay(test_delay_time_ms * 1000);
357 vTaskDelay(test_delay_time_ms * pdMS_TO_TICKS(1000));
358 //_udelay( 1000);
359printf( "enter suspend111..wait\n");
360 if (!test_skip_suspend) {
361 printf("enter resume\n");
362
363 do {
364 wr_reg(AM_DDR_PLL_CNTL0, (rd_reg(AM_DDR_PLL_CNTL0) & (~(0xf << 28))) | (1 << 29));
365 vTaskDelay(pdMS_TO_TICKS(1));
366 wr_reg(AM_DDR_PLL_CNTL0, (rd_reg(AM_DDR_PLL_CNTL0) & (~(0x1 << 29))) | (1 << 28));
367
368 vTaskDelay(pdMS_TO_TICKS(200)); //must wait some time than to read
369 } while ((0 == ((rd_reg(AM_DDR_PLL_CNTL0) >> 31) & 0x1)) && (lock_cnt--));
370
371 printf( "pll relock ok\n"); //need extra delay
372 vTaskDelay(pdMS_TO_TICKS(1));
373 wr_reg(DMC_DRAM_DFIINITCFG, (0 | (0 << 1) | (0 << 6) | (0 << 14) | (1 << 8)));
374 vTaskDelay(pdMS_TO_TICKS(1));
375 wait_set(DMC_DRAM_DFIINITCFG, 31);
376 vTaskDelay(pdMS_TO_TICKS(100)); //extra 10us for vt
377 }
378#if 1 //def CFG_ENABLE_DDR_DMC_TEST
379 if (test_read_loops)
380 ddr_bist_test_error = dmc_ddr_test(dram_base, 0, 1, 1, test_size, 1, 0) + ddr_bist_test_error;
381 //if (ddr_bist_test_error)
382 printf( "dmc full test result = %d\n", ddr_bist_test_error);
383#endif
384
385 if (test_write_loops)
386 test_write_loops--;
387
388 if (test_read_loops)
389 test_read_loops--;
390 }
391 wr_reg(DMC_DRAM_APD_CTRL, apd_value);
392
393 //printf("end resume test11\n");
394} /* ddr_suspend_resume_test */
395#endif
396 //#define DDR_SUSPEND_MODE_DMC_TRIGGER_SUSPEND_1 1
397 #define DDR_SUSPEND_MODE_MANUAL_TRIGGER_DFI_INIT_START 2
398void vDDR_suspend(uint32_t st_f)
399{
400 //printf("aml log : DDR suspend...dummy\n");
401 //return;
402
403 st_f = st_f;
404 //unsigned int time_start, time_end;
405 printf("Enter ddr suspend\n");
406
407 //return ;
408
409 while (0xfffffff != rd_reg(DMC_CHAN_STS)) {
410 printf("DMC_CHAN_STS: 0x%x\n", rd_reg(DMC_CHAN_STS));
411 vTaskDelay(pdMS_TO_TICKS(100000));
412 }
413
414 //time_start = rd_reg(P_ISA_TIMERE);
415
416 /* open DMC reg access for M3 */
417 //apb_sec_ctrl = rd_reg(DDR_APB_SEC_CTRL);
418 //wr_reg(DDR_APB_SEC_CTRL,0x91911);
419
420 wr_reg(DMC_REQ_CTRL, 0); //bit0: A53.
421 _udelay(1);
422
423 /* suspend flow */
424 while ((((rd_reg(DMC_DRAM_STAT))&0xf0) != 0) && (((rd_reg(DMC_DRAM_STAT))&0xf0) != 0x40)) {
425 // printf("DMC_DRAM_STAT11: 0x%x\n", rd_reg(DMC_DRAM_STAT));
426 vTaskDelay(pdMS_TO_TICKS(1));
427 }
428#ifdef DDR_SUSPEND_MODE_DMC_TRIGGER_SUSPEND_1
429 wr_reg(DMC_DRAM_ASR_CTRL,(1<<18)); //bit 18 will auto trigger dfi init start cmd when scfg set to value 2
430 wr_reg(DMC_DRAM_SCFG, 2);
431 while (((((rd_reg(DMC_DRAM_STAT))>>4)&0xf) != 3)) {
432 //printf("DMC_DRAM_STAT22: 0x%x\n", readl(DMC_DRAM_STAT));
433 //_udelay(1);//do not add any delay,since use ao cpu maybe speed too slow
434 }
435
436#endif
437
438#ifdef DDR_SUSPEND_MODE_MANUAL_TRIGGER_DFI_INIT_START
439 wr_reg(DMC_DRAM_SCFG, 1);
440 while (((((rd_reg(DMC_DRAM_STAT))>>4)&0xf) != 1)) {
441 //printf("DMC_DRAM_STAT22: 0x%x\n", readl(DMC_DRAM_STAT));
442 //_udelay(1);//do not add any delay,since use ao cpu maybe speed too slow
443 }
444
445 wr_reg(DMC_DRAM_DFIINITCFG, (1 | (0 << 1) | (0 << 6) | (0 << 14) | (1 << 8)));
446 vTaskDelay(pdMS_TO_TICKS(1));
447 wait_clr(DMC_DRAM_DFIINITCFG, 31);
448#endif //final version, wait_clr
449 vTaskDelay(pdMS_TO_TICKS(3));
450 wr_reg(AM_DDR_PLL_CNTL0, (rd_reg(AM_DDR_PLL_CNTL0) & (~(0xf << 28))) | (1 << 29));
451
452
453 /* print time consumption */
454 //time_end = rd_reg(P_ISA_TIMERE);
455 //printf("ddr suspend time: %dus\n", time_end - time_start);
456 printf("\nddr suspend is done\n");
457 //ddr_suspend_resume_test((1024<<20), 100, 3, 3, 0, 0);
458 //ddr_suspend_resume_test((80<<20), 10000000, 0, 3, 0, 0);
459}
460
461static unsigned int pll_lock(void) {
462 unsigned int lock_cnt = 100;
463 do {
464 wr_reg(AM_DDR_PLL_CNTL0, (rd_reg(AM_DDR_PLL_CNTL0) & (~(0xf<<28))) | (1<<29));
465 vTaskDelay(pdMS_TO_TICKS(1));
466 wr_reg(AM_DDR_PLL_CNTL0, (rd_reg(AM_DDR_PLL_CNTL0) & (~(0x1<<29))) | (1<<28));
467 vTaskDelay(pdMS_TO_TICKS(200));
468 } while((0 == ((rd_reg(AM_DDR_PLL_CNTL0) >> 31) & 0x1)) && (lock_cnt--));
469 return lock_cnt;
470}
471
472void vDDR_resume(uint32_t st_f)
473{
474 //unsigned int time_start, time_end;
475 unsigned int ret = 0;
476
477 st_f = st_f;
478 printf("Enter ddr resume\n");
479
480
481 //return;
482
483 //time_start = rd_reg(P_ISA_TIMERE);
484 /* resume flow */
485 #if 1
486 ret = pll_lock();
487 if (!ret) {
488 printf("ddr pll lock r1\n");
489 wr_reg(AM_DDR_PLL_CNTL3, rd_reg(AM_DDR_PLL_CNTL3)|(1<<31));
490 ret = pll_lock();
491 if (!ret) {
492 printf("ddr pll lock r2\n");
493 wr_reg(AM_DDR_PLL_CNTL6, 0x55540000);
494 ret = pll_lock();
495 if (!ret) {
496 printf("ddr pll lock r2\n");
497 while (1) {};
498 }
499 }
500 }
501#endif
502
503#ifdef DDR_SUSPEND_MODE_DMC_TRIGGER_SUSPEND_1
504
505#endif
506
507#ifdef DDR_SUSPEND_MODE_MANUAL_TRIGGER_DFI_INIT_START
508 wr_reg(DMC_DRAM_DFIINITCFG, (0 | (0 << 1) | (0 << 6) | (0 << 14) | (1 << 8)));
509 vTaskDelay(pdMS_TO_TICKS(1));
510 wait_set(DMC_DRAM_DFIINITCFG, 31);
511 vTaskDelay(pdMS_TO_TICKS(100));
512#endif
513 wr_reg(DMC_DRAM_SCFG, 4);
514 while (((((rd_reg(DMC_DRAM_STAT))>>4)&0xf) != 2)) {
515 //printf("DMC_DRAM_STAT22: 0x%x\n", readl(DMC_DRAM_STAT));
516 //_udelay(1);//do not add any delay,since use ao cpu maybe speed too slow
517 }
518
519 #if 0
520 wr_reg( DMC_DRAM_SCFG, 4);
521 vTaskDelay(pdMS_TO_TICKS(1));
522 #endif
523
524 wr_reg(DMC_REQ_CTRL, 0xffffffff);
525 //wr_reg(DDR_APB_SEC_CTRL, apb_sec_ctrl);
526 /* print time consumption */
527 //time_end = readl(P_ISA_TIMERE);
528 //printf("ddr resume time: %dus\n", time_end - time_start);
529 // unsigned int ddr_bist_test_error = 0;
530 //ddr_bist_test_error = dmc_ddr_test(dram_base, 0, 1, 1, test_size, 1, 0) + ddr_bist_test_error;
531 //ddr_bist_test_error = dmc_ddr_test(0, 0, 1, 1, (80<<20), 1, 0) + ddr_bist_test_error;
532 //printf("ddr_bist_test_error = %d\n", ddr_bist_test_error);
533 //wr_reg(0xfe002440, 2);
534// wr_reg(0xfe002440, 0);
535// _udelay(300);
536 //ddr_bist_test_error = dmc_ddr_test(0, 1, 0, 0, (1<<20), 1, 0) + ddr_bist_test_error;
537 //ddr_bist_test_error = dmc_ddr_test(0, 0, 1, 1, (1<<20), 1, 0) + ddr_bist_test_error;
538// printf("ddr_bist_test_error = %d\n", ddr_bist_test_error);
539 //ddr_suspend_resume_test((1<<20), 2, 1, 3, 0, 0);
540 //ddr_suspend_resume_test((1<<20), 0, 1, 3, 0, 0);
541 //_udelay(300);
542// wr_reg(DMC_REQ_CTRL, 0xffffffff);
543 printf("ddr resume done\n");
544}
545
546