SoC s7d: ir support [1/1]
PD#SWPL-163019
Problem:
s7d need ir support
Solution:
update s7d ir controller irq num
Verify:
s7d_bm201
Change-Id: I5cb144a48415e1a565f148eb330b08241675041a
Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
diff --git a/s7d/irq.h b/s7d/irq.h
index 8b7af1d..17d1d30 100644
--- a/s7d/irq.h
+++ b/s7d/irq.h
@@ -36,7 +36,8 @@
/*You can add other interrupts num here 46~19*/
/* use for ir */
-#define IRQ_NUM_IRIN 136
+#define IRQ_NUM_IRIN 148
+#define IRQ_NUM_IRIN_EXT 147
/* uart */
#define IRQ_NUM_AO_UART_C 138
diff --git a/s7d/register.h b/s7d/register.h
index 4878be1..2fbdcc1 100644
--- a/s7d/register.h
+++ b/s7d/register.h
@@ -3916,50 +3916,8 @@
// -----------------------------------------------
// REG_BASE: REGISTER_BASE_ADDR = 0xfe084000
// -----------------------------------------------
-#define IRCTRL_IR_DEC_LDR_ACTIVE ((0x0000 << 2) + 0xfe084000)
-#define IRCTRL_IR_DEC_LDR_IDLE ((0x0001 << 2) + 0xfe084000)
-#define IRCTRL_IR_DEC_LDR_REPEAT ((0x0002 << 2) + 0xfe084000)
-#define IRCTRL_IR_DEC_BIT_0 ((0x0003 << 2) + 0xfe084000)
-#define IRCTRL_IR_DEC_REG0 ((0x0004 << 2) + 0xfe084000)
-#define IRCTRL_IR_DEC_FRAME ((0x0005 << 2) + 0xfe084000)
-#define IRCTRL_IR_DEC_STATUS ((0x0006 << 2) + 0xfe084000)
-#define IRCTRL_IR_DEC_REG1 ((0x0007 << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_LDR_ACTIVE ((0x0010 << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_LDR_IDLE ((0x0011 << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_LDR_REPEAT ((0x0012 << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_BIT_0 ((0x0013 << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_REG0 ((0x0014 << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_FRAME ((0x0015 << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_STATUS ((0x0016 << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_REG1 ((0x0017 << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_REG2 ((0x0018 << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_DURATN2 ((0x0019 << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_DURATN3 ((0x001a << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_FRAME1 ((0x001b << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_STATUS1 ((0x001c << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_STATUS2 ((0x001d << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_REG3 ((0x001e << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_FRAME_RSV0 ((0x001f << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_FRAME_RSV1 ((0x0020 << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_FILTE ((0x0021 << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_IRQ_CTL ((0x0022 << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_FIFO_CTL ((0x0023 << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_WIDTH_NEW ((0x0024 << 2) + 0xfe084000)
-#define IRCTRL_MF_IR_DEC_REPEAT_DET ((0x0025 << 2) + 0xfe084000)
-#define IRCTRL_IR_DEC_DEMOD_CNTL0 ((0x0030 << 2) + 0xfe084000)
-#define IRCTRL_IR_DEC_DEMOD_CNTL1 ((0x0031 << 2) + 0xfe084000)
-#define IRCTRL_IR_DEC_DEMOD_IIR_THD ((0x0032 << 2) + 0xfe084000)
-#define IRCTRL_IR_DEC_DEMOD_THD0 ((0x0033 << 2) + 0xfe084000)
-#define IRCTRL_IR_DEC_DEMOD_THD1 ((0x0034 << 2) + 0xfe084000)
-#define IRCTRL_IR_DEC_DEMOD_SUM_CNT0 ((0x0035 << 2) + 0xfe084000)
-#define IRCTRL_IR_DEC_DEMOD_SUM_CNT1 ((0x0036 << 2) + 0xfe084000)
-#define IRCTRL_IR_DEC_DEMOD_CNT0 ((0x0037 << 2) + 0xfe084000)
-#define IRCTRL_IR_DEC_DEMOD_CNT1 ((0x0038 << 2) + 0xfe084000)
-#define IRCTRL_IR_DEC_DEMOD_FILTER ((0x0039 << 2) + 0xfe084000)
-#define IRCTRL_IR_BLASTER_ADDR0 ((0x0043 << 2) + 0xfe084000)
-#define IRCTRL_IR_BLASTER_ADDR1 ((0x0044 << 2) + 0xfe084000)
-#define IRCTRL_IR_BLASTER_ADDR2 ((0x0045 << 2) + 0xfe084000)
-#define IRCTRL_IR_BLASTER_ADDR3 ((0x0046 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC0_LDR_ACTIVE ((0x0000 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC1_LDR_ACTIVE ((0x0020 << 2) + 0xfe084000)
//========================================================================
// I2C Master A
//========================================================================