SoC common: aocpu add detection for no access permission [2/3]
PD#SWPL-174194
Problem:
aocpu access addr with no permission would not read or
write successfully, and no exception occurs.
Solution:
aocpu add detection for no access permission.
Verify:
s6_bl201
Change-Id: Ibfa04890056e7f3f2d6fd9e7851528e107125915
Signed-off-by: bangzheng.liu <bangzheng.liu@amlogic.com>
diff --git a/a4/Kconfig b/a4/Kconfig
index 8d73b47..8c19d07 100644
--- a/a4/Kconfig
+++ b/a4/Kconfig
@@ -5,5 +5,6 @@
config SOC_A4
bool "A4"
select RISCV
+ select AOCPU_BUSRESPERR_DETECTION
help
- Enable A4 SOC of RISCV.
\ No newline at end of file
+ Enable A4 SOC of RISCV.
diff --git a/a5/Kconfig b/a5/Kconfig
index f8341c0..a826583 100644
--- a/a5/Kconfig
+++ b/a5/Kconfig
@@ -5,5 +5,6 @@
config SOC_A5
bool "A5"
select RISCV
+ select AOCPU_BUSRESPERR_DETECTION
help
- Enable A5 SOC of RISCV.
\ No newline at end of file
+ Enable A5 SOC of RISCV.
diff --git a/n200_eclic.h b/n200_eclic.h
index 0665ed3..1d327c1 100644
--- a/n200_eclic.h
+++ b/n200_eclic.h
@@ -55,7 +55,9 @@
#define ECLIC_INT_MSIP 3
#define ECLIC_INT_MTIP 7
#define ECLIC_INT_MEIP 11
+#define ECLIC_INT_BUS_RESP_ERR 17
+#define BUS_RESP_ERR_HANDLER eclic_inner_irq17_handler
#define BUTTON_1_HANDLER eclic_irq49_handler
#define MTIME_HANDLER eclic_mtip_handler
diff --git a/n200_func.c b/n200_func.c
index f972456..9fdc8f8 100644
--- a/n200_func.c
+++ b/n200_func.c
@@ -157,6 +157,21 @@
return 0;
}
+
+#ifdef CONFIG_AOCPU_BUSRESPERR_DETECTION
+void config_eclic_busresperr_irq(void)
+{
+ /* enable bus response error interrupt for no access permission */
+ uint8_t bus_err_intattr;
+
+ bus_err_intattr = eclic_get_intattr(ECLIC_INT_BUS_RESP_ERR);
+ bus_err_intattr |= ECLIC_INT_ATTR_SHV | ECLIC_INT_ATTR_TRIG_EDGE;
+ eclic_set_intattr(ECLIC_INT_BUS_RESP_ERR, bus_err_intattr);
+ eclic_set_intctrl(ECLIC_INT_BUS_RESP_ERR, 15 << 4);
+ eclic_enable_interrupt(ECLIC_INT_BUS_RESP_ERR);
+
+}
+#endif
#endif
void switch_m2u_mode(void)
diff --git a/n200_func.h b/n200_func.h
index de57a9f..34595ba 100644
--- a/n200_func.h
+++ b/n200_func.h
@@ -46,7 +46,9 @@
extern uint32_t _etext;
uint32_t config_pmp(void);
-
+#ifdef CONFIG_AOCPU_BUSRESPERR_DETECTION
+void config_eclic_busresperr_irq(void);
+#endif
void pmp_open_all_space(void);
void switch_m2u_mode(void);
diff --git a/s1a/Kconfig b/s1a/Kconfig
index 3d354fa..96eabf4 100644
--- a/s1a/Kconfig
+++ b/s1a/Kconfig
@@ -5,6 +5,7 @@
config SOC_S1A
bool "S1A"
select RISCV
+ select AOCPU_BUSRESPERR_DETECTION
help
Enable S1A SOC of RISCV.
diff --git a/s5/Kconfig b/s5/Kconfig
index d5655c3..72285aa 100644
--- a/s5/Kconfig
+++ b/s5/Kconfig
@@ -5,6 +5,7 @@
config SOC_S5
bool "S5"
select RISCV
+ select AOCPU_BUSRESPERR_DETECTION
help
Enable S5 SOC of RISCV.
diff --git a/s6/Kconfig b/s6/Kconfig
index 7a88315..6a932fa 100644
--- a/s6/Kconfig
+++ b/s6/Kconfig
@@ -5,5 +5,6 @@
config SOC_S6
bool "S6"
select RISCV
+ select AOCPU_BUSRESPERR_DETECTION
help
Enable S6 SOC of RISCV.
diff --git a/s7/Kconfig b/s7/Kconfig
index a2ac089..e5665ae 100644
--- a/s7/Kconfig
+++ b/s7/Kconfig
@@ -5,5 +5,6 @@
config SOC_S7
bool "S7"
select RISCV
+ select AOCPU_BUSRESPERR_DETECTION
help
- Enable S7 SOC of RISCV.
\ No newline at end of file
+ Enable S7 SOC of RISCV.
diff --git a/s7d/Kconfig b/s7d/Kconfig
index 96ef294..9ed1929 100644
--- a/s7d/Kconfig
+++ b/s7d/Kconfig
@@ -5,5 +5,6 @@
config SOC_S7D
bool "S7D"
select RISCV
+ select AOCPU_BUSRESPERR_DETECTION
help
- Enable S7D SOC of RISCV.
\ No newline at end of file
+ Enable S7D SOC of RISCV.
diff --git a/t3x/Kconfig b/t3x/Kconfig
index ab4cea0..360bdae 100644
--- a/t3x/Kconfig
+++ b/t3x/Kconfig
@@ -5,6 +5,7 @@
config SOC_T3X
bool "T3X"
select RISCV
+ select AOCPU_BUSRESPERR_DETECTION
help
Enable T3X SOC of RISCV.
diff --git a/t5m/Kconfig b/t5m/Kconfig
index 4e1c06c..5c0dfc7 100644
--- a/t5m/Kconfig
+++ b/t5m/Kconfig
@@ -5,6 +5,7 @@
config SOC_T5M
bool "T5M"
select RISCV
+ select AOCPU_BUSRESPERR_DETECTION
help
Enable T5M SOC of RISCV.
diff --git a/t6d/Kconfig b/t6d/Kconfig
index fb5134d..4757ae4 100644
--- a/t6d/Kconfig
+++ b/t6d/Kconfig
@@ -5,6 +5,7 @@
config SOC_T6D
bool "T6D"
select RISCV
+ select AOCPU_BUSRESPERR_DETECTION
help
Enable T6D SOC of RISCV.
diff --git a/txhd2/Kconfig b/txhd2/Kconfig
index b38ab48..a5e5734 100644
--- a/txhd2/Kconfig
+++ b/txhd2/Kconfig
@@ -6,5 +6,6 @@
bool "TXHD2"
select RISCV
select SOC_OLD_ARCH
+ select AOCPU_BUSRESPERR_DETECTION
help
Enable TXHD2 SOC of RISCV.