commit 4388c24344068c8020ea5ce5fa7b4524964dd305
author Huqiang Qin <huqiang.qin@amlogic.com> Mon Jul 01 16:21:59 2024 +0800
committer gerrit autosubmit <gerrit.autosubmit@amlogic.com> Tue Jul 02 03:43:42 2024 -0700
tree d06680710e37cc3af3ef4bb17f28e486857ec4fd
parent 724be6c9b79e8dc96bea95b5150c49323689a294

SoC s7d: saradc: optimize register configuration [1/1]

PD#SWPL-174303

Problem:
Adjust according to VLSI suggestions.

Solution:
Optimize register configuration.

Verify:
S7D/BM201

Change-Id: I8fa44122a725953d10f137d87c1c354589ec9e76
Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com>

s7d/saradc-data.h

diff --git a/s7d/saradc-data.h b/s7d/saradc-data.h
index 2215053..4feb03a 100644
--- a/s7d/saradc-data.h
+++ b/s7d/saradc-data.h
@@ -12,7 +12,7 @@
 #define SAR_CLK_BASE CLKCTRL_SAR_CLK_CTRL0
 #define SARADC_BASE SAR_ADC_REG0
 
-#define SARADC_REG7_INIT 0x00000c21
+#define SARADC_REG7_INIT 0x00000c11
 #define SARADC_REG8_INIT 0x0280614d
 #define SARADC_REG3_INIT 0x10a02403
 #define SARADC_REG4_INIT 0x00000080