soc/riscv: Modifications for A5's AOCPU supported. [1/1]

PD#SWPL-67429

Problem:
Modifications for A5's AOCPU supported.

Solution:
Modifications for A5's AOCPU supported.

Verify:
av409_a113x2

Change-Id: I9ee4999197d468f3ff8c846d21c9a9e67bbdb803
Signed-off-by: Xiaohu.Huang <xiaohu.huang@amlogic.com>
diff --git a/n200_func.c b/n200_func.c
index 0fa9f19..7decc50 100644
--- a/n200_func.c
+++ b/n200_func.c
@@ -37,13 +37,21 @@
 
 uint32_t mtime_lo(void)
 {
-  return *(volatile uint32_t *)(TIMER_CTRL_ADDR + TIMER_MTIME);
+#ifdef configSOC_TIMER_AS_TICK
+    return *(volatile uint32_t *)TIMERE_LOW_REG;
+#else
+    return *(volatile uint32_t *)(TIMER_CTRL_ADDR + TIMER_MTIME);
+#endif
 }
 
 
 uint32_t mtime_hi(void)
 {
-  return *(volatile uint32_t *)(TIMER_CTRL_ADDR + TIMER_MTIME + 4);
+#ifdef configSOC_TIMER_AS_TICK
+    return *(volatile uint32_t *)TIMERE_HIG_REG;
+#else
+    return *(volatile uint32_t *)(TIMER_CTRL_ADDR + TIMER_MTIME + 4);
+#endif
 }
 
 uint64_t get_timer_value(void)