bl30: rtos_sdk fix pmp addr config omissions [1/1]
PD#SWPL-140705
Problem:
pmp_addr register need address aligned, for base address
which pmp protect matches conditions as follows:
If base address is 4K aligned, then pmp entry could protect
4K region from base address to base address + 4K.
If base address is 8K aligned, then pmp entry could protect
8K region from base address to base address + 8K.
And so on...
If do not config like this, the region which pmp protect
would have some bias, causing pmp config error and text
could not run ok.
Solution:
Make pmp_addr config aligned to size.
.text/rodata permission: R/X
other region permission: R/W
application to both M and U mode.
Verify:
t3x_bc302
Change-Id: Ic18e033cc1ca41ae2ba13e2d1bc244982d7459a8
Signed-off-by: bangzheng.liu <bangzheng.liu@amlogic.com>
diff --git a/n200_func.h b/n200_func.h
index cf71867..4dabc88 100644
--- a/n200_func.h
+++ b/n200_func.h
@@ -33,8 +33,13 @@
#define PMP_CFG_L_NO (0<<7)
#define PMP_CFG_L_EN (1<<7)
-/* The size should be the number of 2^n */
-#define NAPOT_SIZE(size) (((size) - 1) >> 3)
+#define SIZE_1K 0x400
+#define SIZE_2K 0x800
+#define SIZE_4K 0x1000
+#define SIZE_8K 0x2000
+#define SIZE_16K 0x4000
+#define SIZE_32K 0x8000
+#define PMP_SHIFT 2
extern uint32_t _text;
extern uint32_t _etext;