SoC s6: saradc: fixed the issue of sampling failure during STR [1/1]
PD#SWPL-176149
Problem:
Sampling failure during STR.
Solution:
SARADC digital clock is not enabled, just enable it.
Verify:
S6/BL201 S7D/BM201
Change-Id: I3d3c63e02bc3c796226b349698d1b3ca5cf7fc56
Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com>
diff --git a/s6/saradc-data.h b/s6/saradc-data.h
index 217bdd1..391af17 100644
--- a/s6/saradc-data.h
+++ b/s6/saradc-data.h
@@ -12,6 +12,9 @@
#define SAR_CLK_BASE CLKCTRL_SAR_CLK_CTRL0
#define SARADC_BASE SAR_ADC_REG0
+#define SAR_SYS_CLK_EN_BASE CLKCTRL_SYS_CLK_EN0_REG2
+#define SAR_SYS_CLK_EN_BIT 28
+
#define SARADC_REG7_INIT 0x00000c11
#define SARADC_REG8_INIT 0x0280614d
#define SARADC_REG3_INIT 0x10a02403
@@ -25,6 +28,6 @@
/* s7d saradc interrupt num */
#define SARADC_INTERRUPT_NUM 181
-#define SARADC_REG_NUM ((0x3c >> 2) + 1)
+#define SARADC_REG_NUM ((0x3c >> 2) + 2)
#endif
diff --git a/s7d/saradc-data.h b/s7d/saradc-data.h
index 4feb03a..97005c6 100644
--- a/s7d/saradc-data.h
+++ b/s7d/saradc-data.h
@@ -12,6 +12,9 @@
#define SAR_CLK_BASE CLKCTRL_SAR_CLK_CTRL0
#define SARADC_BASE SAR_ADC_REG0
+#define SAR_SYS_CLK_EN_BASE CLKCTRL_SYS_CLK_EN0_REG2
+#define SAR_SYS_CLK_EN_BIT 28
+
#define SARADC_REG7_INIT 0x00000c11
#define SARADC_REG8_INIT 0x0280614d
#define SARADC_REG3_INIT 0x10a02403
@@ -25,6 +28,6 @@
/* s7d saradc interrupt num */
#define SARADC_INTERRUPT_NUM 181
-#define SARADC_REG_NUM ((0x3c >> 2) + 1)
+#define SARADC_REG_NUM ((0x3c >> 2) + 2)
#endif