ODROID-C5: firmware : set default DDR clock to 1968MHz
Signed-off-by: ckkim <changkon12@gmail.com>
Change-Id: If9a0e701654bf71f2a883e727fd75f03b5cdf22b
diff --git a/board/amlogic/configs/s7d_odroidc5.h b/board/amlogic/configs/s7d_odroidc5.h
index 015e25f..68f6d03 100644
--- a/board/amlogic/configs/s7d_odroidc5.h
+++ b/board/amlogic/configs/s7d_odroidc5.h
@@ -12,11 +12,11 @@
* platform power init config
*/
-#define AML_VCCK_INIT_VOLTAGE 950 //VCCK power up voltage
-#define AML_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+#define AML_VCCK_INIT_VOLTAGE 969 // VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 830 // VDDEE power up voltage
/*Distinguish whether to use efuse to adjust vddee*/
-#define CONFIG_PDVFS_ENABLE
+//#define CONFIG_PDVFS_ENABLE
/* SMP definitions */
#define CPU_RELEASE_ADDR secondary_boot_func
diff --git a/board/amlogic/s7d_odroidc5/firmware/ddr_timing.c b/board/amlogic/s7d_odroidc5/firmware/ddr_timing.c
index bdf7a18..50e2855 100644
--- a/board/amlogic/s7d_odroidc5/firmware/ddr_timing.c
+++ b/board/amlogic/s7d_odroidc5/firmware/ddr_timing.c
@@ -7,8 +7,11 @@
#include <asm/amlogic/arch/timing.h>
#include <asm/amlogic/arch/ddr_define.h>
+#define DDR_FUNC_CONFIG_DISABLE_DDR_DVFS_FUNCTION (0 + (1 << 19))
#define DDR_FUNC_CONFIG_ENABLE_PZQ_DET_DRAM_TYPE_RETURN (0 + (1 << 20))
#define DDR_FUNC_CONFIG_AUTO_DET_DQ_PINMUX_FUNCTION (0 + (1 << 21))
+#define CONFIG_DRAM_MODE_FORCE_DISABLE_X8 0x81
+#define CONFIG_DRAM_MODE_FORCE_ENABLE_X8 0x1
//bit 6 adc_channel bit 0-5 adc value,chan 3 value 8 is layer 2
#define DDR_ID_ACS_ADC ((3 << 6) | (8))
@@ -124,18 +127,269 @@
};
#endif
-#define LPDDR4_SKT 1
-#define DDR4_SKT 1
-#define DDR3_SKT 1
+#define LPDDR4_SKT 0
+#define DDR4_SKT 0
+#define DDR3_SKT 0
+#define DDR4_ODROID 1
ddr_set_ps0_only_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+
+#if DDR4_ODROID
+//ODROID-C5 DDR4 freq
+#define CACLU_CLK_D4 1968 // 600 //1200 //1792//600 //1200 //(1900)// (1440)//(1008)
+//#define CACLU_CLK_D4 1584// 600 //1200 //1792//600 //1200 //(1900)// (1440)//(1008)
+ {
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = 1,
+ .cfg_board_common_setting.timming_struct_version = 9215,
+ .cfg_board_common_setting.timming_struct_org_size =
+ sizeof(ddr_set_ps0_only_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0,
+ .cfg_board_common_setting.fast_boot = {
+ 0, 0, 0, 0
+ },
+ .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION |
+ DDR_FUNC_CONFIG_DISABLE_DDR_DVFS_FUNCTION,
+ //DDR_FUNC_CONFIG_ENABLE_PZQ_DET_DRAM_TYPE_RETURN,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.enable_lpddr4x_mode = 0,
+ .cfg_board_common_setting.dram_rank_config =
+ //CONFIG_DDR0_16BIT_CH0,
+ CONFIG_DDR0_32BIT_RANK0_CH0,
+ //.cfg_board_common_setting.dram_ch0_size_MB =
+ // (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ // (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ // (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ // (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_23_SIZE_256_ID_OFFSET),
+ //.cfg_board_common_setting.dram_ch1_size_MB =
+ // (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ // (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ // (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ // (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_23_SIZE_256_ID_OFFSET),
+ .cfg_board_common_setting.dram_ch0_size_MB = 0xffff,
+ .cfg_board_common_setting.DisabledDbyte[0] = 0x00,
+ //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ //.cfg_board_common_setting.DisabledDbyte[1] = 0xfc,
+ //bit 0 -3 ch1 cs0 ,bit 4-7 ch1
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_FORCE_DISABLE_X8,
+ //.cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_FORCE_ENABLE_X8,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = 0xff,
+ .cfg_board_common_setting.log_level = 4,
+ //4,//LOG_LEVEL_BASIC,
+ .cfg_board_SI_setting_ps.DRAMFreq = CACLU_CLK_D4,
+ .cfg_board_SI_setting_ps.training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps.dfi_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps.dfi_odt_config = DDR_DRAM_ODT_DDR4_PARK_ENABLE,
+ .cfg_board_SI_setting_ps.vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps.vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps.vref_dram_data_permil = 0,//800,
+ .cfg_board_SI_setting_ps.max_core_timmming_frequency = 0,
+ .cfg_board_common_setting.dbi_enable = 0x00000000,
+ .cfg_board_common_setting.ddr_rfc_type = 0,
+ .cfg_board_common_setting.pll_ssc_mode = 0x00000000,
+#if ENABLE_8BIT_DDR4_CS0_CS1_SAME_PHASE
+ //.cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_FORCE_DISABLE_X8,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_FORCE_ENABLE_X8,
+ .cfg_board_SI_setting_ps.clk_drv_ohm = 34,
+ .cfg_board_SI_setting_ps.cs_drv_ohm = 34,
+ .cfg_board_SI_setting_ps.ac_drv_ohm = 34,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_p = 34,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_n = 34,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_p = 60,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_n = 0,
+ .cfg_board_SI_setting_ps.dram_data_drv_ohm = 34,
+ .cfg_board_SI_setting_ps.dram_data_odt_ohm = 60,
+ .cfg_board_SI_setting_ps.dram_data_wr_odt_ohm = 0,
+ .cfg_board_SI_setting_ps.dram_ac_odt_ohm = 120,
+ .cfg_board_SI_setting_ps.dram_drv_pull_up_cal_ohm =
+ DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.lpddr4_dram_vout_range =
+ DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_common_setting.ac_pinmux = {
+ 22, 22, 26, 3, 7, 5, 6, 4, 0, 19,
+ 11, 27, 18, 14, 17, 16, 20, 15, 12, 10, 9,
+ 8, 21, 2, 13, 1, 24, 25, 28, 29,
+ },
+#else
+ .cfg_board_SI_setting_ps.clk_drv_ohm = 40,
+ .cfg_board_SI_setting_ps.cs_drv_ohm = 40,
+ .cfg_board_SI_setting_ps.ac_drv_ohm = 40,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_p = 40,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_n = 40,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_p = 60,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_n = 0,
+ .cfg_board_SI_setting_ps.dram_data_drv_ohm = 34,
+ .cfg_board_SI_setting_ps.dram_data_odt_ohm = 60,
+#ifdef USE_2RANK_16BIT_X2_DDR4
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_FORCE_DISABLE_X8,
+ //.cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_FORCE_ENABLE_X8,
+ .cfg_board_SI_setting_ps.vref_soc_data_permil = 820,
+ .cfg_board_SI_setting_ps.vref_dram_data_permil = 820,//800,
+ .cfg_board_SI_setting_ps.clk_drv_ohm = 34,
+ .cfg_board_SI_setting_ps.cs_drv_ohm = 40,
+ .cfg_board_SI_setting_ps.ac_drv_ohm = 40,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_p = 48,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_n = 48,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_p = 48,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_n = 0,
+ .cfg_board_SI_setting_ps.dram_data_drv_ohm = 48,
+ .cfg_board_SI_setting_ps.dram_data_odt_ohm = 48,
+#endif
+ .cfg_board_SI_setting_ps.dram_data_wr_odt_ohm = 0,
+ .cfg_board_SI_setting_ps.dram_ac_odt_ohm = 120,
+ .cfg_board_SI_setting_ps.dram_drv_pull_up_cal_ohm =
+ DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.lpddr4_dram_vout_range =
+ DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_common_setting.ac_pinmux = {
+ 23, 22, 26, 3, 7, 5, 6, 4, 0, 19,
+ 11, 27, 18, 14, 17, 16, 20, 15, 12, 10, 9,
+ 8, 21, 2, 13, 1, 24, 25, 28, 29,
+ },
+#endif
+ //.cfg_ddr_training_delay_ps.tx_offset[0] = (0 << 7) | 0x0,
+ //.cfg_ddr_training_delay_ps.rx_offset[0] = (0 << 7) | 0x0,
+ .cfg_ddr_training_delay_ps.reserve_para[0] = (1 << 7) | 0x8, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[1] = (1 << 7) | 0x8, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[2] = (1 << 7) | 0x8, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[3] = (1 << 7) | 0x8, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[4] = (1 << 7) | 0x8, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[5] = (1 << 7) | 0x8, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[6] = (1 << 7) | 0x8, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[7] = (1 << 7) | 0x8, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x10,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x10,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x10,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x10,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x10,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x10,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x10,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x10,//read dqs
+ //.cfg_ddr_training_delay_ps.dac_offset[0] = (1 << 7) | 0x3,
+ //.cfg_ddr_training_delay_ps.dac_offset[1] = (0 << 7) | 0xa,
+
+ #define AC_OFFSET (128)
+ #define WL0 (-128)
+ .cfg_ddr_training_delay_ps.ac_trace_delay[0] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[1] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[2] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[3] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[4] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[5] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[6] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[7] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[8] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[9] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[10] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[11] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[12] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[13] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[14] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[15] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[16] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[17] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[18] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[19] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[20] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[21] = 256 + AC_OFFSET,
+ //cke 128 only 1UI margin
+ .cfg_ddr_training_delay_ps.ac_trace_delay[22] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[23] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[24] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[25] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[26] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[27] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[28] = 256 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[29] = 256 + AC_OFFSET,
+
+ .cfg_ddr_training_delay_ps.ac_trace_delay[0] = 128 + AC_OFFSET, //pxp cs
+ .cfg_ddr_training_delay_ps.ac_trace_delay[1] = 128 - 30 + AC_OFFSET, //pxp cs
+ .cfg_ddr_training_delay_ps.ac_trace_delay[29] = 128 + AC_OFFSET, //ck
+ .cfg_ddr_training_delay_ps.ac_trace_delay[28] = 128 + AC_OFFSET,//ck
+ .cfg_ddr_training_delay_ps.ac_trace_delay[26] = 128 + AC_OFFSET, //cke
+ .cfg_ddr_training_delay_ps.ac_trace_delay[27] = 128 + AC_OFFSET, //cke
+ .cfg_ddr_training_delay_ps.ac_trace_delay[2] = 128 + AC_OFFSET,//odt0
+ .cfg_ddr_training_delay_ps.ac_trace_delay[11] = 128 + AC_OFFSET,//odt1
+#if ENABLE_8BIT_DDR4_CS0_CS1_SAME_PHASE
+ .cfg_ddr_training_delay_ps.ac_trace_delay[4] = 256 - 100 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[5] = 256 - 100 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[6] = 256 - 100 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[8] = 256 - 50 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[10] = 256 - 50 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[13] = 256 - 50 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[14] = 256 - 50 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[16] = 256 - 50 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[17] = 256 - 50 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[19] = 256 - 50 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[20] = 256 - 50 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[21] = 256 - 100 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[22] = 256 - 100 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[23] = 256 - 50 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[24] = 256 - 50 + AC_OFFSET,
+
+ .cfg_ddr_training_delay_ps.write_dqs_delay[0] = 128 + AC_OFFSET + WL0 + 40,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[1] = 128 + AC_OFFSET + WL0 + 40,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[2] = 128 + AC_OFFSET + WL0 + 90,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[3] = 128 + AC_OFFSET + WL0 + 90,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[4] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[5] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[6] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[7] = 128 + AC_OFFSET + WL0,
+#else
+#ifdef USE_2RANK_16BIT_X2_DDR4
+ .cfg_ddr_training_delay_ps.ac_trace_delay[0] = 128 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[4] = 256 + AC_OFFSET - 100,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[5] = 256 + AC_OFFSET - 100,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[6] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[7] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[8] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[9] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[10] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[13] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[14] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[17] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[20] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[21] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[22] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[23] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[24] = 256 + AC_OFFSET - 50,
+#endif
+ .cfg_ddr_training_delay_ps.write_dqs_delay[0] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[1] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[2] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[3] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[4] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[5] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[6] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[7] = 128 + AC_OFFSET + WL0,
+#endif
+
+ .cfg_ddr_training_delay_ps.read_dqs_delay[0] = 128,
+ .cfg_ddr_training_delay_ps.read_dqs_delay[1] = 128,
+ .cfg_ddr_training_delay_ps.read_dqs_delay[2] = 128,
+ .cfg_ddr_training_delay_ps.read_dqs_delay[3] = 128,
+ .cfg_ddr_training_delay_ps.read_dqs_delay[4] = 128,
+ .cfg_ddr_training_delay_ps.read_dqs_delay[5] = 128,
+ .cfg_ddr_training_delay_ps.read_dqs_delay[6] = 128,
+ .cfg_ddr_training_delay_ps.read_dqs_delay[7] = 128,
+
+ .cfg_ddr_training_delay_ps.soc_bit_vref0[0] = 0x000000,
+ //0 for auto training
+ .cfg_ddr_training_delay_ps.dram_vref[0] = 0x00000000,
+
+ },
+//};
+#endif
+
#if LPDDR4_SKT
#define CACLU_CLK_LP4 1584 //1792//600 //1200 //(1900)// (1440)//(1008)
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default_lp4 = {
{
.cfg_board_common_setting.timming_magic = 0,
.cfg_board_common_setting.timming_max_valid_configs = 1,
- .cfg_board_common_setting.timming_struct_version = 9175,
+ .cfg_board_common_setting.timming_struct_version = 9215,
.cfg_board_common_setting.timming_struct_org_size =
sizeof(ddr_set_ps0_only_t),
.cfg_board_common_setting.timming_struct_real_size = 0,
@@ -143,7 +397,8 @@
0x0, 0, 0, 0
},
.cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION |
- DDR_FUNC_CONFIG_ENABLE_PZQ_DET_DRAM_TYPE_RETURN,
+ DDR_FUNC_CONFIG_DISABLE_DDR_DVFS_FUNCTION,
+ //DDR_FUNC_CONFIG_ENABLE_PZQ_DET_DRAM_TYPE_RETURN,
.cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
.cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4,
.cfg_board_common_setting.enable_lpddr4x_mode = 0,
@@ -169,7 +424,7 @@
.cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
.cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
.cfg_board_common_setting.log_level = 0xff,
- //.cfg_board_common_setting.log_level = 4,
+ .cfg_board_common_setting.log_level = 4,
//4,//LOG_LEVEL_BASIC,
.cfg_board_common_setting.dbi_enable = 0,
.cfg_board_common_setting.org_tdqs2dq = 0,
@@ -185,14 +440,17 @@
.cfg_board_SI_setting_ps.clk_drv_ohm = 40,
.cfg_board_SI_setting_ps.cs_drv_ohm = 40,
.cfg_board_SI_setting_ps.ac_drv_ohm = 40,
- .cfg_board_SI_setting_ps.soc_data_drv_ohm_p = 40,
- .cfg_board_SI_setting_ps.soc_data_drv_ohm_n = 40,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_p = 34,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_n = 34,
.cfg_board_SI_setting_ps.soc_data_odt_ohm_p = 0,
- .cfg_board_SI_setting_ps.soc_data_odt_ohm_n = 40, //60,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_n = 80, //60,
.cfg_board_SI_setting_ps.dram_data_drv_ohm = 40,
- .cfg_board_SI_setting_ps.dram_data_odt_ohm = 60,
+ .cfg_board_SI_setting_ps.dram_data_odt_ohm = 48,
.cfg_board_SI_setting_ps.dram_data_wr_odt_ohm = 0,
.cfg_board_SI_setting_ps.dram_ac_odt_ohm = 120,//240,//120,
+#ifdef LPDDR4_USE_2LAYER_BOARD
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_n = 120,
+#endif
.cfg_board_SI_setting_ps.dram_drv_pull_up_cal_ohm =
DDR_DRAM_LPDDR4_ODT_40_OHM,
.cfg_board_SI_setting_ps.lpddr4_dram_vout_range =
@@ -294,12 +552,18 @@
#if DDR4_SKT
//s7 signoff with 3200MBPS
-#define CACLU_CLK_D4 1584// 600 //1200 //1792//600 //1200 //(1900)// (1440)//(1008)
+#if defined USE_2RANK_16BIT_X2_DDR4 || defined ENABLE_8BIT_DDR4_CS0_CS1_SAME_PHASE
+//USE_2RANK_16BIT_DDR4 use ap222 board
+//#define ENABLE_8BIT_DDR4_CS0_CS1_SAME_PHASE 1 //t233
+#define CACLU_CLK_D4 1320// 600
+#else
+#define CACLU_CLK_D4 1584
+#endif
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default_ddr4 = {
{
.cfg_board_common_setting.timming_magic = 0,
.cfg_board_common_setting.timming_max_valid_configs = 1,
- .cfg_board_common_setting.timming_struct_version = 9175,
+ .cfg_board_common_setting.timming_struct_version = 9215,
.cfg_board_common_setting.timming_struct_org_size =
sizeof(ddr_set_ps0_only_t),
.cfg_board_common_setting.timming_struct_real_size = 0,
@@ -307,7 +571,8 @@
0, 0, 0, 0
},
.cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION |
- DDR_FUNC_CONFIG_ENABLE_PZQ_DET_DRAM_TYPE_RETURN,
+ DDR_FUNC_CONFIG_DISABLE_DDR_DVFS_FUNCTION,
+ //DDR_FUNC_CONFIG_ENABLE_PZQ_DET_DRAM_TYPE_RETURN,
.cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
.cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
.cfg_board_common_setting.enable_lpddr4x_mode = 0,
@@ -329,10 +594,11 @@
//bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
//.cfg_board_common_setting.DisabledDbyte[1] = 0xfc,
//bit 0 -3 ch1 cs0 ,bit 4-7 ch1
- .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_FORCE_DISABLE_X8,
+ //.cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_FORCE_ENABLE_X8,
.cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
.cfg_board_common_setting.log_level = 0xff,
- //.cfg_board_common_setting.log_level = 4,
+ .cfg_board_common_setting.log_level = 4,
//4,//LOG_LEVEL_BASIC,
.cfg_board_SI_setting_ps.DRAMFreq = CACLU_CLK_D4,
.cfg_board_SI_setting_ps.training_SequenceCtrl = 0,
@@ -340,17 +606,19 @@
.cfg_board_SI_setting_ps.dfi_odt_config = DDR_DRAM_ODT_DDR4_PARK_ENABLE,
.cfg_board_SI_setting_ps.vref_ac_permil = 0,
.cfg_board_SI_setting_ps.vref_soc_data_permil = 0,
- .cfg_board_SI_setting_ps.vref_dram_data_permil = 800,
+ .cfg_board_SI_setting_ps.vref_dram_data_permil = 0,//800,
.cfg_board_SI_setting_ps.max_core_timmming_frequency = 0,
.cfg_board_common_setting.dbi_enable = 0x00000000,
.cfg_board_common_setting.ddr_rfc_type = 0,
.cfg_board_common_setting.pll_ssc_mode = 0x00000000,
-
- .cfg_board_SI_setting_ps.clk_drv_ohm = 40,
- .cfg_board_SI_setting_ps.cs_drv_ohm = 40,
- .cfg_board_SI_setting_ps.ac_drv_ohm = 40,
- .cfg_board_SI_setting_ps.soc_data_drv_ohm_p = 40,
- .cfg_board_SI_setting_ps.soc_data_drv_ohm_n = 40,
+#if ENABLE_8BIT_DDR4_CS0_CS1_SAME_PHASE
+ //.cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_FORCE_DISABLE_X8,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_FORCE_ENABLE_X8,
+ .cfg_board_SI_setting_ps.clk_drv_ohm = 34,
+ .cfg_board_SI_setting_ps.cs_drv_ohm = 34,
+ .cfg_board_SI_setting_ps.ac_drv_ohm = 34,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_p = 34,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_n = 34,
.cfg_board_SI_setting_ps.soc_data_odt_ohm_p = 60,
.cfg_board_SI_setting_ps.soc_data_odt_ohm_n = 0,
.cfg_board_SI_setting_ps.dram_data_drv_ohm = 34,
@@ -362,11 +630,47 @@
.cfg_board_SI_setting_ps.lpddr4_dram_vout_range =
DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
.cfg_board_common_setting.ac_pinmux = {
+ 22, 22, 26, 3, 7, 5, 6, 4, 0, 19,
+ 11, 27, 18, 14, 17, 16, 20, 15, 12, 10, 9,
+ 8, 21, 2, 13, 1, 24, 25, 28, 29,
+ },
+#else
+ .cfg_board_SI_setting_ps.clk_drv_ohm = 40,
+ .cfg_board_SI_setting_ps.cs_drv_ohm = 40,
+ .cfg_board_SI_setting_ps.ac_drv_ohm = 40,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_p = 40,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_n = 40,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_p = 60,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_n = 0,
+ .cfg_board_SI_setting_ps.dram_data_drv_ohm = 34,
+ .cfg_board_SI_setting_ps.dram_data_odt_ohm = 60,
+#ifdef USE_2RANK_16BIT_X2_DDR4
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_FORCE_DISABLE_X8,
+ //.cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_FORCE_ENABLE_X8,
+ .cfg_board_SI_setting_ps.vref_soc_data_permil = 820,
+ .cfg_board_SI_setting_ps.vref_dram_data_permil = 820,//800,
+ .cfg_board_SI_setting_ps.clk_drv_ohm = 34,
+ .cfg_board_SI_setting_ps.cs_drv_ohm = 40,
+ .cfg_board_SI_setting_ps.ac_drv_ohm = 40,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_p = 48,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_n = 48,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_p = 48,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_n = 0,
+ .cfg_board_SI_setting_ps.dram_data_drv_ohm = 48,
+ .cfg_board_SI_setting_ps.dram_data_odt_ohm = 48,
+#endif
+ .cfg_board_SI_setting_ps.dram_data_wr_odt_ohm = 0,
+ .cfg_board_SI_setting_ps.dram_ac_odt_ohm = 120,
+ .cfg_board_SI_setting_ps.dram_drv_pull_up_cal_ohm =
+ DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.lpddr4_dram_vout_range =
+ DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_common_setting.ac_pinmux = {
23, 22, 26, 3, 7, 5, 6, 4, 0, 19,
11, 27, 18, 14, 17, 16, 20, 15, 12, 10, 9,
8, 21, 2, 13, 1, 24, 25, 28, 29,
},
-
+#endif
//.cfg_ddr_training_delay_ps.tx_offset[0] = (0 << 7) | 0x0,
//.cfg_ddr_training_delay_ps.rx_offset[0] = (0 << 7) | 0x0,
.cfg_ddr_training_delay_ps.reserve_para[0] = (1 << 7) | 0x8, //write dqs
@@ -385,9 +689,11 @@
.cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x10,//read dqs
.cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x10,//read dqs
.cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x10,//read dqs
+ //.cfg_ddr_training_delay_ps.dac_offset[0] = (1 << 7) | 0x3,
+ //.cfg_ddr_training_delay_ps.dac_offset[1] = (0 << 7) | 0xa,
#define AC_OFFSET (128)
- //#define WL0 (0)
+ #define WL0 (-128)
.cfg_ddr_training_delay_ps.ac_trace_delay[0] = 256 + AC_OFFSET,
.cfg_ddr_training_delay_ps.ac_trace_delay[1] = 256 + AC_OFFSET,
.cfg_ddr_training_delay_ps.ac_trace_delay[2] = 256 + AC_OFFSET,
@@ -428,15 +734,59 @@
.cfg_ddr_training_delay_ps.ac_trace_delay[27] = 128 + AC_OFFSET, //cke
.cfg_ddr_training_delay_ps.ac_trace_delay[2] = 128 + AC_OFFSET,//odt0
.cfg_ddr_training_delay_ps.ac_trace_delay[11] = 128 + AC_OFFSET,//odt1
+#if ENABLE_8BIT_DDR4_CS0_CS1_SAME_PHASE
+ .cfg_ddr_training_delay_ps.ac_trace_delay[4] = 256 - 100 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[5] = 256 - 100 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[6] = 256 - 100 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[8] = 256 - 50 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[10] = 256 - 50 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[13] = 256 - 50 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[14] = 256 - 50 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[16] = 256 - 50 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[17] = 256 - 50 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[19] = 256 - 50 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[20] = 256 - 50 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[21] = 256 - 100 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[22] = 256 - 100 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[23] = 256 - 50 + AC_OFFSET,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[24] = 256 - 50 + AC_OFFSET,
- .cfg_ddr_training_delay_ps.write_dqs_delay[0] = 128,
- .cfg_ddr_training_delay_ps.write_dqs_delay[1] = 128,
- .cfg_ddr_training_delay_ps.write_dqs_delay[2] = 128,
- .cfg_ddr_training_delay_ps.write_dqs_delay[3] = 128,
- .cfg_ddr_training_delay_ps.write_dqs_delay[4] = 128,
- .cfg_ddr_training_delay_ps.write_dqs_delay[5] = 128,
- .cfg_ddr_training_delay_ps.write_dqs_delay[6] = 128,
- .cfg_ddr_training_delay_ps.write_dqs_delay[7] = 128,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[0] = 128 + AC_OFFSET + WL0 + 40,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[1] = 128 + AC_OFFSET + WL0 + 40,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[2] = 128 + AC_OFFSET + WL0 + 90,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[3] = 128 + AC_OFFSET + WL0 + 90,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[4] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[5] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[6] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[7] = 128 + AC_OFFSET + WL0,
+#else
+#ifdef USE_2RANK_16BIT_X2_DDR4
+ .cfg_ddr_training_delay_ps.ac_trace_delay[0] = 128 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[4] = 256 + AC_OFFSET - 100,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[5] = 256 + AC_OFFSET - 100,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[6] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[7] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[8] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[9] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[10] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[13] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[14] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[17] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[20] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[21] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[22] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[23] = 256 + AC_OFFSET - 50,
+ .cfg_ddr_training_delay_ps.ac_trace_delay[24] = 256 + AC_OFFSET - 50,
+#endif
+ .cfg_ddr_training_delay_ps.write_dqs_delay[0] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[1] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[2] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[3] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[4] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[5] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[6] = 128 + AC_OFFSET + WL0,
+ .cfg_ddr_training_delay_ps.write_dqs_delay[7] = 128 + AC_OFFSET + WL0,
+#endif
.cfg_ddr_training_delay_ps.read_dqs_delay[0] = 128,
.cfg_ddr_training_delay_ps.read_dqs_delay[1] = 128,
@@ -461,7 +811,7 @@
{
.cfg_board_common_setting.timming_magic = 0,
.cfg_board_common_setting.timming_max_valid_configs = 1,
- .cfg_board_common_setting.timming_struct_version = 9175,
+ .cfg_board_common_setting.timming_struct_version = 9215,
.cfg_board_common_setting.timming_struct_org_size =
sizeof(ddr_set_ps0_only_t),
.cfg_board_common_setting.timming_struct_real_size = 0,
@@ -469,7 +819,8 @@
0, 0, 0, 0
},
.cfg_board_common_setting.ddr_func =
- DDR_FUNC_CONFIG_ENABLE_PZQ_DET_DRAM_TYPE_RETURN,
+ DDR_FUNC_CONFIG_DISABLE_DDR_DVFS_FUNCTION,
+ //DDR_FUNC_CONFIG_ENABLE_PZQ_DET_DRAM_TYPE_RETURN,
.cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
.cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3,
.cfg_board_common_setting.enable_lpddr4x_mode = 0,
@@ -492,7 +843,7 @@
.cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
.cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
.cfg_board_common_setting.log_level = 0xff,
- //.cfg_board_common_setting.log_level = 4,
+ .cfg_board_common_setting.log_level = 4,
//4,//LOG_LEVEL_BASIC,
.cfg_board_SI_setting_ps.DRAMFreq = CACLU_CLK_D3,
.cfg_board_SI_setting_ps.training_SequenceCtrl = 0,
diff --git a/board/amlogic/s7d_odroidc5/firmware/timing.c b/board/amlogic/s7d_odroidc5/firmware/timing.c
index da12054..2a2bedb 100644
--- a/board/amlogic/s7d_odroidc5/firmware/timing.c
+++ b/board/amlogic/s7d_odroidc5/firmware/timing.c
@@ -9,7 +9,7 @@
#include <ddr_timing.c>
/* board clk defines */
-#define CPU_CLK 2004
+#define CPU_CLK 2508
/* board vmin_value defines */
#define VMIN_FF_VALUE 670
@@ -37,68 +37,64 @@
#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
/* VCCK PWM table */
-#if (VCCK_VAL == 980)
-#define VCCK_VAL_REG 0x00003e8
-#elif (VCCK_VAL == 970)
-#define VCCK_VAL_REG 0x02003c6
-#elif (VCCK_VAL == 960)
-#define VCCK_VAL_REG 0x04103a5
-#elif (VCCK_VAL == 950)
-#define VCCK_VAL_REG 0x0620384
-#elif (VCCK_VAL == 940)
-#define VCCK_VAL_REG 0x0830363
-#elif (VCCK_VAL == 930)
-#define VCCK_VAL_REG 0x0a40342
-#elif (VCCK_VAL == 920)
-#define VCCK_VAL_REG 0x0c50321
-#elif (VCCK_VAL == 910)
-#define VCCK_VAL_REG 0x0e60300
-#elif (VCCK_VAL == 900)
-#define VCCK_VAL_REG 0x10702df
-#elif (VCCK_VAL == 890)
-#define VCCK_VAL_REG 0x12802be
-#elif (VCCK_VAL == 880)
-#define VCCK_VAL_REG 0x149029d
-#elif (VCCK_VAL == 870)
-#define VCCK_VAL_REG 0x16a027c
-#elif (VCCK_VAL == 860)
-#define VCCK_VAL_REG 0x18b025b
-#elif (VCCK_VAL == 850)
-#define VCCK_VAL_REG 0x1ac023a
-#elif (VCCK_VAL == 840)
-#define VCCK_VAL_REG 0x1cd0219
-#elif (VCCK_VAL == 830)
-#define VCCK_VAL_REG 0x1ee01f8
-#elif (VCCK_VAL == 820)
-#define VCCK_VAL_REG 0x21901cd
-#elif (VCCK_VAL == 810)
-#define VCCK_VAL_REG 0x23a01ac
-#elif (VCCK_VAL == 800)
-#define VCCK_VAL_REG 0x25b018b
-#elif (VCCK_VAL == 790)
-#define VCCK_VAL_REG 0x27c016a
-#elif (VCCK_VAL == 780)
-#define VCCK_VAL_REG 0x29d0149
-#elif (VCCK_VAL == 770)
-#define VCCK_VAL_REG 0x2be0128
-#elif (VCCK_VAL == 760)
-#define VCCK_VAL_REG 0x2df0107
-#elif (VCCK_VAL == 750)
-#define VCCK_VAL_REG 0x30000e6
-#elif (VCCK_VAL == 740)
-#define VCCK_VAL_REG 0x32100c5
-#elif (VCCK_VAL == 730)
-#define VCCK_VAL_REG 0x34200a4
-#elif (VCCK_VAL == 720)
-#define VCCK_VAL_REG 0x3630083
-#elif (VCCK_VAL == 710)
-#define VCCK_VAL_REG 0x3840062
-#elif (VCCK_VAL == 700)
-#define VCCK_VAL_REG 0x3a50041
-#elif (VCCK_VAL == 690)
-#define VCCK_VAL_REG 0x3c60020
-#elif (VCCK_VAL == 680)
-#define VCCK_VAL_REG 0x3e80000
+#if (VCCK_VAL == 969)
+#define VCCK_VAL_REG 0x0000001c
+#elif (VCCK_VAL == 959)
+#define VCCK_VAL_REG 0x0001001b
+#elif (VCCK_VAL == 949)
+#define VCCK_VAL_REG 0x0002001a
+#elif (VCCK_VAL == 939)
+#define VCCK_VAL_REG 0x00030019
+#elif (VCCK_VAL == 929)
+#define VCCK_VAL_REG 0x00040018
+#elif (VCCK_VAL == 919)
+#define VCCK_VAL_REG 0x00050017
+#elif (VCCK_VAL == 909)
+#define VCCK_VAL_REG 0x00060016
+#elif (VCCK_VAL == 899)
+#define VCCK_VAL_REG 0x00070015
+#elif (VCCK_VAL == 889)
+#define VCCK_VAL_REG 0x00080014
+#elif (VCCK_VAL == 879)
+#define VCCK_VAL_REG 0x00090013
+#elif (VCCK_VAL == 869)
+#define VCCK_VAL_REG 0x000a0012
+#elif (VCCK_VAL == 859)
+#define VCCK_VAL_REG 0x000b0011
+#elif (VCCK_VAL == 849)
+#define VCCK_VAL_REG 0x000c0010
+#elif (VCCK_VAL == 839)
+#define VCCK_VAL_REG 0x000d000f
+#elif (VCCK_VAL == 829)
+#define VCCK_VAL_REG 0x000e000e
+#elif (VCCK_VAL == 819)
+#define VCCK_VAL_REG 0x000f000d
+#elif (VCCK_VAL == 809)
+#define VCCK_VAL_REG 0x0010000c
+#elif (VCCK_VAL == 799)
+#define VCCK_VAL_REG 0x0011000b
+#elif (VCCK_VAL == 789)
+#define VCCK_VAL_REG 0x0012000a
+#elif (VCCK_VAL == 779)
+#define VCCK_VAL_REG 0x00130009
+#elif (VCCK_VAL == 769)
+#define VCCK_VAL_REG 0x00140008
+#elif (VCCK_VAL == 759)
+#define VCCK_VAL_REG 0x00150007
+#elif (VCCK_VAL == 749)
+#define VCCK_VAL_REG 0x00160006
+#elif (VCCK_VAL == 739)
+#define VCCK_VAL_REG 0x00170005
+#elif (VCCK_VAL == 729)
+#define VCCK_VAL_REG 0x00180004
+#elif (VCCK_VAL == 719)
+#define VCCK_VAL_REG 0x00190003
+#elif (VCCK_VAL == 709)
+#define VCCK_VAL_REG 0x001a0002
+#elif (VCCK_VAL == 699)
+#define VCCK_VAL_REG 0x001b0001
+#elif (VCCK_VAL == 689)
+#define VCCK_VAL_REG 0x001c0000
#else
#error "VCCK val out of range\n"
#endif
@@ -164,9 +160,9 @@
{ PWM_MISC_REG_H, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
{ PWM_MISC_REG_J, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
/* set pwm h clock rate to 500M, enable them */
- /* set pwm j clock rate to 500M, enable them */
+ /* set pwm j clock rate to fdiv3, enable them */
{ CLKCTRL_PWM_CLK_GH_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
- { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24) | (0x2 << 25), 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 drive strength to 3 */
{ PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */