| commit | 89696e876d5f45df9de1ac6b9114a59cd34fe5ef | [log] [tgz] |
|---|---|---|
| author | zhou.han <zhou.han@amlogic.com> | Thu Dec 26 11:38:28 2024 +0800 |
| committer | zhou.han <zhou.han@amlogic.com> | Thu Dec 26 14:36:33 2024 +0800 |
| tree | 207960a41f5880ddaa44039f99e1f59934a87044 | |
| parent | 74f00a5848d2b7c9c73ed523f5e2c9a29f3d293c [diff] |
hdmitx: Optimize the hdmitx clk source switching process [1/2] PD#SWPL-174933 Problem: hdmitx encp/pixel clk is directly configured by the pll analog path. Solution: Add flag: clk_analog_path, which is 1 by default. 1:Analog frequency division 0:Digital frequency division Verify: s7d/s7 Change-Id: Iea024e12d02e971e62a9786d436410b12613cd68 Signed-off-by: zhou.han <zhou.han@amlogic.com>