Merge "hdmitx: Optimize the hdmitx clk source switching process [1/2]" into amlogic-dev-2023
diff --git a/arch/arm/mach-meson/s6/hdmitx_clk.c b/arch/arm/mach-meson/s6/hdmitx_clk.c
index 84eb3b6..f3cc21f 100644
--- a/arch/arm/mach-meson/s6/hdmitx_clk.c
+++ b/arch/arm/mach-meson/s6/hdmitx_clk.c
@@ -165,7 +165,7 @@
pr_info("pll_od0 = %d, pll_od2 = %d, pll_od1 = %d\n",
pll_od0, pll_od2, pll_od1);
//tx_spll_lock_by_pass_alo
- if (hdev->s7_clk_config)
+ if (hdev->clk_analog_path)
hd21_set_reg_bits(ANACTRL_HDMIPLL_CTRL3, pll_od1, 22, 2);
hd21_set_reg_bits(ANACTRL_HDMIPLL_CTRL3, pll_od2, 24, 6);
hd21_set_reg_bits(ANACTRL_HDMIPLL_CTRL0, pll_od0, 20, 6);
@@ -479,7 +479,7 @@
sspll_dis = env_get("sspll_dis");
if ((!sspll_dis || !strcmp(sspll_dis, "0")) && cd == COLORDEPTH_24B)
set_hpll_sspll_s6(hdev->para->vic);
- if (hdev->s7_clk_config) {
+ if (hdev->clk_analog_path) {
/* bit15
* 1: Analog frequency division
* 0: Digital frequency division(default)
diff --git a/arch/arm/mach-meson/s7/hdmitx_clk.c b/arch/arm/mach-meson/s7/hdmitx_clk.c
index d22f2e0..4e14956 100644
--- a/arch/arm/mach-meson/s7/hdmitx_clk.c
+++ b/arch/arm/mach-meson/s7/hdmitx_clk.c
@@ -144,22 +144,23 @@
pll_od21 = pll_od20 + 1;
pll_od2 = (pll_od20 << 2) | pll_od21;
-
pr_info("pll_od2 = %x\n", pll_od2);
- //pll_od3
- if (cd == COLORDEPTH_24B)
- pll_od3 = 0;//pll_div3 = 5;
- else if (cd == COLORDEPTH_30B)
- pll_od3 = 1;//pll_div3 = 6.25;
- else if (cd == COLORDEPTH_36B)
- pll_od3 = 2;//pll_div3 = 7.5;
+ //pll_od3
+ if (cs != HDMI_COLORSPACE_YUV422) {
+ if (cd == COLORDEPTH_24B)
+ pll_od3 = 0;//pll_div3 = 5;
+ else if (cd == COLORDEPTH_30B)
+ pll_od3 = 1;//pll_div3 = 6.25;
+ else if (cd == COLORDEPTH_36B)
+ pll_od3 = 2;//pll_div3 = 7.5;
+ }
hd21_set_reg_bits(ANACTRL_HDMIPLL_CTRL0, 1, 19, 1);
pr_info("use new pll setting for hdmitx clk\n");
pr_info("pll_od1 = %d, pll_od2 = %d, pll_od3 = %d\n",
pll_od1, pll_od2, pll_od3);
- if (hdev->s7_clk_config)
+ if (hdev->clk_analog_path)
hd21_set_reg_bits(ANACTRL_HDMIPLL_CTRL0, pll_od3, 9, 2);
hd21_set_reg_bits(ANACTRL_HDMIPLL_CTRL2, pll_od2, 15, 4);
hd21_set_reg_bits(ANACTRL_HDMIPLL_CTRL2, pll_od1, 19, 4);
@@ -472,7 +473,7 @@
sspll_dis = env_get("sspll_dis");
if ((!sspll_dis || !strcmp(sspll_dis, "0")) && cd == COLORDEPTH_24B)
set_hpll_sspll_s7(hdev->para->vic);
- if (hdev->s7_clk_config) {
+ if (hdev->clk_analog_path) {
pr_info("select vid_pix_clk source for encp/pixel_clk\n");
return;
}
diff --git a/arch/arm/mach-meson/s7d/hdmitx_clk.c b/arch/arm/mach-meson/s7d/hdmitx_clk.c
index 7a04d43..411f014 100644
--- a/arch/arm/mach-meson/s7d/hdmitx_clk.c
+++ b/arch/arm/mach-meson/s7d/hdmitx_clk.c
@@ -149,19 +149,21 @@
pll_od2 = (pll_od20 << 3) | pll_od21;
//pll_od1
- if (cd == COLORDEPTH_24B)
- pll_od1 = 0;//pll_div3 = 5;
- else if (cd == COLORDEPTH_30B)
- pll_od1 = 1;//pll_div3 = 6.25;
- else if (cd == COLORDEPTH_36B)
- pll_od1 = 2;//pll_div3 = 7.5;
+ if (cs != HDMI_COLORSPACE_YUV422) {
+ if (cd == COLORDEPTH_24B)
+ pll_od1 = 0;//pll_div3 = 5;
+ else if (cd == COLORDEPTH_30B)
+ pll_od1 = 1;//pll_div3 = 6.25;
+ else if (cd == COLORDEPTH_36B)
+ pll_od1 = 2;//pll_div3 = 7.5;
+ }
//tx_spll_hdmi_clk_select
hd21_set_reg_bits(ANACTRL_HDMIPLL_CTRL3, 1, 19, 1);
pr_info("pll_od0 = %d, pll_od2 = %d, pll_od1 = %d\n",
pll_od0, pll_od2, pll_od1);
//tx_spll_lock_by_pass_alo
- if (hdev->s7_clk_config)
+ if (hdev->clk_analog_path)
hd21_set_reg_bits(ANACTRL_HDMIPLL_CTRL3, pll_od1, 22, 2);
hd21_set_reg_bits(ANACTRL_HDMIPLL_CTRL3, pll_od2, 24, 6);
hd21_set_reg_bits(ANACTRL_HDMIPLL_CTRL0, pll_od0, 20, 6);
@@ -474,7 +476,7 @@
sspll_dis = env_get("sspll_dis");
if ((!sspll_dis || !strcmp(sspll_dis, "0")) && cd == COLORDEPTH_24B)
set_hpll_sspll_s7d(hdev->para->vic);
- if (hdev->s7_clk_config) {
+ if (hdev->clk_analog_path) {
pr_info("select vid_pix_clk source for encp/pixel_clk\n");
return;
}
diff --git a/arch/arm/mach-meson/t6d/hdmitx_clk.c b/arch/arm/mach-meson/t6d/hdmitx_clk.c
index 733dd74..903508d 100644
--- a/arch/arm/mach-meson/t6d/hdmitx_clk.c
+++ b/arch/arm/mach-meson/t6d/hdmitx_clk.c
@@ -160,7 +160,7 @@
pr_info("use new pll setting for hdmitx clk\n");
pr_info("pll_od1 = %d, pll_od2 = %d, pll_od3 = %d\n",
pll_od1, pll_od2, pll_od3);
- if (hdev->s7_clk_config)
+ if (hdev->clk_analog_path)
hd21_set_reg_bits(ANACTRL_HDMIPLL_CTRL0, pll_od3, 9, 2);
hd21_set_reg_bits(ANACTRL_HDMIPLL_CTRL2, pll_od2, 15, 4);
hd21_set_reg_bits(ANACTRL_HDMIPLL_CTRL2, pll_od1, 19, 4);
@@ -470,7 +470,7 @@
return;
set_hdmitx_s7_htx_pll(hdev);
- if (hdev->s7_clk_config) {
+ if (hdev->clk_analog_path) {
pr_info("select vid_pix_clk source for encp/pixel_clk\n");
return;
}
diff --git a/cmd/amlogic/cmd_hdmitx21.c b/cmd/amlogic/cmd_hdmitx21.c
index 0cba56d..8311fa6 100644
--- a/cmd/amlogic/cmd_hdmitx21.c
+++ b/cmd/amlogic/cmd_hdmitx21.c
@@ -653,16 +653,16 @@
return 1;
}
-static int do_s7_clk_config(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+static int do_clk_path_config(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
struct hdmitx_dev *hdev = get_hdmitx21_device();
if (strcmp(argv[1], "1") == 0) {
- hdev->s7_clk_config = 1;
- pr_info("s7_clk_config = %d\n", hdev->s7_clk_config);
+ hdev->clk_analog_path = 1;
+ pr_info("clk_analog_path = %d\n", hdev->clk_analog_path);
} if (strcmp(argv[1], "0") == 0) {
- hdev->s7_clk_config = 0;
- pr_info("s7_clk_config = %d\n", hdev->s7_clk_config);
+ hdev->clk_analog_path = 0;
+ pr_info("clk_analog_path = %d\n", hdev->clk_analog_path);
}
return 1;
}
@@ -1882,7 +1882,7 @@
#endif
U_BOOT_CMD_MKENT(pbist, 3, 1, do_pbist, "", ""),
U_BOOT_CMD_MKENT(debug, 3, 1, do_debug, "", ""),
- U_BOOT_CMD_MKENT(s7_clk_config, 3, 1, do_s7_clk_config, "", ""),
+ U_BOOT_CMD_MKENT(clk_analog_path, 3, 1, do_clk_path_config, "", ""),
U_BOOT_CMD_MKENT(get_rterm, 3, 1, get_rterm, "", ""),
};
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx21/hdmitx_drv.c b/drivers/amlogic/media/vout/hdmitx/hdmitx21/hdmitx_drv.c
index c949bcc..93f1c12 100644
--- a/drivers/amlogic/media/vout/hdmitx/hdmitx21/hdmitx_drv.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmitx21/hdmitx_drv.c
@@ -458,9 +458,11 @@
hdev->para = ¶
hdev->dfm_type = -1;
- /* enable analog frequency division by default on S6 */
- if (hdev->chip_type == MESON_CPU_ID_S6)
- hdev->s7_clk_config = 1;
+ /* enable analog frequency division by default on S7 & S7D & S6 */
+ if (hdev->chip_type == MESON_CPU_ID_S7 ||
+ hdev->chip_type == MESON_CPU_ID_S7D ||
+ hdev->chip_type == MESON_CPU_ID_S6)
+ hdev->clk_analog_path = 1;
}
/*
@@ -477,10 +479,11 @@
hd21_set_reg_bits(CLKCTRL_VID_CLK0_CTRL, 0, 16, 3);
hd21_set_reg_bits(CLKCTRL_VID_CLK0_DIV, div - 1, 0, 8);
hd21_set_reg_bits(CLKCTRL_VID_CLK0_CTRL, 7, 0, 3);
- if (hdev->chip_type == MESON_CPU_ID_S7) {
+ if (hdev->chip_type == MESON_CPU_ID_S7||
+ hdev->chip_type == MESON_CPU_ID_S7D) {
/* bit[18:16]:sel clk source.3'h0:vid_pll_clk, 3'h3:vid_pix_clk */
/* [49]hdmi_vx1_pix_clk */
- if (hdev->s7_clk_config)
+ if (hdev->clk_analog_path)
hd21_set_reg_bits(CLKCTRL_VID_CLK0_CTRL, 3, 16, 3);
}
}
@@ -739,7 +742,8 @@
static void hdmitx_mux_vid_pll_clk(struct hdmitx_dev *hdev)
{
/* RA bit[18:16] vid_pll_clk source: 0 vid_pll0_clk, 4 vid_pll1_clk */
- hd21_set_reg_bits(CLKCTRL_VID_CLK0_CTRL, hdev->para->frl_rate ? 4 : 0, 16, 3);
+ if (hdev->chip_type == MESON_CPU_ID_S5)
+ hd21_set_reg_bits(CLKCTRL_VID_CLK0_CTRL, hdev->para->frl_rate ? 4 : 0, 16, 3);
}
/*
diff --git a/include/amlogic/media/vout/hdmitx21/hdmitx_module.h b/include/amlogic/media/vout/hdmitx21/hdmitx_module.h
index fc22982..d2c1736 100644
--- a/include/amlogic/media/vout/hdmitx21/hdmitx_module.h
+++ b/include/amlogic/media/vout/hdmitx21/hdmitx_module.h
@@ -86,12 +86,12 @@
struct rx_cap RXCap;
struct hdmi_format_para *para;
enum hdmi_vic vic; /* qms: tfr_vic normal: vic */
- /* for s7,s7d default 0
+ /* for s7,s7d,s6 default 1
* 1: new clk config, encp/pixel clk is directly configured by the pll simulation part.
* through [ 49]hdmi_vx1_pix_clk to encp/pixel clk
* CLKCTRL_VID_CLK0_CTRL clk source should select vid_pix_clk.
*/
- u8 s7_clk_config;
+ u8 clk_analog_path;
enum frl_rate_enum manual_frl_rate; /* for manual setting */
u8 tx_max_frl_rate; /* configure in dts file */
bool flt_train_st; /* 0 means FLT train failed */