commit | 8933fc4ad7e0f94302846ce6d93c41fbadcfd357 | [log] [tgz] |
---|---|---|
author | Junyi Zhao <junyi.zhao@amlogic.com> | Fri Aug 02 16:33:51 2024 +0800 |
committer | Tao Zeng <tao.zeng@amlogic.com> | Fri Aug 16 02:11:17 2024 -0700 |
tree | bc248eae0bfe0c713593ac0114d44110a1cb362b | |
parent | 5252a220bae3b051a98cdea693e8c4ac058ef221 [diff] |
pwm: s7d: set pwm fdiv3 clock for regulator [1/1] PD#SWPL-180879 Problem: vddee pwm need fixed fdiv3 clock to get more step Solution: set it Verify: s7d Change-Id: I620fb7b391ae78f0bb9cafd093bb5166b326801d Signed-off-by: Junyi Zhao <junyi.zhao@amlogic.com>