blob: 66667b1cf1ed2db7f843173dad79d25047aa1178 [file] [log] [blame]
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
4 */
5
6#include <common.h>
7#include <command.h>
8#include <env.h>
9#include <malloc.h>
10#include <asm/byteorder.h>
11#include <amlogic/clk_measure.h>
12#include <amlogic/media/vout/hdmitx21/hdmitx.h>
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080013#include <linux/delay.h>
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +080014#include <image.h>
Wenjie Qiao8a73a562023-02-23 18:37:14 +080015#include <amlogic/media/dv/dolby_vision.h>
16#include <linux/libfdt_env.h>
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +080017#include <amlogic/media/vout/dsc.h>
xiang.wu114497ab2024-02-21 14:57:05 +080018#include <amlogic/media/vout/aml_vinfo.h>
19#include <linux/arm-smccc.h>
Wenjie Qiao8a73a562023-02-23 18:37:14 +080020
21static unsigned char edid_raw_buf[512] = {0};
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080022/* there may be outputmode/2/3 when in multi-display case,
23 * sel_hdmimode is used to save the selected hdmi mode
24 */
25static char sel_hdmimode[MODE_LEN] = {0};
Wenjie Qiao8a73a562023-02-23 18:37:14 +080026
27static void dump_full_edid(const unsigned char *buf)
28{
29 int i;
30 int blk_no;
31
32 if (!buf)
33 return;
34 blk_no = buf[126] + 1;
35 if (blk_no > 4)
36 blk_no = 4;
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080037
38 if (blk_no == 2)
39 if (buf[128 + 4] == 0xe2 && buf[128 + 5] == 0x78)
40 blk_no = buf[128 + 6] + 1;
xiang.wu114497ab2024-02-21 14:57:05 +080041 if (blk_no > EDID_MAX_BLOCK)
42 blk_no = EDID_MAX_BLOCK;
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080043
Wenjie Qiao8a73a562023-02-23 18:37:14 +080044 printf("dump EDID rawdata\n");
45 printf(" ");
46 for (i = 0; i < blk_no * EDID_BLK_SIZE; i++)
47 printf("%02x", buf[i]);
48 printf("\n");
49}
50
51static int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
52{
53 unsigned char st = 0;
54 struct hdmitx_dev *hdev = get_hdmitx21_device();
55
56 memset(edid_raw_buf, 0, ARRAY_SIZE(edid_raw_buf));
57
58 st = hdev->hwop.read_edid(edid_raw_buf);
59
60 if (!st)
61 printf("edid read failed\n");
62
63 return st;
64}
65
66static int do_rx_det(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
67{
68 unsigned char st = 0;
69 struct hdmitx_dev *hdev = get_hdmitx21_device();
70
71 memset(edid_raw_buf, 0, ARRAY_SIZE(edid_raw_buf));
72
73 // read edid raw data
74 // current only support read 1 byte edid data
75 st = hdev->hwop.read_edid(edid_raw_buf);
76
77 if (st) {
78 if (edid_raw_buf[250] == 0xfb && edid_raw_buf[251] == 0x0c) {
79 printf("RX is FBC\n");
80
81 // set outputmode ENV
82 switch (edid_raw_buf[252] & 0x0f) {
83 case 0x0:
84 run_command("setenv outputmode 1080p50hz", 0);
85 break;
86 case 0x1:
87 run_command("setenv outputmode 2160p50hz420", 0);
88 break;
89 case 0x2:
90 run_command("setenv outputmode 1080p50hz44410bit", 0);
91 break;
92 case 0x3:
93 run_command("setenv outputmode 2160p50hz42010bit", 0);
94 break;
95 case 0x4:
96 run_command("setenv outputmode 2160p50hz42210bit", 0);
97 break;
98 case 0x5:
99 run_command("setenv outputmode 2160p50hz", 0);
100 break;
101 default:
102 run_command("setenv outputmode 1080p50hz", 0);
103 break;
104 }
105
106 /*et RX 3D Info*/
107 switch ((edid_raw_buf[252] >> 4) & 0x0f) {
108 case 0x00:
109 run_command("setenv rx_3d_info 0", 0);
110 break;
111 case 0x01:
112 run_command("setenv rx_3d_info 1", 0);
113 break;
114 case 0x02:
115 run_command("setenv rx_3d_info 2", 0);
116 break;
117 case 0x03:
118 run_command("setenv rx_3d_info 3", 0);
119 break;
120 case 0x04:
121 run_command("setenv rx_3d_info 4", 0);
122 break;
123 default:
124 break;
125 }
126
127 switch (edid_raw_buf[253]) {
128 case 0x1:
129 /*TODO*/
130 break;
131 case 0x2:
132 /*TODO*/
133 break;
134 default:
135 break;
136 }
137 }
138 } else {
139 printf("edid read failed\n");
140 }
141
142 return st;
143}
144
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800145static void save_default_720p(void)
146{
147 memcpy(sel_hdmimode, DEFAULT_HDMI_MODE, sizeof(DEFAULT_HDMI_MODE));
148 if (is_hdmi_mode(env_get("outputmode")))
149 env_set("outputmode", DEFAULT_HDMI_MODE);
150 else if (is_hdmi_mode(env_get("outputmode2")))
151 env_set("outputmode2", DEFAULT_HDMI_MODE);
152 else if (is_hdmi_mode(env_get("outputmode3")))
153 env_set("outputmode3", DEFAULT_HDMI_MODE);
154 env_set("colorattribute", DEFAULT_COLOR_FORMAT);
155}
156
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800157static void hdmitx_mask_rx_info(struct hdmitx_dev *hdev)
158{
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800159 if (!hdev || !hdev->para)
160 return;
161
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800162 if (env_get("colorattribute"))
163 hdmitx21_get_fmtpara(sel_hdmimode, env_get("colorattribute"));
164
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800165 /* when current output color depth is 8bit, mask hdr capability */
166 /* refer to SWPL-44445 for more detail */
167 if (hdev->para->cd == COLORDEPTH_24B)
168 memset(&hdev->RXCap.hdr_info, 0, sizeof(struct hdr_info));
169}
170
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800171/* If environment qms_en is true, and RX supports QMS, and the
172 * output mode is BRR then enable TX QMS
173 */
174static void qms_scene_pre_process(struct hdmitx_dev *hdev)
175{
176 bool env_qms_en = 0;
177 bool rx_qms_cap = 0;
178 enum hdmi_vic qms_brr_vic = HDMI_UNKNOWN;
179 const struct hdmi_timing *t = NULL;
180 char *color = NULL;
181
182 /* check uboot environment */
183 if (env_get("qms_en") && (env_get_ulong("qms_en", 10, 0) == 1))
184 env_qms_en = 1;
185
186 rx_qms_cap = hdev->RXCap.qms;
187
188 qms_brr_vic = hdmitx_find_brr_vic(hdev->vic);
189
190 if (env_qms_en && rx_qms_cap && qms_brr_vic != HDMI_UNKNOWN)
191 hdev->qms_en = 1;
192 pr_info("QMS: env %d rx %d vic %d brr_vic %d\n", env_qms_en, rx_qms_cap,
193 hdev->vic, qms_brr_vic);
194 if (!hdev->qms_en)
195 return;
196 hdev->brr_vic = qms_brr_vic;
197 /* save brr_vic to vic without the environment */
198 hdev->vic = hdev->brr_vic;
199 /* reconfig the hdmi para */
200 t = hdmitx21_gettiming_from_vic(hdev->brr_vic);
201 if (!t) {
202 pr_info("not find brr_vic %d timing\n", hdev->brr_vic);
203 return;
204 }
205 color = env_get("user_colorattribute");
206 if (!color)
207 color = env_get("colorattribute");
208 hdev->para = hdmitx21_get_fmtpara(t->sname ? t->sname : t->name, color);
209}
210
211static void qms_scene_post_process(struct hdmitx_dev *hdev)
212{
213 // Init QMS parameter
214 vrr_init_qms_para(hdev);
215}
216
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800217static int do_output(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
218{
219 const struct hdmi_timing *timing = NULL;
220 struct hdmitx_dev *hdev = get_hdmitx21_device();
221
xiang.wu1a6d6f1d2023-08-04 14:13:00 +0800222#ifdef CONFIG_PXP_EMULATOR
223 hdmitx21_pxp_init(1);
224#endif
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800225 if (argc < 1)
226 return cmd_usage(cmdtp);
227
228 if (strcmp(argv[1], "list") == 0) {
229 hdev->hwop.list_support_modes();
230 } else if (strcmp(argv[1], "bist") == 0) {
231 unsigned int mode = 0;
232
233 if (strcmp(argv[2], "off") == 0)
234 mode = 0;
235 else if (strcmp(argv[2], "line") == 0)
236 mode = 2;
237 else if (strcmp(argv[2], "dot") == 0)
238 mode = 3;
239 else if (strcmp(argv[2], "x") == 0)
240 mode = 'x';
241 else if (strcmp(argv[2], "X") == 0)
242 mode = 'X';
243 else
244 mode = simple_strtoul(argv[2], NULL, 10);
245 hdev->hwop.test_bist(mode);
246 } else if (strcmp(argv[1], "prbs") == 0) {
247 hdev->para->cs = HDMI_COLORSPACE_RGB;
248 hdev->para->cd = COLORDEPTH_24B;
249 hdev->vic = HDMI_16_1920x1080p60_16x9;
250 hdmitx21_set(hdev);
251 hdev->hwop.test_prbs();
252 } else if (strncmp(argv[1], "div40", 5) == 0) {
253 bool div40 = 0;
254
255 if (argv[1][5] == '1')
256 div40 = 1;
257 hdev->hwop.set_div40(div40);
258 } else { /* "output" */
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800259 if (!hdev->pxp_mode) {
xiang.wu114497ab2024-02-21 14:57:05 +0800260 if (!hdmitx_edid_check_data_valid(0, hdev->rawedid)) {
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800261 /* in SWPL-34712: if EDID parsing error in kernel,
262 * only forcely output default mode(480p,RGB,8bit)
263 * in sysctl, not save the default mode to env.
264 * if uboot follow this rule, will cause issue OTT-19333:
265 * uboot read edid error and then output default mode,
266 * without save it mode env. if then kernel edid normal,
267 * sysctrl/kernel get mode from env, the actual output
268 * mode differs with outputmode env,it will
269 * cause display abnormal(such as stretch). so don't
270 * follow this rule in uboot, that's to say the actual
271 * output mode needs to stays with the outputmode env.
272 */
273 printf("edid parsing ng, forcely output 720p, rgb,8bit\n");
274 save_default_720p();
275 hdev->vic = HDMI_4_1280x720p60_16x9;
276 hdev->para =
277 hdmitx21_get_fmtpara("720p60hz", "rgb,8bit");
278 hdev->para->cs = HDMI_COLORSPACE_RGB;
279 hdev->para->cd = COLORDEPTH_24B;
280 hdmitx21_set(hdev);
281 return CMD_RET_SUCCESS;
282 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800283 }
284 if (!env_get("colorattribute"))
285 env_set("colorattribute", "444,8bit");
286 hdev->para = hdmitx21_get_fmtpara(argv[1], env_get("colorattribute"));
287 hdev->vic = hdev->para->timing.vic;
xiang.wu114497ab2024-02-21 14:57:05 +0800288 if (hdev->vic == HDMI_0_UNKNOWN) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800289 /* Not find VIC */
290 printf("Not find '%s' mapped VIC\n", argv[1]);
291 return CMD_RET_FAILURE;
292 }
293 if (strstr(argv[1], "hz420"))
294 hdev->para->cs = HDMI_COLORSPACE_YUV420;
295 /* S5 support over 6G, T7 not support */
296 switch (hdev->vic) {
297 case HDMI_96_3840x2160p50_16x9:
298 case HDMI_97_3840x2160p60_16x9:
299 case HDMI_101_4096x2160p50_256x135:
300 case HDMI_102_4096x2160p60_256x135:
301 case HDMI_106_3840x2160p50_64x27:
302 case HDMI_107_3840x2160p60_64x27:
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800303 if (hdev->chip_type != MESON_CPU_ID_S5) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800304 if (hdev->para->cs == HDMI_COLORSPACE_RGB ||
305 hdev->para->cs == HDMI_COLORSPACE_YUV444) {
306 if (hdev->para->cd != COLORDEPTH_24B) {
307 printf("vic %d cs %d has no cd %d\n",
308 hdev->vic,
309 hdev->para->cs,
310 hdev->para->cd);
311 hdev->para->cd = COLORDEPTH_24B;
312 printf("set cd as %d\n", COLORDEPTH_24B);
313 }
314 }
315 }
316 break;
317 default:
318 /* In Spec2.1 Table 7-34, greater than 2160p30hz will support y420 */
319 timing = hdmitx21_gettiming_from_vic(hdev->vic);
320 if (!timing)
321 break;
322 if (timing->v_active > 2160 && timing->v_freq > 30000)
323 break;
324 if (timing->v_active >= 4320)
325 break;
326 if (hdev->para->cs == HDMI_COLORSPACE_YUV420) {
327 printf("vic %d has no cs %d\n", hdev->vic,
328 hdev->para->cs);
329 hdev->para->cs = HDMI_COLORSPACE_YUV444;
330 printf("set cs as %d\n", HDMI_COLORSPACE_YUV444);
331 }
332 break;
333 }
334 printf("set hdmitx VIC = %d CS = %d CD = %d\n",
335 hdev->vic, hdev->para->cs, hdev->para->cd);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800336 qms_scene_pre_process(hdev);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800337 /* currently, hdmi mode is always set, if
338 * mode set abort/exit, need to add return
339 * result of mode setting, so that vout
340 * driver will pass it to kernel, and do
341 * mode setting again when vout init in kernel
342 */
343 hdmitx21_set(hdev);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800344 qms_scene_post_process(hdev);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800345 if (hdev->frl_rate && !hdev->flt_train_st) {
346 /* FLT training failed, need go to tmds mode */
347 printf("hdmitx frl training failed, set tmds mode\n");
348 run_command("setenv hdmimode 1080p60hz", 0);
349 run_command("setenv colorattribute 422,12bit", 0);
350 run_command("run init_display_base", 0);
351 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800352 }
353 return CMD_RET_SUCCESS;
354}
355
356static int do_clkmsr(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
357{
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800358 struct hdmitx_dev *hdev = get_hdmitx21_device();
359
360 if (hdev->chip_type == MESON_CPU_ID_S5) {
361 clk_msr(4);
362 clk_msr(8);
363 clk_msr(16);
364 clk_msr(27);
365 clk_msr(63);
366 clk_msr(64);
367 clk_msr(66);
368 clk_msr(68);
369 clk_msr(69);
370 clk_msr(70);
371 clk_msr(71);
372 clk_msr(72);
373 clk_msr(73);
374 clk_msr(74);
375 clk_msr(75);
376 clk_msr(76);
377 clk_msr(79);
378 clk_msr(82);
379 clk_msr(89);
380 clk_msr(90);
381 clk_msr(91);
382 clk_msr(92);
383 clk_msr(93);
384 clk_msr(94);
385 clk_msr(95);
386 return CMD_RET_SUCCESS;
387 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800388 clk_msr(51);
389 clk_msr(59);
390 clk_msr(61);
391 clk_msr(76);
392 clk_msr(77);
393 clk_msr(78);
394 clk_msr(80);
395 clk_msr(81);
396 clk_msr(82);
397 clk_msr(83);
398 clk_msr(219);
399 clk_msr(220);
400 clk_msr(221);
401 clk_msr(222);
402 return CMD_RET_SUCCESS;
403}
404
405static int do_blank(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
406{
407 struct hdmitx_dev *hdev = get_hdmitx21_device();
408
409 if (argc < 1)
410 return cmd_usage(cmdtp);
411
412 if (strcmp(argv[1], "1") == 0)
413 hdev->hwop.output_blank(1);
414 if (strcmp(argv[1], "0") == 0)
415 hdev->hwop.output_blank(0);
416
417 return CMD_RET_SUCCESS;
418}
419
420static int do_off(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
421{
422 struct hdmitx_dev *hdev = get_hdmitx21_device();
423
xiang.wu114497ab2024-02-21 14:57:05 +0800424 hdev->vic = HDMI_0_UNKNOWN;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800425 if (hdev->chip_type == MESON_CPU_ID_S5)
426 hdmitx_module_disable();
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800427 hdev->hwop.turn_off();
428 printf("turn off hdmitx\n");
429 return 1;
430}
431
432static int do_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
433{
434 struct hdmitx_dev *hdev = get_hdmitx21_device();
435
436 hdev->hwop.dump_regs();
437 return 1;
438}
439
440static int do_reg(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
441{
442 unsigned long addr = 0;
443 unsigned int data = 0;
444
445 if (argc < 1)
446 return cmd_usage(cmdtp);
447
448 if (strncmp(argv[1], "rh", 2) == 0) {
449 addr = strtoul(argv[1] + 2, NULL, 16);
450 data = hdmitx21_rd_reg((unsigned int)addr);
451 printf("rd[0x%lx] 0x%x\n", addr, data);
452 }
453
454 if (strncmp(argv[1], "wh", 2) == 0) {
455 addr = strtoul(argv[1] + 2, NULL, 16);
456 data = strtoul(argv[2], NULL, 16);
457 hdmitx21_wr_reg(addr, data);
458 printf("wr[0x%lx] 0x%x\n", addr, data);
459 }
460
461 return 1;
462}
463
xiang.wu1a6d6f1d2023-08-04 14:13:00 +0800464static int do_pbist(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
465{
466 struct hdmitx_dev *hdev = get_hdmitx21_device();
467
468 if (strcmp(argv[1], "1") == 0)
469 hdmitx21_pbist_config(hdev, hdev->vic, 1);
470 if (strcmp(argv[1], "0") == 0)
471 hdmitx21_pbist_config(hdev, hdev->vic, 0);
472 return 1;
473}
474
xiang.wu1492f3642024-01-08 14:06:40 +0800475static int do_s7_clk_config(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
476{
477 struct hdmitx_dev *hdev = get_hdmitx21_device();
478
479 if (strcmp(argv[1], "1") == 0) {
480 hdev->s7_clk_config = 1;
481 pr_info("s7_clk_config = %d\n", hdev->s7_clk_config);
482 } if (strcmp(argv[1], "0") == 0) {
483 hdev->s7_clk_config = 0;
484 pr_info("s7_clk_config = %d\n", hdev->s7_clk_config);
485 }
486 return 1;
487}
488
xiang.wu114497ab2024-02-21 14:57:05 +0800489static int get_rterm(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
490{
491 struct arm_smccc_res res;
492 u8 rterm_efuse;
493
494 arm_smccc_smc(HDCPTX_IOOPR, HDMITX_GET_RTERM, 0, 0, 0, 0, 0, 0, &res);
495 rterm_efuse = (unsigned int)((res.a0) & 0xffffffff);
496 pr_info("rterm_efuse = %d\n", rterm_efuse);
497 return 1;
498}
499
xiang.wu1a6d6f1d2023-08-04 14:13:00 +0800500static int do_debug(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
501{
502 unsigned int enable_all = 0;
503 int pkt_op = 0;
504 unsigned int mov_val = 0;
505 unsigned char pb[28] = {0x46, 0xD0, 0x00, 0x00, 0x00, 0x00, 0x46, 0xD0,
506 0x00, 0x10, 0x21, 0xaa, 0x9b, 0x96, 0x19, 0xfc, 0x19, 0x75, 0xd5, 0x78,
507 0x10, 0x21, 0xaa, 0x9b, 0x96, 0x19, 0xfc, 0x19};
508 unsigned char hb[3] = {0x01, 0x02, 0x03};
509
510 if (argc < 1)
511 return cmd_usage(cmdtp);
512
513 if (strncmp(argv[1], "pkt", 3) == 0) {
514 enable_all = strtoul(argv[1] + 3, NULL, 16);
515 pkt_op = strtoul(argv[2], NULL, 16);
516 mov_val = strtoul(argv[3], NULL, 10);
517 pkt_send_position_change(enable_all, pkt_op, mov_val);
518 } else if (strncmp(argv[1], "w_dhdr", 6) == 0 ) {
519 hdmitx21_write_dhdr_sram();
520 } else if (strncmp(argv[1], "r_dhdr", 6) == 0 ) {
521 hdmitx21_read_dhdr_sram();
522 } else if (strncmp(argv[1], "t_avi", 4) == 0 ) {
523 printf("test send avi pkt\n");
524 hdmi_avi_infoframe_rawset(hb, pb);
525 } else if (strncmp(argv[1], "t_audio", 7) == 0 ) {
526 printf("test send audio pkt\n");
527 hdmi_audio_infoframe_rawset(hb, pb);
528 } else if (strncmp(argv[1], "t_sbtm", 6) == 0 ) {
529 printf("test send SBTM pkt\n");
530 hdmitx21_send_sbtm_pkt();
531 }
532
533 return 1;
534}
535
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800536static bool check_vic_exist(struct hdmitx_dev *hdev, enum hdmi_vic vic,
537 int count)
538{
539 struct rx_cap *rxcap = NULL;
540 int i;
541
542 rxcap = &hdev->RXCap;
543 for (i = 0; i < count; i++)
544 if (vic == rxcap->VIC[i])
545 return 1;
546
547 return 0;
548}
549
550static void disp_cap_show(struct hdmitx_dev *hdev)
551{
552 struct rx_cap *rxcap = NULL;
553 const struct hdmi_timing *timing = NULL;
554 enum hdmi_vic vic;
555 int i;
556
557 if (!hdev)
558 return;
559
560 rxcap = &hdev->RXCap;
561 printf("disp_cap\n");
562 for (i = 0; i < rxcap->VIC_count && i < VIC_MAX_NUM; i++) {
563 vic = rxcap->VIC[i];
564 if (check_vic_exist(hdev, vic, i))
565 continue;
566 timing = hdmitx21_gettiming_from_vic(vic);
567 if (timing && vic < HDMITX_VESA_OFFSET && !is_vic_over_limited_1080p(vic))
568 printf(" %s\n", timing->sname ? timing->sname : timing->name);
569 }
xiang.wu114497ab2024-02-21 14:57:05 +0800570 printf("420_cap\n");
571 for (i = 0; i < Y420_VIC_MAX_NUM; i++) {
572 vic = rxcap->y420_vic[i];
573 printf("420vic:%d\n", vic);
574 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800575}
576
577static void vesa_cap_show(struct hdmitx_dev *hdev)
578{
579}
580
581static void dc_cap_show(struct hdmitx_dev *hdev)
582{
583 enum hdmi_vic vic = HDMI_0_UNKNOWN;
584 struct rx_cap *prxcap = &hdev->RXCap;
585 const struct dv_info *dv = &hdev->RXCap.dv_info;
586
587 printf("dc_cap\n");
588 if (prxcap->dc_36bit_420)
589 printf("420,12bit\n");
590 if (prxcap->dc_30bit_420) {
591 printf("420,10bit\n");
592 printf("420,8bit\n");
593 } else {
594 vic = hdmitx_edid_get_VIC(hdev, "2160p60hz420", 0);
595 if (vic != HDMI_0_UNKNOWN) {
596 printf("420,8bit\n");
597 goto next444;
598 }
599 vic = hdmitx_edid_get_VIC(hdev, "2160p50hz420", 0);
600 if (vic != HDMI_0_UNKNOWN) {
601 printf("420,8bit\n");
602 goto next444;
603 }
604 vic = hdmitx_edid_get_VIC(hdev, "smpte60hz420", 0);
605 if (vic != HDMI_0_UNKNOWN) {
606 printf("420,8bit\n");
607 goto next444;
608 }
609 vic = hdmitx_edid_get_VIC(hdev, "smpte50hz420", 0);
610 if (vic != HDMI_0_UNKNOWN) {
611 printf("420,8bit\n");
612 goto next444;
613 }
614 }
615next444:
616 if (prxcap->native_Mode & (1 << 5)) {
617 if (prxcap->dc_y444) {
618 if (prxcap->dc_36bit || dv->sup_10b_12b_444 == 0x2)
619 printf("444,12bit\n");
620 if (prxcap->dc_30bit || dv->sup_10b_12b_444 == 0x1)
621 printf("444,10bit\n");
622 }
623 printf("444,8bit\n");
624 }
625 /* y422, not check dc */
626 if (prxcap->native_Mode & (1 << 4)) {
627 printf("422,12bit\n");
628 printf("422,10bit\n");
629 printf("422,8bit\n");
630 }
631
632 if (prxcap->dc_36bit || dv->sup_10b_12b_444 == 0x2)
633 printf("rgb,12bit\n");
634 if (prxcap->dc_30bit || dv->sup_10b_12b_444 == 0x1)
635 printf("rgb,10bit\n");
636 printf("rgb,8bit\n");
637}
638
639static void aud_cap_show(struct hdmitx_dev *hdev)
640{
641}
642
643static void hdr_cap_show(struct hdmitx_dev *hdev)
644{
645 int hdr10plugsupported = 0;
646 struct hdr_info *hdr = &hdev->RXCap.hdr_info;
xiang.wu114497ab2024-02-21 14:57:05 +0800647 const struct hdr10_plus_info *hdr10p = &hdev->RXCap.hdr_info.hdr10plus_info;
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800648
649 printf("\nhdr_cap\n");
650 if (hdr10p->ieeeoui == HDR10_PLUS_IEEE_OUI &&
651 hdr10p->application_version != 0xFF)
652 hdr10plugsupported = 1;
653 printf("HDR10Plus Supported: %d\n", hdr10plugsupported);
654 printf("HDR Static Metadata:\n");
655 printf(" Supported EOTF:\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800656 printf(" Traditional SDR: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_SDR));
657 printf(" Traditional HDR: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_HDR));
658 printf(" SMPTE ST 2084: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_SMPTE_ST_2084));
659 printf(" Hybrid Log-Gamma: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_HLG));
660 printf(" Supported SMD type1: %d\n", hdr->static_metadata_type1);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800661 printf(" Luminance Data\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800662 printf(" Max: %d\n", hdr->lumi_max);
663 printf(" Avg: %d\n", hdr->lumi_avg);
664 printf(" Min: %d\n\n", hdr->lumi_min);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800665 printf("HDR Dynamic Metadata:");
666}
667
668static void _dv_cap_show(const struct dv_info *dv)
669{
670 int i;
671
672 if (dv->ieeeoui != DV_IEEE_OUI || dv->block_flag != CORRECT) {
673 printf("The Rx don't support DolbyVision\n");
674 return;
675 }
676 printf("DolbyVision RX support list:\n");
677
678 if (dv->ver == 0) {
679 printf("VSVDB Version: V%d\n", dv->ver);
680 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
681 printf("Support mode:\n");
682 printf(" DV_RGB_444_8BIT\n");
683 if (dv->sup_yuv422_12bit)
684 printf(" DV_YCbCr_422_12BIT\n");
685 }
686 if (dv->ver == 1) {
687 printf("VSVDB Version: V%d(%d-byte)\n", dv->ver, dv->length + 1);
688 if (dv->length == 0xB) {
689 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
690 printf("Support mode:\n");
691 printf(" DV_RGB_444_8BIT\n");
692 if (dv->sup_yuv422_12bit)
693 printf(" DV_YCbCr_422_12BIT\n");
694 if (dv->low_latency == 0x01)
695 printf(" LL_YCbCr_422_12BIT\n");
696 }
697
698 if (dv->length == 0xE) {
699 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
700 printf("Support mode:\n");
701 printf(" DV_RGB_444_8BIT\n");
702 if (dv->sup_yuv422_12bit)
703 printf(" DV_YCbCr_422_12BIT\n");
704 }
705 }
706 if (dv->ver == 2) {
707 printf("VSVDB Version: V%d\n", dv->ver);
708 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
709 printf("Support mode:\n");
710 if (dv->Interface != 0x00 && dv->Interface != 0x01) {
711 printf(" DV_RGB_444_8BIT\n");
712 if (dv->sup_yuv422_12bit)
713 printf(" DV_YCbCr_422_12BIT\n");
714 }
715 printf(" LL_YCbCr_422_12BIT\n");
716 if (dv->Interface == 0x01 || dv->Interface == 0x03) {
717 if (dv->sup_10b_12b_444 == 0x1)
718 printf(" LL_RGB_444_10BIT\n");
719 if (dv->sup_10b_12b_444 == 0x2)
720 printf(" LL_RGB_444_12BIT\n");
721 }
722 }
723 printf("IEEEOUI: 0x%06x\n", dv->ieeeoui);
724 printf("VSVDB: ");
725 for (i = 0; i < (dv->length + 1); i++)
726 printf("%02x", dv->rawdata[i]);
727 printf("\n");
728}
729
730static void dv_cap_show(struct hdmitx_dev *hdev)
731{
732 const struct dv_info *dv = &hdev->RXCap.dv_info;
733
734 printf("dv_cap\n");
735 if (dv->ieeeoui != DV_IEEE_OUI) {
736 printf("The Rx don't support DolbyVision\n");
737 return;
738 }
739 _dv_cap_show(dv);
740}
741
742static void edid_cap_show(struct hdmitx_dev *hdev)
743{
744 int i;
745 struct rx_cap *prxcap = &hdev->RXCap;
746
xiang.wu114497ab2024-02-21 14:57:05 +0800747 printf("Rx EDID Parse:\n");
748 printf("Rx Manufacturer Name: %s\n", prxcap->IDManufacturerName);
749 printf("Rx Product Code: %02x%02x\n",
750 prxcap->IDProductCode[0], prxcap->IDProductCode[1]);
751 printf("Rx Serial Number: %02x%02x%02x%02x\n",
752 prxcap->IDSerialNumber[0],
753 prxcap->IDSerialNumber[1],
754 prxcap->IDSerialNumber[2],
755 prxcap->IDSerialNumber[3]);
756 printf("Rx Product Name: %s\n", prxcap->ReceiverProductName);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800757
xiang.wu114497ab2024-02-21 14:57:05 +0800758 printf("Manufacture Week: %d\n", prxcap->manufacture_week);
759 printf("Manufacture Year: %d\n", prxcap->manufacture_year + 1990);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800760
xiang.wu114497ab2024-02-21 14:57:05 +0800761 printf("Physical size(mm): %d x %d\n",
762 prxcap->physical_width, prxcap->physical_height);
763
764 printf("EDID Version: %d.%d\n",
765 prxcap->edid_version, prxcap->edid_revision);
766
767/* printf(
768 * "EDID block number: 0x%x\n", tx_comm->EDID_buf[0x7e]);
769 *
770 *
771 * printf(
772 * "Source Physical Address[a.b.c.d]: %x.%x.%x.%x\n",
773 * hdmitx_device->hdmi_info.vsdb_phy_addr.a,
774 * hdmitx_device->hdmi_info.vsdb_phy_addr.b,
775 * hdmitx_device->hdmi_info.vsdb_phy_addr.c,
776 * hdmitx_device->hdmi_info.vsdb_phy_addr.d);
777 */
778
779 // TODO native_vic2
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800780 printf("native Mode %x, VIC (native %d):\n",
xiang.wu114497ab2024-02-21 14:57:05 +0800781 prxcap->native_Mode, prxcap->native_vic);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800782
783 printf("ColorDeepSupport %x\n", prxcap->ColorDeepSupport);
784
xiang.wu114497ab2024-02-21 14:57:05 +0800785 for (i = 0; i < prxcap->VIC_count ; i++) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800786 printf("%d ", prxcap->VIC[i]);
xiang.wu114497ab2024-02-21 14:57:05 +0800787 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800788 printf("\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800789 printf("Audio {format, channel, freq, cce}\n");
790 for (i = 0; i < prxcap->AUD_count; i++) {
791 printf("{%d, %d, %x, %x}\n",
792 prxcap->RxAudioCap[i].audio_format_code,
793 prxcap->RxAudioCap[i].channel_num_max,
794 prxcap->RxAudioCap[i].freq_cc,
795 prxcap->RxAudioCap[i].cc3);
796 }
797 printf("Speaker Allocation: %x\n", prxcap->RxSpeakerAllocation);
798 printf("Vendor: 0x%x ( %s device)\n", prxcap->ieeeoui, (prxcap->ieeeoui) ? "HDMI" : "DVI");
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800799
800 printf("MaxTMDSClock1 %d MHz\n", prxcap->Max_TMDS_Clock1 * 5);
801
xiang.wu114497ab2024-02-21 14:57:05 +0800802 if (prxcap->hf_ieeeoui) {
803 printf("Vendor2: 0x%x\n",
804 prxcap->hf_ieeeoui);
805 printf("MaxTMDSClock2 %d MHz\n",
806 prxcap->Max_TMDS_Clock2 * 5);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800807 }
808
xiang.wu114497ab2024-02-21 14:57:05 +0800809 printf("MaxFRLRate: %d\n", prxcap->max_frl_rate);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800810
xiang.wu114497ab2024-02-21 14:57:05 +0800811 if (prxcap->allm)
812 printf("ALLM: %x\n", prxcap->allm);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800813
xiang.wu114497ab2024-02-21 14:57:05 +0800814 if (prxcap->cnc3)
815 printf("Game/CNC3: %x\n", prxcap->cnc3);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800816
xiang.wu114497ab2024-02-21 14:57:05 +0800817 printf("vLatency: ");
818 if (prxcap->vLatency == LATENCY_INVALID_UNKNOWN)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800819 printf(" Invalid/Unknown\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800820 else if (prxcap->vLatency == LATENCY_NOT_SUPPORT)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800821 printf(" UnSupported\n");
822 else
xiang.wu114497ab2024-02-21 14:57:05 +0800823 printf(" %d\n", prxcap->vLatency);
824
825 printf("aLatency: ");
826 if (prxcap->aLatency == LATENCY_INVALID_UNKNOWN)
827 printf(" Invalid/Unknown\n");
828 else if (prxcap->aLatency == LATENCY_NOT_SUPPORT)
829 printf(" UnSupported\n");
830 else
831 printf(" %d\n", prxcap->aLatency);
832
833 printf("i_vLatency: ");
834 if (prxcap->i_vLatency == LATENCY_INVALID_UNKNOWN)
835 printf(" Invalid/Unknown\n");
836 else if (prxcap->i_vLatency == LATENCY_NOT_SUPPORT)
837 printf(" UnSupported\n");
838 else
839 printf(" %d\n", prxcap->i_vLatency);
840
841 printf("i_aLatency: ");
842 if (prxcap->i_aLatency == LATENCY_INVALID_UNKNOWN)
843 printf(" Invalid/Unknown\n");
844 else if (prxcap->i_aLatency == LATENCY_NOT_SUPPORT)
845 printf(" UnSupported\n");
846 else
847 printf(" %d\n", prxcap->i_aLatency);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800848
849 if (prxcap->colorimetry_data)
850 printf("ColorMetry: 0x%x\n", prxcap->colorimetry_data);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800851
xiang.wu114497ab2024-02-21 14:57:05 +0800852 printf("SCDC: %x\n", prxcap->scdc_present);
853
854 printf("RR_Cap: %x\n",
855 prxcap->scdc_rr_capable);
856 printf("LTE_340M_Scramble: %x\n",
857 prxcap->lte_340mcsc_scramble);
858 /* dsc capability */
859 printf("dsc_10bpc: %d\n",
860 prxcap->dsc_10bpc);
861 printf("dsc_12bpc: %d\n",
862 prxcap->dsc_12bpc);
863 printf("dsc_16bpc: %d\n",
864 prxcap->dsc_16bpc);
865 printf("dsc_all_bpp: %d\n",
866 prxcap->dsc_all_bpp);
867 printf("dsc_native_420: %d\n",
868 prxcap->dsc_native_420);
869 printf("dsc_1p2: %d\n",
870 prxcap->dsc_1p2);
871 printf("dsc_max_slices: 0x%x(%d slices)\n",
872 prxcap->dsc_max_slices, dsc_max_slices_num[prxcap->dsc_max_slices]);
873 printf("dsc_max_frl_rate: 0x%x\n",
874 prxcap->dsc_max_frl_rate);
875 printf("dsc_total_chunk_bytes: 0x%x\n",
876 prxcap->dsc_total_chunk_bytes);
877 if (prxcap->dv_info.ieeeoui == DOVI_IEEEOUI)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800878 printf(" DolbyVision%d", prxcap->dv_info.ver);
xiang.wu114497ab2024-02-21 14:57:05 +0800879
880 if (prxcap->hdr_info2.hdr_support)
881 printf(" HDR/%d",
882 prxcap->hdr_info2.hdr_support);
883 if (prxcap->hdr_info.sbtm_info.sbtm_support)
884 printf(" SBTM");
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800885 if (prxcap->dc_y444 || prxcap->dc_30bit || prxcap->dc_30bit_420)
886 printf(" DeepColor");
887 printf("\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800888 printf("additional_vsif_num: %d\n", prxcap->additional_vsif_num);
889 printf("ifdb_present: %d\n", prxcap->ifdb_present);
890 /* for checkvalue which maybe used by application to adjust
891 * whether edid is changed
892 */
893 printf("checkvalue: %s\n", prxcap->hdmichecksum);
894
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800895}
896
897static int do_info(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
898{
899 struct hdmitx_dev *hdev = get_hdmitx21_device();
900 struct hdmi_format_para *para;
901
902 if (!hdev) {
903 pr_info("null hdmitx dev\n");
904 return CMD_RET_FAILURE;
905 }
906 if (!hdev->para) {
907 printf("null hdmitx para\n");
908 return CMD_RET_FAILURE;
909 }
910
911 para = hdev->para;
912 printf("current mode %s vic %d\n", para->timing.name, hdev->vic);
913 printf("cd%d cs%d cr%d\n", para->cd, para->cs, para->cr);
914 printf("enc_idx %d\n", hdev->enc_idx);
915 printf("frac_rate: %d\n", hdev->frac_rate_policy);
916 printf("Rx EDID info\n");
917 dump_full_edid(hdev->rawedid);
918 disp_cap_show(hdev);
919 vesa_cap_show(hdev);
920 aud_cap_show(hdev);
921 hdr_cap_show(hdev);
922 dv_cap_show(hdev);
923 dc_cap_show(hdev);
924 edid_cap_show(hdev);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800925 printf("dsc policy: %d, enable: %d\n", hdev->dsc_policy, hdev->dsc_en);
926 printf("frl_rate: %d\n", hdev->frl_rate);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800927 return 1;
928}
929
930static int xtochar(int num, char *checksum)
931{
932 struct hdmitx_dev *hdev = get_hdmitx21_device();
933
934 if (((hdev->rawedid[num] >> 4) & 0xf) <= 9)
935 checksum[0] = ((hdev->rawedid[num] >> 4) & 0xf) + '0';
936 else
937 checksum[0] = ((hdev->rawedid[num] >> 4) & 0xf) - 10 + 'a';
938
939 if ((hdev->rawedid[num] & 0xf) <= 9)
940 checksum[1] = (hdev->rawedid[num] & 0xf) + '0';
941 else
942 checksum[1] = (hdev->rawedid[num] & 0xf) - 10 + 'a';
943
944 return 0;
945}
946
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800947/* hdr_priority definition:
948 * strategy1: bit[3:0]
949 * 0: original cap
950 * 1: disable dolby vision cap
951 * 2: disable dolby vision and hdr/hlg cap
952 * strategy2:
953 * bit4: 1: disable dv 0:enable dv
954 * bit5: 1: disable hdr10/hdr10+ 0: enable hdr10/hdr10+
955 * bit6: 1: disable hlg 0: enable hlg
956 * bit28-bit31 choose strategy: bit[31:28]
957 * 0: strategy1
958 * 1: strategy2
959 */
960
961/* for uboot, there is no need to dynamically change the hdr_priority as
962 * kernel. So below functions only implement the disable_xxx_info() function,
963 * and leave the enable_xxx_info as blank
964 */
965
966/* dv_info */
967static void enable_dv_info(struct dv_info *des, const struct dv_info *src)
968{
969 if (!des || !src)
970 return;
971}
972
973static void disable_dv_info(struct dv_info *des)
974{
975 if (!des)
976 return;
977
978 memset(des, 0, sizeof(*des));
979}
980
981/* hdr10 */
982static void enable_hdr10_info(struct hdr_info *des, const struct hdr_info *src)
983{
984 if (!des || !src)
985 return;
986}
987
988static void disable_hdr10_info(struct hdr_info *des)
989{
990 if (!des)
991 return;
992
xiang.wu114497ab2024-02-21 14:57:05 +0800993 des->hdr_support = des->hdr_support & 0xB;
994 des->static_metadata_type1 = 0;
995 des->lumi_max = 0;
996 des->lumi_avg = 0;
997 des->lumi_min = 0;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800998}
999
1000/* hdr10plus */
1001static void enable_hdr10p_info(struct hdr10_plus_info *des, const struct hdr10_plus_info *src)
1002{
1003 if (!des || !src)
1004 return;
1005}
1006
1007static void disable_hdr10p_info(struct hdr10_plus_info *des)
1008{
1009 if (!des)
1010 return;
1011
1012 memset(des, 0, sizeof(*des));
1013}
1014
1015/* hlg */
1016static void enable_hlg_info(struct hdr_info *des, const struct hdr_info *src)
1017{
1018 if (!des || !src)
1019 return;
1020}
1021
1022static void disable_hlg_info(struct hdr_info *des)
1023{
1024 if (!des)
1025 return;
1026
xiang.wu114497ab2024-02-21 14:57:05 +08001027 des->hdr_support = des->hdr_support & 0x7;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001028}
1029
1030static void enable_all_hdr_info(struct rx_cap *prxcap)
1031{
1032 if (!prxcap)
1033 return;
1034}
1035
1036static void update_hdr_strategy1(struct rx_cap *prxcap, u32 strategy)
1037{
1038 if (!prxcap)
1039 return;
1040
1041 switch (strategy) {
1042 case 0:
1043 enable_all_hdr_info(prxcap);
1044 break;
1045 case 1:
1046 disable_dv_info(&prxcap->dv_info);
1047 break;
1048 case 2:
1049 disable_dv_info(&prxcap->dv_info);
1050 disable_hdr10_info(&prxcap->hdr_info);
xiang.wu114497ab2024-02-21 14:57:05 +08001051 disable_hdr10p_info(&prxcap->hdr_info.hdr10plus_info);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001052 disable_hlg_info(&prxcap->hdr_info);
1053 break;
1054 default:
1055 break;
1056 }
1057}
1058
1059static void update_hdr_strategy2(struct rx_cap *prxcap, u32 strategy)
1060{
1061 if (!prxcap)
1062 return;
1063
1064 /* bit4: 1 disable dv 0 enable dv */
1065 if (strategy & BIT(4))
1066 disable_dv_info(&prxcap->dv_info);
1067 else
1068 enable_dv_info(&prxcap->dv_info, NULL);
1069 /* bit5: 1 disable hdr10/hdr10+ 0 enable hdr10/hdr10+ */
1070 if (strategy & BIT(5)) {
1071 disable_hdr10_info(&prxcap->hdr_info);
xiang.wu114497ab2024-02-21 14:57:05 +08001072 disable_hdr10p_info(&prxcap->hdr_info.hdr10plus_info);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001073 } else {
1074 enable_hdr10_info(&prxcap->hdr_info, NULL);
xiang.wu114497ab2024-02-21 14:57:05 +08001075 enable_hdr10p_info(&prxcap->hdr_info.hdr10plus_info, NULL);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001076 }
1077 /* bit6: 1 disable hlg 0 enable hlg */
1078 if (strategy & BIT(6))
1079 disable_hlg_info(&prxcap->hdr_info);
1080 else
1081 enable_hlg_info(&prxcap->hdr_info, NULL);
1082}
1083
1084static int hdmitx_set_hdr_priority(struct rx_cap *prxcap, u32 hdr_priority)
1085{
1086 u32 choose = 0;
1087 u32 strategy = 0;
1088
1089 if (!prxcap)
1090 return -1;
1091
1092 printf("%s, set hdr_prio: %u\n", __func__, hdr_priority);
1093 /* choose strategy: bit[31:28] */
1094 choose = (hdr_priority >> 28) & 0xf;
1095 switch (choose) {
1096 case 0:
1097 strategy = hdr_priority & 0xf;
1098 update_hdr_strategy1(prxcap, strategy);
1099 break;
1100 case 1:
1101 strategy = hdr_priority & 0xf0;
1102 update_hdr_strategy2(prxcap, strategy);
1103 break;
1104 default:
1105 break;
1106 }
1107 return 0;
1108}
1109
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001110static void get_parse_edid_data(struct hdmitx_dev *hdev)
1111{
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001112 int hdr_priority = get_hdr_strategy_priority();
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001113
1114 hdev->hwop.read_edid(hdev->rawedid);
1115
ruofei.zhao4a2ec0c2023-10-31 19:24:41 +08001116 /* dump edid raw data */
1117 dump_full_edid(hdev->rawedid);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001118
1119 /* parse edid data */
xiang.wu114497ab2024-02-21 14:57:05 +08001120 hdmitx_edid_parse(&hdev->RXCap, hdev->rawedid);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001121
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001122 if (hdr_priority == -1)
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001123 return;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001124 hdmitx_set_hdr_priority(&hdev->RXCap, hdr_priority);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001125}
1126
1127/* policy process: to find the output mode/attr/dv_type */
1128void scene_process(struct hdmitx_dev *hdev,
1129 struct scene_output_info *scene_output_info)
1130{
1131 struct input_hdmi_data hdmidata;
1132
1133 if (!hdev || !scene_output_info)
1134 return;
1135 /* 1.read dolby vision mode from prop(maybe need to env) */
1136 memset(&hdmidata, 0, sizeof(struct input_hdmi_data));
1137 get_hdmi_data(hdev, &hdmidata);
1138
1139 /* 2. dolby vision scene process */
1140 /* only for tv support dv and box enable dv */
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001141 if (is_dv_preference(hdev)) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001142 dolbyvision_scene_process(&hdmidata, scene_output_info);
1143 } else if (is_dolby_enabled()) {
1144 /* for enable dolby vision core when
1145 * first boot connecting non dv tv
1146 * NOTE: let systemcontrol to enable DV core
1147 */
1148 /* scene_output_info->final_dv_type = DOLBY_VISION_ENABLE; */
1149 } else {
1150 /* for UI disable dolby vision core and boot keep the status
1151 * NOTE: TBD if need to disable DV here
1152 */
1153 /* scene_output_info->final_dv_type = DOLBY_VISION_DISABLE; */
1154 }
1155 /* 3.sdr scene process */
1156 /* decide final display mode and deepcolor */
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001157 if (is_dv_preference(hdev)) {
1158 /* do nothing
1159 * already done above, just sync with sysctrl
1160 */
1161 } else if (is_hdr_preference(hdev)) {
1162 hdr_scene_process(&hdmidata, scene_output_info);
1163 } else {
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001164 sdr_scene_process(&hdmidata, scene_output_info);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001165 }
1166 /* not find outputmode and use default mode */
1167 if (strlen(scene_output_info->final_displaymode) == 0)
1168 strcpy(scene_output_info->final_displaymode, DEFAULT_HDMI_MODE);
1169 /* not find color space and use default mode */
1170 if (!strstr(scene_output_info->final_deepcolor, "bit"))
1171 strcpy(scene_output_info->final_deepcolor, DEFAULT_COLOR_FORMAT);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001172}
1173
1174static int do_get_parse_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1175{
1176 struct hdmitx_dev *hdev = get_hdmitx21_device();
1177 unsigned char *edid = hdev->rawedid;
1178 unsigned char *store_checkvalue;
1179
xiang.wu114497ab2024-02-21 14:57:05 +08001180 memset(edid, 0, EDID_BLK_SIZE * EDID_MAX_BLOCK);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001181 unsigned int i;
1182 unsigned int checkvalue[4];
1183 unsigned int checkvalue1;
1184 unsigned int checkvalue2;
1185 char checksum[11];
1186 unsigned char def_cksum[] = {'0', 'x', '0', '0', '0', '0', '0', '0', '0', '0', '\0'};
1187 char *hdmimode;
1188 char *colorattribute;
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001189 int user_dv_mode;
1190 char *last_output_mode;
1191 char *last_colorattribute;
1192 int last_dv_status;
1193 bool over_write = false;
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001194 char dv_type[2] = {0};
1195 struct scene_output_info scene_output_info;
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001196 struct hdmi_format_para *para = NULL;
1197 bool mode_support = false;
1198 /* hdmi_mode / colorattribute may be null or "none".
1199 * if either is null or "none", it means user not
1200 * selected manually, and need to select the best
1201 * mode or colorattribute by policy
1202 */
1203 bool no_manual_output = false;
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001204
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001205 if (!hdev->hpd_state) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001206 printf("HDMI HPD low, no need parse EDID\n");
1207 return 1;
1208 }
1209 memset(&scene_output_info, 0, sizeof(struct scene_output_info));
1210
1211 get_parse_edid_data(hdev);
1212
1213 /* check if the tv has changed or anything wrong */
1214 store_checkvalue = (unsigned char *)env_get("hdmichecksum");
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001215 /* get user selected output mode/color */
1216 colorattribute = env_get("user_colorattribute");
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001217 hdmimode = env_get("hdmimode");
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001218 user_dv_mode = get_ubootenv_dv_type();
1219
1220 last_output_mode = env_get("outputmode");
1221 last_colorattribute = env_get("colorattribute");
1222 last_dv_status = get_ubootenv_dv_status();
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001223 if (!store_checkvalue)
1224 store_checkvalue = def_cksum;
1225
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001226 printf("read hdmichecksum: %s, user hdmimode: %s, colorattribute: %s, dv_type: %d\n",
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001227 store_checkvalue, hdmimode ? hdmimode : "null",
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001228 colorattribute ? colorattribute : "null", user_dv_mode);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001229
1230 for (i = 0; i < 4; i++) {
1231 if (('0' <= store_checkvalue[i * 2 + 2]) && (store_checkvalue[i * 2 + 2] <= '9'))
1232 checkvalue1 = store_checkvalue[i * 2 + 2] - '0';
1233 else
1234 checkvalue1 = store_checkvalue[i * 2 + 2] - 'W';
1235 if (('0' <= store_checkvalue[i * 2 + 3]) && (store_checkvalue[i * 2 + 3] <= '9'))
1236 checkvalue2 = store_checkvalue[i * 2 + 3] - '0';
1237 else
1238 checkvalue2 = store_checkvalue[i * 2 + 3] - 'W';
1239 checkvalue[i] = checkvalue1 * 16 + checkvalue2;
1240 }
1241
1242 if (checkvalue[0] != hdev->rawedid[0x7f] ||
1243 checkvalue[1] != hdev->rawedid[0xff] ||
1244 checkvalue[2] != hdev->rawedid[0x17f] ||
1245 checkvalue[3] != hdev->rawedid[0x1ff]) {
1246 hdev->RXCap.edid_changed = 1;
1247
1248 checksum[0] = '0';
1249 checksum[1] = 'x';
1250 for (i = 0; i < 4; i++)
1251 xtochar(0x80 * i + 0x7f, &checksum[2 * i + 2]);
1252 checksum[10] = '\0';
xiang.wu114497ab2024-02-21 14:57:05 +08001253 memcpy(hdev->RXCap.hdmichecksum, checksum, 10);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001254 printf("TV has changed, now crc: %s\n", checksum);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001255 } else {
xiang.wu114497ab2024-02-21 14:57:05 +08001256 memcpy(hdev->RXCap.hdmichecksum, store_checkvalue, 10);
1257 printf("TV is same, checksum: %s\n", hdev->RXCap.hdmichecksum);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001258 }
1259
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001260 /* check user have selected both mode/color or not */
1261 if (!hdmimode || !strcmp(hdmimode, "none") ||
1262 !colorattribute || !strcmp(colorattribute, "none"))
1263 no_manual_output = true;
1264 else
1265 no_manual_output = false;
1266
1267 if (!no_manual_output) {
1268 /* check current user selected mode + color support or not */
1269 para = hdmitx21_get_fmtpara(hdmimode, colorattribute);
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001270 if (hdmitx_edid_check_valid_mode(hdev, para)) {
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001271 mode_support = true;
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001272 } else {
1273 printf("saved output mode not supported!\n");
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001274 mode_support = false;
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001275 }
1276
1277 /* if user selected mode/color/dv type which saved in ubootenv of
1278 * hdmimode/user_colorattribute/user_prefer_dv_type are different
1279 * with last actual output mode/color/dv type which saved in
1280 * ubootenv of outputmode/colorattribute/dolby_status, then it means
1281 * that the user selected format is over-writen by policy(for example:
1282 * firstly user has selected HDR priority to HDR, and select color
1283 * to rgb,12bit(now the "user_colorattribute" env will be "rgb,12bit"),
1284 * but then it selected HDR priority to DV, the actual output color
1285 * will be "444,8bit" or "422,12bit" according to dv type, and
1286 * the ubootenv "colorattribute" will be "444,8bit" or "422,12bit"),
1287 * then uboot should use the policy to select the output format,
1288 * otherwise, uboot use hdmimode/user_colorattribute/user_prefer_dv_type
1289 * env, while system use outputmode/colorattribute/dolby_status env,
1290 * there will be always a mode change during bootup
1291 */
1292 if (mode_support) {
1293 /* note that for T7 multi-display, it may store panel in
1294 * "outputmode" env, and will always run uboot policy
1295 */
1296 if (!last_output_mode || strcmp(hdmimode, last_output_mode))
1297 over_write = true;
1298 else if (!last_colorattribute ||
1299 strcmp(colorattribute, last_colorattribute))
1300 over_write = true;
1301 else if (user_dv_mode != last_dv_status)
1302 over_write = true;
1303 else
1304 over_write = false;
1305
1306 if (over_write)
1307 printf("last output_mode:%s, colorattribute:%s, dolby_status:%d\n",
1308 last_output_mode ? last_output_mode : "null",
1309 last_colorattribute ? last_colorattribute : "null",
1310 last_dv_status);
1311 }
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001312 }
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001313 /* 4 cases need to decide output by uboot mode select policy:
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001314 * 1.TV changed
1315 * 2.either hdmimode or colorattribute is NULL or "none",
1316 * which means that user have not selected mode or colorattribute,
1317 * and need to select the auto best mode or best colorattribute.
1318 * 3.user selected mode not supportted by uboot (probably
1319 * means mode select policy or edid parse between sysctrl and
1320 * uboot have some gap), then need to find proper output mode
1321 * with uboot policy.
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001322 * 4.user selected mode is over writen by system policy
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001323 */
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001324 if (hdev->RXCap.edid_changed || no_manual_output || !mode_support || over_write) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001325 /* find proper mode if EDID changed */
1326 scene_process(hdev, &scene_output_info);
xiang.wu114497ab2024-02-21 14:57:05 +08001327 env_set("hdmichecksum", hdev->RXCap.hdmichecksum);
1328 if (hdmitx_edid_check_data_valid(0, hdev->rawedid)) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001329 /* SWPL-34712: if EDID parsing error case, not save env,
1330 * only output default mode(480p,RGB,8bit). after
1331 * EDID read OK, systemcontrol will recover the hdmi
1332 * mode from env, to avoid keep the default hdmi output
1333 */
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001334 memcpy(sel_hdmimode, scene_output_info.final_displaymode,
1335 sizeof(scene_output_info.final_displaymode));
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001336 if (is_hdmi_mode(env_get("outputmode"))) {
1337 env_set("outputmode",
1338 scene_output_info.final_displaymode);
1339 } else if (is_hdmi_mode(env_get("outputmode2"))) {
1340 env_set("outputmode2",
1341 scene_output_info.final_displaymode);
1342 } else if (is_hdmi_mode(env_get("outputmode3"))) {
1343 env_set("outputmode3",
1344 scene_output_info.final_displaymode);
1345 }
1346 env_set("colorattribute",
1347 scene_output_info.final_deepcolor);
1348 /* if change from DV TV to HDR/SDR TV, don't change
1349 * DV status to disabled, as DV core need to be enabled.
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001350 * that's to say connect DV TV & output DV-> power down box ->
1351 * connect HDR/SDR TV -> power on box, the dolby_status
1352 * will keep the same as that when connect DV TV under follow sink.
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001353 */
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001354 if (scene_output_info.final_dv_type != get_ubootenv_dv_status() &&
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001355 scene_output_info.final_dv_type != DOLBY_VISION_DISABLE) {
1356 sprintf(dv_type, "%d", scene_output_info.final_dv_type);
1357 env_set("dolby_status", dv_type);
1358 /* according to the policy of systemcontrol,
1359 * if current DV mode is not supported by TV
1360 * EDID, DV type maybe changed to one witch
1361 * TV support, and need VPP/DV module to
1362 * update new DV output mode.
1363 */
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001364 printf("update dolby_status: %d\n",
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001365 scene_output_info.final_dv_type);
1366 }
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001367 } else {
1368 save_default_720p();
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001369 }
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001370 printf("update outputmode: %s\n", sel_hdmimode);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001371 printf("update colorattribute: %s\n", env_get("colorattribute"));
1372 printf("update hdmichecksum: %s\n", env_get("hdmichecksum"));
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001373 } else {
1374 memset(sel_hdmimode, 0, sizeof(sel_hdmimode));
1375 memcpy(sel_hdmimode, hdmimode, strlen(hdmimode));
1376 if (is_hdmi_mode(env_get("outputmode")))
1377 env_set("outputmode", hdmimode);
1378 else if (is_hdmi_mode(env_get("outputmode2")))
1379 env_set("outputmode2", hdmimode);
1380 else if (is_hdmi_mode(env_get("outputmode3")))
1381 env_set("outputmode3", hdmimode);
1382 env_set("colorattribute", colorattribute);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001383 }
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001384 env_set("save_outputmode", sel_hdmimode);
1385 /* ubootenv dolby_status is used for is_dv_preference() decision,
1386 * system_control save current dv output status in it.
1387 * it will be used by dv module later to decide DV output later.
1388 * if currently adaptive hdr, then we should set dolby_status to
1389 * 0, so that DV module won't enable DV.
1390 */
1391 if (get_hdr_policy() == 1)
1392 env_set("dolby_status", 0);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001393 hdev->para = hdmitx21_get_fmtpara(sel_hdmimode, env_get("colorattribute"));
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001394 hdev->vic = hdev->para->timing.vic;
1395 hdmitx_mask_rx_info(hdev);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001396 hdmitx21_select_frl(hdev);
1397 return 0;
1398}
1399
1400static int do_dsc_policy(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1401{
1402 struct hdmitx_dev *hdev = get_hdmitx21_device();
1403
1404 if (argc < 1)
1405 return cmd_usage(cmdtp);
1406
1407 if (strcmp(argv[1], "0") == 0)
1408 hdev->dsc_policy = 0;
1409 else if (strcmp(argv[1], "1") == 0)
1410 hdev->dsc_policy = 1;
1411 else if (strcmp(argv[1], "2") == 0)
1412 hdev->dsc_policy = 2;
1413 else if (strcmp(argv[1], "3") == 0)
1414 hdev->dsc_policy = 3;
1415 else if (strcmp(argv[1], "4") == 0)
1416 hdev->dsc_policy = 4;
1417 else
1418 printf("note: please set dsc policy as 0~4\n");
1419 if (hdev->dsc_policy <= 4)
1420 printf("use dsc policy: %d\n", hdev->dsc_policy);
1421
1422 return CMD_RET_SUCCESS;
1423}
1424
1425static int do_manual_frl_rate(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1426{
1427 struct hdmitx_dev *hdev = get_hdmitx21_device();
1428 unsigned int temp = 0;
1429 char *ptr;
1430
1431 /* if rx don't support FRL, return */
1432 if (!hdev->RXCap.max_frl_rate) {
1433 printf("rx not support FRL\n");
1434 return 0;
1435 }
1436
1437 temp = strtoul(argv[1], &ptr, 16);
1438 /* forced FRL rate setting */
1439 if (temp <= 6) {
1440 hdev->manual_frl_rate = temp;
1441 pr_info("force set frl_rate as %d\n", hdev->manual_frl_rate);
1442 } else {
1443 pr_info("error: should set frl_rate in 0 ~ 6\n");
1444 }
1445 if (hdev->manual_frl_rate > hdev->RXCap.max_frl_rate)
1446 pr_info("warning: larger than rx max_frl_rate %d\n", hdev->RXCap.max_frl_rate);
1447 return 0;
1448}
1449
1450static int do_manual_dfm_type(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1451{
1452 struct hdmitx_dev *hdev = get_hdmitx21_device();
1453 unsigned int temp = 0;
1454 char *ptr;
1455
1456 temp = strtoul(argv[1], &ptr, 10);
1457 /* forced dfm_type setting */
1458 if (temp <= 2) {
1459 hdev->dfm_type = temp;
1460 pr_info("force set dfm_type as %d\n", hdev->dfm_type);
1461 } else {
1462 pr_info("error: should set frl_rate in 0 ~ 2\n");
1463 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001464 return 0;
1465}
1466
Wenjie Qiao77833902023-12-18 19:01:59 +08001467#ifdef CONFIG_EFUSE_OBJ_API
1468static int do_efuse_show(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1469{
1470 struct hdmitx_dev *hdev = get_hdmitx21_device();
1471
1472 get_hdmi_efuse(hdev);
1473 pr_info("FEAT_DISABLE_HDMI_60HZ = %d\n", hdev->efuse_dis_hdmi_4k60);
1474 pr_info("FEAT_DISABLE_OUTPUT_4K = %d\n", hdev->efuse_dis_output_4k);
1475 pr_info("FEAT_DISABLE_HDCP_TX_22 = %d\n", hdev->efuse_dis_hdcp_tx22);
1476 pr_info("FEAT_DISABLE_HDMI_TX_3D = %d\n", hdev->efuse_dis_hdmi_tx3d);
1477 pr_info("FEAT_DISABLE_HDMI = %d\n", hdev->efuse_dis_hdcp_tx14);
1478
1479 return 0;
1480}
1481#endif
1482
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001483static cmd_tbl_t cmd_hdmi_sub[] = {
1484 U_BOOT_CMD_MKENT(hpd, 1, 1, do_hpd_detect, "", ""),
1485 U_BOOT_CMD_MKENT(edid, 3, 1, do_edid, "", ""),
1486 U_BOOT_CMD_MKENT(rx_det, 1, 1, do_rx_det, "", ""),
1487 U_BOOT_CMD_MKENT(output, 3, 1, do_output, "", ""),
1488 U_BOOT_CMD_MKENT(clkmsr, 3, 1, do_clkmsr, "", ""),
1489 U_BOOT_CMD_MKENT(blank, 3, 1, do_blank, "", ""),
1490 U_BOOT_CMD_MKENT(off, 1, 1, do_off, "", ""),
1491 U_BOOT_CMD_MKENT(dump, 1, 1, do_dump, "", ""),
1492 U_BOOT_CMD_MKENT(info, 1, 1, do_info, "", ""),
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001493 U_BOOT_CMD_MKENT(reg, 3, 1, do_reg, "", ""),
1494 U_BOOT_CMD_MKENT(get_parse_edid, 1, 1, do_get_parse_edid, "", ""),
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001495 U_BOOT_CMD_MKENT(dsc_policy, 1, 1, do_dsc_policy, "", ""),
1496 U_BOOT_CMD_MKENT(frl_rate, 1, 1, do_manual_frl_rate, "", ""),
1497 U_BOOT_CMD_MKENT(dfm_type, 1, 1, do_manual_dfm_type, "", ""),
Wenjie Qiao77833902023-12-18 19:01:59 +08001498#ifdef CONFIG_EFUSE_OBJ_API
1499 U_BOOT_CMD_MKENT(efuse, 1, 1, do_efuse_show, "", ""),
1500#endif
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001501 U_BOOT_CMD_MKENT(pbist, 3, 1, do_pbist, "", ""),
1502 U_BOOT_CMD_MKENT(debug, 3, 1, do_debug, "", ""),
xiang.wu1492f3642024-01-08 14:06:40 +08001503 U_BOOT_CMD_MKENT(s7_clk_config, 3, 1, do_s7_clk_config, "", ""),
xiang.wu114497ab2024-02-21 14:57:05 +08001504 U_BOOT_CMD_MKENT(get_rterm, 3, 1, get_rterm, "", ""),
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001505};
1506
1507static int do_hdmitx(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1508{
1509 cmd_tbl_t *c;
1510
1511 if (argc < 2)
1512 return cmd_usage(cmdtp);
1513
1514 argc--;
1515 argv++;
1516
1517 c = find_cmd_tbl(argv[0], &cmd_hdmi_sub[0], ARRAY_SIZE(cmd_hdmi_sub));
1518
1519 if (c)
1520 return c->cmd(cmdtp, flag, argc, argv);
1521 else
1522 return cmd_usage(cmdtp);
1523}
1524
1525U_BOOT_CMD(hdmitx, CONFIG_SYS_MAXARGS, 0, do_hdmitx,
1526 "HDMITX sub-system",
1527 "hdmitx version:20200618\n"
1528 "hdmitx hpd\n"
1529 " Detect hdmi rx plug-in\n"
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001530 "hdmitx output [list | FORMAT | bist PATTERN]\n"
1531 " list: list support formats\n"
1532 " FORMAT can be 720p60/50hz, 1080i60/50hz, 1080p60hz, etc\n"
1533 " extend with 8bits/10bits, y444/y422/y420/rgb\n"
1534 " such as 2160p60hz,10bits,y420\n"
1535 " PATTERN: can be as: line, dot, off, or 1920(width)\n"
1536 "hdmitx blank [0|1]\n"
1537 " 1: output blank 0: output normal\n"
1538 "hdmitx clkmsr\n"
1539 " show hdmitx clocks\n"
1540 "hdmitx off\n"
1541 " Turn off hdmitx output\n"
1542 "hdmitx info\n"
1543 " current mode info\n"
1544 "hdmitx rx_det\n"
1545 " Auto detect if RX is FBC and set outputmode\n"
1546);
1547
1548struct hdr_info *hdmitx_get_rx_hdr_info(void)
1549{
1550 struct hdmitx_dev *hdev = get_hdmitx21_device();
1551
1552 return &hdev->RXCap.hdr_info;
1553}
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001554
1555static int do_list_dsc_mode(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1556{
1557#ifdef CONFIG_AML_DSC_ENC
1558 dsc_enc_cap_show();
1559#endif
1560 return 0;
1561}
1562
1563static int do_dsc_debug(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1564{
1565#ifdef CONFIG_AML_DSC_ENC
1566 dsc_debug(argc - 1, argv + 1);
1567#endif
1568 return 0;
1569}
1570
1571static cmd_tbl_t cmd_dsc_sub[] = {
1572 U_BOOT_CMD_MKENT(list_mode, 1, 1, do_list_dsc_mode, "", ""),
1573 U_BOOT_CMD_MKENT(dbg, 20, 1, do_dsc_debug, "", ""),
1574};
1575
1576static int do_dsc_enc(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1577{
1578 cmd_tbl_t *c;
1579
1580 if (argc < 2)
1581 return cmd_usage(cmdtp);
1582
1583 argc--;
1584 argv++;
1585
1586 c = find_cmd_tbl(argv[0], &cmd_dsc_sub[0], ARRAY_SIZE(cmd_dsc_sub));
1587
1588 if (c)
1589 return c->cmd(cmdtp, flag, argc, argv);
1590 else
1591 return cmd_usage(cmdtp);
1592}
1593
1594U_BOOT_CMD(dsc, CONFIG_SYS_MAXARGS, 0, do_dsc_enc,
1595 "dsc cmd",
1596 "dsc help function\n"
1597 "dsc dbg state\n"
1598 " dump dsc status\n"
1599 "dsc dbg dump_reg\n"
1600 " dump dsc registers and venc registers\n"
1601 "dsc dbg read addr\n"
1602 " read dsc asic register\n"
1603 "dsc dbg write addr value\n"
1604 " write dsc asic register\n"
1605 "dsc dbg rst_dsc\n"
1606 " reset dsc enc\n"
1607 "dsc list_mode\n"
1608 " show supported dsc encode mode list\n"
1609);
1610