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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Lei Wenaf62a552011-06-28 21:50:06 +00002/*
3 * Copyright 2011, Marvell Semiconductor Inc.
4 * Lei Wen <leiwen@marvell.com>
5 *
Lei Wenaf62a552011-06-28 21:50:06 +00006 * Back ported to the 8xx platform (from the 8260 platform) by
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
8 */
9
10#include <common.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070011#include <cpu_func.h>
Faiz Abbas3d296362019-06-11 00:43:34 +053012#include <dm.h>
Simon Glass2a809092016-06-12 23:30:27 -060013#include <errno.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060014#include <log.h>
Lei Wenaf62a552011-06-28 21:50:06 +000015#include <malloc.h>
16#include <mmc.h>
17#include <sdhci.h>
Simon Glass90526e92020-05-10 11:39:56 -060018#include <asm/cache.h>
Simon Glasscd93d622020-05-10 11:40:13 -060019#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060020#include <linux/delay.h>
Masahiro Yamada58d8ace2020-02-14 16:40:26 +090021#include <linux/dma-mapping.h>
Jaehoon Chungfac8bfd2020-03-27 13:08:00 +090022#include <phys2bus.h>
Faiz Abbas43392b52021-02-04 15:10:46 +053023#include <power/regulator.h>
Lei Wenaf62a552011-06-28 21:50:06 +000024
Lei Wenaf62a552011-06-28 21:50:06 +000025static void sdhci_reset(struct sdhci_host *host, u8 mask)
26{
27 unsigned long timeout;
28
29 /* Wait max 100 ms */
30 timeout = 100;
31 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
32 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
33 if (timeout == 0) {
Darwin Rambo30e6d972013-12-19 15:13:25 -080034 printf("%s: Reset 0x%x never completed.\n",
35 __func__, (int)mask);
Lei Wenaf62a552011-06-28 21:50:06 +000036 return;
37 }
38 timeout--;
39 udelay(1000);
40 }
41}
42
43static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
44{
45 int i;
46 if (cmd->resp_type & MMC_RSP_136) {
47 /* CRC is stripped so we need to do some shifting. */
48 for (i = 0; i < 4; i++) {
49 cmd->response[i] = sdhci_readl(host,
50 SDHCI_RESPONSE + (3-i)*4) << 8;
51 if (i != 3)
52 cmd->response[i] |= sdhci_readb(host,
53 SDHCI_RESPONSE + (3-i)*4-1);
54 }
55 } else {
56 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
57 }
58}
59
60static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
61{
62 int i;
63 char *offs;
64 for (i = 0; i < data->blocksize; i += 4) {
65 offs = data->dest + i;
66 if (data->flags == MMC_DATA_READ)
67 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
68 else
69 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
70 }
71}
Faiz Abbas37cb6262019-04-16 23:06:58 +053072
Faiz Abbas37cb6262019-04-16 23:06:58 +053073#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
Faiz Abbas6d6af202019-04-16 23:06:57 +053074static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
75 int *is_aligned, int trans_bytes)
76{
Nicolas Saenz Juliennec89c96d2021-01-12 13:55:29 +010077 dma_addr_t dma_addr;
Jaehoon Chung804c7f42012-09-20 20:31:55 +000078 unsigned char ctrl;
Masahiro Yamada58d8ace2020-02-14 16:40:26 +090079 void *buf;
Faiz Abbas6d6af202019-04-16 23:06:57 +053080
81 if (data->flags == MMC_DATA_READ)
Masahiro Yamada58d8ace2020-02-14 16:40:26 +090082 buf = data->dest;
Faiz Abbas6d6af202019-04-16 23:06:57 +053083 else
Masahiro Yamada58d8ace2020-02-14 16:40:26 +090084 buf = (void *)data->src;
Faiz Abbas6d6af202019-04-16 23:06:57 +053085
Faiz Abbas37cb6262019-04-16 23:06:58 +053086 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
87 ctrl &= ~SDHCI_CTRL_DMA_MASK;
88 if (host->flags & USE_ADMA64)
89 ctrl |= SDHCI_CTRL_ADMA64;
90 else if (host->flags & USE_ADMA)
91 ctrl |= SDHCI_CTRL_ADMA32;
92 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
93
Masahiro Yamada58d8ace2020-02-14 16:40:26 +090094 if (host->flags & USE_SDMA &&
95 (host->force_align_buffer ||
96 (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
97 ((unsigned long)buf & 0x7) != 0x0))) {
98 *is_aligned = 0;
99 if (data->flags != MMC_DATA_READ)
100 memcpy(host->align_buffer, buf, trans_bytes);
101 buf = host->align_buffer;
102 }
103
104 host->start_addr = dma_map_single(buf, trans_bytes,
105 mmc_get_dma_dir(data));
106
Faiz Abbas37cb6262019-04-16 23:06:58 +0530107 if (host->flags & USE_SDMA) {
Nicolas Saenz Juliennec89c96d2021-01-12 13:55:29 +0100108 dma_addr = dev_phys_to_bus(mmc_to_dev(host->mmc), host->start_addr);
109 sdhci_writel(host, dma_addr, SDHCI_DMA_ADDRESS);
Michael Walle4d6a7732020-09-23 12:42:51 +0200110 }
111#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
112 else if (host->flags & (USE_ADMA | USE_ADMA64)) {
113 sdhci_prepare_adma_table(host->adma_desc_table, data,
114 host->start_addr);
Faiz Abbas37cb6262019-04-16 23:06:58 +0530115
Masahiro Yamadaa2b02212020-02-14 16:40:23 +0900116 sdhci_writel(host, lower_32_bits(host->adma_addr),
117 SDHCI_ADMA_ADDRESS);
Faiz Abbas37cb6262019-04-16 23:06:58 +0530118 if (host->flags & USE_ADMA64)
Masahiro Yamadaa2b02212020-02-14 16:40:23 +0900119 sdhci_writel(host, upper_32_bits(host->adma_addr),
Faiz Abbas37cb6262019-04-16 23:06:58 +0530120 SDHCI_ADMA_ADDRESS_HI);
Faiz Abbas6d6af202019-04-16 23:06:57 +0530121 }
Michael Walle4d6a7732020-09-23 12:42:51 +0200122#endif
Faiz Abbas6d6af202019-04-16 23:06:57 +0530123}
124#else
125static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
126 int *is_aligned, int trans_bytes)
127{}
128#endif
129static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
130{
131 dma_addr_t start_addr = host->start_addr;
132 unsigned int stat, rdy, mask, timeout, block = 0;
133 bool transfer_done = false;
Lei Wenaf62a552011-06-28 21:50:06 +0000134
Jaehoon Chung5d48e422012-09-20 20:31:54 +0000135 timeout = 1000000;
Lei Wenaf62a552011-06-28 21:50:06 +0000136 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
137 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
138 do {
139 stat = sdhci_readl(host, SDHCI_INT_STATUS);
140 if (stat & SDHCI_INT_ERROR) {
Masahiro Yamada61f2e5e2017-12-30 02:00:12 +0900141 pr_debug("%s: Error detected in status(0x%X)!\n",
142 __func__, stat);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900143 return -EIO;
Lei Wenaf62a552011-06-28 21:50:06 +0000144 }
Alex Deymo7dde50d2017-04-02 01:24:34 -0700145 if (!transfer_done && (stat & rdy)) {
Lei Wenaf62a552011-06-28 21:50:06 +0000146 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
147 continue;
148 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
149 sdhci_transfer_pio(host, data);
150 data->dest += data->blocksize;
Alex Deymo7dde50d2017-04-02 01:24:34 -0700151 if (++block >= data->blocks) {
152 /* Keep looping until the SDHCI_INT_DATA_END is
153 * cleared, even if we finished sending all the
154 * blocks.
155 */
156 transfer_done = true;
157 continue;
158 }
Lei Wenaf62a552011-06-28 21:50:06 +0000159 }
Faiz Abbas37cb6262019-04-16 23:06:58 +0530160 if ((host->flags & USE_DMA) && !transfer_done &&
Faiz Abbas6d6af202019-04-16 23:06:57 +0530161 (stat & SDHCI_INT_DMA_END)) {
Lei Wenaf62a552011-06-28 21:50:06 +0000162 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
Faiz Abbas37cb6262019-04-16 23:06:58 +0530163 if (host->flags & USE_SDMA) {
164 start_addr &=
165 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
166 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
Nicolas Saenz Juliennec89c96d2021-01-12 13:55:29 +0100167 start_addr = dev_phys_to_bus(mmc_to_dev(host->mmc),
168 start_addr);
169 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
Faiz Abbas37cb6262019-04-16 23:06:58 +0530170 }
Lei Wenaf62a552011-06-28 21:50:06 +0000171 }
Lei Wena004abd2011-10-08 04:14:57 +0000172 if (timeout-- > 0)
173 udelay(10);
174 else {
Darwin Rambo30e6d972013-12-19 15:13:25 -0800175 printf("%s: Transfer data timeout\n", __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900176 return -ETIMEDOUT;
Lei Wena004abd2011-10-08 04:14:57 +0000177 }
Lei Wenaf62a552011-06-28 21:50:06 +0000178 } while (!(stat & SDHCI_INT_DATA_END));
Masahiro Yamada4155ad92020-02-14 16:40:27 +0900179
180 dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
181 mmc_get_dma_dir(data));
182
Lei Wenaf62a552011-06-28 21:50:06 +0000183 return 0;
184}
185
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200186/*
187 * No command will be sent by driver if card is busy, so driver must wait
188 * for card ready state.
189 * Every time when card is busy after timeout then (last) timeout value will be
190 * increased twice but only if it doesn't exceed global defined maximum.
Masahiro Yamada65a25b22016-08-25 16:07:39 +0900191 * Each function call will use last timeout value.
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200192 */
Masahiro Yamada65a25b22016-08-25 16:07:39 +0900193#define SDHCI_CMD_MAX_TIMEOUT 3200
Masahiro Yamadad8ce77b2016-08-25 16:07:38 +0900194#define SDHCI_CMD_DEFAULT_TIMEOUT 100
Steve Raed90bb432016-06-29 13:42:01 -0700195#define SDHCI_READ_STATUS_TIMEOUT 1000
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200196
Simon Glasse7881d82017-07-29 11:35:31 -0600197#ifdef CONFIG_DM_MMC
Simon Glassef1e4ed2016-06-12 23:30:28 -0600198static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
199 struct mmc_data *data)
Lei Wenaf62a552011-06-28 21:50:06 +0000200{
Simon Glassef1e4ed2016-06-12 23:30:28 -0600201 struct mmc *mmc = mmc_get_mmc_dev(dev);
202
203#else
204static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
205 struct mmc_data *data)
206{
207#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200208 struct sdhci_host *host = mmc->priv;
Lei Wenaf62a552011-06-28 21:50:06 +0000209 unsigned int stat = 0;
210 int ret = 0;
211 int trans_bytes = 0, is_aligned = 1;
212 u32 mask, flags, mode;
Faiz Abbas6d6af202019-04-16 23:06:57 +0530213 unsigned int time = 0;
Simon Glass19d2e342016-05-14 14:03:04 -0600214 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
Vipul Kumar36332b62018-05-03 12:20:54 +0530215 ulong start = get_timer(0);
Lei Wenaf62a552011-06-28 21:50:06 +0000216
Faiz Abbas6d6af202019-04-16 23:06:57 +0530217 host->start_addr = 0;
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200218 /* Timeout unit - ms */
Masahiro Yamadad8ce77b2016-08-25 16:07:38 +0900219 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
Lei Wenaf62a552011-06-28 21:50:06 +0000220
Lei Wenaf62a552011-06-28 21:50:06 +0000221 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
222
223 /* We shouldn't wait for data inihibit for stop commands, even
224 though they might use busy signaling */
Siva Durga Prasad Paladugub88a7a42018-04-19 12:37:05 +0530225 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
Siva Durga Prasad Paladugu1a7414f2018-06-13 11:43:01 +0530226 ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
227 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
Lei Wenaf62a552011-06-28 21:50:06 +0000228 mask &= ~SDHCI_DATA_INHIBIT;
229
230 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200231 if (time >= cmd_timeout) {
Darwin Rambo30e6d972013-12-19 15:13:25 -0800232 printf("%s: MMC: %d busy ", __func__, mmc_dev);
Masahiro Yamada65a25b22016-08-25 16:07:39 +0900233 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200234 cmd_timeout += cmd_timeout;
235 printf("timeout increasing to: %u ms.\n",
236 cmd_timeout);
237 } else {
238 puts("timeout.\n");
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900239 return -ECOMM;
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200240 }
Lei Wenaf62a552011-06-28 21:50:06 +0000241 }
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200242 time++;
Lei Wenaf62a552011-06-28 21:50:06 +0000243 udelay(1000);
244 }
245
Jorge Ramirez-Ortiz713e6812017-11-02 15:10:21 +0100246 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
247
Lei Wenaf62a552011-06-28 21:50:06 +0000248 mask = SDHCI_INT_RESPONSE;
Siva Durga Prasad Paladugu1a7414f2018-06-13 11:43:01 +0530249 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
250 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
Siva Durga Prasad Paladugub88a7a42018-04-19 12:37:05 +0530251 mask = SDHCI_INT_DATA_AVAIL;
252
Lei Wenaf62a552011-06-28 21:50:06 +0000253 if (!(cmd->resp_type & MMC_RSP_PRESENT))
254 flags = SDHCI_CMD_RESP_NONE;
255 else if (cmd->resp_type & MMC_RSP_136)
256 flags = SDHCI_CMD_RESP_LONG;
257 else if (cmd->resp_type & MMC_RSP_BUSY) {
258 flags = SDHCI_CMD_RESP_SHORT_BUSY;
Jaehoon Chung17ea3c82016-07-12 21:18:46 +0900259 if (data)
260 mask |= SDHCI_INT_DATA_END;
Lei Wenaf62a552011-06-28 21:50:06 +0000261 } else
262 flags = SDHCI_CMD_RESP_SHORT;
263
264 if (cmd->resp_type & MMC_RSP_CRC)
265 flags |= SDHCI_CMD_CRC;
266 if (cmd->resp_type & MMC_RSP_OPCODE)
267 flags |= SDHCI_CMD_INDEX;
Siva Durga Prasad Paladugu434f9d42018-05-29 20:03:10 +0530268 if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
269 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
Lei Wenaf62a552011-06-28 21:50:06 +0000270 flags |= SDHCI_CMD_DATA;
271
Darwin Rambo30e6d972013-12-19 15:13:25 -0800272 /* Set Transfer mode regarding to data flag */
Heinrich Schuchardtbb7b4ef2017-11-10 21:13:34 +0100273 if (data) {
Lei Wenaf62a552011-06-28 21:50:06 +0000274 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
275 mode = SDHCI_TRNS_BLK_CNT_EN;
276 trans_bytes = data->blocks * data->blocksize;
277 if (data->blocks > 1)
278 mode |= SDHCI_TRNS_MULTI;
279
280 if (data->flags == MMC_DATA_READ)
281 mode |= SDHCI_TRNS_READ;
282
Faiz Abbas37cb6262019-04-16 23:06:58 +0530283 if (host->flags & USE_DMA) {
Faiz Abbas6d6af202019-04-16 23:06:57 +0530284 mode |= SDHCI_TRNS_DMA;
285 sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
Lei Wenaf62a552011-06-28 21:50:06 +0000286 }
287
Lei Wenaf62a552011-06-28 21:50:06 +0000288 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
289 data->blocksize),
290 SDHCI_BLOCK_SIZE);
291 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
292 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
Kevin Liu5e1c23c2015-03-23 17:57:00 -0500293 } else if (cmd->resp_type & MMC_RSP_BUSY) {
294 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
Lei Wenaf62a552011-06-28 21:50:06 +0000295 }
296
297 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
Lei Wenaf62a552011-06-28 21:50:06 +0000298 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
Stefan Roese29905a42015-06-29 14:58:08 +0200299 start = get_timer(0);
Lei Wenaf62a552011-06-28 21:50:06 +0000300 do {
301 stat = sdhci_readl(host, SDHCI_INT_STATUS);
302 if (stat & SDHCI_INT_ERROR)
303 break;
Lei Wenaf62a552011-06-28 21:50:06 +0000304
Masahiro Yamadabae4a1f2016-07-10 00:40:22 +0900305 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
306 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
307 return 0;
308 } else {
309 printf("%s: Timeout for status update!\n",
310 __func__);
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900311 return -ETIMEDOUT;
Masahiro Yamadabae4a1f2016-07-10 00:40:22 +0900312 }
Jaehoon Chung3a638322012-04-23 02:36:25 +0000313 }
Masahiro Yamadabae4a1f2016-07-10 00:40:22 +0900314 } while ((stat & mask) != mask);
Jaehoon Chung3a638322012-04-23 02:36:25 +0000315
Lei Wenaf62a552011-06-28 21:50:06 +0000316 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
317 sdhci_cmd_done(host, cmd);
318 sdhci_writel(host, mask, SDHCI_INT_STATUS);
319 } else
320 ret = -1;
321
322 if (!ret && data)
Faiz Abbas6d6af202019-04-16 23:06:57 +0530323 ret = sdhci_transfer_data(host, data);
Lei Wenaf62a552011-06-28 21:50:06 +0000324
Tushar Behera13243f22012-09-20 20:31:57 +0000325 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
326 udelay(1000);
327
Lei Wenaf62a552011-06-28 21:50:06 +0000328 stat = sdhci_readl(host, SDHCI_INT_STATUS);
329 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
330 if (!ret) {
331 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
332 !is_aligned && (data->flags == MMC_DATA_READ))
Masahiro Yamadac8cc18b2020-02-14 16:40:21 +0900333 memcpy(data->dest, host->align_buffer, trans_bytes);
Lei Wenaf62a552011-06-28 21:50:06 +0000334 return 0;
335 }
336
337 sdhci_reset(host, SDHCI_RESET_CMD);
338 sdhci_reset(host, SDHCI_RESET_DATA);
339 if (stat & SDHCI_INT_TIMEOUT)
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900340 return -ETIMEDOUT;
Lei Wenaf62a552011-06-28 21:50:06 +0000341 else
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900342 return -ECOMM;
Lei Wenaf62a552011-06-28 21:50:06 +0000343}
344
Siva Durga Prasad Paladuguca992e82018-04-19 12:37:07 +0530345#if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
346static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
347{
348 int err;
349 struct mmc *mmc = mmc_get_mmc_dev(dev);
350 struct sdhci_host *host = mmc->priv;
351
352 debug("%s\n", __func__);
353
Ramon Friedb70fe962018-05-14 15:02:30 +0300354 if (host->ops && host->ops->platform_execute_tuning) {
Siva Durga Prasad Paladuguca992e82018-04-19 12:37:07 +0530355 err = host->ops->platform_execute_tuning(mmc, opcode);
356 if (err)
357 return err;
358 return 0;
359 }
360 return 0;
361}
362#endif
Faiz Abbas3966c7d2019-06-11 00:43:35 +0530363int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
Lei Wenaf62a552011-06-28 21:50:06 +0000364{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200365 struct sdhci_host *host = mmc->priv;
Stefan Roese899fb9e2016-12-12 08:34:42 +0100366 unsigned int div, clk = 0, timeout;
Lei Wenaf62a552011-06-28 21:50:06 +0000367
Wenyou Yang79667b72015-09-22 14:59:25 +0800368 /* Wait max 20 ms */
369 timeout = 200;
370 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
371 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
372 if (timeout == 0) {
373 printf("%s: Timeout to wait cmd & data inhibit\n",
374 __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900375 return -EBUSY;
Wenyou Yang79667b72015-09-22 14:59:25 +0800376 }
377
378 timeout--;
379 udelay(100);
380 }
381
Stefan Roese899fb9e2016-12-12 08:34:42 +0100382 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
Lei Wenaf62a552011-06-28 21:50:06 +0000383
384 if (clock == 0)
385 return 0;
386
Ramon Friedb70fe962018-05-14 15:02:30 +0300387 if (host->ops && host->ops->set_delay)
Siva Durga Prasad Paladuguca992e82018-04-19 12:37:07 +0530388 host->ops->set_delay(host);
389
Jaehoon Chung113e5df2013-07-19 17:44:49 +0900390 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800391 /*
392 * Check if the Host Controller supports Programmable Clock
393 * Mode.
394 */
395 if (host->clk_mul) {
396 for (div = 1; div <= 1024; div++) {
Wenyou Yang0e0dcc12017-04-26 09:32:30 +0800397 if ((host->max_clk / div) <= clock)
Lei Wenaf62a552011-06-28 21:50:06 +0000398 break;
399 }
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800400
401 /*
402 * Set Programmable Clock Mode in the Clock
403 * Control register.
404 */
405 clk = SDHCI_PROG_CLOCK_MODE;
406 div--;
407 } else {
408 /* Version 3.00 divisors must be a multiple of 2. */
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100409 if (host->max_clk <= clock) {
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800410 div = 1;
411 } else {
412 for (div = 2;
413 div < SDHCI_MAX_DIV_SPEC_300;
414 div += 2) {
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100415 if ((host->max_clk / div) <= clock)
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800416 break;
417 }
418 }
419 div >>= 1;
Lei Wenaf62a552011-06-28 21:50:06 +0000420 }
421 } else {
422 /* Version 2.00 divisors must be a power of 2. */
423 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100424 if ((host->max_clk / div) <= clock)
Lei Wenaf62a552011-06-28 21:50:06 +0000425 break;
426 }
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800427 div >>= 1;
Lei Wenaf62a552011-06-28 21:50:06 +0000428 }
Lei Wenaf62a552011-06-28 21:50:06 +0000429
Masahiro Yamadabf9c4d12017-01-13 11:51:51 +0900430 if (host->ops && host->ops->set_clock)
Jaehoon Chung62226b62016-12-30 15:30:18 +0900431 host->ops->set_clock(host, div);
Jaehoon Chungb09ed6e2012-08-30 16:24:11 +0000432
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800433 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
Lei Wenaf62a552011-06-28 21:50:06 +0000434 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
435 << SDHCI_DIVIDER_HI_SHIFT;
436 clk |= SDHCI_CLOCK_INT_EN;
437 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
438
439 /* Wait max 20 ms */
440 timeout = 20;
441 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
442 & SDHCI_CLOCK_INT_STABLE)) {
443 if (timeout == 0) {
Darwin Rambo30e6d972013-12-19 15:13:25 -0800444 printf("%s: Internal clock never stabilised.\n",
445 __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900446 return -EBUSY;
Lei Wenaf62a552011-06-28 21:50:06 +0000447 }
448 timeout--;
449 udelay(1000);
450 }
451
452 clk |= SDHCI_CLOCK_CARD_EN;
453 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
454 return 0;
455}
456
457static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
458{
459 u8 pwr = 0;
460
461 if (power != (unsigned short)-1) {
462 switch (1 << power) {
463 case MMC_VDD_165_195:
464 pwr = SDHCI_POWER_180;
465 break;
466 case MMC_VDD_29_30:
467 case MMC_VDD_30_31:
468 pwr = SDHCI_POWER_300;
469 break;
470 case MMC_VDD_32_33:
471 case MMC_VDD_33_34:
472 pwr = SDHCI_POWER_330;
473 break;
474 }
475 }
476
477 if (pwr == 0) {
478 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
479 return;
480 }
481
482 pwr |= SDHCI_POWER_ON;
483
484 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
485}
486
Faiz Abbasd1c0a222019-06-11 00:43:40 +0530487void sdhci_set_uhs_timing(struct sdhci_host *host)
488{
Masahiro Yamadafdd84c82020-02-14 16:40:24 +0900489 struct mmc *mmc = host->mmc;
Faiz Abbasd1c0a222019-06-11 00:43:40 +0530490 u32 reg;
491
492 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
493 reg &= ~SDHCI_CTRL_UHS_MASK;
494
495 switch (mmc->selected_mode) {
496 case UHS_SDR50:
497 case MMC_HS_52:
498 reg |= SDHCI_CTRL_UHS_SDR50;
499 break;
500 case UHS_DDR50:
501 case MMC_DDR_52:
502 reg |= SDHCI_CTRL_UHS_DDR50;
503 break;
504 case UHS_SDR104:
505 case MMC_HS_200:
506 reg |= SDHCI_CTRL_UHS_SDR104;
507 break;
508 default:
509 reg |= SDHCI_CTRL_UHS_SDR12;
510 }
511
512 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
513}
514
Faiz Abbas43392b52021-02-04 15:10:46 +0530515static void sdhci_set_voltage(struct sdhci_host *host)
516{
517 if (IS_ENABLED(CONFIG_MMC_IO_VOLTAGE)) {
518 struct mmc *mmc = (struct mmc *)host->mmc;
519 u32 ctrl;
520
521 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
522
523 switch (mmc->signal_voltage) {
524 case MMC_SIGNAL_VOLTAGE_330:
525#if CONFIG_IS_ENABLED(DM_REGULATOR)
526 if (mmc->vqmmc_supply) {
527 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
528 pr_err("failed to disable vqmmc-supply\n");
529 return;
530 }
531
532 if (regulator_set_value(mmc->vqmmc_supply, 3300000)) {
533 pr_err("failed to set vqmmc-voltage to 3.3V\n");
534 return;
535 }
536
537 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
538 pr_err("failed to enable vqmmc-supply\n");
539 return;
540 }
541 }
542#endif
543 if (IS_SD(mmc)) {
544 ctrl &= ~SDHCI_CTRL_VDD_180;
545 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
546 }
547
548 /* Wait for 5ms */
549 mdelay(5);
550
551 /* 3.3V regulator output should be stable within 5 ms */
552 if (IS_SD(mmc)) {
553 if (ctrl & SDHCI_CTRL_VDD_180) {
554 pr_err("3.3V regulator output did not become stable\n");
555 return;
556 }
557 }
558
559 break;
560 case MMC_SIGNAL_VOLTAGE_180:
561#if CONFIG_IS_ENABLED(DM_REGULATOR)
562 if (mmc->vqmmc_supply) {
563 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
564 pr_err("failed to disable vqmmc-supply\n");
565 return;
566 }
567
568 if (regulator_set_value(mmc->vqmmc_supply, 1800000)) {
569 pr_err("failed to set vqmmc-voltage to 1.8V\n");
570 return;
571 }
572
573 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
574 pr_err("failed to enable vqmmc-supply\n");
575 return;
576 }
577 }
578#endif
579 if (IS_SD(mmc)) {
580 ctrl |= SDHCI_CTRL_VDD_180;
581 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
582 }
583
584 /* Wait for 5 ms */
585 mdelay(5);
586
587 /* 1.8V regulator output has to be stable within 5 ms */
588 if (IS_SD(mmc)) {
589 if (!(ctrl & SDHCI_CTRL_VDD_180)) {
590 pr_err("1.8V regulator output did not become stable\n");
591 return;
592 }
593 }
594
595 break;
596 default:
597 /* No signal voltage switch required */
598 return;
599 }
600 }
601}
602
603void sdhci_set_control_reg(struct sdhci_host *host)
604{
605 sdhci_set_voltage(host);
606 sdhci_set_uhs_timing(host);
607}
608
Simon Glasse7881d82017-07-29 11:35:31 -0600609#ifdef CONFIG_DM_MMC
Simon Glassef1e4ed2016-06-12 23:30:28 -0600610static int sdhci_set_ios(struct udevice *dev)
611{
612 struct mmc *mmc = mmc_get_mmc_dev(dev);
613#else
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900614static int sdhci_set_ios(struct mmc *mmc)
Lei Wenaf62a552011-06-28 21:50:06 +0000615{
Simon Glassef1e4ed2016-06-12 23:30:28 -0600616#endif
Lei Wenaf62a552011-06-28 21:50:06 +0000617 u32 ctrl;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200618 struct sdhci_host *host = mmc->priv;
Jagan Tekif12341a2020-06-18 19:33:12 +0530619 bool no_hispd_bit = false;
Lei Wenaf62a552011-06-28 21:50:06 +0000620
Masahiro Yamadabf9c4d12017-01-13 11:51:51 +0900621 if (host->ops && host->ops->set_control_reg)
Jaehoon Chung62226b62016-12-30 15:30:18 +0900622 host->ops->set_control_reg(host);
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000623
Lei Wenaf62a552011-06-28 21:50:06 +0000624 if (mmc->clock != host->clock)
625 sdhci_set_clock(mmc, mmc->clock);
626
Siva Durga Prasad Paladugu2a2d7ef2018-04-19 12:37:04 +0530627 if (mmc->clk_disable)
628 sdhci_set_clock(mmc, 0);
629
Lei Wenaf62a552011-06-28 21:50:06 +0000630 /* Set bus width */
631 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
632 if (mmc->bus_width == 8) {
633 ctrl &= ~SDHCI_CTRL_4BITBUS;
Jaehoon Chung113e5df2013-07-19 17:44:49 +0900634 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
635 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
Lei Wenaf62a552011-06-28 21:50:06 +0000636 ctrl |= SDHCI_CTRL_8BITBUS;
637 } else {
Matt Reimerf88a4292015-02-19 11:22:53 -0700638 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
639 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
Lei Wenaf62a552011-06-28 21:50:06 +0000640 ctrl &= ~SDHCI_CTRL_8BITBUS;
641 if (mmc->bus_width == 4)
642 ctrl |= SDHCI_CTRL_4BITBUS;
643 else
644 ctrl &= ~SDHCI_CTRL_4BITBUS;
645 }
646
Hannes Schmelzer88a57122018-03-07 08:00:56 +0100647 if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
Jagan Tekif12341a2020-06-18 19:33:12 +0530648 (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) {
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000649 ctrl &= ~SDHCI_CTRL_HISPD;
Jagan Tekif12341a2020-06-18 19:33:12 +0530650 no_hispd_bit = true;
651 }
652
653 if (!no_hispd_bit) {
654 if (mmc->selected_mode == MMC_HS ||
655 mmc->selected_mode == SD_HS ||
656 mmc->selected_mode == MMC_DDR_52 ||
657 mmc->selected_mode == MMC_HS_200 ||
658 mmc->selected_mode == MMC_HS_400 ||
659 mmc->selected_mode == UHS_SDR25 ||
660 mmc->selected_mode == UHS_SDR50 ||
661 mmc->selected_mode == UHS_SDR104 ||
662 mmc->selected_mode == UHS_DDR50)
663 ctrl |= SDHCI_CTRL_HISPD;
664 else
665 ctrl &= ~SDHCI_CTRL_HISPD;
666 }
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000667
Lei Wenaf62a552011-06-28 21:50:06 +0000668 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900669
Stefan Roese210841c2016-12-12 08:24:56 +0100670 /* If available, call the driver specific "post" set_ios() function */
671 if (host->ops && host->ops->set_ios_post)
Faiz Abbasa8185c52019-06-11 00:43:37 +0530672 return host->ops->set_ios_post(host);
Stefan Roese210841c2016-12-12 08:24:56 +0100673
Simon Glassef1e4ed2016-06-12 23:30:28 -0600674 return 0;
Lei Wenaf62a552011-06-28 21:50:06 +0000675}
676
Jeroen Hofstee6588c782014-10-08 22:57:43 +0200677static int sdhci_init(struct mmc *mmc)
Lei Wenaf62a552011-06-28 21:50:06 +0000678{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200679 struct sdhci_host *host = mmc->priv;
T Karthik Reddy451931e2019-06-25 13:39:03 +0200680#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
681 struct udevice *dev = mmc->dev;
682
Baruch Siach58d65d52019-07-22 19:14:06 +0300683 gpio_request_by_name(dev, "cd-gpios", 0,
T Karthik Reddy451931e2019-06-25 13:39:03 +0200684 &host->cd_gpio, GPIOD_IS_IN);
685#endif
Lei Wenaf62a552011-06-28 21:50:06 +0000686
Masahiro Yamada8d549b62016-08-25 16:07:34 +0900687 sdhci_reset(host, SDHCI_RESET_ALL);
688
Masahiro Yamadac8cc18b2020-02-14 16:40:21 +0900689#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
690 host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
Masahiro Yamadaf5df6aa2020-02-14 16:40:22 +0900691 /*
692 * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
693 * is defined.
694 */
695 host->force_align_buffer = true;
Masahiro Yamadac8cc18b2020-02-14 16:40:21 +0900696#else
697 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
698 host->align_buffer = memalign(8, 512 * 1024);
699 if (!host->align_buffer) {
Darwin Rambo30e6d972013-12-19 15:13:25 -0800700 printf("%s: Aligned buffer alloc failed!!!\n",
701 __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900702 return -ENOMEM;
Lei Wenaf62a552011-06-28 21:50:06 +0000703 }
704 }
Masahiro Yamadac8cc18b2020-02-14 16:40:21 +0900705#endif
Lei Wenaf62a552011-06-28 21:50:06 +0000706
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200707 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
Joe Hershberger470dcc72012-08-17 10:18:55 +0000708
Masahiro Yamadabf9c4d12017-01-13 11:51:51 +0900709 if (host->ops && host->ops->get_cd)
Jaehoon Chung6f88a3a2016-12-30 15:30:15 +0900710 host->ops->get_cd(host);
Joe Hershberger470dcc72012-08-17 10:18:55 +0000711
Łukasz Majewskice0c1bc2013-01-11 05:08:54 +0000712 /* Enable only interrupts served by the SD controller */
Darwin Rambo30e6d972013-12-19 15:13:25 -0800713 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
714 SDHCI_INT_ENABLE);
Łukasz Majewskice0c1bc2013-01-11 05:08:54 +0000715 /* Mask all sdhci interrupt sources */
716 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
Lei Wenaf62a552011-06-28 21:50:06 +0000717
Lei Wenaf62a552011-06-28 21:50:06 +0000718 return 0;
719}
720
Simon Glasse7881d82017-07-29 11:35:31 -0600721#ifdef CONFIG_DM_MMC
Simon Glassef1e4ed2016-06-12 23:30:28 -0600722int sdhci_probe(struct udevice *dev)
723{
724 struct mmc *mmc = mmc_get_mmc_dev(dev);
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200725
Simon Glassef1e4ed2016-06-12 23:30:28 -0600726 return sdhci_init(mmc);
727}
728
Faiz Abbascb884342020-02-26 13:44:31 +0530729static int sdhci_deferred_probe(struct udevice *dev)
730{
731 int err;
732 struct mmc *mmc = mmc_get_mmc_dev(dev);
733 struct sdhci_host *host = mmc->priv;
734
735 if (host->ops && host->ops->deferred_probe) {
736 err = host->ops->deferred_probe(host);
737 if (err)
738 return err;
739 }
740 return 0;
741}
742
Baruch Siach1b716952019-11-03 12:00:27 +0200743static int sdhci_get_cd(struct udevice *dev)
T Karthik Reddyda18c622019-06-25 13:39:04 +0200744{
745 struct mmc *mmc = mmc_get_mmc_dev(dev);
746 struct sdhci_host *host = mmc->priv;
747 int value;
748
749 /* If nonremovable, assume that the card is always present. */
750 if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
751 return 1;
752 /* If polling, assume that the card is always present. */
753 if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
754 return 1;
755
756#if CONFIG_IS_ENABLED(DM_GPIO)
757 value = dm_gpio_get_value(&host->cd_gpio);
758 if (value >= 0) {
759 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
760 return !value;
761 else
762 return value;
763 }
764#endif
765 value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
766 SDHCI_CARD_PRESENT);
767 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
768 return !value;
769 else
770 return value;
771}
772
Simon Glassef1e4ed2016-06-12 23:30:28 -0600773const struct dm_mmc_ops sdhci_ops = {
774 .send_cmd = sdhci_send_command,
775 .set_ios = sdhci_set_ios,
T Karthik Reddyda18c622019-06-25 13:39:04 +0200776 .get_cd = sdhci_get_cd,
Faiz Abbascb884342020-02-26 13:44:31 +0530777 .deferred_probe = sdhci_deferred_probe,
Siva Durga Prasad Paladuguca992e82018-04-19 12:37:07 +0530778#ifdef MMC_SUPPORTS_TUNING
779 .execute_tuning = sdhci_execute_tuning,
780#endif
Simon Glassef1e4ed2016-06-12 23:30:28 -0600781};
782#else
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200783static const struct mmc_ops sdhci_ops = {
784 .send_cmd = sdhci_send_command,
785 .set_ios = sdhci_set_ios,
786 .init = sdhci_init,
787};
Simon Glassef1e4ed2016-06-12 23:30:28 -0600788#endif
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200789
Jaehoon Chung14bed522016-07-26 19:06:24 +0900790int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100791 u32 f_max, u32 f_min)
Simon Glass2a809092016-06-12 23:30:27 -0600792{
Siva Durga Prasad Paladugub8e25ef2018-04-19 12:37:08 +0530793 u32 caps, caps_1 = 0;
Faiz Abbas3d296362019-06-11 00:43:34 +0530794#if CONFIG_IS_ENABLED(DM_MMC)
T Karthik Reddycd45d6f2019-09-02 16:34:31 +0200795 u64 dt_caps, dt_caps_mask;
Jaehoon Chung14bed522016-07-26 19:06:24 +0900796
T Karthik Reddycd45d6f2019-09-02 16:34:31 +0200797 dt_caps_mask = dev_read_u64_default(host->mmc->dev,
798 "sdhci-caps-mask", 0);
799 dt_caps = dev_read_u64_default(host->mmc->dev,
800 "sdhci-caps", 0);
Michal Simekb5a33872020-07-29 15:42:26 +0200801 caps = ~lower_32_bits(dt_caps_mask) &
T Karthik Reddycd45d6f2019-09-02 16:34:31 +0200802 sdhci_readl(host, SDHCI_CAPABILITIES);
Michal Simekb5a33872020-07-29 15:42:26 +0200803 caps |= lower_32_bits(dt_caps);
Faiz Abbas3d296362019-06-11 00:43:34 +0530804#else
Jaehoon Chung14bed522016-07-26 19:06:24 +0900805 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
Faiz Abbas3d296362019-06-11 00:43:34 +0530806#endif
T Karthik Reddycd45d6f2019-09-02 16:34:31 +0200807 debug("%s, caps: 0x%x\n", __func__, caps);
Masahiro Yamada15bd0992016-08-25 16:07:37 +0900808
Masahiro Yamada45a68fe2016-12-07 22:10:29 +0900809#ifdef CONFIG_MMC_SDHCI_SDMA
Jaehoon Chungfabb3a42020-03-27 13:08:01 +0900810 if ((caps & SDHCI_CAN_DO_SDMA)) {
811 host->flags |= USE_SDMA;
812 } else {
Matthias Brugger7acdc9a2020-05-12 12:02:06 +0200813 debug("%s: Your controller doesn't support SDMA!!\n",
814 __func__);
Masahiro Yamada15bd0992016-08-25 16:07:37 +0900815 }
816#endif
Faiz Abbas37cb6262019-04-16 23:06:58 +0530817#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
818 if (!(caps & SDHCI_CAN_DO_ADMA2)) {
819 printf("%s: Your controller doesn't support SDMA!!\n",
820 __func__);
821 return -EINVAL;
822 }
Michael Walle4d6a7732020-09-23 12:42:51 +0200823 host->adma_desc_table = sdhci_adma_init();
Faiz Abbas37cb6262019-04-16 23:06:58 +0530824 host->adma_addr = (dma_addr_t)host->adma_desc_table;
Michael Walle4d6a7732020-09-23 12:42:51 +0200825
Faiz Abbas37cb6262019-04-16 23:06:58 +0530826#ifdef CONFIG_DMA_ADDR_T_64BIT
827 host->flags |= USE_ADMA64;
828#else
829 host->flags |= USE_ADMA;
830#endif
831#endif
Jaehoon Chung895549a2016-09-26 08:10:01 +0900832 if (host->quirks & SDHCI_QUIRK_REG32_RW)
833 host->version =
834 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
835 else
836 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
Jaehoon Chung14bed522016-07-26 19:06:24 +0900837
838 cfg->name = host->name;
Simon Glasse7881d82017-07-29 11:35:31 -0600839#ifndef CONFIG_DM_MMC
Simon Glass2a809092016-06-12 23:30:27 -0600840 cfg->ops = &sdhci_ops;
841#endif
Wenyou Yang0e0dcc12017-04-26 09:32:30 +0800842
843 /* Check whether the clock multiplier is supported or not */
844 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
Faiz Abbas3d296362019-06-11 00:43:34 +0530845#if CONFIG_IS_ENABLED(DM_MMC)
Michal Simekb5a33872020-07-29 15:42:26 +0200846 caps_1 = ~upper_32_bits(dt_caps_mask) &
T Karthik Reddycd45d6f2019-09-02 16:34:31 +0200847 sdhci_readl(host, SDHCI_CAPABILITIES_1);
Michal Simekb5a33872020-07-29 15:42:26 +0200848 caps_1 |= upper_32_bits(dt_caps);
Faiz Abbas3d296362019-06-11 00:43:34 +0530849#else
Wenyou Yang0e0dcc12017-04-26 09:32:30 +0800850 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
Faiz Abbas3d296362019-06-11 00:43:34 +0530851#endif
T Karthik Reddycd45d6f2019-09-02 16:34:31 +0200852 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
Wenyou Yang0e0dcc12017-04-26 09:32:30 +0800853 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
854 SDHCI_CLOCK_MUL_SHIFT;
855 }
856
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100857 if (host->max_clk == 0) {
Jaehoon Chung14bed522016-07-26 19:06:24 +0900858 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100859 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
Simon Glass2a809092016-06-12 23:30:27 -0600860 SDHCI_CLOCK_BASE_SHIFT;
861 else
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100862 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
Simon Glass2a809092016-06-12 23:30:27 -0600863 SDHCI_CLOCK_BASE_SHIFT;
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100864 host->max_clk *= 1000000;
Wenyou Yang0e0dcc12017-04-26 09:32:30 +0800865 if (host->clk_mul)
866 host->max_clk *= host->clk_mul;
Simon Glass2a809092016-06-12 23:30:27 -0600867 }
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100868 if (host->max_clk == 0) {
Masahiro Yamada6c679542016-08-25 16:07:35 +0900869 printf("%s: Hardware doesn't specify base clock frequency\n",
870 __func__);
Simon Glass2a809092016-06-12 23:30:27 -0600871 return -EINVAL;
Masahiro Yamada6c679542016-08-25 16:07:35 +0900872 }
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100873 if (f_max && (f_max < host->max_clk))
874 cfg->f_max = f_max;
875 else
876 cfg->f_max = host->max_clk;
877 if (f_min)
878 cfg->f_min = f_min;
Simon Glass2a809092016-06-12 23:30:27 -0600879 else {
Jaehoon Chung14bed522016-07-26 19:06:24 +0900880 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
Simon Glass2a809092016-06-12 23:30:27 -0600881 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
882 else
883 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
884 }
885 cfg->voltages = 0;
886 if (caps & SDHCI_CAN_VDD_330)
887 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
888 if (caps & SDHCI_CAN_VDD_300)
889 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
890 if (caps & SDHCI_CAN_VDD_180)
891 cfg->voltages |= MMC_VDD_165_195;
892
Masahiro Yamada3137e642016-08-25 16:07:36 +0900893 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
894 cfg->voltages |= host->voltages;
895
Faiz Abbas620bb462020-07-23 09:42:19 +0530896 if (caps & SDHCI_CAN_DO_HISPD)
897 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
898
899 cfg->host_caps |= MMC_MODE_4BIT;
Jaehoon Chung3fd0a9b2016-12-30 15:30:21 +0900900
901 /* Since Host Controller Version3.0 */
Jaehoon Chung14bed522016-07-26 19:06:24 +0900902 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
Jaehoon Chungecd7b242016-12-30 15:30:11 +0900903 if (!(caps & SDHCI_CAN_DO_8BIT))
904 cfg->host_caps &= ~MMC_MODE_8BIT;
Simon Glass2a809092016-06-12 23:30:27 -0600905 }
906
Hannes Schmelzer88a57122018-03-07 08:00:56 +0100907 if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
908 cfg->host_caps &= ~MMC_MODE_HS;
909 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
910 }
911
Ashok Reddy Soma7a49a162020-10-23 04:58:57 -0600912 if (!(cfg->voltages & MMC_VDD_165_195) ||
913 (host->quirks & SDHCI_QUIRK_NO_1_8_V))
Siva Durga Prasad Paladugub8e25ef2018-04-19 12:37:08 +0530914 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
915 SDHCI_SUPPORT_DDR50);
916
917 if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
918 SDHCI_SUPPORT_DDR50))
919 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
920
921 if (caps_1 & SDHCI_SUPPORT_SDR104) {
922 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
923 /*
924 * SD3.0: SDR104 is supported so (for eMMC) the caps2
925 * field can be promoted to support HS200.
926 */
927 cfg->host_caps |= MMC_CAP(MMC_HS_200);
928 } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
929 cfg->host_caps |= MMC_CAP(UHS_SDR50);
930 }
931
932 if (caps_1 & SDHCI_SUPPORT_DDR50)
933 cfg->host_caps |= MMC_CAP(UHS_DDR50);
934
Jaehoon Chung14bed522016-07-26 19:06:24 +0900935 if (host->host_caps)
936 cfg->host_caps |= host->host_caps;
Simon Glass2a809092016-06-12 23:30:27 -0600937
938 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
939
940 return 0;
941}
942
Simon Glassef1e4ed2016-06-12 23:30:28 -0600943#ifdef CONFIG_BLK
944int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
945{
946 return mmc_bind(dev, mmc, cfg);
947}
948#else
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100949int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
Lei Wenaf62a552011-06-28 21:50:06 +0000950{
Masahiro Yamada6c679542016-08-25 16:07:35 +0900951 int ret;
952
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100953 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
Masahiro Yamada6c679542016-08-25 16:07:35 +0900954 if (ret)
955 return ret;
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000956
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200957 host->mmc = mmc_create(&host->cfg, host);
958 if (host->mmc == NULL) {
959 printf("%s: mmc create fail!\n", __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900960 return -ENOMEM;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200961 }
Lei Wenaf62a552011-06-28 21:50:06 +0000962
963 return 0;
964}
Simon Glassef1e4ed2016-06-12 23:30:28 -0600965#endif