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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +09002/*
3 * SH7751 PCI Controller (PCIC) for U-Boot.
4 * (C) Dustin McIntire (dustin@sensoria.com)
5 * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +09006 */
7
8#include <common.h>
Marek Vasut72c2f4a2019-09-01 15:56:41 +02009#include <dm.h>
Nobuhiro Iwamatsub5d10a12008-09-18 19:34:36 +090010#include <pci.h>
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +090011#include <asm/processor.h>
12#include <asm/io.h>
Nobuhiro Iwamatsub5d10a12008-09-18 19:34:36 +090013#include <asm/pci.h>
Simon Glassc05ed002020-05-10 11:40:11 -060014#include <linux/delay.h>
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +090015
16/* Register addresses and such */
17#define SH7751_BCR1 (vu_long *)0xFF800000
Nobuhiro Iwamatsub5d10a12008-09-18 19:34:36 +090018#define SH7751_BCR2 (vu_short *)0xFF800004
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +090019#define SH7751_WCR1 (vu_long *)0xFF800008
20#define SH7751_WCR2 (vu_long *)0xFF80000C
21#define SH7751_WCR3 (vu_long *)0xFF800010
22#define SH7751_MCR (vu_long *)0xFF800014
Nobuhiro Iwamatsub5d10a12008-09-18 19:34:36 +090023#define SH7751_BCR3 (vu_short *)0xFF800050
Marek Vasut72c2f4a2019-09-01 15:56:41 +020024#define SH7751_PCICONF0 (vu_long *)0xFE200000
25#define SH7751_PCICONF1 (vu_long *)0xFE200004
26#define SH7751_PCICONF2 (vu_long *)0xFE200008
27#define SH7751_PCICONF3 (vu_long *)0xFE20000C
28#define SH7751_PCICONF4 (vu_long *)0xFE200010
29#define SH7751_PCICONF5 (vu_long *)0xFE200014
30#define SH7751_PCICONF6 (vu_long *)0xFE200018
31#define SH7751_PCICR (vu_long *)0xFE200100
32#define SH7751_PCILSR0 (vu_long *)0xFE200104
33#define SH7751_PCILSR1 (vu_long *)0xFE200108
34#define SH7751_PCILAR0 (vu_long *)0xFE20010C
35#define SH7751_PCILAR1 (vu_long *)0xFE200110
36#define SH7751_PCIMBR (vu_long *)0xFE2001C4
37#define SH7751_PCIIOBR (vu_long *)0xFE2001C8
38#define SH7751_PCIPINT (vu_long *)0xFE2001CC
39#define SH7751_PCIPINTM (vu_long *)0xFE2001D0
40#define SH7751_PCICLKR (vu_long *)0xFE2001D4
41#define SH7751_PCIBCR1 (vu_long *)0xFE2001E0
42#define SH7751_PCIBCR2 (vu_long *)0xFE2001E4
43#define SH7751_PCIWCR1 (vu_long *)0xFE2001E8
44#define SH7751_PCIWCR2 (vu_long *)0xFE2001EC
45#define SH7751_PCIWCR3 (vu_long *)0xFE2001F0
46#define SH7751_PCIMCR (vu_long *)0xFE2001F4
47#define SH7751_PCIBCR3 (vu_long *)0xFE2001F8
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +090048
Marek Vasut72c2f4a2019-09-01 15:56:41 +020049#define BCR1_BREQEN 0x00080000
50#define PCI_SH7751_ID 0x35051054
51#define PCI_SH7751R_ID 0x350E1054
52#define SH7751_PCICONF1_WCC 0x00000080
53#define SH7751_PCICONF1_PER 0x00000040
54#define SH7751_PCICONF1_BUM 0x00000004
55#define SH7751_PCICONF1_MES 0x00000002
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +090056#define SH7751_PCICONF1_CMDS 0x000000C6
57#define SH7751_PCI_HOST_BRIDGE 0x6
Marek Vasut72c2f4a2019-09-01 15:56:41 +020058#define SH7751_PCICR_PREFIX 0xa5000000
59#define SH7751_PCICR_PRST 0x00000002
60#define SH7751_PCICR_CFIN 0x00000001
61#define SH7751_PCIPINT_D3 0x00000002
62#define SH7751_PCIPINT_D0 0x00000001
63#define SH7751_PCICLKR_PREFIX 0xa5000000
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +090064
Marek Vasut72c2f4a2019-09-01 15:56:41 +020065#define SH7751_PCI_MEM_BASE 0xFD000000
66#define SH7751_PCI_MEM_SIZE 0x01000000
67#define SH7751_PCI_IO_BASE 0xFE240000
68#define SH7751_PCI_IO_SIZE 0x00040000
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +090069
Marek Vasut72c2f4a2019-09-01 15:56:41 +020070#define SH7751_PCIPAR (vu_long *)0xFE2001C0
71#define SH7751_PCIPDR (vu_long *)0xFE200220
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +090072
Nobuhiro Iwamatsub5d10a12008-09-18 19:34:36 +090073#define p4_in(addr) (*addr)
74#define p4_out(data, addr) (*addr) = (data)
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +090075
Marek Vasut72c2f4a2019-09-01 15:56:41 +020076static int sh7751_pci_addr_valid(pci_dev_t d, uint offset)
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +090077{
Marek Vasut72c2f4a2019-09-01 15:56:41 +020078 if (PCI_FUNC(d))
79 return -EINVAL;
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +090080
81 return 0;
82}
83
Simon Glassc4e72c42020-01-27 08:49:37 -070084static u32 get_bus_address(const struct udevice *dev, pci_dev_t bdf, u32 offset)
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +090085{
Marek Vasut72c2f4a2019-09-01 15:56:41 +020086 return BIT(31) | (PCI_DEV(bdf) << 8) | (offset & ~3);
87}
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +090088
Simon Glassc4e72c42020-01-27 08:49:37 -070089static int sh7751_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
Marek Vasut72c2f4a2019-09-01 15:56:41 +020090 uint offset, ulong *value,
91 enum pci_size_t size)
92{
93 u32 addr, reg;
94 int ret;
95
96 ret = sh7751_pci_addr_valid(bdf, offset);
97 if (ret) {
98 *value = pci_get_ff(size);
99 return 0;
100 }
101
102 addr = get_bus_address(dev, bdf, offset);
103 p4_out(addr, SH7751_PCIPAR);
104 reg = p4_in(SH7751_PCIPDR);
105 *value = pci_conv_32_to_size(reg, offset, size);
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +0900106
107 return 0;
108}
109
Marek Vasut72c2f4a2019-09-01 15:56:41 +0200110static int sh7751_pci_write_config(struct udevice *dev, pci_dev_t bdf,
111 uint offset, ulong value,
112 enum pci_size_t size)
113{
114 u32 addr, reg, old;
115 int ret;
116
117 ret = sh7751_pci_addr_valid(bdf, offset);
118 if (ret)
119 return ret;
120
121 addr = get_bus_address(dev, bdf, offset);
122 p4_out(addr, SH7751_PCIPAR);
123 old = p4_in(SH7751_PCIPDR);
124 reg = pci_conv_size_to_32(old, value, offset, size);
125 p4_out(reg, SH7751_PCIPDR);
126
127 return 0;
128}
129
130static int sh7751_pci_probe(struct udevice *dev)
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +0900131{
132 /* Double-check that we're a 7751 or 7751R chip */
133 if (p4_in(SH7751_PCICONF0) != PCI_SH7751_ID
134 && p4_in(SH7751_PCICONF0) != PCI_SH7751R_ID) {
135 printf("PCI: Unknown PCI host bridge.\n");
136 return 1;
137 }
138 printf("PCI: SH7751 PCI host bridge found.\n");
139
140 /* Double-check some BSC config settings */
141 /* (Area 3 non-MPX 32-bit, PCI bus pins) */
142 if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
Nobuhiro Iwamatsub5d10a12008-09-18 19:34:36 +0900143 printf("SH7751_BCR1 value is wrong(0x%08X)\n",
144 (unsigned int)p4_in(SH7751_BCR1));
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +0900145 return 2;
146 }
147 if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
Nobuhiro Iwamatsub5d10a12008-09-18 19:34:36 +0900148 printf("SH7751_BCR2 value is wrong(0x%08X)\n",
149 (unsigned int)p4_in(SH7751_BCR2));
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +0900150 return 3;
151 }
152 if (p4_in(SH7751_BCR2) & 0x01) {
Nobuhiro Iwamatsub5d10a12008-09-18 19:34:36 +0900153 printf("SH7751_BCR2 value is wrong(0x%08X)\n",
154 (unsigned int)p4_in(SH7751_BCR2));
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +0900155 return 4;
156 }
157
158 /* Force BREQEN in BCR1 to allow PCIC access */
159 p4_out((p4_in(SH7751_BCR1) | BCR1_BREQEN), SH7751_BCR1);
160
161 /* Toggle PCI reset pin */
162 p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_PRST), SH7751_PCICR);
163 udelay(32);
164 p4_out(SH7751_PCICR_PREFIX, SH7751_PCICR);
165
166 /* Set cmd bits: WCC, PER, BUM, MES */
167 /* (Addr/Data stepping, Parity enabled, Bus Master, Memory enabled) */
168 p4_out(0xfb900047, SH7751_PCICONF1); /* K.Kino */
169
170 /* Define this host as the host bridge */
171 p4_out((SH7751_PCI_HOST_BRIDGE << 24), SH7751_PCICONF2);
172
173 /* Force PCI clock(s) on */
174 p4_out(0, SH7751_PCICLKR);
175 p4_out(0x03, SH7751_PCICLKR);
176
177 /* Clear powerdown IRQs, also mask them (unused) */
178 p4_out((SH7751_PCIPINT_D0 | SH7751_PCIPINT_D3), SH7751_PCIPINT);
179 p4_out(0, SH7751_PCIPINTM);
180
181 p4_out(0xab000001, SH7751_PCICONF4);
182
183 /* Set up target memory mappings (for external DMA access) */
184 /* Map both P0 and P2 range to Area 3 RAM for ease of use */
Vladimir Zapolskiy30391de2016-11-28 00:15:20 +0200185 p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
186 p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
187 p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
188
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +0900189 p4_out(0, SH7751_PCILSR1);
190 p4_out(0, SH7751_PCILAR1);
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +0900191 p4_out(0xd0000000, SH7751_PCICONF6);
192
193 /* Map memory window to same address on PCI bus */
194 p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR);
195
196 /* Map IO window to same address on PCI bus */
Vladimir Zapolskiyd44cf292016-11-28 00:15:19 +0200197 p4_out(SH7751_PCI_IO_BASE, SH7751_PCIIOBR);
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +0900198
199 /* set BREQEN */
200 p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1);
201
202 /* Copy BSC registers into PCI BSC */
203 p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1);
Jean-Christophe PLAGNIOL-VILLARDa319f142008-12-05 07:27:37 +0100204 p4_out(inw(SH7751_BCR2), SH7751_PCIBCR2);
205 p4_out(inw(SH7751_BCR3), SH7751_PCIBCR3);
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +0900206 p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1);
207 p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2);
208 p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3);
209 p4_out(inl(SH7751_MCR), SH7751_PCIMCR);
210
211 /* Finally, set central function init complete */
212 p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN), SH7751_PCICR);
213
Nobuhiro Iwamatsu28e5efd2008-03-24 01:53:01 +0900214 return 0;
215}
Marek Vasut72c2f4a2019-09-01 15:56:41 +0200216
217static const struct dm_pci_ops sh7751_pci_ops = {
218 .read_config = sh7751_pci_read_config,
219 .write_config = sh7751_pci_write_config,
220};
221
222static const struct udevice_id sh7751_pci_ids[] = {
223 { .compatible = "renesas,pci-sh7751" },
224 { }
225};
226
227U_BOOT_DRIVER(sh7751_pci) = {
228 .name = "sh7751_pci",
229 .id = UCLASS_PCI,
230 .of_match = sh7751_pci_ids,
231 .ops = &sh7751_pci_ops,
232 .probe = sh7751_pci_probe,
233};