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Fabio Estevam6126fd82018-05-02 16:18:29 -03001// SPDX-License-Identifier: GPL-2.0+
2//
3// Freescale i.MX7ULP LPSPI driver
4//
5// Copyright 2016 Freescale Semiconductor, Inc.
Clark Wang07d71552018-12-07 02:50:34 +00006// Copyright 2018 NXP Semiconductors
Gao Pan53149872016-11-22 21:52:17 +08007
8#include <linux/clk.h>
9#include <linux/completion.h>
10#include <linux/delay.h>
Clark Wang09c04462019-03-06 06:30:45 +000011#include <linux/dmaengine.h>
12#include <linux/dma-mapping.h>
Gao Pan53149872016-11-22 21:52:17 +080013#include <linux/err.h>
Clark Wangc7a40252019-03-06 06:30:43 +000014#include <linux/gpio.h>
Gao Pan53149872016-11-22 21:52:17 +080015#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/irq.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
Clark Wangc7a40252019-03-06 06:30:43 +000022#include <linux/of_gpio.h>
Han Xu944c01a2019-03-06 06:30:39 +000023#include <linux/pinctrl/consumer.h>
Gao Pan53149872016-11-22 21:52:17 +080024#include <linux/platform_device.h>
Clark Wang09c04462019-03-06 06:30:45 +000025#include <linux/platform_data/dma-imx.h>
Clark Wangc7a40252019-03-06 06:30:43 +000026#include <linux/platform_data/spi-imx.h>
Han Xu944c01a2019-03-06 06:30:39 +000027#include <linux/pm_runtime.h>
Gao Pan53149872016-11-22 21:52:17 +080028#include <linux/slab.h>
29#include <linux/spi/spi.h>
30#include <linux/spi/spi_bitbang.h>
31#include <linux/types.h>
32
33#define DRIVER_NAME "fsl_lpspi"
34
Han Xu944c01a2019-03-06 06:30:39 +000035#define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */
36
Clark Wang09c04462019-03-06 06:30:45 +000037/* The maximum bytes that edma can transfer once.*/
38#define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
39
Gao Pan53149872016-11-22 21:52:17 +080040/* i.MX7ULP LPSPI registers */
41#define IMX7ULP_VERID 0x0
42#define IMX7ULP_PARAM 0x4
43#define IMX7ULP_CR 0x10
44#define IMX7ULP_SR 0x14
45#define IMX7ULP_IER 0x18
46#define IMX7ULP_DER 0x1c
47#define IMX7ULP_CFGR0 0x20
48#define IMX7ULP_CFGR1 0x24
49#define IMX7ULP_DMR0 0x30
50#define IMX7ULP_DMR1 0x34
51#define IMX7ULP_CCR 0x40
52#define IMX7ULP_FCR 0x58
53#define IMX7ULP_FSR 0x5c
54#define IMX7ULP_TCR 0x60
55#define IMX7ULP_TDR 0x64
56#define IMX7ULP_RSR 0x70
57#define IMX7ULP_RDR 0x74
58
59/* General control register field define */
60#define CR_RRF BIT(9)
61#define CR_RTF BIT(8)
62#define CR_RST BIT(1)
63#define CR_MEN BIT(0)
Clark Wang6a130442019-01-07 07:47:41 +000064#define SR_MBF BIT(24)
Gao Pan53149872016-11-22 21:52:17 +080065#define SR_TCF BIT(10)
Clark Wangc23fdef2019-01-07 07:47:38 +000066#define SR_FCF BIT(9)
Gao Pan53149872016-11-22 21:52:17 +080067#define SR_RDF BIT(1)
68#define SR_TDF BIT(0)
69#define IER_TCIE BIT(10)
Clark Wangc23fdef2019-01-07 07:47:38 +000070#define IER_FCIE BIT(9)
Gao Pan53149872016-11-22 21:52:17 +080071#define IER_RDIE BIT(1)
72#define IER_TDIE BIT(0)
Clark Wang09c04462019-03-06 06:30:45 +000073#define DER_RDDE BIT(1)
74#define DER_TDDE BIT(0)
Gao Pan53149872016-11-22 21:52:17 +080075#define CFGR1_PCSCFG BIT(27)
Clark Wangbcd87312018-12-07 02:50:36 +000076#define CFGR1_PINCFG (BIT(24)|BIT(25))
Gao Pan53149872016-11-22 21:52:17 +080077#define CFGR1_PCSPOL BIT(8)
78#define CFGR1_NOSTALL BIT(3)
79#define CFGR1_MASTER BIT(0)
Clark Wang6a130442019-01-07 07:47:41 +000080#define FSR_RXCOUNT (BIT(16)|BIT(17)|BIT(18))
Gao Pan53149872016-11-22 21:52:17 +080081#define RSR_RXEMPTY BIT(1)
82#define TCR_CPOL BIT(31)
83#define TCR_CPHA BIT(30)
84#define TCR_CONT BIT(21)
85#define TCR_CONTC BIT(20)
86#define TCR_RXMSK BIT(19)
87#define TCR_TXMSK BIT(18)
88
89static int clkdivs[] = {1, 2, 4, 8, 16, 32, 64, 128};
90
91struct lpspi_config {
92 u8 bpw;
93 u8 chip_select;
94 u8 prescale;
95 u16 mode;
96 u32 speed_hz;
97};
98
99struct fsl_lpspi_data {
100 struct device *dev;
101 void __iomem *base;
Clark Wang09c04462019-03-06 06:30:45 +0000102 unsigned long base_phys;
Clark Wangf5e5afd2019-03-06 06:30:34 +0000103 struct clk *clk_ipg;
104 struct clk *clk_per;
Clark Wangbcd87312018-12-07 02:50:36 +0000105 bool is_slave;
Clark Wangc7a40252019-03-06 06:30:43 +0000106 bool is_first_byte;
Gao Pan53149872016-11-22 21:52:17 +0800107
108 void *rx_buf;
109 const void *tx_buf;
110 void (*tx)(struct fsl_lpspi_data *);
111 void (*rx)(struct fsl_lpspi_data *);
112
113 u32 remain;
Clark Wangcf868742018-12-07 02:50:38 +0000114 u8 watermark;
Gao Pan53149872016-11-22 21:52:17 +0800115 u8 txfifosize;
116 u8 rxfifosize;
117
118 struct lpspi_config config;
119 struct completion xfer_done;
Clark Wangbcd87312018-12-07 02:50:36 +0000120
121 bool slave_aborted;
Clark Wangc7a40252019-03-06 06:30:43 +0000122
Clark Wang09c04462019-03-06 06:30:45 +0000123 /* DMA */
124 bool usedma;
125 struct completion dma_rx_completion;
126 struct completion dma_tx_completion;
127
Clark Wangc7a40252019-03-06 06:30:43 +0000128 int chipselect[0];
Gao Pan53149872016-11-22 21:52:17 +0800129};
130
131static const struct of_device_id fsl_lpspi_dt_ids[] = {
132 { .compatible = "fsl,imx7ulp-spi", },
133 { /* sentinel */ }
134};
135MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
136
137#define LPSPI_BUF_RX(type) \
138static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \
139{ \
140 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
141 \
142 if (fsl_lpspi->rx_buf) { \
143 *(type *)fsl_lpspi->rx_buf = val; \
144 fsl_lpspi->rx_buf += sizeof(type); \
145 } \
146}
147
148#define LPSPI_BUF_TX(type) \
149static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \
150{ \
151 type val = 0; \
152 \
153 if (fsl_lpspi->tx_buf) { \
154 val = *(type *)fsl_lpspi->tx_buf; \
155 fsl_lpspi->tx_buf += sizeof(type); \
156 } \
157 \
158 fsl_lpspi->remain -= sizeof(type); \
159 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
160}
161
162LPSPI_BUF_RX(u8)
163LPSPI_BUF_TX(u8)
164LPSPI_BUF_RX(u16)
165LPSPI_BUF_TX(u16)
166LPSPI_BUF_RX(u32)
167LPSPI_BUF_TX(u32)
168
169static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
170 unsigned int enable)
171{
172 writel(enable, fsl_lpspi->base + IMX7ULP_IER);
173}
174
Clark Wang09c04462019-03-06 06:30:45 +0000175static int fsl_lpspi_bytes_per_word(const int bpw)
176{
177 return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
178}
179
180static bool fsl_lpspi_can_dma(struct spi_controller *controller,
181 struct spi_device *spi,
182 struct spi_transfer *transfer)
183{
184 unsigned int bytes_per_word;
185
186 if (!controller->dma_rx)
187 return false;
188
189 bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
190
191 switch (bytes_per_word)
192 {
193 case 1:
194 case 2:
195 case 4:
196 break;
197 default:
198 return false;
199 }
200
201 return true;
202}
203
Clark Wang07d71552018-12-07 02:50:34 +0000204static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
Gao Pan53149872016-11-22 21:52:17 +0800205{
Clark Wang07d71552018-12-07 02:50:34 +0000206 struct fsl_lpspi_data *fsl_lpspi =
207 spi_controller_get_devdata(controller);
Clark Wangf5e5afd2019-03-06 06:30:34 +0000208 int ret;
Gao Pan53149872016-11-22 21:52:17 +0800209
Han Xu944c01a2019-03-06 06:30:39 +0000210 ret = pm_runtime_get_sync(fsl_lpspi->dev);
211 if (ret < 0) {
212 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
Clark Wangf5e5afd2019-03-06 06:30:34 +0000213 return ret;
214 }
215
216 return 0;
Gao Pan53149872016-11-22 21:52:17 +0800217}
218
Clark Wang07d71552018-12-07 02:50:34 +0000219static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
Gao Pan53149872016-11-22 21:52:17 +0800220{
Clark Wang07d71552018-12-07 02:50:34 +0000221 struct fsl_lpspi_data *fsl_lpspi =
222 spi_controller_get_devdata(controller);
Gao Pan53149872016-11-22 21:52:17 +0800223
Han Xu944c01a2019-03-06 06:30:39 +0000224 pm_runtime_mark_last_busy(fsl_lpspi->dev);
225 pm_runtime_put_autosuspend(fsl_lpspi->dev);
Gao Pan53149872016-11-22 21:52:17 +0800226
227 return 0;
228}
229
Clark Wangc7a40252019-03-06 06:30:43 +0000230static int fsl_lpspi_prepare_message(struct spi_controller *controller,
231 struct spi_message *msg)
232{
233 struct fsl_lpspi_data *fsl_lpspi =
234 spi_controller_get_devdata(controller);
235 struct spi_device *spi = msg->spi;
236 int gpio = fsl_lpspi->chipselect[spi->chip_select];
237
238 if (gpio_is_valid(gpio))
239 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
240
241 return 0;
242}
243
Gao Pan53149872016-11-22 21:52:17 +0800244static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
245{
246 u8 txfifo_cnt;
Clark Wangc23fdef2019-01-07 07:47:38 +0000247 u32 temp;
Gao Pan53149872016-11-22 21:52:17 +0800248
249 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
250
251 while (txfifo_cnt < fsl_lpspi->txfifosize) {
252 if (!fsl_lpspi->remain)
253 break;
254 fsl_lpspi->tx(fsl_lpspi);
255 txfifo_cnt++;
256 }
257
Clark Wangc23fdef2019-01-07 07:47:38 +0000258 if (txfifo_cnt < fsl_lpspi->txfifosize) {
259 if (!fsl_lpspi->is_slave) {
260 temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
261 temp &= ~TCR_CONTC;
262 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
263 }
264
265 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
266 } else
Gao Pan53149872016-11-22 21:52:17 +0800267 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
268}
269
270static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
271{
272 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
273 fsl_lpspi->rx(fsl_lpspi);
274}
275
Clark Wangc7a40252019-03-06 06:30:43 +0000276static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
Gao Pan53149872016-11-22 21:52:17 +0800277{
278 u32 temp = 0;
279
280 temp |= fsl_lpspi->config.bpw - 1;
Gao Pane3a49392016-11-24 19:04:43 +0800281 temp |= (fsl_lpspi->config.mode & 0x3) << 30;
Clark Wangbcd87312018-12-07 02:50:36 +0000282 if (!fsl_lpspi->is_slave) {
283 temp |= fsl_lpspi->config.prescale << 27;
284 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
Gao Pan53149872016-11-22 21:52:17 +0800285
Clark Wangbcd87312018-12-07 02:50:36 +0000286 /*
287 * Set TCR_CONT will keep SS asserted after current transfer.
288 * For the first transfer, clear TCR_CONTC to assert SS.
289 * For subsequent transfer, set TCR_CONTC to keep SS asserted.
290 */
Clark Wang09c04462019-03-06 06:30:45 +0000291 if (!fsl_lpspi->usedma) {
292 temp |= TCR_CONT;
293 if (fsl_lpspi->is_first_byte)
294 temp &= ~TCR_CONTC;
295 else
296 temp |= TCR_CONTC;
297 }
Clark Wangbcd87312018-12-07 02:50:36 +0000298 }
Gao Pan53149872016-11-22 21:52:17 +0800299 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
300
301 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
302}
303
304static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
305{
Gao Pan53149872016-11-22 21:52:17 +0800306 u32 temp;
307
Clark Wang09c04462019-03-06 06:30:45 +0000308 if (!fsl_lpspi->usedma)
309 temp = fsl_lpspi->watermark >> 1 |
310 (fsl_lpspi->watermark >> 1) << 16;
311 else
312 temp = fsl_lpspi->watermark >> 1;
Gao Pan53149872016-11-22 21:52:17 +0800313
314 writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
315
316 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
317}
318
319static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
320{
321 struct lpspi_config config = fsl_lpspi->config;
322 unsigned int perclk_rate, scldiv;
323 u8 prescale;
324
Clark Wangf5e5afd2019-03-06 06:30:34 +0000325 perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
Clark Wang77736a92019-03-06 06:30:41 +0000326
327 if (config.speed_hz > perclk_rate / 2) {
328 dev_err(fsl_lpspi->dev,
329 "per-clk should be at least two times of transfer speed");
330 return -EINVAL;
331 }
332
Gao Pan53149872016-11-22 21:52:17 +0800333 for (prescale = 0; prescale < 8; prescale++) {
334 scldiv = perclk_rate /
335 (clkdivs[prescale] * config.speed_hz) - 2;
336 if (scldiv < 256) {
337 fsl_lpspi->config.prescale = prescale;
338 break;
339 }
340 }
341
342 if (prescale == 8 && scldiv >= 256)
343 return -EINVAL;
344
Clark Wangcf868742018-12-07 02:50:38 +0000345 writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
346 fsl_lpspi->base + IMX7ULP_CCR);
Gao Pan53149872016-11-22 21:52:17 +0800347
348 dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale =%d, scldiv=%d\n",
349 perclk_rate, config.speed_hz, prescale, scldiv);
350
351 return 0;
352}
353
Clark Wang09c04462019-03-06 06:30:45 +0000354static int fsl_lpspi_dma_configure(struct spi_controller *controller)
355{
356 int ret;
357 enum dma_slave_buswidth buswidth;
358 struct dma_slave_config rx = {}, tx = {};
359 struct fsl_lpspi_data *fsl_lpspi =
360 spi_controller_get_devdata(controller);
361
362 switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
363 case 4:
364 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
365 break;
366 case 2:
367 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
368 break;
369 case 1:
370 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
371 break;
372 default:
373 return -EINVAL;
374 }
375
376 tx.direction = DMA_MEM_TO_DEV;
377 tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
378 tx.dst_addr_width = buswidth;
379 tx.dst_maxburst = 1;
380 ret = dmaengine_slave_config(controller->dma_tx, &tx);
381 if (ret) {
382 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
383 ret);
384 return ret;
385 }
386
387 rx.direction = DMA_DEV_TO_MEM;
388 rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
389 rx.src_addr_width = buswidth;
390 rx.src_maxburst = 1;
391 ret = dmaengine_slave_config(controller->dma_rx, &rx);
392 if (ret) {
393 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
394 ret);
395 return ret;
396 }
397
398 return 0;
399}
400
Gao Pan53149872016-11-22 21:52:17 +0800401static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
402{
403 u32 temp;
404 int ret;
405
Clark Wangbcd87312018-12-07 02:50:36 +0000406 if (!fsl_lpspi->is_slave) {
407 ret = fsl_lpspi_set_bitrate(fsl_lpspi);
408 if (ret)
409 return ret;
410 }
Gao Pan53149872016-11-22 21:52:17 +0800411
412 fsl_lpspi_set_watermark(fsl_lpspi);
413
Clark Wangbcd87312018-12-07 02:50:36 +0000414 if (!fsl_lpspi->is_slave)
415 temp = CFGR1_MASTER;
416 else
417 temp = CFGR1_PINCFG;
Gao Pan53149872016-11-22 21:52:17 +0800418 if (fsl_lpspi->config.mode & SPI_CS_HIGH)
419 temp |= CFGR1_PCSPOL;
420 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
421
422 temp = readl(fsl_lpspi->base + IMX7ULP_CR);
423 temp |= CR_RRF | CR_RTF | CR_MEN;
424 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
425
Clark Wang09c04462019-03-06 06:30:45 +0000426 temp = 0;
427 if (fsl_lpspi->usedma)
428 temp = DER_TDDE | DER_RDDE;
429 writel(temp, fsl_lpspi->base + IMX7ULP_DER);
430
Gao Pan53149872016-11-22 21:52:17 +0800431 return 0;
432}
433
Clark Wang09c04462019-03-06 06:30:45 +0000434static int fsl_lpspi_setup_transfer(struct spi_controller *controller,
435 struct spi_device *spi,
Gao Pan53149872016-11-22 21:52:17 +0800436 struct spi_transfer *t)
437{
Clark Wang07d71552018-12-07 02:50:34 +0000438 struct fsl_lpspi_data *fsl_lpspi =
439 spi_controller_get_devdata(spi->controller);
Gao Pan53149872016-11-22 21:52:17 +0800440
441 fsl_lpspi->config.mode = spi->mode;
442 fsl_lpspi->config.bpw = t ? t->bits_per_word : spi->bits_per_word;
443 fsl_lpspi->config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
444 fsl_lpspi->config.chip_select = spi->chip_select;
445
446 if (!fsl_lpspi->config.speed_hz)
447 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
448 if (!fsl_lpspi->config.bpw)
449 fsl_lpspi->config.bpw = spi->bits_per_word;
450
451 /* Initialize the functions for transfer */
452 if (fsl_lpspi->config.bpw <= 8) {
453 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
454 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
455 } else if (fsl_lpspi->config.bpw <= 16) {
456 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
457 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
458 } else {
459 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
460 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
461 }
462
Clark Wangcf868742018-12-07 02:50:38 +0000463 if (t->len <= fsl_lpspi->txfifosize)
464 fsl_lpspi->watermark = t->len;
465 else
466 fsl_lpspi->watermark = fsl_lpspi->txfifosize;
467
Clark Wang09c04462019-03-06 06:30:45 +0000468 if (fsl_lpspi_can_dma(controller, spi, t))
469 fsl_lpspi->usedma = 1;
470 else
471 fsl_lpspi->usedma = 0;
472
Clark Wang77736a92019-03-06 06:30:41 +0000473 return fsl_lpspi_config(fsl_lpspi);
Gao Pan53149872016-11-22 21:52:17 +0800474}
475
Clark Wangbcd87312018-12-07 02:50:36 +0000476static int fsl_lpspi_slave_abort(struct spi_controller *controller)
477{
478 struct fsl_lpspi_data *fsl_lpspi =
479 spi_controller_get_devdata(controller);
480
481 fsl_lpspi->slave_aborted = true;
482 complete(&fsl_lpspi->xfer_done);
483 return 0;
484}
485
486static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
487{
488 struct fsl_lpspi_data *fsl_lpspi =
489 spi_controller_get_devdata(controller);
490
491 if (fsl_lpspi->is_slave) {
492 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
493 fsl_lpspi->slave_aborted) {
494 dev_dbg(fsl_lpspi->dev, "interrupted\n");
495 return -EINTR;
496 }
497 } else {
498 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
499 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
500 return -ETIMEDOUT;
501 }
502 }
503
504 return 0;
505}
506
Clark Wanga15dc3d2019-01-07 07:47:43 +0000507static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
508{
509 u32 temp;
510
Clark Wang09c04462019-03-06 06:30:45 +0000511 if (!fsl_lpspi->usedma) {
512 /* Disable all interrupt */
513 fsl_lpspi_intctrl(fsl_lpspi, 0);
514 }
Clark Wanga15dc3d2019-01-07 07:47:43 +0000515
516 /* W1C for all flags in SR */
517 temp = 0x3F << 8;
518 writel(temp, fsl_lpspi->base + IMX7ULP_SR);
519
520 /* Clear FIFO and disable module */
521 temp = CR_RRF | CR_RTF;
522 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
523
524 return 0;
525}
526
Clark Wang09c04462019-03-06 06:30:45 +0000527static void fsl_lpspi_dma_rx_callback(void *cookie)
528{
529 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
530
531 complete(&fsl_lpspi->dma_rx_completion);
532}
533
534static void fsl_lpspi_dma_tx_callback(void *cookie)
535{
536 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
537
538 complete(&fsl_lpspi->dma_tx_completion);
539}
540
541static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
542 int size)
543{
544 unsigned long timeout = 0;
545
546 /* Time with actual data transfer and CS change delay related to HW */
547 timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
548
549 /* Add extra second for scheduler related activities */
550 timeout += 1;
551
552 /* Double calculated timeout */
553 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
554}
555
556static int fsl_lpspi_dma_transfer(struct spi_controller *controller,
557 struct fsl_lpspi_data *fsl_lpspi,
558 struct spi_transfer *transfer)
559{
560 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
561 unsigned long transfer_timeout;
562 unsigned long timeout;
563 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
564 int ret;
565
566 ret = fsl_lpspi_dma_configure(controller);
567 if (ret)
568 return ret;
569
570 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
571 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
572 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
573 if (!desc_rx)
574 return -EINVAL;
575
576 desc_rx->callback = fsl_lpspi_dma_rx_callback;
577 desc_rx->callback_param = (void *)fsl_lpspi;
578 dmaengine_submit(desc_rx);
579 reinit_completion(&fsl_lpspi->dma_rx_completion);
580 dma_async_issue_pending(controller->dma_rx);
581
582 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
583 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
584 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
585 if (!desc_tx) {
586 dmaengine_terminate_all(controller->dma_tx);
587 return -EINVAL;
588 }
589
590 desc_tx->callback = fsl_lpspi_dma_tx_callback;
591 desc_tx->callback_param = (void *)fsl_lpspi;
592 dmaengine_submit(desc_tx);
593 reinit_completion(&fsl_lpspi->dma_tx_completion);
594 dma_async_issue_pending(controller->dma_tx);
595
596 fsl_lpspi->slave_aborted = false;
597
598 if (!fsl_lpspi->is_slave) {
599 transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
600 transfer->len);
601
602 /* Wait eDMA to finish the data transfer.*/
603 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
604 transfer_timeout);
605 if (!timeout) {
606 dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
607 dmaengine_terminate_all(controller->dma_tx);
608 dmaengine_terminate_all(controller->dma_rx);
609 fsl_lpspi_reset(fsl_lpspi);
610 return -ETIMEDOUT;
611 }
612
613 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
614 transfer_timeout);
615 if (!timeout) {
616 dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
617 dmaengine_terminate_all(controller->dma_tx);
618 dmaengine_terminate_all(controller->dma_rx);
619 fsl_lpspi_reset(fsl_lpspi);
620 return -ETIMEDOUT;
621 }
622 } else {
623 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
624 fsl_lpspi->slave_aborted) {
625 dev_dbg(fsl_lpspi->dev,
626 "I/O Error in DMA TX interrupted\n");
627 dmaengine_terminate_all(controller->dma_tx);
628 dmaengine_terminate_all(controller->dma_rx);
629 fsl_lpspi_reset(fsl_lpspi);
630 return -EINTR;
631 }
632
633 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
634 fsl_lpspi->slave_aborted) {
635 dev_dbg(fsl_lpspi->dev,
636 "I/O Error in DMA RX interrupted\n");
637 dmaengine_terminate_all(controller->dma_tx);
638 dmaengine_terminate_all(controller->dma_rx);
639 fsl_lpspi_reset(fsl_lpspi);
640 return -EINTR;
641 }
642 }
643
644 fsl_lpspi_reset(fsl_lpspi);
645
646 return 0;
647}
648
649static void fsl_lpspi_dma_exit(struct spi_controller *controller)
650{
651 if (controller->dma_rx) {
652 dma_release_channel(controller->dma_rx);
653 controller->dma_rx = NULL;
654 }
655
656 if (controller->dma_tx) {
657 dma_release_channel(controller->dma_tx);
658 controller->dma_tx = NULL;
659 }
660}
661
662static int fsl_lpspi_dma_init(struct device *dev,
663 struct fsl_lpspi_data *fsl_lpspi,
664 struct spi_controller *controller)
665{
666 int ret;
667
668 /* Prepare for TX DMA: */
669 controller->dma_tx = dma_request_slave_channel_reason(dev, "tx");
670 if (IS_ERR(controller->dma_tx)) {
671 ret = PTR_ERR(controller->dma_tx);
672 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
673 controller->dma_tx = NULL;
674 goto err;
675 }
676
677 /* Prepare for RX DMA: */
678 controller->dma_rx = dma_request_slave_channel_reason(dev, "rx");
679 if (IS_ERR(controller->dma_rx)) {
680 ret = PTR_ERR(controller->dma_rx);
681 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
682 controller->dma_rx = NULL;
683 goto err;
684 }
685
686 init_completion(&fsl_lpspi->dma_rx_completion);
687 init_completion(&fsl_lpspi->dma_tx_completion);
688 controller->can_dma = fsl_lpspi_can_dma;
689 controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
690
691 return 0;
692err:
693 fsl_lpspi_dma_exit(controller);
694 return ret;
695}
696
Clark Wangc7a40252019-03-06 06:30:43 +0000697static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
Gao Pan53149872016-11-22 21:52:17 +0800698 struct spi_transfer *t)
699{
Clark Wang07d71552018-12-07 02:50:34 +0000700 struct fsl_lpspi_data *fsl_lpspi =
701 spi_controller_get_devdata(controller);
Gao Pan53149872016-11-22 21:52:17 +0800702 int ret;
703
704 fsl_lpspi->tx_buf = t->tx_buf;
705 fsl_lpspi->rx_buf = t->rx_buf;
706 fsl_lpspi->remain = t->len;
707
708 reinit_completion(&fsl_lpspi->xfer_done);
Clark Wangbcd87312018-12-07 02:50:36 +0000709 fsl_lpspi->slave_aborted = false;
710
Gao Pan53149872016-11-22 21:52:17 +0800711 fsl_lpspi_write_tx_fifo(fsl_lpspi);
Gao Pand2ad0a622016-11-28 11:02:59 +0800712
Clark Wangbcd87312018-12-07 02:50:36 +0000713 ret = fsl_lpspi_wait_for_completion(controller);
714 if (ret)
715 return ret;
Gao Pan53149872016-11-22 21:52:17 +0800716
Clark Wanga15dc3d2019-01-07 07:47:43 +0000717 fsl_lpspi_reset(fsl_lpspi);
718
Gao Pand989eed2016-12-02 11:50:01 +0800719 return 0;
Gao Pan53149872016-11-22 21:52:17 +0800720}
721
Clark Wangc7a40252019-03-06 06:30:43 +0000722static int fsl_lpspi_transfer_one(struct spi_controller *controller,
723 struct spi_device *spi,
724 struct spi_transfer *t)
Gao Pan53149872016-11-22 21:52:17 +0800725{
Clark Wang07d71552018-12-07 02:50:34 +0000726 struct fsl_lpspi_data *fsl_lpspi =
Clark Wangc7a40252019-03-06 06:30:43 +0000727 spi_controller_get_devdata(controller);
728 int ret;
Gao Pan53149872016-11-22 21:52:17 +0800729
Clark Wangc7a40252019-03-06 06:30:43 +0000730 fsl_lpspi->is_first_byte = true;
Clark Wang09c04462019-03-06 06:30:45 +0000731 ret = fsl_lpspi_setup_transfer(controller, spi, t);
Clark Wangc7a40252019-03-06 06:30:43 +0000732 if (ret < 0)
733 return ret;
Gao Pan53149872016-11-22 21:52:17 +0800734
Clark Wangc7a40252019-03-06 06:30:43 +0000735 fsl_lpspi_set_cmd(fsl_lpspi);
736 fsl_lpspi->is_first_byte = false;
Clark Wang77736a92019-03-06 06:30:41 +0000737
Clark Wang09c04462019-03-06 06:30:45 +0000738 if (fsl_lpspi->usedma)
739 ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
740 else
741 ret = fsl_lpspi_pio_transfer(controller, t);
Clark Wangc7a40252019-03-06 06:30:43 +0000742 if (ret < 0)
743 return ret;
Gao Pan53149872016-11-22 21:52:17 +0800744
Clark Wangc7a40252019-03-06 06:30:43 +0000745 return 0;
Gao Pan53149872016-11-22 21:52:17 +0800746}
747
748static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
749{
Clark Wangc23fdef2019-01-07 07:47:38 +0000750 u32 temp_SR, temp_IER;
Gao Pan53149872016-11-22 21:52:17 +0800751 struct fsl_lpspi_data *fsl_lpspi = dev_id;
Gao Pan53149872016-11-22 21:52:17 +0800752
Clark Wangc23fdef2019-01-07 07:47:38 +0000753 temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
Gao Pan53149872016-11-22 21:52:17 +0800754 fsl_lpspi_intctrl(fsl_lpspi, 0);
Clark Wangc23fdef2019-01-07 07:47:38 +0000755 temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
Gao Pan53149872016-11-22 21:52:17 +0800756
757 fsl_lpspi_read_rx_fifo(fsl_lpspi);
758
Clark Wangc23fdef2019-01-07 07:47:38 +0000759 if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
Gao Pan53149872016-11-22 21:52:17 +0800760 fsl_lpspi_write_tx_fifo(fsl_lpspi);
Clark Wangc23fdef2019-01-07 07:47:38 +0000761 return IRQ_HANDLED;
762 }
Gao Pan53149872016-11-22 21:52:17 +0800763
Clark Wang6a130442019-01-07 07:47:41 +0000764 if (temp_SR & SR_MBF ||
765 readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_RXCOUNT) {
766 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
767 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
768 return IRQ_HANDLED;
769 }
770
Clark Wangc23fdef2019-01-07 07:47:38 +0000771 if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
772 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
Gao Pan53149872016-11-22 21:52:17 +0800773 complete(&fsl_lpspi->xfer_done);
Gao Pan53149872016-11-22 21:52:17 +0800774 return IRQ_HANDLED;
775 }
776
777 return IRQ_NONE;
778}
779
Han Xu944c01a2019-03-06 06:30:39 +0000780int fsl_lpspi_runtime_resume(struct device *dev)
781{
782 struct fsl_lpspi_data *fsl_lpspi = dev_get_drvdata(dev);
783 int ret;
784
785 ret = clk_prepare_enable(fsl_lpspi->clk_per);
786 if (ret)
787 return ret;
788
789 ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
790 if (ret) {
791 clk_disable_unprepare(fsl_lpspi->clk_per);
792 return ret;
793 }
794
795 return 0;
796}
797
798int fsl_lpspi_runtime_suspend(struct device *dev)
799{
800 struct fsl_lpspi_data *fsl_lpspi = dev_get_drvdata(dev);
801
802 clk_disable_unprepare(fsl_lpspi->clk_per);
803 clk_disable_unprepare(fsl_lpspi->clk_ipg);
804
805 return 0;
806}
807
808static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
809{
810 struct device *dev = fsl_lpspi->dev;
811
812 pm_runtime_enable(dev);
813 pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT);
814 pm_runtime_use_autosuspend(dev);
815
816 return 0;
817}
818
Gao Pan53149872016-11-22 21:52:17 +0800819static int fsl_lpspi_probe(struct platform_device *pdev)
820{
Clark Wangc7a40252019-03-06 06:30:43 +0000821 struct device_node *np = pdev->dev.of_node;
Gao Pan53149872016-11-22 21:52:17 +0800822 struct fsl_lpspi_data *fsl_lpspi;
Clark Wang07d71552018-12-07 02:50:34 +0000823 struct spi_controller *controller;
Clark Wangc7a40252019-03-06 06:30:43 +0000824 struct spi_imx_master *lpspi_platform_info =
825 dev_get_platdata(&pdev->dev);
Gao Pan53149872016-11-22 21:52:17 +0800826 struct resource *res;
Clark Wangc7a40252019-03-06 06:30:43 +0000827 int i, ret, irq;
Gao Panb88a0de2016-11-28 11:03:00 +0800828 u32 temp;
Gao Pan53149872016-11-22 21:52:17 +0800829
Clark Wangbcd87312018-12-07 02:50:36 +0000830 if (of_property_read_bool((&pdev->dev)->of_node, "spi-slave"))
831 controller = spi_alloc_slave(&pdev->dev,
Clark Wang07d71552018-12-07 02:50:34 +0000832 sizeof(struct fsl_lpspi_data));
Clark Wangbcd87312018-12-07 02:50:36 +0000833 else
834 controller = spi_alloc_master(&pdev->dev,
835 sizeof(struct fsl_lpspi_data));
836
Clark Wang07d71552018-12-07 02:50:34 +0000837 if (!controller)
Gao Pan53149872016-11-22 21:52:17 +0800838 return -ENOMEM;
839
Clark Wang07d71552018-12-07 02:50:34 +0000840 platform_set_drvdata(pdev, controller);
Gao Pan53149872016-11-22 21:52:17 +0800841
Clark Wang07d71552018-12-07 02:50:34 +0000842 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
843 controller->bus_num = pdev->id;
Gao Pan53149872016-11-22 21:52:17 +0800844
Clark Wang07d71552018-12-07 02:50:34 +0000845 fsl_lpspi = spi_controller_get_devdata(controller);
Gao Pan53149872016-11-22 21:52:17 +0800846 fsl_lpspi->dev = &pdev->dev;
Han Xu944c01a2019-03-06 06:30:39 +0000847 dev_set_drvdata(&pdev->dev, fsl_lpspi);
Clark Wangbcd87312018-12-07 02:50:36 +0000848 fsl_lpspi->is_slave = of_property_read_bool((&pdev->dev)->of_node,
849 "spi-slave");
Gao Pan53149872016-11-22 21:52:17 +0800850
Clark Wangc7a40252019-03-06 06:30:43 +0000851 if (!fsl_lpspi->is_slave) {
852 for (i = 0; i < controller->num_chipselect; i++) {
853 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
854
855 if (!gpio_is_valid(cs_gpio) && lpspi_platform_info)
856 cs_gpio = lpspi_platform_info->chipselect[i];
857
858 fsl_lpspi->chipselect[i] = cs_gpio;
859 if (!gpio_is_valid(cs_gpio))
860 continue;
861
862 ret = devm_gpio_request(&pdev->dev,
863 fsl_lpspi->chipselect[i],
864 DRIVER_NAME);
865 if (ret) {
866 dev_err(&pdev->dev, "can't get cs gpios\n");
867 goto out_controller_put;
868 }
869 }
870 controller->cs_gpios = fsl_lpspi->chipselect;
871 controller->prepare_message = fsl_lpspi_prepare_message;
872 }
873
874 controller->transfer_one = fsl_lpspi_transfer_one;
Clark Wang07d71552018-12-07 02:50:34 +0000875 controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
876 controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
877 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
878 controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
879 controller->dev.of_node = pdev->dev.of_node;
880 controller->bus_num = pdev->id;
Clark Wangbcd87312018-12-07 02:50:36 +0000881 controller->slave_abort = fsl_lpspi_slave_abort;
Gao Pan53149872016-11-22 21:52:17 +0800882
883 init_completion(&fsl_lpspi->xfer_done);
884
885 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
886 fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res);
887 if (IS_ERR(fsl_lpspi->base)) {
888 ret = PTR_ERR(fsl_lpspi->base);
Clark Wang07d71552018-12-07 02:50:34 +0000889 goto out_controller_put;
Gao Pan53149872016-11-22 21:52:17 +0800890 }
Clark Wang09c04462019-03-06 06:30:45 +0000891 fsl_lpspi->base_phys = res->start;
Gao Pan53149872016-11-22 21:52:17 +0800892
893 irq = platform_get_irq(pdev, 0);
894 if (irq < 0) {
895 ret = irq;
Clark Wang07d71552018-12-07 02:50:34 +0000896 goto out_controller_put;
Gao Pan53149872016-11-22 21:52:17 +0800897 }
898
899 ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
900 dev_name(&pdev->dev), fsl_lpspi);
901 if (ret) {
902 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
Clark Wang07d71552018-12-07 02:50:34 +0000903 goto out_controller_put;
Gao Pan53149872016-11-22 21:52:17 +0800904 }
905
Clark Wangf5e5afd2019-03-06 06:30:34 +0000906 fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
907 if (IS_ERR(fsl_lpspi->clk_per)) {
908 ret = PTR_ERR(fsl_lpspi->clk_per);
Clark Wang07d71552018-12-07 02:50:34 +0000909 goto out_controller_put;
Gao Pan53149872016-11-22 21:52:17 +0800910 }
911
Clark Wangf5e5afd2019-03-06 06:30:34 +0000912 fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
913 if (IS_ERR(fsl_lpspi->clk_ipg)) {
914 ret = PTR_ERR(fsl_lpspi->clk_ipg);
915 goto out_controller_put;
916 }
917
Han Xu944c01a2019-03-06 06:30:39 +0000918 /* enable the clock */
919 ret = fsl_lpspi_init_rpm(fsl_lpspi);
920 if (ret)
Clark Wangf5e5afd2019-03-06 06:30:34 +0000921 goto out_controller_put;
Clark Wangf5e5afd2019-03-06 06:30:34 +0000922
Han Xu944c01a2019-03-06 06:30:39 +0000923 ret = pm_runtime_get_sync(fsl_lpspi->dev);
924 if (ret < 0) {
925 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
926 return ret;
Gao Panb88a0de2016-11-28 11:03:00 +0800927 }
928
929 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
930 fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
931 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
932
Clark Wang09c04462019-03-06 06:30:45 +0000933 ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
934 if (ret == -EPROBE_DEFER)
935 goto out_controller_put;
936
937 if (ret < 0)
938 dev_err(&pdev->dev, "dma setup error %d, use pio\n", ret);
939
Clark Wang07d71552018-12-07 02:50:34 +0000940 ret = devm_spi_register_controller(&pdev->dev, controller);
Gao Pan53149872016-11-22 21:52:17 +0800941 if (ret < 0) {
Clark Wang07d71552018-12-07 02:50:34 +0000942 dev_err(&pdev->dev, "spi_register_controller error.\n");
943 goto out_controller_put;
Gao Pan53149872016-11-22 21:52:17 +0800944 }
945
946 return 0;
947
Clark Wang07d71552018-12-07 02:50:34 +0000948out_controller_put:
949 spi_controller_put(controller);
Gao Pan53149872016-11-22 21:52:17 +0800950
951 return ret;
952}
953
954static int fsl_lpspi_remove(struct platform_device *pdev)
955{
Clark Wang07d71552018-12-07 02:50:34 +0000956 struct spi_controller *controller = platform_get_drvdata(pdev);
957 struct fsl_lpspi_data *fsl_lpspi =
958 spi_controller_get_devdata(controller);
Gao Pan53149872016-11-22 21:52:17 +0800959
Han Xu944c01a2019-03-06 06:30:39 +0000960 pm_runtime_disable(fsl_lpspi->dev);
961
962 spi_master_put(controller);
Gao Pan53149872016-11-22 21:52:17 +0800963
964 return 0;
965}
966
Han Xu944c01a2019-03-06 06:30:39 +0000967#ifdef CONFIG_PM_SLEEP
968static int fsl_lpspi_suspend(struct device *dev)
969{
970 int ret;
971
972 pinctrl_pm_select_sleep_state(dev);
973 ret = pm_runtime_force_suspend(dev);
974 return ret;
975}
976
977static int fsl_lpspi_resume(struct device *dev)
978{
979 int ret;
980
981 ret = pm_runtime_force_resume(dev);
982 if (ret) {
983 dev_err(dev, "Error in resume: %d\n", ret);
984 return ret;
985 }
986
987 pinctrl_pm_select_default_state(dev);
988
989 return 0;
990}
991#endif /* CONFIG_PM_SLEEP */
992
993static const struct dev_pm_ops fsl_lpspi_pm_ops = {
994 SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend,
995 fsl_lpspi_runtime_resume, NULL)
996 SET_SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume)
997};
998
Gao Pan53149872016-11-22 21:52:17 +0800999static struct platform_driver fsl_lpspi_driver = {
1000 .driver = {
Gao Pan102ecc472017-01-04 17:38:16 +08001001 .name = DRIVER_NAME,
1002 .of_match_table = fsl_lpspi_dt_ids,
Han Xu944c01a2019-03-06 06:30:39 +00001003 .pm = &fsl_lpspi_pm_ops,
Gao Pan102ecc472017-01-04 17:38:16 +08001004 },
Gao Pan53149872016-11-22 21:52:17 +08001005 .probe = fsl_lpspi_probe,
1006 .remove = fsl_lpspi_remove,
1007};
1008module_platform_driver(fsl_lpspi_driver);
1009
Clark Wang07d71552018-12-07 02:50:34 +00001010MODULE_DESCRIPTION("LPSPI Controller driver");
Gao Pan53149872016-11-22 21:52:17 +08001011MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
Gao Panb6787b62016-12-02 11:50:00 +08001012MODULE_LICENSE("GPL");