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Philippe Reynes632506a2012-11-12 21:28:33 +01001/*
2 * Copyright 2012 Philippe Reynes <tremyfr@yahoo.fr>
3 * Copyright 2012 Armadeus Systems <support@armadeus.com>
4 *
5 * Based on code which is: Copyright 2012 Sascha Hauer, Pengutronix
6 *
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14
15/dts-v1/;
Shawn Guo36dffd82013-04-07 10:49:34 +080016#include "imx27.dtsi"
Philippe Reynes632506a2012-11-12 21:28:33 +010017
18/ {
19 model = "Armadeus Systems APF27 module";
20 compatible = "armadeus,imx27-apf27", "fsl,imx27";
21
Marco Franchiad00e082018-01-24 11:22:14 -020022 memory@a0000000 {
Philippe Reynes632506a2012-11-12 21:28:33 +010023 reg = <0xa0000000 0x04000000>;
24 };
Shawn Guo0c414b02018-05-04 08:16:04 +080025};
Philippe Reynes632506a2012-11-12 21:28:33 +010026
Shawn Guo0c414b02018-05-04 08:16:04 +080027&clk_osc26m {
28 clock-frequency = <0>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +080029};
Philippe Reynes632506a2012-11-12 21:28:33 +010030
Gwenhael Goavec-Merou7672d8e2013-11-28 08:19:31 +010031&iomuxc {
32 imx27-apf27 {
33 pinctrl_fec1: fec1grp {
34 fsl,pins = <
35 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
36 MX27_PAD_SD3_CLK__FEC_TXD1 0x0
37 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
38 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
39 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
40 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
41 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
42 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
43 MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
44 MX27_PAD_ATA_DATA7__FEC_MDC 0x0
45 MX27_PAD_ATA_DATA8__FEC_CRS 0x0
46 MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
47 MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
48 MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
49 MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
50 MX27_PAD_ATA_DATA13__FEC_COL 0x0
51 MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
52 MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
53 >;
54 };
55
56 pinctrl_uart1: uart1grp {
57 fsl,pins = <
58 MX27_PAD_UART1_TXD__UART1_TXD 0x0
59 MX27_PAD_UART1_RXD__UART1_RXD 0x0
60 >;
61 };
62 };
63};
64
Shawn Guobe4ccfc2012-12-31 11:32:48 +080065&uart1 {
Gwenhael Goavec-Merou7672d8e2013-11-28 08:19:31 +010066 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_uart1>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +080068 status = "okay";
69};
Philippe Reynes632506a2012-11-12 21:28:33 +010070
Shawn Guobe4ccfc2012-12-31 11:32:48 +080071&fec {
Gwenhael Goavec-Merou7672d8e2013-11-28 08:19:31 +010072 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_fec1>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +080074 status = "okay";
75};
Philippe Reynes632506a2012-11-12 21:28:33 +010076
Shawn Guobe4ccfc2012-12-31 11:32:48 +080077&nfc {
78 status = "okay";
79 nand-bus-width = <16>;
80 nand-ecc-mode = "hw";
81 nand-on-flash-bbt;
Philippe Reynes632506a2012-11-12 21:28:33 +010082
Shawn Guobe4ccfc2012-12-31 11:32:48 +080083 partition@0 {
84 label = "u-boot";
85 reg = <0x0 0x100000>;
86 };
Philippe Reynes632506a2012-11-12 21:28:33 +010087
Shawn Guobe4ccfc2012-12-31 11:32:48 +080088 partition@100000 {
89 label = "env";
90 reg = <0x100000 0x80000>;
91 };
Philippe Reynes632506a2012-11-12 21:28:33 +010092
Shawn Guobe4ccfc2012-12-31 11:32:48 +080093 partition@180000 {
94 label = "env2";
95 reg = <0x180000 0x80000>;
96 };
Philippe Reynes632506a2012-11-12 21:28:33 +010097
Shawn Guobe4ccfc2012-12-31 11:32:48 +080098 partition@200000 {
99 label = "firmware";
100 reg = <0x200000 0x80000>;
101 };
Philippe Reynes632506a2012-11-12 21:28:33 +0100102
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800103 partition@280000 {
104 label = "dtb";
105 reg = <0x280000 0x80000>;
106 };
Philippe Reynes632506a2012-11-12 21:28:33 +0100107
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800108 partition@300000 {
109 label = "kernel";
110 reg = <0x300000 0x500000>;
111 };
Philippe Reynes632506a2012-11-12 21:28:33 +0100112
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800113 partition@800000 {
114 label = "rootfs";
115 reg = <0x800000 0xf800000>;
Philippe Reynes632506a2012-11-12 21:28:33 +0100116 };
117};