Boris Brezillon | 10d4e75 | 2016-06-08 10:38:57 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2017 Free Electrons |
| 3 | * Copyright (C) 2017 NextThing Co |
| 4 | * |
| 5 | * Author: Boris Brezillon <boris.brezillon@free-electrons.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
Boris Brezillon | d4092d7 | 2017-08-04 17:29:10 +0200 | [diff] [blame] | 18 | #include <linux/mtd/rawnand.h> |
Boris Brezillon | 10d4e75 | 2016-06-08 10:38:57 +0200 | [diff] [blame] | 19 | |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 20 | /* |
| 21 | * Special Micron status bit that indicates when the block has been |
| 22 | * corrected by on-die ECC and should be rewritten |
| 23 | */ |
| 24 | #define NAND_STATUS_WRITE_RECOMMENDED BIT(3) |
| 25 | |
Boris Brezillon | 10d4e75 | 2016-06-08 10:38:57 +0200 | [diff] [blame] | 26 | struct nand_onfi_vendor_micron { |
| 27 | u8 two_plane_read; |
| 28 | u8 read_cache; |
| 29 | u8 read_unique_id; |
| 30 | u8 dq_imped; |
| 31 | u8 dq_imped_num_settings; |
| 32 | u8 dq_imped_feat_addr; |
| 33 | u8 rb_pulldown_strength; |
| 34 | u8 rb_pulldown_strength_feat_addr; |
| 35 | u8 rb_pulldown_strength_num_settings; |
| 36 | u8 otp_mode; |
| 37 | u8 otp_page_start; |
| 38 | u8 otp_data_prot_addr; |
| 39 | u8 otp_num_pages; |
| 40 | u8 otp_feat_addr; |
| 41 | u8 read_retry_options; |
| 42 | u8 reserved[72]; |
| 43 | u8 param_revision; |
| 44 | } __packed; |
| 45 | |
| 46 | static int micron_nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) |
| 47 | { |
| 48 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 49 | u8 feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; |
| 50 | |
Miquel Raynal | 97baea1 | 2018-03-19 14:47:20 +0100 | [diff] [blame] | 51 | return nand_set_features(chip, ONFI_FEATURE_ADDR_READ_RETRY, feature); |
Boris Brezillon | 10d4e75 | 2016-06-08 10:38:57 +0200 | [diff] [blame] | 52 | } |
| 53 | |
| 54 | /* |
| 55 | * Configure chip properties from Micron vendor-specific ONFI table |
| 56 | */ |
| 57 | static int micron_nand_onfi_init(struct nand_chip *chip) |
| 58 | { |
Miquel Raynal | a97421c | 2018-03-19 14:47:27 +0100 | [diff] [blame] | 59 | struct nand_parameters *p = &chip->parameters; |
| 60 | struct nand_onfi_vendor_micron *micron = (void *)p->onfi.vendor; |
Boris Brezillon | 10d4e75 | 2016-06-08 10:38:57 +0200 | [diff] [blame] | 61 | |
Miquel Raynal | a97421c | 2018-03-19 14:47:27 +0100 | [diff] [blame] | 62 | if (chip->parameters.onfi.version && p->onfi.vendor_revision) { |
| 63 | chip->read_retries = micron->read_retry_options; |
| 64 | chip->setup_read_retry = micron_nand_setup_read_retry; |
| 65 | } |
Boris Brezillon | 10d4e75 | 2016-06-08 10:38:57 +0200 | [diff] [blame] | 66 | |
Miquel Raynal | 789157e | 2018-03-19 14:47:28 +0100 | [diff] [blame] | 67 | if (p->supports_set_get_features) { |
| 68 | set_bit(ONFI_FEATURE_ADDR_READ_RETRY, p->set_feature_list); |
Chris Packham | 12baf77 | 2018-06-19 17:31:24 +1200 | [diff] [blame^] | 69 | set_bit(ONFI_FEATURE_ON_DIE_ECC, p->set_feature_list); |
Miquel Raynal | 789157e | 2018-03-19 14:47:28 +0100 | [diff] [blame] | 70 | set_bit(ONFI_FEATURE_ADDR_READ_RETRY, p->get_feature_list); |
Chris Packham | 12baf77 | 2018-06-19 17:31:24 +1200 | [diff] [blame^] | 71 | set_bit(ONFI_FEATURE_ON_DIE_ECC, p->get_feature_list); |
Miquel Raynal | 789157e | 2018-03-19 14:47:28 +0100 | [diff] [blame] | 72 | } |
Boris Brezillon | 10d4e75 | 2016-06-08 10:38:57 +0200 | [diff] [blame] | 73 | |
| 74 | return 0; |
| 75 | } |
| 76 | |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 77 | static int micron_nand_on_die_ooblayout_ecc(struct mtd_info *mtd, int section, |
| 78 | struct mtd_oob_region *oobregion) |
| 79 | { |
| 80 | if (section >= 4) |
| 81 | return -ERANGE; |
| 82 | |
| 83 | oobregion->offset = (section * 16) + 8; |
| 84 | oobregion->length = 8; |
| 85 | |
| 86 | return 0; |
| 87 | } |
| 88 | |
| 89 | static int micron_nand_on_die_ooblayout_free(struct mtd_info *mtd, int section, |
| 90 | struct mtd_oob_region *oobregion) |
| 91 | { |
| 92 | if (section >= 4) |
| 93 | return -ERANGE; |
| 94 | |
| 95 | oobregion->offset = (section * 16) + 2; |
| 96 | oobregion->length = 6; |
| 97 | |
| 98 | return 0; |
| 99 | } |
| 100 | |
| 101 | static const struct mtd_ooblayout_ops micron_nand_on_die_ooblayout_ops = { |
| 102 | .ecc = micron_nand_on_die_ooblayout_ecc, |
| 103 | .free = micron_nand_on_die_ooblayout_free, |
| 104 | }; |
| 105 | |
| 106 | static int micron_nand_on_die_ecc_setup(struct nand_chip *chip, bool enable) |
| 107 | { |
| 108 | u8 feature[ONFI_SUBFEATURE_PARAM_LEN] = { 0, }; |
| 109 | |
| 110 | if (enable) |
| 111 | feature[0] |= ONFI_FEATURE_ON_DIE_ECC_EN; |
| 112 | |
Miquel Raynal | 97baea1 | 2018-03-19 14:47:20 +0100 | [diff] [blame] | 113 | return nand_set_features(chip, ONFI_FEATURE_ON_DIE_ECC, feature); |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 114 | } |
| 115 | |
| 116 | static int |
| 117 | micron_nand_read_page_on_die_ecc(struct mtd_info *mtd, struct nand_chip *chip, |
| 118 | uint8_t *buf, int oob_required, |
| 119 | int page) |
| 120 | { |
Boris Brezillon | 97d90da | 2017-11-30 18:01:29 +0100 | [diff] [blame] | 121 | u8 status; |
| 122 | int ret, max_bitflips = 0; |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 123 | |
Boris Brezillon | 97d90da | 2017-11-30 18:01:29 +0100 | [diff] [blame] | 124 | ret = micron_nand_on_die_ecc_setup(chip, true); |
| 125 | if (ret) |
| 126 | return ret; |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 127 | |
Boris Brezillon | 97d90da | 2017-11-30 18:01:29 +0100 | [diff] [blame] | 128 | ret = nand_read_page_op(chip, page, 0, NULL, 0); |
| 129 | if (ret) |
| 130 | goto out; |
| 131 | |
| 132 | ret = nand_status_op(chip, &status); |
| 133 | if (ret) |
| 134 | goto out; |
| 135 | |
| 136 | ret = nand_exit_status_op(chip); |
| 137 | if (ret) |
| 138 | goto out; |
| 139 | |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 140 | if (status & NAND_STATUS_FAIL) |
| 141 | mtd->ecc_stats.failed++; |
Boris Brezillon | 97d90da | 2017-11-30 18:01:29 +0100 | [diff] [blame] | 142 | |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 143 | /* |
| 144 | * The internal ECC doesn't tell us the number of bitflips |
| 145 | * that have been corrected, but tells us if it recommends to |
| 146 | * rewrite the block. If it's the case, then we pretend we had |
| 147 | * a number of bitflips equal to the ECC strength, which will |
| 148 | * hint the NAND core to rewrite the block. |
| 149 | */ |
| 150 | else if (status & NAND_STATUS_WRITE_RECOMMENDED) |
| 151 | max_bitflips = chip->ecc.strength; |
| 152 | |
Boris Brezillon | 25f815f | 2017-11-30 18:01:30 +0100 | [diff] [blame] | 153 | ret = nand_read_data_op(chip, buf, mtd->writesize, false); |
| 154 | if (!ret && oob_required) |
| 155 | ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, |
| 156 | false); |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 157 | |
Boris Brezillon | 97d90da | 2017-11-30 18:01:29 +0100 | [diff] [blame] | 158 | out: |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 159 | micron_nand_on_die_ecc_setup(chip, false); |
| 160 | |
Boris Brezillon | 97d90da | 2017-11-30 18:01:29 +0100 | [diff] [blame] | 161 | return ret ? ret : max_bitflips; |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 162 | } |
| 163 | |
| 164 | static int |
| 165 | micron_nand_write_page_on_die_ecc(struct mtd_info *mtd, struct nand_chip *chip, |
| 166 | const uint8_t *buf, int oob_required, |
| 167 | int page) |
| 168 | { |
Boris Brezillon | 97d90da | 2017-11-30 18:01:29 +0100 | [diff] [blame] | 169 | int ret; |
Boris Brezillon | 4114564 | 2017-05-16 18:27:49 +0200 | [diff] [blame] | 170 | |
Boris Brezillon | 97d90da | 2017-11-30 18:01:29 +0100 | [diff] [blame] | 171 | ret = micron_nand_on_die_ecc_setup(chip, true); |
| 172 | if (ret) |
| 173 | return ret; |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 174 | |
Boris Brezillon | 97d90da | 2017-11-30 18:01:29 +0100 | [diff] [blame] | 175 | ret = nand_write_page_raw(mtd, chip, buf, oob_required, page); |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 176 | micron_nand_on_die_ecc_setup(chip, false); |
| 177 | |
Boris Brezillon | 97d90da | 2017-11-30 18:01:29 +0100 | [diff] [blame] | 178 | return ret; |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 179 | } |
| 180 | |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 181 | enum { |
| 182 | /* The NAND flash doesn't support on-die ECC */ |
| 183 | MICRON_ON_DIE_UNSUPPORTED, |
| 184 | |
| 185 | /* |
| 186 | * The NAND flash supports on-die ECC and it can be |
| 187 | * enabled/disabled by a set features command. |
| 188 | */ |
| 189 | MICRON_ON_DIE_SUPPORTED, |
| 190 | |
| 191 | /* |
| 192 | * The NAND flash supports on-die ECC, and it cannot be |
| 193 | * disabled. |
| 194 | */ |
| 195 | MICRON_ON_DIE_MANDATORY, |
| 196 | }; |
| 197 | |
| 198 | /* |
| 199 | * Try to detect if the NAND support on-die ECC. To do this, we enable |
| 200 | * the feature, and read back if it has been enabled as expected. We |
| 201 | * also check if it can be disabled, because some Micron NANDs do not |
| 202 | * allow disabling the on-die ECC and we don't support such NANDs for |
| 203 | * now. |
| 204 | * |
| 205 | * This function also has the side effect of disabling on-die ECC if |
| 206 | * it had been left enabled by the firmware/bootloader. |
| 207 | */ |
| 208 | static int micron_supports_on_die_ecc(struct nand_chip *chip) |
| 209 | { |
| 210 | u8 feature[ONFI_SUBFEATURE_PARAM_LEN] = { 0, }; |
| 211 | int ret; |
| 212 | |
Miquel Raynal | a97421c | 2018-03-19 14:47:27 +0100 | [diff] [blame] | 213 | if (!chip->parameters.onfi.version) |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 214 | return MICRON_ON_DIE_UNSUPPORTED; |
| 215 | |
| 216 | if (chip->bits_per_cell != 1) |
| 217 | return MICRON_ON_DIE_UNSUPPORTED; |
| 218 | |
| 219 | ret = micron_nand_on_die_ecc_setup(chip, true); |
| 220 | if (ret) |
| 221 | return MICRON_ON_DIE_UNSUPPORTED; |
| 222 | |
Miquel Raynal | 97baea1 | 2018-03-19 14:47:20 +0100 | [diff] [blame] | 223 | ret = nand_get_features(chip, ONFI_FEATURE_ON_DIE_ECC, feature); |
| 224 | if (ret < 0) |
| 225 | return ret; |
| 226 | |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 227 | if ((feature[0] & ONFI_FEATURE_ON_DIE_ECC_EN) == 0) |
| 228 | return MICRON_ON_DIE_UNSUPPORTED; |
| 229 | |
| 230 | ret = micron_nand_on_die_ecc_setup(chip, false); |
| 231 | if (ret) |
| 232 | return MICRON_ON_DIE_UNSUPPORTED; |
| 233 | |
Miquel Raynal | 97baea1 | 2018-03-19 14:47:20 +0100 | [diff] [blame] | 234 | ret = nand_get_features(chip, ONFI_FEATURE_ON_DIE_ECC, feature); |
| 235 | if (ret < 0) |
| 236 | return ret; |
| 237 | |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 238 | if (feature[0] & ONFI_FEATURE_ON_DIE_ECC_EN) |
| 239 | return MICRON_ON_DIE_MANDATORY; |
| 240 | |
| 241 | /* |
| 242 | * Some Micron NANDs have an on-die ECC of 4/512, some other |
| 243 | * 8/512. We only support the former. |
| 244 | */ |
Miquel Raynal | a97421c | 2018-03-19 14:47:27 +0100 | [diff] [blame] | 245 | if (chip->ecc_strength_ds != 4) |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 246 | return MICRON_ON_DIE_UNSUPPORTED; |
| 247 | |
| 248 | return MICRON_ON_DIE_SUPPORTED; |
| 249 | } |
| 250 | |
Boris Brezillon | 10d4e75 | 2016-06-08 10:38:57 +0200 | [diff] [blame] | 251 | static int micron_nand_init(struct nand_chip *chip) |
| 252 | { |
| 253 | struct mtd_info *mtd = nand_to_mtd(chip); |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 254 | int ondie; |
Boris Brezillon | 10d4e75 | 2016-06-08 10:38:57 +0200 | [diff] [blame] | 255 | int ret; |
| 256 | |
| 257 | ret = micron_nand_onfi_init(chip); |
| 258 | if (ret) |
| 259 | return ret; |
| 260 | |
| 261 | if (mtd->writesize == 2048) |
| 262 | chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; |
| 263 | |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 264 | ondie = micron_supports_on_die_ecc(chip); |
| 265 | |
| 266 | if (ondie == MICRON_ON_DIE_MANDATORY) { |
| 267 | pr_err("On-die ECC forcefully enabled, not supported\n"); |
| 268 | return -EINVAL; |
| 269 | } |
| 270 | |
| 271 | if (chip->ecc.mode == NAND_ECC_ON_DIE) { |
| 272 | if (ondie == MICRON_ON_DIE_UNSUPPORTED) { |
| 273 | pr_err("On-die ECC selected but not supported\n"); |
| 274 | return -EINVAL; |
| 275 | } |
| 276 | |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 277 | chip->ecc.bytes = 8; |
| 278 | chip->ecc.size = 512; |
| 279 | chip->ecc.strength = 4; |
| 280 | chip->ecc.algo = NAND_ECC_BCH; |
| 281 | chip->ecc.read_page = micron_nand_read_page_on_die_ecc; |
| 282 | chip->ecc.write_page = micron_nand_write_page_on_die_ecc; |
Boris Brezillon | 25f815f | 2017-11-30 18:01:30 +0100 | [diff] [blame] | 283 | chip->ecc.read_page_raw = nand_read_page_raw; |
| 284 | chip->ecc.write_page_raw = nand_write_page_raw; |
Thomas Petazzoni | 9748e1d | 2017-04-29 11:06:45 +0200 | [diff] [blame] | 285 | |
| 286 | mtd_set_ooblayout(mtd, µn_nand_on_die_ooblayout_ops); |
| 287 | } |
| 288 | |
Boris Brezillon | 10d4e75 | 2016-06-08 10:38:57 +0200 | [diff] [blame] | 289 | return 0; |
| 290 | } |
| 291 | |
| 292 | const struct nand_manufacturer_ops micron_nand_manuf_ops = { |
| 293 | .init = micron_nand_init, |
| 294 | }; |