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git.odroid.com / yocto / kernel / common / 29bc643ddd7efb741d07c8b2d9a4c3dd9228865b / . / sound / soc / codecs / rt1305.c
blob: 90baab91d11b7b01bc8bb662c468ee4258c8ce0f [file] [log] [blame]
Shuming Fan29bc6432018-03-29 20:05:14 +0800[diff] [blame^]1/*
2 * rt1305.c -- RT1305 ALSA SoC amplifier component driver
3 *
4 * Copyright 2018 Realtek Semiconductor Corp.
5 * Author: Shuming Fan <shumingf@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/gpio.h>
18#include <linux/i2c.h>
19#include <linux/regmap.h>
20#include <linux/of_gpio.h>
21#include <linux/platform_device.h>
22#include <linux/firmware.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
30
31#include "rl6231.h"
32#include "rt1305.h"
33
34
35#define RT1305_PR_RANGE_BASE (0xff + 1)
36#define RT1305_PR_SPACING 0x100
37
38#define RT1305_PR_BASE (RT1305_PR_RANGE_BASE + (0 * RT1305_PR_SPACING))
39
40
41static const struct regmap_range_cfg rt1305_ranges[] = {
42 {
43 .name = "PR",
44 .range_min = RT1305_PR_BASE,
45 .range_max = RT1305_PR_BASE + 0xff,
46 .selector_reg = RT1305_PRIV_INDEX,
47 .selector_mask = 0xff,
48 .selector_shift = 0x0,
49 .window_start = RT1305_PRIV_DATA,
50 .window_len = 0x1,
51 },
52};
53
54
55static const struct reg_sequence init_list[] = {
56
57 { RT1305_PR_BASE + 0xcf, 0x5548 },
58 { RT1305_PR_BASE + 0x5d, 0x0442 },
59 { RT1305_PR_BASE + 0xc1, 0x0320 },
60
61 { RT1305_POWER_STATUS, 0x0000 },
62
63 { RT1305_SPK_TEMP_PROTECTION_1, 0xd6de },
64 { RT1305_SPK_TEMP_PROTECTION_2, 0x0707 },
65 { RT1305_SPK_TEMP_PROTECTION_3, 0x4090 },
66
67 { RT1305_DAC_SET_1, 0xdfdf }, /* 4 ohm 2W */
68 { RT1305_ADC_SET_3, 0x0219 },
69 { RT1305_ADC_SET_1, 0x170f }, /* 0.2 ohm RSense*/
70
71};
72#define RT1305_INIT_REG_LEN ARRAY_SIZE(init_list)
73
74struct rt1305_priv {
75 struct snd_soc_component *component;
76 struct regmap *regmap;
77
78 int sysclk;
79 int sysclk_src;
80 int lrck;
81 int bclk;
82 int master;
83
84 int pll_src;
85 int pll_in;
86 int pll_out;
87};
88
89static const struct reg_default rt1305_reg[] = {
90
91 { 0x04, 0x0400 },
92 { 0x05, 0x0880 },
93 { 0x06, 0x0000 },
94 { 0x07, 0x3100 },
95 { 0x08, 0x8000 },
96 { 0x09, 0x0000 },
97 { 0x0a, 0x087e },
98 { 0x0b, 0x0020 },
99 { 0x0c, 0x0802 },
100 { 0x0d, 0x0020 },
101 { 0x10, 0x1d1d },
102 { 0x11, 0x1d1d },
103 { 0x12, 0xffff },
104 { 0x14, 0x000c },
105 { 0x16, 0x1717 },
106 { 0x17, 0x4000 },
107 { 0x18, 0x0019 },
108 { 0x20, 0x0000 },
109 { 0x22, 0x0000 },
110 { 0x24, 0x0000 },
111 { 0x26, 0x0000 },
112 { 0x28, 0x0000 },
113 { 0x2a, 0x4000 },
114 { 0x2b, 0x3000 },
115 { 0x2d, 0x6000 },
116 { 0x2e, 0x0000 },
117 { 0x2f, 0x8000 },
118 { 0x32, 0x0000 },
119 { 0x39, 0x0001 },
120 { 0x3a, 0x0000 },
121 { 0x3b, 0x1020 },
122 { 0x3c, 0x0000 },
123 { 0x3d, 0x0000 },
124 { 0x3e, 0x4c00 },
125 { 0x3f, 0x3000 },
126 { 0x40, 0x000c },
127 { 0x42, 0x0400 },
128 { 0x46, 0xc22c },
129 { 0x47, 0x0000 },
130 { 0x4b, 0x0000 },
131 { 0x4c, 0x0300 },
132 { 0x4f, 0xf000 },
133 { 0x50, 0xc200 },
134 { 0x51, 0x1f1f },
135 { 0x52, 0x01f0 },
136 { 0x53, 0x407f },
137 { 0x54, 0xffff },
138 { 0x58, 0x4005 },
139 { 0x5e, 0x0000 },
140 { 0x5f, 0x0000 },
141 { 0x60, 0xee13 },
142 { 0x62, 0x0000 },
143 { 0x63, 0x5f5f },
144 { 0x64, 0x0040 },
145 { 0x65, 0x4000 },
146 { 0x66, 0x4004 },
147 { 0x67, 0x0306 },
148 { 0x68, 0x8c04 },
149 { 0x69, 0xe021 },
150 { 0x6a, 0x0000 },
151 { 0x6c, 0xaaaa },
152 { 0x70, 0x0333 },
153 { 0x71, 0x3330 },
154 { 0x72, 0x3333 },
155 { 0x73, 0x3300 },
156 { 0x74, 0x0000 },
157 { 0x75, 0x0000 },
158 { 0x76, 0x0000 },
159 { 0x7a, 0x0003 },
160 { 0x7c, 0x10ec },
161 { 0x7e, 0x6251 },
162 { 0x80, 0x0800 },
163 { 0x81, 0x4000 },
164 { 0x82, 0x0000 },
165 { 0x90, 0x7a01 },
166 { 0x91, 0x8431 },
167 { 0x92, 0x0180 },
168 { 0x93, 0x0000 },
169 { 0x94, 0x0000 },
170 { 0x95, 0x0000 },
171 { 0x96, 0x0000 },
172 { 0x97, 0x0000 },
173 { 0x98, 0x0000 },
174 { 0x99, 0x0000 },
175 { 0x9a, 0x0000 },
176 { 0x9b, 0x0000 },
177 { 0x9c, 0x0000 },
178 { 0x9d, 0x0000 },
179 { 0x9e, 0x0000 },
180 { 0x9f, 0x0000 },
181 { 0xa0, 0x0000 },
182 { 0xb0, 0x8200 },
183 { 0xb1, 0x00ff },
184 { 0xb2, 0x0008 },
185 { 0xc0, 0x0200 },
186 { 0xc1, 0x0000 },
187 { 0xc2, 0x0000 },
188 { 0xc3, 0x0000 },
189 { 0xc4, 0x0000 },
190 { 0xc5, 0x0000 },
191 { 0xc6, 0x0000 },
192 { 0xc7, 0x0000 },
193 { 0xc8, 0x0000 },
194 { 0xc9, 0x0000 },
195 { 0xca, 0x0200 },
196 { 0xcb, 0x0000 },
197 { 0xcc, 0x0000 },
198 { 0xcd, 0x0000 },
199 { 0xce, 0x0000 },
200 { 0xcf, 0x0000 },
201 { 0xd0, 0x0000 },
202 { 0xd1, 0x0000 },
203 { 0xd2, 0x0000 },
204 { 0xd3, 0x0000 },
205 { 0xd4, 0x0200 },
206 { 0xd5, 0x0000 },
207 { 0xd6, 0x0000 },
208 { 0xd7, 0x0000 },
209 { 0xd8, 0x0000 },
210 { 0xd9, 0x0000 },
211 { 0xda, 0x0000 },
212 { 0xdb, 0x0000 },
213 { 0xdc, 0x0000 },
214 { 0xdd, 0x0000 },
215 { 0xde, 0x0200 },
216 { 0xdf, 0x0000 },
217 { 0xe0, 0x0000 },
218 { 0xe1, 0x0000 },
219 { 0xe2, 0x0000 },
220 { 0xe3, 0x0000 },
221 { 0xe4, 0x0000 },
222 { 0xe5, 0x0000 },
223 { 0xe6, 0x0000 },
224 { 0xe7, 0x0000 },
225 { 0xe8, 0x0200 },
226 { 0xe9, 0x0000 },
227 { 0xea, 0x0000 },
228 { 0xeb, 0x0000 },
229 { 0xec, 0x0000 },
230 { 0xed, 0x0000 },
231 { 0xee, 0x0000 },
232 { 0xef, 0x0000 },
233 { 0xf0, 0x0000 },
234 { 0xf1, 0x0000 },
235 { 0xf2, 0x0200 },
236 { 0xf3, 0x0000 },
237 { 0xf4, 0x0000 },
238 { 0xf5, 0x0000 },
239 { 0xf6, 0x0000 },
240 { 0xf7, 0x0000 },
241 { 0xf8, 0x0000 },
242 { 0xf9, 0x0000 },
243 { 0xfa, 0x0000 },
244 { 0xfb, 0x0000 },
245};
246
247static int rt1305_reg_init(struct snd_soc_component *component)
248{
249 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
250
251 regmap_multi_reg_write(rt1305->regmap, init_list, RT1305_INIT_REG_LEN);
252 return 0;
253}
254
255static bool rt1305_volatile_register(struct device *dev, unsigned int reg)
256{
257 int i;
258
259 for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {
260 if (reg >= rt1305_ranges[i].range_min &&
261 reg <= rt1305_ranges[i].range_max) {
262 return true;
263 }
264 }
265
266 switch (reg) {
267 case RT1305_RESET:
268 case RT1305_SPDIF_IN_SET_1:
269 case RT1305_SPDIF_IN_SET_2:
270 case RT1305_SPDIF_IN_SET_3:
271 case RT1305_POWER_CTRL_2:
272 case RT1305_CLOCK_DETECT:
273 case RT1305_BIQUAD_SET_1:
274 case RT1305_BIQUAD_SET_2:
275 case RT1305_EQ_SET_2:
276 case RT1305_SPK_TEMP_PROTECTION_0:
277 case RT1305_SPK_TEMP_PROTECTION_2:
278 case RT1305_SPK_DC_DETECT_1:
279 case RT1305_SILENCE_DETECT:
280 case RT1305_VERSION_ID:
281 case RT1305_VENDOR_ID:
282 case RT1305_DEVICE_ID:
283 case RT1305_EFUSE_1:
284 case RT1305_EFUSE_3:
285 case RT1305_DC_CALIB_1:
286 case RT1305_DC_CALIB_3:
287 case RT1305_DAC_OFFSET_1:
288 case RT1305_DAC_OFFSET_2:
289 case RT1305_DAC_OFFSET_3:
290 case RT1305_DAC_OFFSET_4:
291 case RT1305_DAC_OFFSET_5:
292 case RT1305_DAC_OFFSET_6:
293 case RT1305_DAC_OFFSET_7:
294 case RT1305_DAC_OFFSET_8:
295 case RT1305_DAC_OFFSET_9:
296 case RT1305_DAC_OFFSET_10:
297 case RT1305_DAC_OFFSET_11:
298 case RT1305_TRIM_1:
299 case RT1305_TRIM_2:
300 return true;
301
302 default:
303 return false;
304 }
305}
306
307static bool rt1305_readable_register(struct device *dev, unsigned int reg)
308{
309 int i;
310
311 for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {
312 if (reg >= rt1305_ranges[i].range_min &&
313 reg <= rt1305_ranges[i].range_max) {
314 return true;
315 }
316 }
317
318 switch (reg) {
319 case RT1305_RESET:
320 case RT1305_CLK_1 ... RT1305_CAL_EFUSE_CLOCK:
321 case RT1305_PLL0_1 ... RT1305_PLL1_2:
322 case RT1305_MIXER_CTRL_1:
323 case RT1305_MIXER_CTRL_2:
324 case RT1305_DAC_SET_1:
325 case RT1305_DAC_SET_2:
326 case RT1305_ADC_SET_1:
327 case RT1305_ADC_SET_2:
328 case RT1305_ADC_SET_3:
329 case RT1305_PATH_SET:
330 case RT1305_SPDIF_IN_SET_1:
331 case RT1305_SPDIF_IN_SET_2:
332 case RT1305_SPDIF_IN_SET_3:
333 case RT1305_SPDIF_OUT_SET_1:
334 case RT1305_SPDIF_OUT_SET_2:
335 case RT1305_SPDIF_OUT_SET_3:
336 case RT1305_I2S_SET_1:
337 case RT1305_I2S_SET_2:
338 case RT1305_PBTL_MONO_MODE_SRC:
339 case RT1305_MANUALLY_I2C_DEVICE:
340 case RT1305_POWER_STATUS:
341 case RT1305_POWER_CTRL_1:
342 case RT1305_POWER_CTRL_2:
343 case RT1305_POWER_CTRL_3:
344 case RT1305_POWER_CTRL_4:
345 case RT1305_POWER_CTRL_5:
346 case RT1305_CLOCK_DETECT:
347 case RT1305_BIQUAD_SET_1:
348 case RT1305_BIQUAD_SET_2:
349 case RT1305_ADJUSTED_HPF_1:
350 case RT1305_ADJUSTED_HPF_2:
351 case RT1305_EQ_SET_1:
352 case RT1305_EQ_SET_2:
353 case RT1305_SPK_TEMP_PROTECTION_0:
354 case RT1305_SPK_TEMP_PROTECTION_1:
355 case RT1305_SPK_TEMP_PROTECTION_2:
356 case RT1305_SPK_TEMP_PROTECTION_3:
357 case RT1305_SPK_DC_DETECT_1:
358 case RT1305_SPK_DC_DETECT_2:
359 case RT1305_LOUDNESS:
360 case RT1305_THERMAL_FOLD_BACK_1:
361 case RT1305_THERMAL_FOLD_BACK_2:
362 case RT1305_SILENCE_DETECT ... RT1305_SPK_EXCURSION_LIMITER_7:
363 case RT1305_VERSION_ID:
364 case RT1305_VENDOR_ID:
365 case RT1305_DEVICE_ID:
366 case RT1305_EFUSE_1:
367 case RT1305_EFUSE_2:
368 case RT1305_EFUSE_3:
369 case RT1305_DC_CALIB_1:
370 case RT1305_DC_CALIB_2:
371 case RT1305_DC_CALIB_3:
372 case RT1305_DAC_OFFSET_1 ... RT1305_DAC_OFFSET_14:
373 case RT1305_TRIM_1:
374 case RT1305_TRIM_2:
375 case RT1305_TUNE_INTERNAL_OSC:
376 case RT1305_BIQUAD1_H0_L_28_16 ... RT1305_BIQUAD3_A2_R_15_0:
377 return true;
378 default:
379 return false;
380 }
381}
382
383static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9435, 37, 0);
384
385static const char * const rt1305_rx_data_ch_select[] = {
386 "LR",
387 "RL",
388 "Copy L",
389 "Copy R",
390};
391
392static SOC_ENUM_SINGLE_DECL(rt1305_rx_data_ch_enum, RT1305_I2S_SET_2, 2,
393 rt1305_rx_data_ch_select);
394
395static void rt1305_reset(struct regmap *regmap)
396{
397 regmap_write(regmap, RT1305_RESET, 0);
398}
399
400static const struct snd_kcontrol_new rt1305_snd_controls[] = {
401 SOC_DOUBLE_TLV("DAC Playback Volume", RT1305_DAC_SET_1,
402 8, 0, 0xff, 0, dac_vol_tlv),
403
404 /* I2S Data Channel Selection */
405 SOC_ENUM("RX Channel Select", rt1305_rx_data_ch_enum),
406};
407
408static int rt1305_is_rc_clk_from_pll(struct snd_soc_dapm_widget *source,
409 struct snd_soc_dapm_widget *sink)
410{
411 struct snd_soc_component *component =
412 snd_soc_dapm_to_component(source->dapm);
413 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
414 unsigned int val;
415
416 snd_soc_component_read(component, RT1305_CLK_1, &val);
417
418 if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1 &&
419 (val & RT1305_SEL_PLL_SRC_2_RCCLK))
420 return 1;
421 else
422 return 0;
423}
424
425static int rt1305_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
426 struct snd_soc_dapm_widget *sink)
427{
428 struct snd_soc_component *component =
429 snd_soc_dapm_to_component(source->dapm);
430 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
431
432 if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1)
433 return 1;
434 else
435 return 0;
436}
437
438static int rt1305_classd_event(struct snd_soc_dapm_widget *w,
439 struct snd_kcontrol *kcontrol, int event)
440{
441 struct snd_soc_component *component =
442 snd_soc_dapm_to_component(w->dapm);
443
444 switch (event) {
445 case SND_SOC_DAPM_POST_PMU:
446 snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1,
447 RT1305_POW_PDB_JD_MASK, RT1305_POW_PDB_JD);
448 break;
449 case SND_SOC_DAPM_PRE_PMD:
450 snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1,
451 RT1305_POW_PDB_JD_MASK, 0);
452 usleep_range(150000, 200000);
453 break;
454
455 default:
456 return 0;
457 }
458
459 return 0;
460}
461
462static const struct snd_kcontrol_new rt1305_sto_dac_l =
463 SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2,
464 RT1305_DVOL_MUTE_L_EN_SFT, 1, 1);
465
466static const struct snd_kcontrol_new rt1305_sto_dac_r =
467 SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2,
468 RT1305_DVOL_MUTE_R_EN_SFT, 1, 1);
469
470static const struct snd_soc_dapm_widget rt1305_dapm_widgets[] = {
471 SND_SOC_DAPM_SUPPLY("PLL0", RT1305_POWER_CTRL_1,
472 RT1305_POW_PLL0_EN_BIT, 0, NULL, 0),
473 SND_SOC_DAPM_SUPPLY("PLL1", RT1305_POWER_CTRL_1,
474 RT1305_POW_PLL1_EN_BIT, 0, NULL, 0),
475 SND_SOC_DAPM_SUPPLY("MBIAS", RT1305_POWER_CTRL_1,
476 RT1305_POW_MBIAS_LV_BIT, 0, NULL, 0),
477 SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1305_POWER_CTRL_1,
478 RT1305_POW_BG_MBIAS_LV_BIT, 0, NULL, 0),
479 SND_SOC_DAPM_SUPPLY("LDO2", RT1305_POWER_CTRL_1,
480 RT1305_POW_LDO2_BIT, 0, NULL, 0),
481 SND_SOC_DAPM_SUPPLY("BG2", RT1305_POWER_CTRL_1,
482 RT1305_POW_BG2_BIT, 0, NULL, 0),
483 SND_SOC_DAPM_SUPPLY("LDO2 IB2", RT1305_POWER_CTRL_1,
484 RT1305_POW_LDO2_IB2_BIT, 0, NULL, 0),
485 SND_SOC_DAPM_SUPPLY("VREF", RT1305_POWER_CTRL_1,
486 RT1305_POW_VREF_BIT, 0, NULL, 0),
487 SND_SOC_DAPM_SUPPLY("VREF1", RT1305_POWER_CTRL_1,
488 RT1305_POW_VREF1_BIT, 0, NULL, 0),
489 SND_SOC_DAPM_SUPPLY("VREF2", RT1305_POWER_CTRL_1,
490 RT1305_POW_VREF2_BIT, 0, NULL, 0),
491
492
493 SND_SOC_DAPM_SUPPLY("DISC VREF", RT1305_POWER_CTRL_2,
494 RT1305_POW_DISC_VREF_BIT, 0, NULL, 0),
495 SND_SOC_DAPM_SUPPLY("FASTB VREF", RT1305_POWER_CTRL_2,
496 RT1305_POW_FASTB_VREF_BIT, 0, NULL, 0),
497 SND_SOC_DAPM_SUPPLY("ULTRA FAST VREF", RT1305_POWER_CTRL_2,
498 RT1305_POW_ULTRA_FAST_VREF_BIT, 0, NULL, 0),
499 SND_SOC_DAPM_SUPPLY("CHOP DAC", RT1305_POWER_CTRL_2,
500 RT1305_POW_CKXEN_DAC_BIT, 0, NULL, 0),
501 SND_SOC_DAPM_SUPPLY("CKGEN DAC", RT1305_POWER_CTRL_2,
502 RT1305_POW_EN_CKGEN_DAC_BIT, 0, NULL, 0),
503 SND_SOC_DAPM_SUPPLY("CLAMP", RT1305_POWER_CTRL_2,
504 RT1305_POW_CLAMP_BIT, 0, NULL, 0),
505 SND_SOC_DAPM_SUPPLY("BUFL", RT1305_POWER_CTRL_2,
506 RT1305_POW_BUFL_BIT, 0, NULL, 0),
507 SND_SOC_DAPM_SUPPLY("BUFR", RT1305_POWER_CTRL_2,
508 RT1305_POW_BUFR_BIT, 0, NULL, 0),
509 SND_SOC_DAPM_SUPPLY("CKGEN ADC", RT1305_POWER_CTRL_2,
510 RT1305_POW_EN_CKGEN_ADC_BIT, 0, NULL, 0),
511 SND_SOC_DAPM_SUPPLY("ADC3 L", RT1305_POWER_CTRL_2,
512 RT1305_POW_ADC3_L_BIT, 0, NULL, 0),
513 SND_SOC_DAPM_SUPPLY("ADC3 R", RT1305_POWER_CTRL_2,
514 RT1305_POW_ADC3_R_BIT, 0, NULL, 0),
515 SND_SOC_DAPM_SUPPLY("TRIOSC", RT1305_POWER_CTRL_2,
516 RT1305_POW_TRIOSC_BIT, 0, NULL, 0),
517 SND_SOC_DAPM_SUPPLY("AVDD1", RT1305_POWER_CTRL_2,
518 RT1305_POR_AVDD1_BIT, 0, NULL, 0),
519 SND_SOC_DAPM_SUPPLY("AVDD2", RT1305_POWER_CTRL_2,
520 RT1305_POR_AVDD2_BIT, 0, NULL, 0),
521
522
523 SND_SOC_DAPM_SUPPLY("VSENSE R", RT1305_POWER_CTRL_3,
524 RT1305_POW_VSENSE_RCH_BIT, 0, NULL, 0),
525 SND_SOC_DAPM_SUPPLY("VSENSE L", RT1305_POWER_CTRL_3,
526 RT1305_POW_VSENSE_LCH_BIT, 0, NULL, 0),
527 SND_SOC_DAPM_SUPPLY("ISENSE R", RT1305_POWER_CTRL_3,
528 RT1305_POW_ISENSE_RCH_BIT, 0, NULL, 0),
529 SND_SOC_DAPM_SUPPLY("ISENSE L", RT1305_POWER_CTRL_3,
530 RT1305_POW_ISENSE_LCH_BIT, 0, NULL, 0),
531 SND_SOC_DAPM_SUPPLY("POR AVDD1", RT1305_POWER_CTRL_3,
532 RT1305_POW_POR_AVDD1_BIT, 0, NULL, 0),
533 SND_SOC_DAPM_SUPPLY("POR AVDD2", RT1305_POWER_CTRL_3,
534 RT1305_POW_POR_AVDD2_BIT, 0, NULL, 0),
535 SND_SOC_DAPM_SUPPLY("VCM 6172", RT1305_POWER_CTRL_3,
536 RT1305_EN_VCM_6172_BIT, 0, NULL, 0),
537
538
539 /* Audio Interface */
540 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
541
542 /* Digital Interface */
543 SND_SOC_DAPM_SUPPLY("DAC L Power", RT1305_POWER_CTRL_2,
544 RT1305_POW_DAC1_L_BIT, 0, NULL, 0),
545 SND_SOC_DAPM_SUPPLY("DAC R Power", RT1305_POWER_CTRL_2,
546 RT1305_POW_DAC1_R_BIT, 0, NULL, 0),
547 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
548 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_l),
549 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_r),
550
551 /* Output Lines */
552 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
553 rt1305_classd_event,
554 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
555 SND_SOC_DAPM_OUTPUT("SPOL"),
556 SND_SOC_DAPM_OUTPUT("SPOR"),
557};
558
559static const struct snd_soc_dapm_route rt1305_dapm_routes[] = {
560
561 { "DAC", NULL, "AIF1RX" },
562
563 { "DAC", NULL, "PLL0", rt1305_is_rc_clk_from_pll },
564 { "DAC", NULL, "PLL1", rt1305_is_sys_clk_from_pll },
565
566 { "DAC", NULL, "MBIAS" },
567 { "DAC", NULL, "BG MBIAS" },
568 { "DAC", NULL, "LDO2" },
569 { "DAC", NULL, "BG2" },
570 { "DAC", NULL, "LDO2 IB2" },
571 { "DAC", NULL, "VREF" },
572 { "DAC", NULL, "VREF1" },
573 { "DAC", NULL, "VREF2" },
574
575 { "DAC", NULL, "DISC VREF" },
576 { "DAC", NULL, "FASTB VREF" },
577 { "DAC", NULL, "ULTRA FAST VREF" },
578 { "DAC", NULL, "CHOP DAC" },
579 { "DAC", NULL, "CKGEN DAC" },
580 { "DAC", NULL, "CLAMP" },
581 { "DAC", NULL, "CKGEN ADC" },
582 { "DAC", NULL, "TRIOSC" },
583 { "DAC", NULL, "AVDD1" },
584 { "DAC", NULL, "AVDD2" },
585
586 { "DAC", NULL, "POR AVDD1" },
587 { "DAC", NULL, "POR AVDD2" },
588 { "DAC", NULL, "VCM 6172" },
589
590 { "DAC L", "Switch", "DAC" },
591 { "DAC R", "Switch", "DAC" },
592
593 { "DAC R", NULL, "VSENSE R" },
594 { "DAC L", NULL, "VSENSE L" },
595 { "DAC R", NULL, "ISENSE R" },
596 { "DAC L", NULL, "ISENSE L" },
597 { "DAC L", NULL, "ADC3 L" },
598 { "DAC R", NULL, "ADC3 R" },
599 { "DAC L", NULL, "BUFL" },
600 { "DAC R", NULL, "BUFR" },
601 { "DAC L", NULL, "DAC L Power" },
602 { "DAC R", NULL, "DAC R Power" },
603
604 { "CLASS D", NULL, "DAC L" },
605 { "CLASS D", NULL, "DAC R" },
606
607 { "SPOL", NULL, "CLASS D" },
608 { "SPOR", NULL, "CLASS D" },
609};
610
611static int rt1305_get_clk_info(int sclk, int rate)
612{
613 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
614
615 if (sclk <= 0 || rate <= 0)
616 return -EINVAL;
617
618 rate = rate << 8;
619 for (i = 0; i < ARRAY_SIZE(pd); i++)
620 if (sclk == rate * pd[i])
621 return i;
622
623 return -EINVAL;
624}
625
626static int rt1305_hw_params(struct snd_pcm_substream *substream,
627 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
628{
629 struct snd_soc_component *component = dai->component;
630 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
631 unsigned int val_len = 0, val_clk, mask_clk;
632 int pre_div, bclk_ms, frame_size;
633
634 rt1305->lrck = params_rate(params);
635 pre_div = rt1305_get_clk_info(rt1305->sysclk, rt1305->lrck);
636 if (pre_div < 0) {
637 dev_warn(component->dev, "Force using PLL ");
638 snd_soc_dai_set_pll(dai, 0, RT1305_PLL1_S_BCLK,
639 rt1305->lrck * 64, rt1305->lrck * 256);
640 snd_soc_dai_set_sysclk(dai, RT1305_FS_SYS_PRE_S_PLL1,
641 rt1305->lrck * 256, SND_SOC_CLOCK_IN);
642 pre_div = 0;
643 }
644 frame_size = snd_soc_params_to_frame_size(params);
645 if (frame_size < 0) {
646 dev_err(component->dev, "Unsupported frame size: %d\n",
647 frame_size);
648 return -EINVAL;
649 }
650
651 bclk_ms = frame_size > 32;
652 rt1305->bclk = rt1305->lrck * (32 << bclk_ms);
653
654 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
655 bclk_ms, pre_div, dai->id);
656
657 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
658 rt1305->lrck, pre_div, dai->id);
659
660 switch (params_width(params)) {
661 case 16:
662 val_len |= RT1305_I2S_DL_SEL_16B;
663 break;
664 case 20:
665 val_len |= RT1305_I2S_DL_SEL_20B;
666 break;
667 case 24:
668 val_len |= RT1305_I2S_DL_SEL_24B;
669 break;
670 case 8:
671 val_len |= RT1305_I2S_DL_SEL_8B;
672 break;
673 default:
674 return -EINVAL;
675 }
676
677 switch (dai->id) {
678 case RT1305_AIF1:
679 mask_clk = RT1305_DIV_FS_SYS_MASK;
680 val_clk = pre_div << RT1305_DIV_FS_SYS_SFT;
681 snd_soc_component_update_bits(component, RT1305_I2S_SET_2,
682 RT1305_I2S_DL_SEL_MASK,
683 val_len);
684 break;
685 default:
686 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
687 return -EINVAL;
688 }
689
690 snd_soc_component_update_bits(component, RT1305_CLK_2,
691 mask_clk, val_clk);
692
693 return 0;
694}
695
696static int rt1305_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
697{
698 struct snd_soc_component *component = dai->component;
699 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
700 unsigned int reg_val = 0, reg1_val = 0;
701
702 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
703 case SND_SOC_DAIFMT_CBM_CFM:
704 reg_val |= RT1305_SEL_I2S_OUT_MODE_M;
705 rt1305->master = 1;
706 break;
707 case SND_SOC_DAIFMT_CBS_CFS:
708 reg_val |= RT1305_SEL_I2S_OUT_MODE_S;
709 rt1305->master = 0;
710 break;
711 default:
712 return -EINVAL;
713 }
714
715 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
716 case SND_SOC_DAIFMT_NB_NF:
717 break;
718 case SND_SOC_DAIFMT_IB_NF:
719 reg1_val |= RT1305_I2S_BCLK_INV;
720 break;
721 default:
722 return -EINVAL;
723 }
724
725 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
726 case SND_SOC_DAIFMT_I2S:
727 break;
728 case SND_SOC_DAIFMT_LEFT_J:
729 reg1_val |= RT1305_I2S_DF_SEL_LEFT;
730 break;
731 case SND_SOC_DAIFMT_DSP_A:
732 reg1_val |= RT1305_I2S_DF_SEL_PCM_A;
733 break;
734 case SND_SOC_DAIFMT_DSP_B:
735 reg1_val |= RT1305_I2S_DF_SEL_PCM_B;
736 break;
737 default:
738 return -EINVAL;
739 }
740
741 switch (dai->id) {
742 case RT1305_AIF1:
743 snd_soc_component_update_bits(component, RT1305_I2S_SET_1,
744 RT1305_SEL_I2S_OUT_MODE_MASK, reg_val);
745 snd_soc_component_update_bits(component, RT1305_I2S_SET_2,
746 RT1305_I2S_DF_SEL_MASK | RT1305_I2S_BCLK_MASK,
747 reg1_val);
748 break;
749 default:
750 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
751 return -EINVAL;
752 }
753 return 0;
754}
755
756static int rt1305_set_component_sysclk(struct snd_soc_component *component,
757 int clk_id, int source, unsigned int freq, int dir)
758{
759 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
760 unsigned int reg_val = 0;
761
762 if (freq == rt1305->sysclk && clk_id == rt1305->sysclk_src)
763 return 0;
764
765 switch (clk_id) {
766 case RT1305_FS_SYS_PRE_S_MCLK:
767 reg_val |= RT1305_SEL_FS_SYS_PRE_MCLK;
768 snd_soc_component_update_bits(component,
769 RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK,
770 RT1305_SEL_CLK_DET_SRC_MCLK);
771 break;
772 case RT1305_FS_SYS_PRE_S_PLL1:
773 reg_val |= RT1305_SEL_FS_SYS_PRE_PLL;
774 break;
775 case RT1305_FS_SYS_PRE_S_RCCLK:
776 reg_val |= RT1305_SEL_FS_SYS_PRE_RCCLK;
777 break;
778 default:
779 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
780 return -EINVAL;
781 }
782 snd_soc_component_update_bits(component, RT1305_CLK_1,
783 RT1305_SEL_FS_SYS_PRE_MASK, reg_val);
784 rt1305->sysclk = freq;
785 rt1305->sysclk_src = clk_id;
786
787 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
788 freq, clk_id);
789
790 return 0;
791}
792
793static int rt1305_set_component_pll(struct snd_soc_component *component,
794 int pll_id, int source, unsigned int freq_in,
795 unsigned int freq_out)
796{
797 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
798 struct rl6231_pll_code pll_code;
799 int ret;
800
801 if (source == rt1305->pll_src && freq_in == rt1305->pll_in &&
802 freq_out == rt1305->pll_out)
803 return 0;
804
805 if (!freq_in || !freq_out) {
806 dev_dbg(component->dev, "PLL disabled\n");
807
808 rt1305->pll_in = 0;
809 rt1305->pll_out = 0;
810 snd_soc_component_update_bits(component, RT1305_CLK_1,
811 RT1305_SEL_FS_SYS_PRE_MASK | RT1305_SEL_PLL_SRC_1_MASK,
812 RT1305_SEL_FS_SYS_PRE_PLL | RT1305_SEL_PLL_SRC_1_BCLK);
813 return 0;
814 }
815
816 switch (source) {
817 case RT1305_PLL2_S_MCLK:
818 snd_soc_component_update_bits(component, RT1305_CLK_1,
819 RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK |
820 RT1305_DIV_PLL_SRC_2_MASK,
821 RT1305_SEL_PLL_SRC_2_MCLK | RT1305_SEL_PLL_SRC_1_PLL2);
822 snd_soc_component_update_bits(component,
823 RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK,
824 RT1305_SEL_CLK_DET_SRC_MCLK);
825 break;
826 case RT1305_PLL1_S_BCLK:
827 snd_soc_component_update_bits(component,
828 RT1305_CLK_1, RT1305_SEL_PLL_SRC_1_MASK,
829 RT1305_SEL_PLL_SRC_1_BCLK);
830 break;
831 case RT1305_PLL2_S_RCCLK:
832 snd_soc_component_update_bits(component, RT1305_CLK_1,
833 RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK |
834 RT1305_DIV_PLL_SRC_2_MASK,
835 RT1305_SEL_PLL_SRC_2_RCCLK | RT1305_SEL_PLL_SRC_1_PLL2);
836 freq_in = 98304000;
837 break;
838 default:
839 dev_err(component->dev, "Unknown PLL Source %d\n", source);
840 return -EINVAL;
841 }
842
843 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
844 if (ret < 0) {
845 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
846 return ret;
847 }
848
849 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
850 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
851 pll_code.n_code, pll_code.k_code);
852
853 snd_soc_component_write(component, RT1305_PLL1_1,
854 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1305_PLL_1_M_SFT |
855 pll_code.m_bp << RT1305_PLL_1_M_BYPASS_SFT |
856 pll_code.n_code);
857 snd_soc_component_write(component, RT1305_PLL1_2,
858 pll_code.k_code);
859
860 rt1305->pll_in = freq_in;
861 rt1305->pll_out = freq_out;
862 rt1305->pll_src = source;
863
864 return 0;
865}
866
867static int rt1305_probe(struct snd_soc_component *component)
868{
869 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
870
871 rt1305->component = component;
872
873 /* initial settings */
874 rt1305_reg_init(component);
875
876 return 0;
877}
878
879static void rt1305_remove(struct snd_soc_component *component)
880{
881 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
882
883 rt1305_reset(rt1305->regmap);
884}
885
886#ifdef CONFIG_PM
887static int rt1305_suspend(struct snd_soc_component *component)
888{
889 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
890
891 regcache_cache_only(rt1305->regmap, true);
892 regcache_mark_dirty(rt1305->regmap);
893
894 return 0;
895}
896
897static int rt1305_resume(struct snd_soc_component *component)
898{
899 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
900
901 regcache_cache_only(rt1305->regmap, false);
902 regcache_sync(rt1305->regmap);
903
904 return 0;
905}
906#else
907#define rt1305_suspend NULL
908#define rt1305_resume NULL
909#endif
910
911#define RT1305_STEREO_RATES SNDRV_PCM_RATE_8000_192000
912#define RT1305_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
913 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
914 SNDRV_PCM_FMTBIT_S24_LE)
915
916static const struct snd_soc_dai_ops rt1305_aif_dai_ops = {
917 .hw_params = rt1305_hw_params,
918 .set_fmt = rt1305_set_dai_fmt,
919};
920
921static struct snd_soc_dai_driver rt1305_dai[] = {
922 {
923 .name = "rt1305-aif",
924 .playback = {
925 .stream_name = "AIF1 Playback",
926 .channels_min = 1,
927 .channels_max = 2,
928 .rates = RT1305_STEREO_RATES,
929 .formats = RT1305_FORMATS,
930 },
931 .ops = &rt1305_aif_dai_ops,
932 },
933};
934
935static const struct snd_soc_component_driver soc_component_dev_rt1305 = {
936 .probe = rt1305_probe,
937 .remove = rt1305_remove,
938 .suspend = rt1305_suspend,
939 .resume = rt1305_resume,
940 .controls = rt1305_snd_controls,
941 .num_controls = ARRAY_SIZE(rt1305_snd_controls),
942 .dapm_widgets = rt1305_dapm_widgets,
943 .num_dapm_widgets = ARRAY_SIZE(rt1305_dapm_widgets),
944 .dapm_routes = rt1305_dapm_routes,
945 .num_dapm_routes = ARRAY_SIZE(rt1305_dapm_routes),
946 .set_sysclk = rt1305_set_component_sysclk,
947 .set_pll = rt1305_set_component_pll,
948 .use_pmdown_time = 1,
949 .endianness = 1,
950 .non_legacy_dai_naming = 1,
951};
952
953static const struct regmap_config rt1305_regmap = {
954 .reg_bits = 8,
955 .val_bits = 16,
956 .max_register = RT1305_MAX_REG + 1 + (ARRAY_SIZE(rt1305_ranges) *
957 RT1305_PR_SPACING),
958 .volatile_reg = rt1305_volatile_register,
959 .readable_reg = rt1305_readable_register,
960 .cache_type = REGCACHE_RBTREE,
961 .reg_defaults = rt1305_reg,
962 .num_reg_defaults = ARRAY_SIZE(rt1305_reg),
963 .ranges = rt1305_ranges,
964 .num_ranges = ARRAY_SIZE(rt1305_ranges),
965 .use_single_rw = true,
966};
967
968#if defined(CONFIG_OF)
969static const struct of_device_id rt1305_of_match[] = {
970 { .compatible = "realtek,rt1305", },
971 { .compatible = "realtek,rt1306", },
972 {},
973};
974MODULE_DEVICE_TABLE(of, rt1305_of_match);
975#endif
976
977#ifdef CONFIG_ACPI
978static struct acpi_device_id rt1305_acpi_match[] = {
979 {"10EC1305", 0,},
980 {"10EC1306", 0,},
981 {},
982};
983MODULE_DEVICE_TABLE(acpi, rt1305_acpi_match);
984#endif
985
986static const struct i2c_device_id rt1305_i2c_id[] = {
987 { "rt1305", 0 },
988 { "rt1306", 0 },
989 { }
990};
991MODULE_DEVICE_TABLE(i2c, rt1305_i2c_id);
992
993static void rt1305_calibrate(struct rt1305_priv *rt1305)
994{
995 unsigned int valmsb, vallsb, offsetl, offsetr;
996 unsigned int rh, rl, rhl, r0ohm;
997 u64 r0l, r0r;
998
999 regcache_cache_bypass(rt1305->regmap, true);
1000
1001 rt1305_reset(rt1305->regmap);
1002 regmap_write(rt1305->regmap, RT1305_ADC_SET_3, 0x0219);
1003 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcf, 0x5548);
1004 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);
1005 regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x1000);
1006 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0600);
1007 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xffd0);
1008 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);
1009 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1010 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);
1011
1012 /* Sin Gen */
1013 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);
1014
1015 regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0xb000);
1016 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc3, 0xd4a0);
1017 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcc, 0x00cc);
1018 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);
1019 regmap_write(rt1305->regmap, RT1305_POWER_STATUS, 0x0000);
1020 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);
1021 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);
1022 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x00c0);
1023 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);
1024 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);
1025 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);
1026
1027 /* EFUSE read */
1028 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);
1029 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1030 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1031 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);
1032 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);
1033 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);
1034 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x0000);
1035 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0000);
1036
1037 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_5, &valmsb);
1038 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_6, &vallsb);
1039 offsetl = valmsb << 16 | vallsb;
1040 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_7, &valmsb);
1041 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_8, &vallsb);
1042 offsetr = valmsb << 16 | vallsb;
1043 pr_info("DC offsetl=0x%x, offsetr=0x%x\n", offsetl, offsetr);
1044
1045 /* R0 calibration */
1046 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x9542);
1047 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);
1048 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);
1049 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x1dfe);
1050 regmap_write(rt1305->regmap, RT1305_SILENCE_DETECT, 0x0e13);
1051 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0650);
1052
1053 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x50, 0x0064);
1054 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x51, 0x0770);
1055 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x52, 0xc30c);
1056 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x8200);
1057 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);
1058 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);
1059 msleep(2000);
1060 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);
1061 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);
1062 rhl = (rh << 16) | rl;
1063 r0ohm = (rhl*10) / 33554432;
1064
1065 pr_debug("Left_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);
1066 pr_info("Left channel %d.%dohm\n", (r0ohm/10), (r0ohm%10));
1067
1068 r0l = 562949953421312;
1069 if (rhl != 0)
1070 do_div(r0l, rhl);
1071 pr_debug("Left_r0 = 0x%llx\n", r0l);
1072
1073 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x9200);
1074 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);
1075 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);
1076 msleep(2000);
1077 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);
1078 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);
1079 rhl = (rh << 16) | rl;
1080 r0ohm = (rhl*10) / 33554432;
1081
1082 pr_debug("Right_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);
1083 pr_info("Right channel %d.%dohm\n", (r0ohm/10), (r0ohm%10));
1084
1085 r0r = 562949953421312;
1086 if (rhl != 0)
1087 do_div(r0r, rhl);
1088 pr_debug("Right_r0 = 0x%llx\n", r0r);
1089
1090 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0xc2ec);
1091
1092 if ((r0l > R0_UPPER) && (r0l < R0_LOWER) &&
1093 (r0r > R0_UPPER) && (r0r < R0_LOWER)) {
1094 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4e,
1095 (r0l >> 16) & 0xffff);
1096 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4f,
1097 r0l & 0xffff);
1098 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfe,
1099 ((r0r >> 16) & 0xffff) | 0xf800);
1100 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfd,
1101 r0r & 0xffff);
1102 } else {
1103 pr_err("R0 calibration failed\n");
1104 }
1105
1106 /* restore some registers */
1107 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);
1108 usleep_range(200000, 400000);
1109 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);
1110 regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x3000);
1111 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0400);
1112 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0000);
1113 regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0x8000);
1114 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0x1020);
1115 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0x0000);
1116
1117 regcache_cache_bypass(rt1305->regmap, false);
1118}
1119
1120static int rt1305_i2c_probe(struct i2c_client *i2c,
1121 const struct i2c_device_id *id)
1122{
1123 struct rt1305_priv *rt1305;
1124 int ret;
1125 unsigned int val;
1126
1127 rt1305 = devm_kzalloc(&i2c->dev, sizeof(struct rt1305_priv),
1128 GFP_KERNEL);
1129 if (rt1305 == NULL)
1130 return -ENOMEM;
1131
1132 i2c_set_clientdata(i2c, rt1305);
1133
1134 rt1305->regmap = devm_regmap_init_i2c(i2c, &rt1305_regmap);
1135 if (IS_ERR(rt1305->regmap)) {
1136 ret = PTR_ERR(rt1305->regmap);
1137 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1138 ret);
1139 return ret;
1140 }
1141
1142 regmap_read(rt1305->regmap, RT1305_DEVICE_ID, &val);
1143 if (val != RT1305_DEVICE_ID_NUM) {
1144 dev_err(&i2c->dev,
1145 "Device with ID register %x is not rt1305\n", val);
1146 return -ENODEV;
1147 }
1148
1149 rt1305_reset(rt1305->regmap);
1150 rt1305_calibrate(rt1305);
1151
1152 return snd_soc_register_component(&i2c->dev, &soc_component_dev_rt1305,
1153 rt1305_dai, ARRAY_SIZE(rt1305_dai));
1154}
1155
1156static int rt1305_i2c_remove(struct i2c_client *i2c)
1157{
1158 snd_soc_unregister_component(&i2c->dev);
1159
1160 return 0;
1161}
1162
1163static void rt1305_i2c_shutdown(struct i2c_client *client)
1164{
1165 struct rt1305_priv *rt1305 = i2c_get_clientdata(client);
1166
1167 rt1305_reset(rt1305->regmap);
1168}
1169
1170
1171static struct i2c_driver rt1305_i2c_driver = {
1172 .driver = {
1173 .name = "rt1305",
1174 .owner = THIS_MODULE,
1175#if defined(CONFIG_OF)
1176 .of_match_table = rt1305_of_match,
1177#endif
1178#if defined(CONFIG_ACPI)
1179 .acpi_match_table = ACPI_PTR(rt1305_acpi_match)
1180#endif
1181 },
1182 .probe = rt1305_i2c_probe,
1183 .remove = rt1305_i2c_remove,
1184 .shutdown = rt1305_i2c_shutdown,
1185 .id_table = rt1305_i2c_id,
1186};
1187module_i2c_driver(rt1305_i2c_driver);
1188
1189MODULE_DESCRIPTION("ASoC RT1305 amplifier driver");
1190MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
1191MODULE_LICENSE("GPL v2");