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git.odroid.com / yocto / kernel / common / 6ccf3a6d031c47d6319cb56ee35dd4b546905e91 / . / sound / soc / codecs / rt5663.c
blob: 71c073c638668fdef0f1eb3263f32ee2e84b8b28 [file] [log] [blame]
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1/*
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2 * rt5663.c -- RT5663 ALSA SoC audio codec driver
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3 *
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Jack Yu <jack.yu@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/pm.h>
16#include <linux/i2c.h>
17#include <linux/platform_device.h>
18#include <linux/spi/spi.h>
19#include <linux/acpi.h>
20#include <linux/workqueue.h>
21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/jack.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29
30#include "rt5663.h"
31#include "rl6231.h"
32
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]33#define RT5663_DEVICE_ID_2 0x6451
34#define RT5663_DEVICE_ID_1 0x6406
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]35
36enum {
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]37 CODEC_VER_1,
38 CODEC_VER_0,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]39};
40
41struct rt5663_priv {
42 struct snd_soc_codec *codec;
oder_chiou@realtek.com450f0f62017-07-10 11:14:56 +0800[diff] [blame]43 struct rt5663_platform_data pdata;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]44 struct regmap *regmap;
45 struct delayed_work jack_detect_work;
46 struct snd_soc_jack *hs_jack;
47 struct timer_list btn_check_timer;
48
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]49 int codec_ver;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]50 int sysclk;
51 int sysclk_src;
52 int lrck;
53
54 int pll_src;
55 int pll_in;
56 int pll_out;
57
58 int jack_type;
59};
60
oder_chiou@realtek.com450f0f62017-07-10 11:14:56 +0800[diff] [blame]61static const struct reg_sequence rt5663_patch_list[] = {
62 { 0x002a, 0x8080 },
63};
64
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]65static const struct reg_default rt5663_v2_reg[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]66 { 0x0000, 0x0000 },
67 { 0x0001, 0xc8c8 },
68 { 0x0002, 0x8080 },
69 { 0x0003, 0x8000 },
70 { 0x0004, 0xc80a },
71 { 0x0005, 0x0000 },
72 { 0x0006, 0x0000 },
73 { 0x0007, 0x0000 },
74 { 0x000a, 0x0000 },
75 { 0x000b, 0x0000 },
76 { 0x000c, 0x0000 },
77 { 0x000d, 0x0000 },
78 { 0x000f, 0x0808 },
79 { 0x0010, 0x4000 },
80 { 0x0011, 0x0000 },
81 { 0x0012, 0x1404 },
82 { 0x0013, 0x1000 },
83 { 0x0014, 0xa00a },
84 { 0x0015, 0x0404 },
85 { 0x0016, 0x0404 },
86 { 0x0017, 0x0011 },
87 { 0x0018, 0xafaf },
88 { 0x0019, 0xafaf },
89 { 0x001a, 0xafaf },
90 { 0x001b, 0x0011 },
91 { 0x001c, 0x2f2f },
92 { 0x001d, 0x2f2f },
93 { 0x001e, 0x2f2f },
94 { 0x001f, 0x0000 },
95 { 0x0020, 0x0000 },
96 { 0x0021, 0x0000 },
97 { 0x0022, 0x5757 },
98 { 0x0023, 0x0039 },
99 { 0x0024, 0x000b },
100 { 0x0026, 0xc0c0 },
101 { 0x0027, 0xc0c0 },
102 { 0x0028, 0xc0c0 },
103 { 0x0029, 0x8080 },
104 { 0x002a, 0xaaaa },
105 { 0x002b, 0xaaaa },
106 { 0x002c, 0xaba8 },
107 { 0x002d, 0x0000 },
108 { 0x002e, 0x0000 },
109 { 0x002f, 0x0000 },
110 { 0x0030, 0x0000 },
111 { 0x0031, 0x5000 },
112 { 0x0032, 0x0000 },
113 { 0x0033, 0x0000 },
114 { 0x0034, 0x0000 },
115 { 0x0035, 0x0000 },
116 { 0x003a, 0x0000 },
117 { 0x003b, 0x0000 },
118 { 0x003c, 0x00ff },
119 { 0x003d, 0x0000 },
120 { 0x003e, 0x00ff },
121 { 0x003f, 0x0000 },
122 { 0x0040, 0x0000 },
123 { 0x0041, 0x00ff },
124 { 0x0042, 0x0000 },
125 { 0x0043, 0x00ff },
126 { 0x0044, 0x0c0c },
127 { 0x0049, 0xc00b },
128 { 0x004a, 0x0000 },
129 { 0x004b, 0x031f },
130 { 0x004d, 0x0000 },
131 { 0x004e, 0x001f },
132 { 0x004f, 0x0000 },
133 { 0x0050, 0x001f },
134 { 0x0052, 0xf000 },
135 { 0x0061, 0x0000 },
136 { 0x0062, 0x0000 },
137 { 0x0063, 0x003e },
138 { 0x0064, 0x0000 },
139 { 0x0065, 0x0000 },
140 { 0x0066, 0x003f },
141 { 0x0067, 0x0000 },
142 { 0x006b, 0x0000 },
143 { 0x006d, 0xff00 },
144 { 0x006e, 0x2808 },
145 { 0x006f, 0x000a },
146 { 0x0070, 0x8000 },
147 { 0x0071, 0x8000 },
148 { 0x0072, 0x8000 },
149 { 0x0073, 0x7000 },
150 { 0x0074, 0x7770 },
151 { 0x0075, 0x0002 },
152 { 0x0076, 0x0001 },
153 { 0x0078, 0x00f0 },
154 { 0x0079, 0x0000 },
155 { 0x007a, 0x0000 },
156 { 0x007b, 0x0000 },
157 { 0x007c, 0x0000 },
158 { 0x007d, 0x0123 },
159 { 0x007e, 0x4500 },
160 { 0x007f, 0x8003 },
161 { 0x0080, 0x0000 },
162 { 0x0081, 0x0000 },
163 { 0x0082, 0x0000 },
164 { 0x0083, 0x0000 },
165 { 0x0084, 0x0000 },
166 { 0x0085, 0x0000 },
167 { 0x0086, 0x0008 },
168 { 0x0087, 0x0000 },
169 { 0x0088, 0x0000 },
170 { 0x0089, 0x0000 },
171 { 0x008a, 0x0000 },
172 { 0x008b, 0x0000 },
173 { 0x008c, 0x0003 },
174 { 0x008e, 0x0060 },
175 { 0x008f, 0x1000 },
176 { 0x0091, 0x0c26 },
177 { 0x0092, 0x0073 },
178 { 0x0093, 0x0000 },
179 { 0x0094, 0x0080 },
180 { 0x0098, 0x0000 },
181 { 0x0099, 0x0000 },
182 { 0x009a, 0x0007 },
183 { 0x009f, 0x0000 },
184 { 0x00a0, 0x0000 },
185 { 0x00a1, 0x0002 },
186 { 0x00a2, 0x0001 },
187 { 0x00a3, 0x0002 },
188 { 0x00a4, 0x0001 },
189 { 0x00ae, 0x2040 },
190 { 0x00af, 0x0000 },
191 { 0x00b6, 0x0000 },
192 { 0x00b7, 0x0000 },
193 { 0x00b8, 0x0000 },
194 { 0x00b9, 0x0000 },
195 { 0x00ba, 0x0002 },
196 { 0x00bb, 0x0000 },
197 { 0x00be, 0x0000 },
198 { 0x00c0, 0x0000 },
199 { 0x00c1, 0x0aaa },
200 { 0x00c2, 0xaa80 },
201 { 0x00c3, 0x0003 },
202 { 0x00c4, 0x0000 },
203 { 0x00d0, 0x0000 },
204 { 0x00d1, 0x2244 },
205 { 0x00d2, 0x0000 },
206 { 0x00d3, 0x3300 },
207 { 0x00d4, 0x2200 },
208 { 0x00d9, 0x0809 },
209 { 0x00da, 0x0000 },
210 { 0x00db, 0x0008 },
211 { 0x00dc, 0x00c0 },
212 { 0x00dd, 0x6724 },
213 { 0x00de, 0x3131 },
214 { 0x00df, 0x0008 },
215 { 0x00e0, 0x4000 },
216 { 0x00e1, 0x3131 },
217 { 0x00e2, 0x600c },
218 { 0x00ea, 0xb320 },
219 { 0x00eb, 0x0000 },
220 { 0x00ec, 0xb300 },
221 { 0x00ed, 0x0000 },
222 { 0x00ee, 0xb320 },
223 { 0x00ef, 0x0000 },
224 { 0x00f0, 0x0201 },
225 { 0x00f1, 0x0ddd },
226 { 0x00f2, 0x0ddd },
227 { 0x00f6, 0x0000 },
228 { 0x00f7, 0x0000 },
229 { 0x00f8, 0x0000 },
230 { 0x00fa, 0x0000 },
231 { 0x00fb, 0x0000 },
232 { 0x00fc, 0x0000 },
233 { 0x00fd, 0x0000 },
234 { 0x00fe, 0x10ec },
235 { 0x00ff, 0x6451 },
236 { 0x0100, 0xaaaa },
237 { 0x0101, 0x000a },
238 { 0x010a, 0xaaaa },
239 { 0x010b, 0xa0a0 },
240 { 0x010c, 0xaeae },
241 { 0x010d, 0xaaaa },
242 { 0x010e, 0xaaaa },
243 { 0x010f, 0xaaaa },
244 { 0x0110, 0xe002 },
245 { 0x0111, 0xa602 },
246 { 0x0112, 0xaaaa },
247 { 0x0113, 0x2000 },
248 { 0x0117, 0x0f00 },
249 { 0x0125, 0x0420 },
250 { 0x0132, 0x0000 },
251 { 0x0133, 0x0000 },
252 { 0x0136, 0x5555 },
253 { 0x0137, 0x5540 },
254 { 0x0138, 0x3700 },
255 { 0x0139, 0x79a1 },
256 { 0x013a, 0x2020 },
257 { 0x013b, 0x2020 },
258 { 0x013c, 0x2005 },
259 { 0x013f, 0x0000 },
260 { 0x0145, 0x0002 },
261 { 0x0146, 0x0000 },
262 { 0x0147, 0x0000 },
263 { 0x0148, 0x0000 },
264 { 0x0160, 0x4ec0 },
265 { 0x0161, 0x0080 },
266 { 0x0162, 0x0200 },
267 { 0x0163, 0x0800 },
268 { 0x0164, 0x0000 },
269 { 0x0165, 0x0000 },
270 { 0x0166, 0x0000 },
271 { 0x0167, 0x000f },
272 { 0x0168, 0x000f },
273 { 0x0170, 0x4e80 },
274 { 0x0171, 0x0080 },
275 { 0x0172, 0x0200 },
276 { 0x0173, 0x0800 },
277 { 0x0174, 0x00ff },
278 { 0x0175, 0x0000 },
279 { 0x0190, 0x4131 },
280 { 0x0191, 0x4131 },
281 { 0x0192, 0x4131 },
282 { 0x0193, 0x4131 },
283 { 0x0194, 0x0000 },
284 { 0x0195, 0x0000 },
285 { 0x0196, 0x0000 },
286 { 0x0197, 0x0000 },
287 { 0x0198, 0x0000 },
288 { 0x0199, 0x0000 },
289 { 0x01a0, 0x1e64 },
290 { 0x01a1, 0x06a3 },
291 { 0x01a2, 0x0000 },
292 { 0x01a3, 0x0000 },
293 { 0x01a4, 0x0000 },
294 { 0x01a5, 0x0000 },
295 { 0x01a6, 0x0000 },
296 { 0x01a7, 0x0000 },
297 { 0x01a8, 0x0000 },
298 { 0x01a9, 0x0000 },
299 { 0x01aa, 0x0000 },
300 { 0x01ab, 0x0000 },
301 { 0x01b5, 0x0000 },
302 { 0x01b6, 0x01c3 },
303 { 0x01b7, 0x02a0 },
304 { 0x01b8, 0x03e9 },
305 { 0x01b9, 0x1389 },
306 { 0x01ba, 0xc351 },
307 { 0x01bb, 0x0009 },
308 { 0x01bc, 0x0018 },
309 { 0x01bd, 0x002a },
310 { 0x01be, 0x004c },
311 { 0x01bf, 0x0097 },
312 { 0x01c0, 0x433d },
313 { 0x01c1, 0x0000 },
314 { 0x01c2, 0x0000 },
315 { 0x01c3, 0x0000 },
316 { 0x01c4, 0x0000 },
317 { 0x01c5, 0x0000 },
318 { 0x01c6, 0x0000 },
319 { 0x01c7, 0x0000 },
320 { 0x01c8, 0x40af },
321 { 0x01c9, 0x0702 },
322 { 0x01ca, 0x0000 },
323 { 0x01cb, 0x0000 },
324 { 0x01cc, 0x5757 },
325 { 0x01cd, 0x5757 },
326 { 0x01ce, 0x5757 },
327 { 0x01cf, 0x5757 },
328 { 0x01d0, 0x5757 },
329 { 0x01d1, 0x5757 },
330 { 0x01d2, 0x5757 },
331 { 0x01d3, 0x5757 },
332 { 0x01d4, 0x5757 },
333 { 0x01d5, 0x5757 },
334 { 0x01d6, 0x003c },
335 { 0x01da, 0x0000 },
336 { 0x01db, 0x0000 },
337 { 0x01dc, 0x0000 },
338 { 0x01de, 0x7c00 },
339 { 0x01df, 0x0320 },
340 { 0x01e0, 0x06a1 },
341 { 0x01e1, 0x0000 },
342 { 0x01e2, 0x0000 },
343 { 0x01e3, 0x0000 },
344 { 0x01e4, 0x0000 },
345 { 0x01e5, 0x0000 },
346 { 0x01e6, 0x0001 },
347 { 0x01e7, 0x0000 },
348 { 0x01e8, 0x0000 },
349 { 0x01ea, 0x0000 },
350 { 0x01eb, 0x0000 },
351 { 0x01ec, 0x0000 },
352 { 0x01ed, 0x0000 },
353 { 0x01ee, 0x0000 },
354 { 0x01ef, 0x0000 },
355 { 0x01f0, 0x0000 },
356 { 0x01f1, 0x0000 },
357 { 0x01f2, 0x0000 },
358 { 0x01f3, 0x0000 },
359 { 0x01f4, 0x0000 },
360 { 0x0200, 0x0000 },
361 { 0x0201, 0x0000 },
362 { 0x0202, 0x0000 },
363 { 0x0203, 0x0000 },
364 { 0x0204, 0x0000 },
365 { 0x0205, 0x0000 },
366 { 0x0206, 0x0000 },
367 { 0x0207, 0x0000 },
368 { 0x0208, 0x0000 },
369 { 0x0210, 0x60b1 },
370 { 0x0211, 0xa000 },
371 { 0x0212, 0x024c },
372 { 0x0213, 0xf7ff },
373 { 0x0214, 0x024c },
374 { 0x0215, 0x0102 },
375 { 0x0216, 0x00a3 },
376 { 0x0217, 0x0048 },
377 { 0x0218, 0x92c0 },
378 { 0x0219, 0x0000 },
379 { 0x021a, 0x00c8 },
380 { 0x021b, 0x0020 },
381 { 0x02fa, 0x0000 },
382 { 0x02fb, 0x0000 },
383 { 0x02fc, 0x0000 },
384 { 0x02ff, 0x0110 },
385 { 0x0300, 0x001f },
386 { 0x0301, 0x032c },
387 { 0x0302, 0x5f21 },
388 { 0x0303, 0x4000 },
389 { 0x0304, 0x4000 },
390 { 0x0305, 0x06d5 },
391 { 0x0306, 0x8000 },
392 { 0x0307, 0x0700 },
393 { 0x0310, 0x4560 },
394 { 0x0311, 0xa4a8 },
395 { 0x0312, 0x7418 },
396 { 0x0313, 0x0000 },
397 { 0x0314, 0x0006 },
398 { 0x0315, 0xffff },
399 { 0x0316, 0xc400 },
400 { 0x0317, 0x0000 },
401 { 0x0330, 0x00a6 },
402 { 0x0331, 0x04c3 },
403 { 0x0332, 0x27c8 },
404 { 0x0333, 0xbf50 },
405 { 0x0334, 0x0045 },
406 { 0x0335, 0x0007 },
407 { 0x0336, 0x7418 },
408 { 0x0337, 0x0501 },
409 { 0x0338, 0x0000 },
410 { 0x0339, 0x0010 },
411 { 0x033a, 0x1010 },
412 { 0x03c0, 0x7e00 },
413 { 0x03c1, 0x8000 },
414 { 0x03c2, 0x8000 },
415 { 0x03c3, 0x8000 },
416 { 0x03c4, 0x8000 },
417 { 0x03c5, 0x8000 },
418 { 0x03c6, 0x8000 },
419 { 0x03c7, 0x8000 },
420 { 0x03c8, 0x8000 },
421 { 0x03c9, 0x8000 },
422 { 0x03ca, 0x8000 },
423 { 0x03cb, 0x8000 },
424 { 0x03cc, 0x8000 },
425 { 0x03d0, 0x0000 },
426 { 0x03d1, 0x0000 },
427 { 0x03d2, 0x0000 },
428 { 0x03d3, 0x0000 },
429 { 0x03d4, 0x2000 },
430 { 0x03d5, 0x2000 },
431 { 0x03d6, 0x0000 },
432 { 0x03d7, 0x0000 },
433 { 0x03d8, 0x2000 },
434 { 0x03d9, 0x2000 },
435 { 0x03da, 0x2000 },
436 { 0x03db, 0x2000 },
437 { 0x03dc, 0x0000 },
438 { 0x03dd, 0x0000 },
439 { 0x03de, 0x0000 },
440 { 0x03df, 0x2000 },
441 { 0x03e0, 0x0000 },
442 { 0x03e1, 0x0000 },
443 { 0x03e2, 0x0000 },
444 { 0x03e3, 0x0000 },
445 { 0x03e4, 0x0000 },
446 { 0x03e5, 0x0000 },
447 { 0x03e6, 0x0000 },
448 { 0x03e7, 0x0000 },
449 { 0x03e8, 0x0000 },
450 { 0x03e9, 0x0000 },
451 { 0x03ea, 0x0000 },
452 { 0x03eb, 0x0000 },
453 { 0x03ec, 0x0000 },
454 { 0x03ed, 0x0000 },
455 { 0x03ee, 0x0000 },
456 { 0x03ef, 0x0000 },
457 { 0x03f0, 0x0800 },
458 { 0x03f1, 0x0800 },
459 { 0x03f2, 0x0800 },
460 { 0x03f3, 0x0800 },
461 { 0x03fe, 0x0000 },
462 { 0x03ff, 0x0000 },
463 { 0x07f0, 0x0000 },
464 { 0x07fa, 0x0000 },
465};
466
467static const struct reg_default rt5663_reg[] = {
468 { 0x0000, 0x0000 },
469 { 0x0002, 0x0008 },
470 { 0x0005, 0x1000 },
471 { 0x0006, 0x1000 },
472 { 0x000a, 0x0000 },
473 { 0x0010, 0x000f },
474 { 0x0015, 0x42c1 },
475 { 0x0016, 0x0000 },
476 { 0x0018, 0x000b },
477 { 0x0019, 0xafaf },
478 { 0x001c, 0x2f2f },
479 { 0x001f, 0x0000 },
480 { 0x0022, 0x5757 },
481 { 0x0023, 0x0039 },
482 { 0x0026, 0xc0c0 },
483 { 0x0029, 0x8080 },
oder_chiou@realtek.com450f0f62017-07-10 11:14:56 +0800[diff] [blame]484 { 0x002a, 0x8080 },
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]485 { 0x002c, 0x000c },
486 { 0x002d, 0x0000 },
487 { 0x0040, 0x0808 },
488 { 0x0061, 0x0000 },
489 { 0x0062, 0x0000 },
490 { 0x0063, 0x003e },
491 { 0x0064, 0x0000 },
492 { 0x0065, 0x0000 },
493 { 0x0066, 0x0000 },
494 { 0x006b, 0x0000 },
495 { 0x006e, 0x0000 },
496 { 0x006f, 0x0000 },
497 { 0x0070, 0x8020 },
498 { 0x0073, 0x1000 },
499 { 0x0074, 0xe400 },
500 { 0x0075, 0x0002 },
501 { 0x0076, 0x0001 },
502 { 0x0077, 0x00f0 },
503 { 0x0078, 0x0000 },
504 { 0x0079, 0x0000 },
505 { 0x007a, 0x0123 },
506 { 0x007b, 0x8003 },
507 { 0x0080, 0x0000 },
508 { 0x0081, 0x0000 },
509 { 0x0082, 0x0000 },
510 { 0x0083, 0x0000 },
511 { 0x0084, 0x0000 },
512 { 0x0086, 0x0008 },
513 { 0x0087, 0x0000 },
514 { 0x008a, 0x0000 },
515 { 0x008b, 0x0000 },
516 { 0x008c, 0x0003 },
517 { 0x008e, 0x0004 },
518 { 0x008f, 0x1000 },
519 { 0x0090, 0x0646 },
520 { 0x0091, 0x0e3e },
521 { 0x0092, 0x1071 },
522 { 0x0093, 0x0000 },
523 { 0x0094, 0x0080 },
524 { 0x0097, 0x0000 },
525 { 0x0098, 0x0000 },
526 { 0x009a, 0x0000 },
527 { 0x009f, 0x0000 },
528 { 0x00ae, 0x2000 },
529 { 0x00af, 0x0000 },
530 { 0x00b6, 0x0000 },
531 { 0x00b7, 0x0000 },
532 { 0x00b8, 0x0000 },
533 { 0x00ba, 0x0000 },
534 { 0x00bb, 0x0000 },
535 { 0x00be, 0x0000 },
536 { 0x00bf, 0x0000 },
537 { 0x00c0, 0x0000 },
538 { 0x00c1, 0x0000 },
539 { 0x00c5, 0x0000 },
540 { 0x00cb, 0xa02f },
541 { 0x00cc, 0x0000 },
542 { 0x00cd, 0x0e02 },
543 { 0x00d9, 0x08f9 },
544 { 0x00db, 0x0008 },
545 { 0x00dc, 0x00c0 },
546 { 0x00dd, 0x6724 },
547 { 0x00de, 0x3131 },
548 { 0x00df, 0x0008 },
549 { 0x00e0, 0x4000 },
550 { 0x00e1, 0x3131 },
551 { 0x00e2, 0x0043 },
552 { 0x00e4, 0x400b },
553 { 0x00e5, 0x8031 },
554 { 0x00e6, 0x3080 },
555 { 0x00e7, 0x4100 },
556 { 0x00e8, 0x1400 },
557 { 0x00e9, 0xe00a },
558 { 0x00ea, 0x0404 },
559 { 0x00eb, 0x0404 },
560 { 0x00ec, 0xb320 },
561 { 0x00ed, 0x0000 },
562 { 0x00f4, 0x0000 },
563 { 0x00f6, 0x0000 },
564 { 0x00f8, 0x0000 },
565 { 0x00fa, 0x8000 },
566 { 0x00fd, 0x0001 },
567 { 0x00fe, 0x10ec },
568 { 0x00ff, 0x6406 },
569 { 0x0100, 0xa0a0 },
570 { 0x0108, 0x4444 },
571 { 0x0109, 0x4444 },
572 { 0x010a, 0xaaaa },
573 { 0x010b, 0x00a0 },
574 { 0x010c, 0x8aaa },
575 { 0x010d, 0xaaaa },
576 { 0x010e, 0x2aaa },
577 { 0x010f, 0x002a },
578 { 0x0110, 0xa0a4 },
579 { 0x0111, 0x4602 },
580 { 0x0112, 0x0101 },
581 { 0x0113, 0x2000 },
582 { 0x0114, 0x0000 },
583 { 0x0116, 0x0000 },
584 { 0x0117, 0x0f00 },
585 { 0x0118, 0x0006 },
586 { 0x0125, 0x2224 },
587 { 0x0126, 0x5550 },
588 { 0x0127, 0x0400 },
589 { 0x0128, 0x7711 },
590 { 0x0132, 0x0004 },
591 { 0x0137, 0x5441 },
592 { 0x0139, 0x79a1 },
593 { 0x013a, 0x30c0 },
594 { 0x013b, 0x2000 },
595 { 0x013c, 0x2005 },
596 { 0x013d, 0x30c0 },
597 { 0x013e, 0x0000 },
598 { 0x0140, 0x3700 },
599 { 0x0141, 0x1f00 },
600 { 0x0144, 0x0000 },
601 { 0x0145, 0x0002 },
602 { 0x0146, 0x0000 },
603 { 0x0160, 0x0e80 },
604 { 0x0161, 0x0020 },
605 { 0x0162, 0x0080 },
606 { 0x0163, 0x0800 },
607 { 0x0164, 0x0000 },
608 { 0x0165, 0x0000 },
609 { 0x0166, 0x0000 },
610 { 0x0167, 0x1417 },
611 { 0x0168, 0x0017 },
612 { 0x0169, 0x0017 },
613 { 0x0180, 0x2000 },
614 { 0x0181, 0x0000 },
615 { 0x0182, 0x0000 },
616 { 0x0183, 0x2000 },
617 { 0x0184, 0x0000 },
618 { 0x0185, 0x0000 },
619 { 0x01b0, 0x4b30 },
620 { 0x01b1, 0x0000 },
621 { 0x01b2, 0xd870 },
622 { 0x01b3, 0x0000 },
623 { 0x01b4, 0x0030 },
624 { 0x01b5, 0x5757 },
625 { 0x01b6, 0x5757 },
626 { 0x01b7, 0x5757 },
627 { 0x01b8, 0x5757 },
628 { 0x01c0, 0x433d },
629 { 0x01c1, 0x0540 },
630 { 0x01c2, 0x0000 },
631 { 0x01c3, 0x0000 },
632 { 0x01c4, 0x0000 },
633 { 0x01c5, 0x0009 },
634 { 0x01c6, 0x0018 },
635 { 0x01c7, 0x002a },
636 { 0x01c8, 0x004c },
637 { 0x01c9, 0x0097 },
638 { 0x01ca, 0x01c3 },
639 { 0x01cb, 0x03e9 },
640 { 0x01cc, 0x1389 },
641 { 0x01cd, 0xc351 },
642 { 0x01ce, 0x0000 },
643 { 0x01cf, 0x0000 },
644 { 0x01d0, 0x0000 },
645 { 0x01d1, 0x0000 },
646 { 0x01d2, 0x0000 },
647 { 0x01d3, 0x003c },
648 { 0x01d4, 0x5757 },
649 { 0x01d5, 0x5757 },
650 { 0x01d6, 0x5757 },
651 { 0x01d7, 0x5757 },
652 { 0x01d8, 0x5757 },
653 { 0x01d9, 0x5757 },
654 { 0x01da, 0x0000 },
655 { 0x01db, 0x0000 },
656 { 0x01dd, 0x0009 },
657 { 0x01de, 0x7f00 },
658 { 0x01df, 0x00c8 },
659 { 0x01e0, 0x0691 },
660 { 0x01e1, 0x0000 },
661 { 0x01e2, 0x0000 },
662 { 0x01e3, 0x0000 },
663 { 0x01e4, 0x0000 },
664 { 0x01e5, 0x0040 },
665 { 0x01e6, 0x0000 },
666 { 0x01e7, 0x0000 },
667 { 0x01e8, 0x0000 },
668 { 0x01ea, 0x0000 },
669 { 0x01eb, 0x0000 },
670 { 0x01ec, 0x0000 },
671 { 0x01ed, 0x0000 },
672 { 0x01ee, 0x0000 },
673 { 0x01ef, 0x0000 },
674 { 0x01f0, 0x0000 },
675 { 0x01f1, 0x0000 },
676 { 0x01f2, 0x0000 },
677 { 0x0200, 0x0000 },
678 { 0x0201, 0x2244 },
679 { 0x0202, 0xaaaa },
680 { 0x0250, 0x8010 },
681 { 0x0251, 0x0000 },
682 { 0x0252, 0x028a },
683 { 0x02fa, 0x0000 },
684 { 0x02fb, 0x0000 },
685 { 0x02fc, 0x0000 },
686 { 0x0300, 0x0000 },
687 { 0x03d0, 0x0000 },
688 { 0x03d1, 0x0000 },
689 { 0x03d2, 0x0000 },
690 { 0x03d3, 0x0000 },
691 { 0x03d4, 0x2000 },
692 { 0x03d5, 0x2000 },
693 { 0x03d6, 0x0000 },
694 { 0x03d7, 0x0000 },
695 { 0x03d8, 0x2000 },
696 { 0x03d9, 0x2000 },
697 { 0x03da, 0x2000 },
698 { 0x03db, 0x2000 },
699 { 0x03dc, 0x0000 },
700 { 0x03dd, 0x0000 },
701 { 0x03de, 0x0000 },
702 { 0x03df, 0x2000 },
703 { 0x03e0, 0x0000 },
704 { 0x03e1, 0x0000 },
705 { 0x03e2, 0x0000 },
706 { 0x03e3, 0x0000 },
707 { 0x03e4, 0x0000 },
708 { 0x03e5, 0x0000 },
709 { 0x03e6, 0x0000 },
710 { 0x03e7, 0x0000 },
711 { 0x03e8, 0x0000 },
712 { 0x03e9, 0x0000 },
713 { 0x03ea, 0x0000 },
714 { 0x03eb, 0x0000 },
715 { 0x03ec, 0x0000 },
716 { 0x03ed, 0x0000 },
717 { 0x03ee, 0x0000 },
718 { 0x03ef, 0x0000 },
719 { 0x03f0, 0x0800 },
720 { 0x03f1, 0x0800 },
721 { 0x03f2, 0x0800 },
722 { 0x03f3, 0x0800 },
723};
724
725static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
726{
727 switch (reg) {
728 case RT5663_RESET:
729 case RT5663_SIL_DET_CTL:
730 case RT5663_HP_IMP_GAIN_2:
731 case RT5663_AD_DA_MIXER:
732 case RT5663_FRAC_DIV_2:
733 case RT5663_MICBIAS_1:
734 case RT5663_ASRC_11_2:
735 case RT5663_ADC_EQ_1:
736 case RT5663_INT_ST_1:
737 case RT5663_INT_ST_2:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]738 case RT5663_GPIO_STA1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]739 case RT5663_SIN_GEN_1:
740 case RT5663_IL_CMD_1:
741 case RT5663_IL_CMD_5:
742 case RT5663_IL_CMD_PWRSAV1:
743 case RT5663_EM_JACK_TYPE_1:
744 case RT5663_EM_JACK_TYPE_2:
745 case RT5663_EM_JACK_TYPE_3:
746 case RT5663_JD_CTRL2:
747 case RT5663_VENDOR_ID:
748 case RT5663_VENDOR_ID_1:
749 case RT5663_VENDOR_ID_2:
750 case RT5663_PLL_INT_REG:
751 case RT5663_SOFT_RAMP:
752 case RT5663_STO_DRE_1:
753 case RT5663_STO_DRE_5:
754 case RT5663_STO_DRE_6:
755 case RT5663_STO_DRE_7:
756 case RT5663_MIC_DECRO_1:
757 case RT5663_MIC_DECRO_4:
758 case RT5663_HP_IMP_SEN_1:
759 case RT5663_HP_IMP_SEN_3:
760 case RT5663_HP_IMP_SEN_4:
761 case RT5663_HP_IMP_SEN_5:
762 case RT5663_HP_CALIB_1_1:
763 case RT5663_HP_CALIB_9:
764 case RT5663_HP_CALIB_ST1:
765 case RT5663_HP_CALIB_ST2:
766 case RT5663_HP_CALIB_ST3:
767 case RT5663_HP_CALIB_ST4:
768 case RT5663_HP_CALIB_ST5:
769 case RT5663_HP_CALIB_ST6:
770 case RT5663_HP_CALIB_ST7:
771 case RT5663_HP_CALIB_ST8:
772 case RT5663_HP_CALIB_ST9:
773 case RT5663_ANA_JD:
774 return true;
775 default:
776 return false;
777 }
778}
779
780static bool rt5663_readable_register(struct device *dev, unsigned int reg)
781{
782 switch (reg) {
783 case RT5663_RESET:
784 case RT5663_HP_OUT_EN:
785 case RT5663_HP_LCH_DRE:
786 case RT5663_HP_RCH_DRE:
787 case RT5663_CALIB_BST:
788 case RT5663_RECMIX:
789 case RT5663_SIL_DET_CTL:
790 case RT5663_PWR_SAV_SILDET:
791 case RT5663_SIDETONE_CTL:
792 case RT5663_STO1_DAC_DIG_VOL:
793 case RT5663_STO1_ADC_DIG_VOL:
794 case RT5663_STO1_BOOST:
795 case RT5663_HP_IMP_GAIN_1:
796 case RT5663_HP_IMP_GAIN_2:
797 case RT5663_STO1_ADC_MIXER:
798 case RT5663_AD_DA_MIXER:
799 case RT5663_STO_DAC_MIXER:
800 case RT5663_DIG_SIDE_MIXER:
801 case RT5663_BYPASS_STO_DAC:
802 case RT5663_CALIB_REC_MIX:
803 case RT5663_PWR_DIG_1:
804 case RT5663_PWR_DIG_2:
805 case RT5663_PWR_ANLG_1:
806 case RT5663_PWR_ANLG_2:
807 case RT5663_PWR_ANLG_3:
808 case RT5663_PWR_MIXER:
809 case RT5663_SIG_CLK_DET:
810 case RT5663_PRE_DIV_GATING_1:
811 case RT5663_PRE_DIV_GATING_2:
812 case RT5663_I2S1_SDP:
813 case RT5663_ADDA_CLK_1:
814 case RT5663_ADDA_RST:
815 case RT5663_FRAC_DIV_1:
816 case RT5663_FRAC_DIV_2:
817 case RT5663_TDM_1:
818 case RT5663_TDM_2:
819 case RT5663_TDM_3:
820 case RT5663_TDM_4:
821 case RT5663_TDM_5:
822 case RT5663_GLB_CLK:
823 case RT5663_PLL_1:
824 case RT5663_PLL_2:
825 case RT5663_ASRC_1:
826 case RT5663_ASRC_2:
827 case RT5663_ASRC_4:
828 case RT5663_DUMMY_REG:
829 case RT5663_ASRC_8:
830 case RT5663_ASRC_9:
831 case RT5663_ASRC_11:
832 case RT5663_DEPOP_1:
833 case RT5663_DEPOP_2:
834 case RT5663_DEPOP_3:
835 case RT5663_HP_CHARGE_PUMP_1:
836 case RT5663_HP_CHARGE_PUMP_2:
837 case RT5663_MICBIAS_1:
838 case RT5663_RC_CLK:
839 case RT5663_ASRC_11_2:
840 case RT5663_DUMMY_REG_2:
841 case RT5663_REC_PATH_GAIN:
842 case RT5663_AUTO_1MRC_CLK:
843 case RT5663_ADC_EQ_1:
844 case RT5663_ADC_EQ_2:
845 case RT5663_IRQ_1:
846 case RT5663_IRQ_2:
847 case RT5663_IRQ_3:
848 case RT5663_IRQ_4:
849 case RT5663_IRQ_5:
850 case RT5663_INT_ST_1:
851 case RT5663_INT_ST_2:
852 case RT5663_GPIO_1:
853 case RT5663_GPIO_2:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]854 case RT5663_GPIO_STA1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]855 case RT5663_SIN_GEN_1:
856 case RT5663_SIN_GEN_2:
857 case RT5663_SIN_GEN_3:
858 case RT5663_SOF_VOL_ZC1:
859 case RT5663_IL_CMD_1:
860 case RT5663_IL_CMD_2:
861 case RT5663_IL_CMD_3:
862 case RT5663_IL_CMD_4:
863 case RT5663_IL_CMD_5:
864 case RT5663_IL_CMD_6:
865 case RT5663_IL_CMD_7:
866 case RT5663_IL_CMD_8:
867 case RT5663_IL_CMD_PWRSAV1:
868 case RT5663_IL_CMD_PWRSAV2:
869 case RT5663_EM_JACK_TYPE_1:
870 case RT5663_EM_JACK_TYPE_2:
871 case RT5663_EM_JACK_TYPE_3:
872 case RT5663_EM_JACK_TYPE_4:
873 case RT5663_EM_JACK_TYPE_5:
874 case RT5663_EM_JACK_TYPE_6:
875 case RT5663_STO1_HPF_ADJ1:
876 case RT5663_STO1_HPF_ADJ2:
877 case RT5663_FAST_OFF_MICBIAS:
878 case RT5663_JD_CTRL1:
879 case RT5663_JD_CTRL2:
880 case RT5663_DIG_MISC:
881 case RT5663_VENDOR_ID:
882 case RT5663_VENDOR_ID_1:
883 case RT5663_VENDOR_ID_2:
884 case RT5663_DIG_VOL_ZCD:
885 case RT5663_ANA_BIAS_CUR_1:
886 case RT5663_ANA_BIAS_CUR_2:
887 case RT5663_ANA_BIAS_CUR_3:
888 case RT5663_ANA_BIAS_CUR_4:
889 case RT5663_ANA_BIAS_CUR_5:
890 case RT5663_ANA_BIAS_CUR_6:
891 case RT5663_BIAS_CUR_5:
892 case RT5663_BIAS_CUR_6:
893 case RT5663_BIAS_CUR_7:
894 case RT5663_BIAS_CUR_8:
895 case RT5663_DACREF_LDO:
896 case RT5663_DUMMY_REG_3:
897 case RT5663_BIAS_CUR_9:
898 case RT5663_DUMMY_REG_4:
899 case RT5663_VREFADJ_OP:
900 case RT5663_VREF_RECMIX:
901 case RT5663_CHARGE_PUMP_1:
902 case RT5663_CHARGE_PUMP_1_2:
903 case RT5663_CHARGE_PUMP_1_3:
904 case RT5663_CHARGE_PUMP_2:
905 case RT5663_DIG_IN_PIN1:
906 case RT5663_PAD_DRV_CTL:
907 case RT5663_PLL_INT_REG:
908 case RT5663_CHOP_DAC_L:
909 case RT5663_CHOP_ADC:
910 case RT5663_CALIB_ADC:
911 case RT5663_CHOP_DAC_R:
912 case RT5663_DUMMY_CTL_DACLR:
913 case RT5663_DUMMY_REG_5:
914 case RT5663_SOFT_RAMP:
915 case RT5663_TEST_MODE_1:
916 case RT5663_TEST_MODE_2:
917 case RT5663_TEST_MODE_3:
918 case RT5663_STO_DRE_1:
919 case RT5663_STO_DRE_2:
920 case RT5663_STO_DRE_3:
921 case RT5663_STO_DRE_4:
922 case RT5663_STO_DRE_5:
923 case RT5663_STO_DRE_6:
924 case RT5663_STO_DRE_7:
925 case RT5663_STO_DRE_8:
926 case RT5663_STO_DRE_9:
927 case RT5663_STO_DRE_10:
928 case RT5663_MIC_DECRO_1:
929 case RT5663_MIC_DECRO_2:
930 case RT5663_MIC_DECRO_3:
931 case RT5663_MIC_DECRO_4:
932 case RT5663_MIC_DECRO_5:
933 case RT5663_MIC_DECRO_6:
934 case RT5663_HP_DECRO_1:
935 case RT5663_HP_DECRO_2:
936 case RT5663_HP_DECRO_3:
937 case RT5663_HP_DECRO_4:
938 case RT5663_HP_DECOUP:
939 case RT5663_HP_IMP_SEN_MAP8:
940 case RT5663_HP_IMP_SEN_MAP9:
941 case RT5663_HP_IMP_SEN_MAP10:
942 case RT5663_HP_IMP_SEN_MAP11:
943 case RT5663_HP_IMP_SEN_1:
944 case RT5663_HP_IMP_SEN_2:
945 case RT5663_HP_IMP_SEN_3:
946 case RT5663_HP_IMP_SEN_4:
947 case RT5663_HP_IMP_SEN_5:
948 case RT5663_HP_IMP_SEN_6:
949 case RT5663_HP_IMP_SEN_7:
950 case RT5663_HP_IMP_SEN_8:
951 case RT5663_HP_IMP_SEN_9:
952 case RT5663_HP_IMP_SEN_10:
953 case RT5663_HP_IMP_SEN_11:
954 case RT5663_HP_IMP_SEN_12:
955 case RT5663_HP_IMP_SEN_13:
956 case RT5663_HP_IMP_SEN_14:
957 case RT5663_HP_IMP_SEN_15:
958 case RT5663_HP_IMP_SEN_16:
959 case RT5663_HP_IMP_SEN_17:
960 case RT5663_HP_IMP_SEN_18:
961 case RT5663_HP_IMP_SEN_19:
962 case RT5663_HP_IMPSEN_DIG5:
963 case RT5663_HP_IMPSEN_MAP1:
964 case RT5663_HP_IMPSEN_MAP2:
965 case RT5663_HP_IMPSEN_MAP3:
966 case RT5663_HP_IMPSEN_MAP4:
967 case RT5663_HP_IMPSEN_MAP5:
968 case RT5663_HP_IMPSEN_MAP7:
969 case RT5663_HP_LOGIC_1:
970 case RT5663_HP_LOGIC_2:
971 case RT5663_HP_CALIB_1:
972 case RT5663_HP_CALIB_1_1:
973 case RT5663_HP_CALIB_2:
974 case RT5663_HP_CALIB_3:
975 case RT5663_HP_CALIB_4:
976 case RT5663_HP_CALIB_5:
977 case RT5663_HP_CALIB_5_1:
978 case RT5663_HP_CALIB_6:
979 case RT5663_HP_CALIB_7:
980 case RT5663_HP_CALIB_9:
981 case RT5663_HP_CALIB_10:
982 case RT5663_HP_CALIB_11:
983 case RT5663_HP_CALIB_ST1:
984 case RT5663_HP_CALIB_ST2:
985 case RT5663_HP_CALIB_ST3:
986 case RT5663_HP_CALIB_ST4:
987 case RT5663_HP_CALIB_ST5:
988 case RT5663_HP_CALIB_ST6:
989 case RT5663_HP_CALIB_ST7:
990 case RT5663_HP_CALIB_ST8:
991 case RT5663_HP_CALIB_ST9:
992 case RT5663_HP_AMP_DET:
993 case RT5663_DUMMY_REG_6:
994 case RT5663_HP_BIAS:
995 case RT5663_CBJ_1:
996 case RT5663_CBJ_2:
997 case RT5663_CBJ_3:
998 case RT5663_DUMMY_1:
999 case RT5663_DUMMY_2:
1000 case RT5663_DUMMY_3:
1001 case RT5663_ANA_JD:
1002 case RT5663_ADC_LCH_LPF1_A1:
1003 case RT5663_ADC_RCH_LPF1_A1:
1004 case RT5663_ADC_LCH_LPF1_H0:
1005 case RT5663_ADC_RCH_LPF1_H0:
1006 case RT5663_ADC_LCH_BPF1_A1:
1007 case RT5663_ADC_RCH_BPF1_A1:
1008 case RT5663_ADC_LCH_BPF1_A2:
1009 case RT5663_ADC_RCH_BPF1_A2:
1010 case RT5663_ADC_LCH_BPF1_H0:
1011 case RT5663_ADC_RCH_BPF1_H0:
1012 case RT5663_ADC_LCH_BPF2_A1:
1013 case RT5663_ADC_RCH_BPF2_A1:
1014 case RT5663_ADC_LCH_BPF2_A2:
1015 case RT5663_ADC_RCH_BPF2_A2:
1016 case RT5663_ADC_LCH_BPF2_H0:
1017 case RT5663_ADC_RCH_BPF2_H0:
1018 case RT5663_ADC_LCH_BPF3_A1:
1019 case RT5663_ADC_RCH_BPF3_A1:
1020 case RT5663_ADC_LCH_BPF3_A2:
1021 case RT5663_ADC_RCH_BPF3_A2:
1022 case RT5663_ADC_LCH_BPF3_H0:
1023 case RT5663_ADC_RCH_BPF3_H0:
1024 case RT5663_ADC_LCH_BPF4_A1:
1025 case RT5663_ADC_RCH_BPF4_A1:
1026 case RT5663_ADC_LCH_BPF4_A2:
1027 case RT5663_ADC_RCH_BPF4_A2:
1028 case RT5663_ADC_LCH_BPF4_H0:
1029 case RT5663_ADC_RCH_BPF4_H0:
1030 case RT5663_ADC_LCH_HPF1_A1:
1031 case RT5663_ADC_RCH_HPF1_A1:
1032 case RT5663_ADC_LCH_HPF1_H0:
1033 case RT5663_ADC_RCH_HPF1_H0:
1034 case RT5663_ADC_EQ_PRE_VOL_L:
1035 case RT5663_ADC_EQ_PRE_VOL_R:
1036 case RT5663_ADC_EQ_POST_VOL_L:
1037 case RT5663_ADC_EQ_POST_VOL_R:
1038 return true;
1039 default:
1040 return false;
1041 }
1042}
1043
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1044static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg)
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1045{
1046 switch (reg) {
1047 case RT5663_RESET:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1048 case RT5663_CBJ_TYPE_2:
1049 case RT5663_PDM_OUT_CTL:
1050 case RT5663_PDM_I2C_DATA_CTL1:
1051 case RT5663_PDM_I2C_DATA_CTL4:
1052 case RT5663_ALC_BK_GAIN:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1053 case RT5663_PLL_2:
1054 case RT5663_MICBIAS_1:
1055 case RT5663_ADC_EQ_1:
1056 case RT5663_INT_ST_1:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1057 case RT5663_GPIO_STA2:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1058 case RT5663_IL_CMD_1:
1059 case RT5663_IL_CMD_5:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1060 case RT5663_A_JD_CTRL:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1061 case RT5663_JD_CTRL2:
1062 case RT5663_VENDOR_ID:
1063 case RT5663_VENDOR_ID_1:
1064 case RT5663_VENDOR_ID_2:
1065 case RT5663_STO_DRE_1:
1066 case RT5663_STO_DRE_5:
1067 case RT5663_STO_DRE_6:
1068 case RT5663_STO_DRE_7:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1069 case RT5663_MONO_DYNA_6:
1070 case RT5663_STO1_SIL_DET:
1071 case RT5663_MONOL_SIL_DET:
1072 case RT5663_MONOR_SIL_DET:
1073 case RT5663_STO2_DAC_SIL:
1074 case RT5663_MONO_AMP_CAL_ST1:
1075 case RT5663_MONO_AMP_CAL_ST2:
1076 case RT5663_MONO_AMP_CAL_ST3:
1077 case RT5663_MONO_AMP_CAL_ST4:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1078 case RT5663_HP_IMP_SEN_2:
1079 case RT5663_HP_IMP_SEN_3:
1080 case RT5663_HP_IMP_SEN_4:
1081 case RT5663_HP_IMP_SEN_10:
1082 case RT5663_HP_CALIB_1:
1083 case RT5663_HP_CALIB_10:
1084 case RT5663_HP_CALIB_ST1:
1085 case RT5663_HP_CALIB_ST4:
1086 case RT5663_HP_CALIB_ST5:
1087 case RT5663_HP_CALIB_ST6:
1088 case RT5663_HP_CALIB_ST7:
1089 case RT5663_HP_CALIB_ST8:
1090 case RT5663_HP_CALIB_ST9:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1091 case RT5663_HP_CALIB_ST10:
1092 case RT5663_HP_CALIB_ST11:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1093 return true;
1094 default:
1095 return false;
1096 }
1097}
1098
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1099static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg)
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1100{
1101 switch (reg) {
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1102 case RT5663_LOUT_CTRL:
1103 case RT5663_HP_AMP_2:
1104 case RT5663_MONO_OUT:
1105 case RT5663_MONO_GAIN:
1106 case RT5663_AEC_BST:
1107 case RT5663_IN1_IN2:
1108 case RT5663_IN3_IN4:
1109 case RT5663_INL1_INR1:
1110 case RT5663_CBJ_TYPE_2:
1111 case RT5663_CBJ_TYPE_3:
1112 case RT5663_CBJ_TYPE_4:
1113 case RT5663_CBJ_TYPE_5:
1114 case RT5663_CBJ_TYPE_8:
1115 case RT5663_DAC3_DIG_VOL:
1116 case RT5663_DAC3_CTRL:
1117 case RT5663_MONO_ADC_DIG_VOL:
1118 case RT5663_STO2_ADC_DIG_VOL:
1119 case RT5663_MONO_ADC_BST_GAIN:
1120 case RT5663_STO2_ADC_BST_GAIN:
1121 case RT5663_SIDETONE_CTRL:
1122 case RT5663_MONO1_ADC_MIXER:
1123 case RT5663_STO2_ADC_MIXER:
1124 case RT5663_MONO_DAC_MIXER:
1125 case RT5663_DAC2_SRC_CTRL:
1126 case RT5663_IF_3_4_DATA_CTL:
1127 case RT5663_IF_5_DATA_CTL:
1128 case RT5663_PDM_OUT_CTL:
1129 case RT5663_PDM_I2C_DATA_CTL1:
1130 case RT5663_PDM_I2C_DATA_CTL2:
1131 case RT5663_PDM_I2C_DATA_CTL3:
1132 case RT5663_PDM_I2C_DATA_CTL4:
1133 case RT5663_RECMIX1_NEW:
1134 case RT5663_RECMIX1L_0:
1135 case RT5663_RECMIX1L:
1136 case RT5663_RECMIX1R_0:
1137 case RT5663_RECMIX1R:
1138 case RT5663_RECMIX2_NEW:
1139 case RT5663_RECMIX2_L_2:
1140 case RT5663_RECMIX2_R:
1141 case RT5663_RECMIX2_R_2:
1142 case RT5663_CALIB_REC_LR:
1143 case RT5663_ALC_BK_GAIN:
1144 case RT5663_MONOMIX_GAIN:
1145 case RT5663_MONOMIX_IN_GAIN:
1146 case RT5663_OUT_MIXL_GAIN:
1147 case RT5663_OUT_LMIX_IN_GAIN:
1148 case RT5663_OUT_RMIX_IN_GAIN:
1149 case RT5663_OUT_RMIX_IN_GAIN1:
1150 case RT5663_LOUT_MIXER_CTRL:
1151 case RT5663_PWR_VOL:
1152 case RT5663_ADCDAC_RST:
1153 case RT5663_I2S34_SDP:
1154 case RT5663_I2S5_SDP:
1155 case RT5663_TDM_6:
1156 case RT5663_TDM_7:
1157 case RT5663_TDM_8:
1158 case RT5663_TDM_9:
1159 case RT5663_ASRC_3:
1160 case RT5663_ASRC_6:
1161 case RT5663_ASRC_7:
1162 case RT5663_PLL_TRK_13:
1163 case RT5663_I2S_M_CLK_CTL:
1164 case RT5663_FDIV_I2S34_M_CLK:
1165 case RT5663_FDIV_I2S34_M_CLK2:
1166 case RT5663_FDIV_I2S5_M_CLK:
1167 case RT5663_FDIV_I2S5_M_CLK2:
1168 case RT5663_V2_IRQ_4:
1169 case RT5663_GPIO_3:
1170 case RT5663_GPIO_4:
1171 case RT5663_GPIO_STA2:
1172 case RT5663_HP_AMP_DET1:
1173 case RT5663_HP_AMP_DET2:
1174 case RT5663_HP_AMP_DET3:
1175 case RT5663_MID_BD_HP_AMP:
1176 case RT5663_LOW_BD_HP_AMP:
1177 case RT5663_SOF_VOL_ZC2:
1178 case RT5663_ADC_STO2_ADJ1:
1179 case RT5663_ADC_STO2_ADJ2:
1180 case RT5663_A_JD_CTRL:
1181 case RT5663_JD1_TRES_CTRL:
1182 case RT5663_JD2_TRES_CTRL:
1183 case RT5663_V2_JD_CTRL2:
1184 case RT5663_DUM_REG_2:
1185 case RT5663_DUM_REG_3:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1186 case RT5663_VENDOR_ID:
1187 case RT5663_VENDOR_ID_1:
1188 case RT5663_VENDOR_ID_2:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1189 case RT5663_DACADC_DIG_VOL2:
1190 case RT5663_DIG_IN_PIN2:
1191 case RT5663_PAD_DRV_CTL1:
1192 case RT5663_SOF_RAM_DEPOP:
1193 case RT5663_VOL_TEST:
1194 case RT5663_TEST_MODE_4:
1195 case RT5663_TEST_MODE_5:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1196 case RT5663_STO_DRE_9:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1197 case RT5663_MONO_DYNA_1:
1198 case RT5663_MONO_DYNA_2:
1199 case RT5663_MONO_DYNA_3:
1200 case RT5663_MONO_DYNA_4:
1201 case RT5663_MONO_DYNA_5:
1202 case RT5663_MONO_DYNA_6:
1203 case RT5663_STO1_SIL_DET:
1204 case RT5663_MONOL_SIL_DET:
1205 case RT5663_MONOR_SIL_DET:
1206 case RT5663_STO2_DAC_SIL:
1207 case RT5663_PWR_SAV_CTL1:
1208 case RT5663_PWR_SAV_CTL2:
1209 case RT5663_PWR_SAV_CTL3:
1210 case RT5663_PWR_SAV_CTL4:
1211 case RT5663_PWR_SAV_CTL5:
1212 case RT5663_PWR_SAV_CTL6:
1213 case RT5663_MONO_AMP_CAL1:
1214 case RT5663_MONO_AMP_CAL2:
1215 case RT5663_MONO_AMP_CAL3:
1216 case RT5663_MONO_AMP_CAL4:
1217 case RT5663_MONO_AMP_CAL5:
1218 case RT5663_MONO_AMP_CAL6:
1219 case RT5663_MONO_AMP_CAL7:
1220 case RT5663_MONO_AMP_CAL_ST1:
1221 case RT5663_MONO_AMP_CAL_ST2:
1222 case RT5663_MONO_AMP_CAL_ST3:
1223 case RT5663_MONO_AMP_CAL_ST4:
1224 case RT5663_MONO_AMP_CAL_ST5:
1225 case RT5663_V2_HP_IMP_SEN_13:
1226 case RT5663_V2_HP_IMP_SEN_14:
1227 case RT5663_V2_HP_IMP_SEN_6:
1228 case RT5663_V2_HP_IMP_SEN_7:
1229 case RT5663_V2_HP_IMP_SEN_8:
1230 case RT5663_V2_HP_IMP_SEN_9:
1231 case RT5663_V2_HP_IMP_SEN_10:
1232 case RT5663_HP_LOGIC_3:
1233 case RT5663_HP_CALIB_ST10:
1234 case RT5663_HP_CALIB_ST11:
1235 case RT5663_PRO_REG_TBL_4:
1236 case RT5663_PRO_REG_TBL_5:
1237 case RT5663_PRO_REG_TBL_6:
1238 case RT5663_PRO_REG_TBL_7:
1239 case RT5663_PRO_REG_TBL_8:
1240 case RT5663_PRO_REG_TBL_9:
1241 case RT5663_SAR_ADC_INL_1:
1242 case RT5663_SAR_ADC_INL_2:
1243 case RT5663_SAR_ADC_INL_3:
1244 case RT5663_SAR_ADC_INL_4:
1245 case RT5663_SAR_ADC_INL_5:
1246 case RT5663_SAR_ADC_INL_6:
1247 case RT5663_SAR_ADC_INL_7:
1248 case RT5663_SAR_ADC_INL_8:
1249 case RT5663_SAR_ADC_INL_9:
1250 case RT5663_SAR_ADC_INL_10:
1251 case RT5663_SAR_ADC_INL_11:
1252 case RT5663_SAR_ADC_INL_12:
1253 case RT5663_DRC_CTRL_1:
1254 case RT5663_DRC1_CTRL_2:
1255 case RT5663_DRC1_CTRL_3:
1256 case RT5663_DRC1_CTRL_4:
1257 case RT5663_DRC1_CTRL_5:
1258 case RT5663_DRC1_CTRL_6:
1259 case RT5663_DRC1_HD_CTRL_1:
1260 case RT5663_DRC1_HD_CTRL_2:
1261 case RT5663_DRC1_PRI_REG_1:
1262 case RT5663_DRC1_PRI_REG_2:
1263 case RT5663_DRC1_PRI_REG_3:
1264 case RT5663_DRC1_PRI_REG_4:
1265 case RT5663_DRC1_PRI_REG_5:
1266 case RT5663_DRC1_PRI_REG_6:
1267 case RT5663_DRC1_PRI_REG_7:
1268 case RT5663_DRC1_PRI_REG_8:
1269 case RT5663_ALC_PGA_CTL_1:
1270 case RT5663_ALC_PGA_CTL_2:
1271 case RT5663_ALC_PGA_CTL_3:
1272 case RT5663_ALC_PGA_CTL_4:
1273 case RT5663_ALC_PGA_CTL_5:
1274 case RT5663_ALC_PGA_CTL_6:
1275 case RT5663_ALC_PGA_CTL_7:
1276 case RT5663_ALC_PGA_CTL_8:
1277 case RT5663_ALC_PGA_REG_1:
1278 case RT5663_ALC_PGA_REG_2:
1279 case RT5663_ALC_PGA_REG_3:
1280 case RT5663_ADC_EQ_RECOV_1:
1281 case RT5663_ADC_EQ_RECOV_2:
1282 case RT5663_ADC_EQ_RECOV_3:
1283 case RT5663_ADC_EQ_RECOV_4:
1284 case RT5663_ADC_EQ_RECOV_5:
1285 case RT5663_ADC_EQ_RECOV_6:
1286 case RT5663_ADC_EQ_RECOV_7:
1287 case RT5663_ADC_EQ_RECOV_8:
1288 case RT5663_ADC_EQ_RECOV_9:
1289 case RT5663_ADC_EQ_RECOV_10:
1290 case RT5663_ADC_EQ_RECOV_11:
1291 case RT5663_ADC_EQ_RECOV_12:
1292 case RT5663_ADC_EQ_RECOV_13:
1293 case RT5663_VID_HIDDEN:
1294 case RT5663_VID_CUSTOMER:
1295 case RT5663_SCAN_MODE:
1296 case RT5663_I2C_BYPA:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1297 return true;
1298 case RT5663_TDM_1:
1299 case RT5663_DEPOP_3:
1300 case RT5663_ASRC_11_2:
1301 case RT5663_INT_ST_2:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1302 case RT5663_GPIO_STA1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1303 case RT5663_SIN_GEN_1:
1304 case RT5663_SIN_GEN_2:
1305 case RT5663_SIN_GEN_3:
1306 case RT5663_IL_CMD_PWRSAV1:
1307 case RT5663_IL_CMD_PWRSAV2:
1308 case RT5663_EM_JACK_TYPE_1:
1309 case RT5663_EM_JACK_TYPE_2:
1310 case RT5663_EM_JACK_TYPE_3:
1311 case RT5663_EM_JACK_TYPE_4:
1312 case RT5663_FAST_OFF_MICBIAS:
1313 case RT5663_ANA_BIAS_CUR_1:
1314 case RT5663_ANA_BIAS_CUR_2:
1315 case RT5663_BIAS_CUR_9:
1316 case RT5663_DUMMY_REG_4:
1317 case RT5663_VREF_RECMIX:
1318 case RT5663_CHARGE_PUMP_1_2:
1319 case RT5663_CHARGE_PUMP_1_3:
1320 case RT5663_CHARGE_PUMP_2:
1321 case RT5663_CHOP_DAC_R:
1322 case RT5663_DUMMY_CTL_DACLR:
1323 case RT5663_DUMMY_REG_5:
1324 case RT5663_SOFT_RAMP:
1325 case RT5663_TEST_MODE_1:
1326 case RT5663_STO_DRE_10:
1327 case RT5663_MIC_DECRO_1:
1328 case RT5663_MIC_DECRO_2:
1329 case RT5663_MIC_DECRO_3:
1330 case RT5663_MIC_DECRO_4:
1331 case RT5663_MIC_DECRO_5:
1332 case RT5663_MIC_DECRO_6:
1333 case RT5663_HP_DECRO_1:
1334 case RT5663_HP_DECRO_2:
1335 case RT5663_HP_DECRO_3:
1336 case RT5663_HP_DECRO_4:
1337 case RT5663_HP_DECOUP:
1338 case RT5663_HP_IMPSEN_MAP4:
1339 case RT5663_HP_IMPSEN_MAP5:
1340 case RT5663_HP_IMPSEN_MAP7:
1341 case RT5663_HP_CALIB_1:
1342 case RT5663_CBJ_1:
1343 case RT5663_CBJ_2:
1344 case RT5663_CBJ_3:
1345 return false;
1346 default:
1347 return rt5663_readable_register(dev, reg);
1348 }
1349}
1350
1351static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1352static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1353static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1354static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1355
1356/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
1357static const DECLARE_TLV_DB_RANGE(in_bst_tlv,
1358 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1359 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
1360 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
1361 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
1362 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
1363 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
1364 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
1365);
1366
1367/* Interface data select */
1368static const char * const rt5663_if1_adc_data_select[] = {
1369 "L/R", "R/L", "L/L", "R/R"
1370};
1371
Wei Yongjun66d7c262016-09-17 01:34:09 +0000[diff] [blame]1372static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1373 RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select);
1374
1375static void rt5663_enable_push_button_irq(struct snd_soc_codec *codec,
1376 bool enable)
1377{
1378 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1379
1380 if (enable) {
1381 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1382 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1383 /* reset in-line command */
1384 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1385 RT5663_RESET_4BTN_INL_MASK,
1386 RT5663_RESET_4BTN_INL_RESET);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1387 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1388 RT5663_RESET_4BTN_INL_MASK,
1389 RT5663_RESET_4BTN_INL_NOR);
1390 switch (rt5663->codec_ver) {
1391 case CODEC_VER_1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1392 snd_soc_update_bits(codec, RT5663_IRQ_3,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1393 RT5663_V2_EN_IRQ_INLINE_MASK,
1394 RT5663_V2_EN_IRQ_INLINE_NOR);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1395 break;
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1396 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1397 snd_soc_update_bits(codec, RT5663_IRQ_2,
1398 RT5663_EN_IRQ_INLINE_MASK,
1399 RT5663_EN_IRQ_INLINE_NOR);
1400 break;
1401 default:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1402 dev_err(codec->dev, "Unknown CODEC Version\n");
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1403 }
1404 } else {
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1405 switch (rt5663->codec_ver) {
1406 case CODEC_VER_1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1407 snd_soc_update_bits(codec, RT5663_IRQ_3,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1408 RT5663_V2_EN_IRQ_INLINE_MASK,
1409 RT5663_V2_EN_IRQ_INLINE_BYP);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1410 break;
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1411 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1412 snd_soc_update_bits(codec, RT5663_IRQ_2,
1413 RT5663_EN_IRQ_INLINE_MASK,
1414 RT5663_EN_IRQ_INLINE_BYP);
1415 break;
1416 default:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1417 dev_err(codec->dev, "Unknown CODEC Version\n");
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1418 }
1419 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1420 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1421 /* reset in-line command */
1422 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1423 RT5663_RESET_4BTN_INL_MASK,
1424 RT5663_RESET_4BTN_INL_RESET);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1425 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1426 RT5663_RESET_4BTN_INL_MASK,
1427 RT5663_RESET_4BTN_INL_NOR);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1428 }
1429}
1430
1431/**
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1432 * rt5663_v2_jack_detect - Detect headset.
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1433 * @codec: SoC audio codec device.
1434 * @jack_insert: Jack insert or not.
1435 *
1436 * Detect whether is headset or not when jack inserted.
1437 *
1438 * Returns detect status.
1439 */
1440
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1441static int rt5663_v2_jack_detect(struct snd_soc_codec *codec, int jack_insert)
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1442{
1443 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1444 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1445 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1446
1447 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1448 if (jack_insert) {
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1449 snd_soc_write(codec, RT5663_CBJ_TYPE_2, 0x8040);
1450 snd_soc_write(codec, RT5663_CBJ_TYPE_3, 0x1484);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1451
1452 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1453 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
1454 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
1455 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
1456 snd_soc_dapm_sync(dapm);
1457 snd_soc_update_bits(codec, RT5663_RC_CLK,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1458 RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1459 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x8);
1460
1461 while (i < 5) {
1462 msleep(sleep_time[i]);
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1463 val = snd_soc_read(codec, RT5663_CBJ_TYPE_2) & 0x0003;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1464 if (val == 0x1 || val == 0x2 || val == 0x3)
1465 break;
1466 dev_dbg(codec->dev, "%s: MX-0011 val=%x sleep %d\n",
1467 __func__, val, sleep_time[i]);
1468 i++;
1469 }
1470 dev_dbg(codec->dev, "%s val = %d\n", __func__, val);
1471 switch (val) {
1472 case 1:
1473 case 2:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1474 rt5663->jack_type = SND_JACK_HEADSET;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1475 rt5663_enable_push_button_irq(codec, true);
1476 break;
1477 default:
1478 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1479 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1480 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1481 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1482 snd_soc_dapm_sync(dapm);
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1483 rt5663->jack_type = SND_JACK_HEADPHONE;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1484 break;
1485 }
1486 } else {
1487 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x0);
1488
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1489 if (rt5663->jack_type == SND_JACK_HEADSET) {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1490 rt5663_enable_push_button_irq(codec, false);
1491 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1492 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1493 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1494 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1495 snd_soc_dapm_sync(dapm);
1496 }
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1497 rt5663->jack_type = 0;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1498 }
1499
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1500 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type);
1501 return rt5663->jack_type;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1502}
1503
1504/**
1505 * rt5663_jack_detect - Detect headset.
1506 * @codec: SoC audio codec device.
1507 * @jack_insert: Jack insert or not.
1508 *
1509 * Detect whether is headset or not when jack inserted.
1510 *
1511 * Returns detect status.
1512 */
1513static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1514{
1515 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
oder_chiou@realtek.com8f244122017-07-07 16:58:58 +0800[diff] [blame]1516 int val, i = 0;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1517
1518 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1519
1520 if (jack_insert) {
1521 snd_soc_update_bits(codec, RT5663_DIG_MISC,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1522 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1523 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1524 RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK |
1525 RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN |
1526 RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1527 snd_soc_update_bits(codec, RT5663_DUMMY_1,
1528 RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
1529 RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
1530 RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1);
1531 snd_soc_update_bits(codec, RT5663_CBJ_1,
1532 RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK,
1533 RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L);
1534 snd_soc_update_bits(codec, RT5663_IL_CMD_2,
1535 RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
1536 /* BST1 power on for JD */
1537 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1538 RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1539 snd_soc_update_bits(codec, RT5663_EM_JACK_TYPE_1,
1540 RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
1541 RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
1542 RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
1543 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1544 RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK |
1545 RT5663_AMP_HP_MASK, RT5663_PWR_MB |
1546 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1547 snd_soc_update_bits(codec, RT5663_AUTO_1MRC_CLK,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1548 RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1549 snd_soc_update_bits(codec, RT5663_IRQ_1,
1550 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
oder_chiou@realtek.com8f244122017-07-07 16:58:58 +0800[diff] [blame]1551
1552 while (true) {
1553 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val);
1554 if (!(val & 0x80))
1555 usleep_range(10000, 10005);
1556 else
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1557 break;
oder_chiou@realtek.com8f244122017-07-07 16:58:58 +0800[diff] [blame]1558
1559 if (i > 200)
1560 break;
1561 i++;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1562 }
oder_chiou@realtek.com8f244122017-07-07 16:58:58 +0800[diff] [blame]1563
1564 val = snd_soc_read(codec, RT5663_EM_JACK_TYPE_2) & 0x0003;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1565 dev_dbg(codec->dev, "%s val = %d\n", __func__, val);
oder_chiou@realtek.com8f244122017-07-07 16:58:58 +0800[diff] [blame]1566
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1567 switch (val) {
1568 case 1:
1569 case 2:
1570 rt5663->jack_type = SND_JACK_HEADSET;
1571 rt5663_enable_push_button_irq(codec, true);
1572 break;
1573 default:
1574 rt5663->jack_type = SND_JACK_HEADPHONE;
1575 break;
1576 }
1577 } else {
1578 if (rt5663->jack_type == SND_JACK_HEADSET)
1579 rt5663_enable_push_button_irq(codec, false);
1580 rt5663->jack_type = 0;
1581 }
1582
1583 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type);
1584 return rt5663->jack_type;
1585}
1586
Wei Yongjun66d7c262016-09-17 01:34:09 +0000[diff] [blame]1587static int rt5663_button_detect(struct snd_soc_codec *codec)
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1588{
1589 int btn_type, val;
1590
1591 val = snd_soc_read(codec, RT5663_IL_CMD_5);
1592 dev_dbg(codec->dev, "%s: val=0x%x\n", __func__, val);
1593 btn_type = val & 0xfff0;
1594 snd_soc_write(codec, RT5663_IL_CMD_5, val);
1595
1596 return btn_type;
1597}
1598
1599static irqreturn_t rt5663_irq(int irq, void *data)
1600{
1601 struct rt5663_priv *rt5663 = data;
1602
1603 dev_dbg(rt5663->codec->dev, "%s IRQ queue work\n", __func__);
1604
1605 queue_delayed_work(system_wq, &rt5663->jack_detect_work,
1606 msecs_to_jiffies(250));
1607
1608 return IRQ_HANDLED;
1609}
1610
1611int rt5663_set_jack_detect(struct snd_soc_codec *codec,
1612 struct snd_soc_jack *hs_jack)
1613{
1614 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1615
1616 rt5663->hs_jack = hs_jack;
1617
1618 rt5663_irq(0, rt5663);
1619
1620 return 0;
1621}
1622EXPORT_SYMBOL_GPL(rt5663_set_jack_detect);
1623
1624static bool rt5663_check_jd_status(struct snd_soc_codec *codec)
1625{
1626 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1627 int val = snd_soc_read(codec, RT5663_INT_ST_1);
1628
1629 dev_dbg(codec->dev, "%s val=%x\n", __func__, val);
1630
1631 /* JD1 */
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1632 switch (rt5663->codec_ver) {
1633 case CODEC_VER_1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1634 return !(val & 0x2000);
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1635 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1636 return !(val & 0x1000);
1637 default:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1638 dev_err(codec->dev, "Unknown CODEC Version\n");
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1639 }
1640
1641 return false;
1642}
1643
1644static void rt5663_jack_detect_work(struct work_struct *work)
1645{
1646 struct rt5663_priv *rt5663 =
1647 container_of(work, struct rt5663_priv, jack_detect_work.work);
1648 struct snd_soc_codec *codec = rt5663->codec;
1649 int btn_type, report = 0;
1650
1651 if (!codec)
1652 return;
1653
1654 if (rt5663_check_jd_status(codec)) {
1655 /* jack in */
1656 if (rt5663->jack_type == 0) {
1657 /* jack was out, report jack type */
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1658 switch (rt5663->codec_ver) {
1659 case CODEC_VER_1:
1660 report = rt5663_v2_jack_detect(
1661 rt5663->codec, 1);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1662 break;
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1663 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1664 report = rt5663_jack_detect(rt5663->codec, 1);
1665 break;
1666 default:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1667 dev_err(codec->dev, "Unknown CODEC Version\n");
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1668 }
1669 } else {
1670 /* jack is already in, report button event */
1671 report = SND_JACK_HEADSET;
1672 btn_type = rt5663_button_detect(rt5663->codec);
1673 /**
1674 * rt5663 can report three kinds of button behavior,
1675 * one click, double click and hold. However,
1676 * currently we will report button pressed/released
1677 * event. So all the three button behaviors are
1678 * treated as button pressed.
1679 */
1680 switch (btn_type) {
1681 case 0x8000:
1682 case 0x4000:
1683 case 0x2000:
1684 report |= SND_JACK_BTN_0;
1685 break;
1686 case 0x1000:
1687 case 0x0800:
1688 case 0x0400:
1689 report |= SND_JACK_BTN_1;
1690 break;
1691 case 0x0200:
1692 case 0x0100:
1693 case 0x0080:
1694 report |= SND_JACK_BTN_2;
1695 break;
1696 case 0x0040:
1697 case 0x0020:
1698 case 0x0010:
1699 report |= SND_JACK_BTN_3;
1700 break;
1701 case 0x0000: /* unpressed */
1702 break;
1703 default:
1704 btn_type = 0;
1705 dev_err(rt5663->codec->dev,
1706 "Unexpected button code 0x%04x\n",
1707 btn_type);
1708 break;
1709 }
1710 /* button release or spurious interrput*/
1711 if (btn_type == 0)
1712 report = rt5663->jack_type;
1713 }
1714 } else {
1715 /* jack out */
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1716 switch (rt5663->codec_ver) {
1717 case CODEC_VER_1:
1718 report = rt5663_v2_jack_detect(rt5663->codec, 0);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1719 break;
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1720 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1721 report = rt5663_jack_detect(rt5663->codec, 0);
1722 break;
1723 default:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1724 dev_err(codec->dev, "Unknown CODEC Version\n");
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1725 }
1726 }
1727 dev_dbg(codec->dev, "%s jack report: 0x%04x\n", __func__, report);
1728 snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET |
1729 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1730 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1731}
1732
1733static const struct snd_kcontrol_new rt5663_snd_controls[] = {
1734 /* DAC Digital Volume */
1735 SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1736 RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1737 87, 0, dac_vol_tlv),
1738 /* ADC Digital Volume Control */
1739 SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1740 RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1741 SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1742 RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1743 63, 0, adc_vol_tlv),
1744};
1745
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1746static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1747 /* Headphone Output Volume */
1748 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1749 RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1,
1750 rt5663_v2_hp_vol_tlv),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1751 /* Mic Boost Volume */
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1752 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST,
1753 RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1754};
1755
1756static const struct snd_kcontrol_new rt5663_specific_controls[] = {
1757 /* Headphone Output Volume */
1758 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9,
1759 RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1,
1760 rt5663_hp_vol_tlv),
1761 /* Mic Boost Volume*/
1762 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2,
1763 RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv),
1764 /* Data Swap for Slot0/1 in ADCDAT1 */
1765 SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum),
1766};
1767
1768static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1769 struct snd_soc_dapm_widget *sink)
1770{
1771 unsigned int val;
1772 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1773
1774 val = snd_soc_read(codec, RT5663_GLB_CLK);
1775 val &= RT5663_SCLK_SRC_MASK;
1776 if (val == RT5663_SCLK_SRC_PLL1)
1777 return 1;
1778 else
1779 return 0;
1780}
1781
1782static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
1783 struct snd_soc_dapm_widget *sink)
1784{
1785 unsigned int reg, shift, val;
1786 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1787 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1788
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1789 if (rt5663->codec_ver == CODEC_VER_1) {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1790 switch (w->shift) {
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1791 case RT5663_ADC_STO1_ASRC_SHIFT:
1792 reg = RT5663_ASRC_3;
1793 shift = RT5663_V2_AD_STO1_TRACK_SHIFT;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1794 break;
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1795 case RT5663_DAC_STO1_ASRC_SHIFT:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1796 reg = RT5663_ASRC_2;
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1797 shift = RT5663_DA_STO1_TRACK_SHIFT;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1798 break;
1799 default:
1800 return 0;
1801 }
1802 } else {
1803 switch (w->shift) {
1804 case RT5663_ADC_STO1_ASRC_SHIFT:
1805 reg = RT5663_ASRC_2;
1806 shift = RT5663_AD_STO1_TRACK_SHIFT;
1807 break;
1808 case RT5663_DAC_STO1_ASRC_SHIFT:
1809 reg = RT5663_ASRC_2;
1810 shift = RT5663_DA_STO1_TRACK_SHIFT;
1811 break;
1812 default:
1813 return 0;
1814 }
1815 }
1816
1817 val = (snd_soc_read(codec, reg) >> shift) & 0x7;
1818
1819 if (val)
1820 return 1;
1821
1822 return 0;
1823}
1824
1825static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
1826 struct snd_soc_dapm_widget *sink)
1827{
1828 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1829 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1830 int da_asrc_en, ad_asrc_en;
1831
1832 da_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
1833 RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1834 switch (rt5663->codec_ver) {
1835 case CODEC_VER_1:
1836 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_3) &
1837 RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1838 break;
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1839 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1840 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
1841 RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
1842 break;
1843 default:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1844 dev_err(codec->dev, "Unknown CODEC Version\n");
Arnd Bergmann56efaed2016-09-15 17:42:21 +0200[diff] [blame]1845 return 1;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1846 }
1847
1848 if (da_asrc_en || ad_asrc_en)
1849 if (rt5663->sysclk > rt5663->lrck * 384)
1850 return 1;
1851
1852 dev_err(codec->dev, "sysclk < 384 x fs, disable i2s asrc\n");
1853
1854 return 0;
1855}
1856
1857/**
1858 * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters
1859 * @codec: SoC audio codec device.
1860 * @filter_mask: mask of filters.
1861 * @clk_src: clock source
1862 *
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1863 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1864 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1865 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1866 * ASRC function will track i2s clock and generate a corresponding system clock
1867 * for codec. This function provides an API to select the clock source for a
1868 * set of filters specified by the mask. And the codec driver will turn on ASRC
1869 * for these filters if ASRC is selected as their clock source.
1870 */
1871int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
1872 unsigned int filter_mask, unsigned int clk_src)
1873{
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1874 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1875 unsigned int asrc2_mask = 0;
1876 unsigned int asrc2_value = 0;
1877 unsigned int asrc3_mask = 0;
1878 unsigned int asrc3_value = 0;
1879
1880 switch (clk_src) {
1881 case RT5663_CLK_SEL_SYS:
1882 case RT5663_CLK_SEL_I2S1_ASRC:
1883 break;
1884
1885 default:
1886 return -EINVAL;
1887 }
1888
1889 if (filter_mask & RT5663_DA_STEREO_FILTER) {
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1890 asrc2_mask |= RT5663_DA_STO1_TRACK_MASK;
1891 asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1892 }
1893
1894 if (filter_mask & RT5663_AD_STEREO_FILTER) {
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1895 switch (rt5663->codec_ver) {
1896 case CODEC_VER_1:
1897 asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK;
1898 asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1899 break;
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1900 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1901 asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
1902 asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
1903 break;
1904 default:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1905 dev_err(codec->dev, "Unknown CODEC Version\n");
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1906 }
1907 }
1908
1909 if (asrc2_mask)
1910 snd_soc_update_bits(codec, RT5663_ASRC_2, asrc2_mask,
1911 asrc2_value);
1912
1913 if (asrc3_mask)
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1914 snd_soc_update_bits(codec, RT5663_ASRC_3, asrc3_mask,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1915 asrc3_value);
1916
1917 return 0;
1918}
1919EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
1920
1921/* Analog Mixer */
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1922static const struct snd_kcontrol_new rt5663_recmix1l[] = {
1923 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L,
1924 RT5663_RECMIX1L_BST2_SHIFT, 1, 1),
1925 SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L,
1926 RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1927};
1928
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1929static const struct snd_kcontrol_new rt5663_recmix1r[] = {
1930 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R,
1931 RT5663_RECMIX1R_BST2_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1932};
1933
1934/* Digital Mixer */
1935static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
1936 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1937 RT5663_M_STO1_ADC_L1_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1938 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1939 RT5663_M_STO1_ADC_L2_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1940};
1941
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1942static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1943 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1944 RT5663_M_STO1_ADC_R1_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1945 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1946 RT5663_M_STO1_ADC_R2_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1947};
1948
1949static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
1950 SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1951 RT5663_M_ADCMIX_L_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1952 SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1953 RT5663_M_DAC1_L_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1954};
1955
1956static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
1957 SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1958 RT5663_M_ADCMIX_R_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1959 SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1960 RT5663_M_DAC1_R_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1961};
1962
1963static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
1964 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1965 RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1966};
1967
1968static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
1969 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1970 RT5663_M_DAC_L1_STO_R_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1971};
1972
1973/* Out Switch */
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1974static const struct snd_kcontrol_new rt5663_hpo_switch =
1975 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2,
1976 RT5663_EN_DAC_HPO_SHIFT, 1, 0);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1977
1978/* Stereo ADC source */
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1979static const char * const rt5663_sto1_adc_src[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1980 "ADC L", "ADC R"
1981};
1982
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1983static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
1984 RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1985
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1986static const struct snd_kcontrol_new rt5663_sto1_adcl_mux =
1987 SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1988
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1989static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
1990 RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1991
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]1992static const struct snd_kcontrol_new rt5663_sto1_adcr_mux =
1993 SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1994
1995/* RT5663: Analog DACL1 input source */
1996static const char * const rt5663_alg_dacl_src[] = {
1997 "DAC L", "STO DAC MIXL"
1998};
1999
2000static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC,
2001 RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src);
2002
2003static const struct snd_kcontrol_new rt5663_alg_dacl_mux =
2004 SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum);
2005
2006/* RT5663: Analog DACR1 input source */
2007static const char * const rt5663_alg_dacr_src[] = {
2008 "DAC R", "STO DAC MIXR"
2009};
2010
2011static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC,
2012 RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src);
2013
2014static const struct snd_kcontrol_new rt5663_alg_dacr_mux =
2015 SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum);
2016
2017static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2018 struct snd_kcontrol *kcontrol, int event)
2019{
2020 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2021 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2022
2023 switch (event) {
2024 case SND_SOC_DAPM_POST_PMU:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2025 if (rt5663->codec_ver == CODEC_VER_1) {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2026 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2027 RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2028 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2029 RT5663_HP_SIG_SRC1_MASK,
2030 RT5663_HP_SIG_SRC1_SILENCE);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2031 } else {
2032 snd_soc_write(codec, RT5663_DEPOP_2, 0x3003);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2033 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2034 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2035 snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371);
2036 snd_soc_write(codec, RT5663_HP_BIAS, 0xabba);
2037 snd_soc_write(codec, RT5663_CHARGE_PUMP_1, 0x2224);
2038 snd_soc_write(codec, RT5663_ANA_BIAS_CUR_1, 0x7766);
2039 snd_soc_write(codec, RT5663_HP_BIAS, 0xafaa);
2040 snd_soc_write(codec, RT5663_CHARGE_PUMP_2, 0x7777);
2041 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000,
2042 0x3000);
2043 }
2044 break;
2045
2046 case SND_SOC_DAPM_PRE_PMD:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2047 if (rt5663->codec_ver == CODEC_VER_1) {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2048 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2049 RT5663_HP_SIG_SRC1_MASK,
2050 RT5663_HP_SIG_SRC1_REG);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2051 } else {
2052 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x0);
2053 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2054 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2055 }
2056 break;
2057
2058 default:
2059 return 0;
2060 }
2061
2062 return 0;
2063}
2064
oder_chiou@realtek.com13257342017-07-07 16:58:59 +0800[diff] [blame]2065static int rt5663_charge_pump_event(struct snd_soc_dapm_widget *w,
2066 struct snd_kcontrol *kcontrol, int event)
2067{
2068 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2069 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2070
2071 switch (event) {
2072 case SND_SOC_DAPM_PRE_PMU:
2073 if (rt5663->codec_ver == CODEC_VER_0)
2074 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x003b,
2075 0x003b);
2076 break;
2077
2078 case SND_SOC_DAPM_POST_PMD:
2079 if (rt5663->codec_ver == CODEC_VER_0)
2080 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x003b, 0);
2081 break;
2082
2083 default:
2084 return 0;
2085 }
2086
2087 return 0;
2088}
2089
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2090static int rt5663_bst2_power(struct snd_soc_dapm_widget *w,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2091 struct snd_kcontrol *kcontrol, int event)
2092{
2093 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2094
2095 switch (event) {
2096 case SND_SOC_DAPM_POST_PMU:
2097 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2098 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK,
2099 RT5663_PWR_BST2 | RT5663_PWR_BST2_OP);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2100 break;
2101
2102 case SND_SOC_DAPM_PRE_PMD:
2103 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2104 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2105 break;
2106
2107 default:
2108 return 0;
2109 }
2110
2111 return 0;
2112}
2113
2114static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
2115 struct snd_kcontrol *kcontrol, int event)
2116{
2117 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2118
2119 switch (event) {
2120 case SND_SOC_DAPM_POST_PMU:
2121 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0xff00);
2122 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0xfffc);
2123 break;
2124
2125 case SND_SOC_DAPM_PRE_PMD:
2126 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0x0000);
2127 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0x0000);
2128 break;
2129
2130 default:
2131 return 0;
2132 }
2133
2134 return 0;
2135}
2136
2137static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2138 SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2139 NULL, 0),
2140
2141 /* micbias */
2142 SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2143 RT5663_PWR_MB1_SHIFT, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2144 SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2145 RT5663_PWR_MB2_SHIFT, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2146
2147 /* Input Lines */
2148 SND_SOC_DAPM_INPUT("IN1P"),
2149 SND_SOC_DAPM_INPUT("IN1N"),
2150
2151 /* REC Mixer Power */
2152 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2153 RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2154
2155 /* ADCs */
2156 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2157 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2158 RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2159 SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2160 RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2161
2162 /* ADC Mixer */
2163 SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
2164 0, 0, rt5663_sto1_adc_l_mix,
2165 ARRAY_SIZE(rt5663_sto1_adc_l_mix)),
2166
2167 /* ADC Filter Power */
2168 SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2169 RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2170
2171 /* Digital Interface */
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2172 SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2173 NULL, 0),
2174 SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2175 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2176 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2177 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2178 SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2179
2180 /* Audio Interface */
2181 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
2182 SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0),
2183
2184 /* DAC mixer before sound effect */
2185 SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix,
2186 ARRAY_SIZE(rt5663_adda_l_mix)),
2187 SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix,
2188 ARRAY_SIZE(rt5663_adda_r_mix)),
2189 SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2190 SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
2191
2192 /* DAC Mixer */
2193 SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2194 RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2195 SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
2196 rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
2197 SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
2198 rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)),
2199
2200 /* DACs */
2201 SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2202 RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2203 SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2204 RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2205 SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
2206 SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
2207
2208 /* Headphone*/
oder_chiou@realtek.com13257342017-07-07 16:58:59 +0800[diff] [blame]2209 SND_SOC_DAPM_SUPPLY("HP Charge Pump", SND_SOC_NOPM, 0, 0,
2210 rt5663_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
2211 SND_SOC_DAPM_POST_PMD),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2212 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event,
2213 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2214
2215 /* Output Lines */
2216 SND_SOC_DAPM_OUTPUT("HPOL"),
2217 SND_SOC_DAPM_OUTPUT("HPOR"),
2218};
2219
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2220static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2221 SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2222 RT5663_PWR_LDO2_SHIFT, 0, NULL, 0),
2223 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL,
2224 RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2225 SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2226 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2227
2228 /* ASRC */
2229 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2230 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2231 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2232 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2233 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2234 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2235
2236 /* Input Lines */
2237 SND_SOC_DAPM_INPUT("IN2P"),
2238 SND_SOC_DAPM_INPUT("IN2N"),
2239
2240 /* Boost */
2241 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
2242 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2243 RT5663_PWR_CBJ_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2244 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
2245 SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2246 rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD |
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2247 SND_SOC_DAPM_POST_PMU),
2248
2249 /* REC Mixer */
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2250 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l,
2251 ARRAY_SIZE(rt5663_recmix1l)),
2252 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r,
2253 ARRAY_SIZE(rt5663_recmix1r)),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2254 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2255 RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2256
2257 /* ADC */
2258 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2259 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2260 RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2261
2262 /* ADC Mux */
2263 SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2264 RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2265 SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2266 RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2267 SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2268 RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2269 SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2270 RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2271
2272 SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2273 &rt5663_sto1_adcl_mux),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2274 SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2275 &rt5663_sto1_adcr_mux),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2276
2277 /* ADC Mix */
2278 SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2279 rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2280
2281 /* Analog DAC Clock */
2282 SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2283 RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2284
2285 /* Headphone out */
2286 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2287 &rt5663_hpo_switch),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2288};
2289
2290static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
2291 /* System Clock Pre Divider Gating */
2292 SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0,
2293 rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU |
2294 SND_SOC_DAPM_PRE_PMD),
2295
2296 /* LDO */
2297 SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2298 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2299
2300 /* ASRC */
2301 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2302 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2303 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2304 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2305 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2306 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2307
2308 /* Boost */
2309 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0),
2310
2311 /* STO ADC */
2312 SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2313 SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
2314
2315 /* Analog DAC source */
2316 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux),
2317 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux),
2318};
2319
2320static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
2321 /* PLL */
2322 { "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll },
2323
2324 /* ASRC */
2325 { "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc },
2326 { "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc },
2327 { "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc },
2328
2329 { "ADC L", NULL, "ADC L Power" },
2330 { "ADC L", NULL, "ADC Clock" },
2331
2332 { "STO1 ADC L2", NULL, "STO1 DAC MIXL" },
2333
2334 { "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" },
2335 { "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" },
2336 { "STO1 ADC MIXL", NULL, "STO1 ADC Filter" },
2337
2338 { "IF1 ADC1", NULL, "STO1 ADC MIXL" },
2339 { "IF ADC", NULL, "IF1 ADC1" },
2340 { "AIFTX", NULL, "IF ADC" },
2341 { "AIFTX", NULL, "I2S" },
2342
2343 { "AIFRX", NULL, "I2S" },
2344 { "IF DAC", NULL, "AIFRX" },
2345 { "IF1 DAC1 L", NULL, "IF DAC" },
2346 { "IF1 DAC1 R", NULL, "IF DAC" },
2347
2348 { "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" },
2349 { "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" },
2350 { "ADDA MIXL", NULL, "STO1 DAC Filter" },
2351 { "ADDA MIXL", NULL, "STO1 DAC L Power" },
2352 { "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" },
2353 { "ADDA MIXR", NULL, "STO1 DAC Filter" },
2354 { "ADDA MIXR", NULL, "STO1 DAC R Power" },
2355
2356 { "DAC L1", NULL, "ADDA MIXL" },
2357 { "DAC R1", NULL, "ADDA MIXR" },
2358
2359 { "STO1 DAC MIXL", "DAC L Switch", "DAC L1" },
2360 { "STO1 DAC MIXL", "DAC R Switch", "DAC R1" },
2361 { "STO1 DAC MIXL", NULL, "STO1 DAC L Power" },
2362 { "STO1 DAC MIXL", NULL, "STO1 DAC Filter" },
2363 { "STO1 DAC MIXR", "DAC R Switch", "DAC R1" },
2364 { "STO1 DAC MIXR", "DAC L Switch", "DAC L1" },
2365 { "STO1 DAC MIXR", NULL, "STO1 DAC R Power" },
2366 { "STO1 DAC MIXR", NULL, "STO1 DAC Filter" },
2367
oder_chiou@realtek.com13257342017-07-07 16:58:59 +0800[diff] [blame]2368 { "HP Amp", NULL, "HP Charge Pump" },
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2369 { "HP Amp", NULL, "DAC L" },
2370 { "HP Amp", NULL, "DAC R" },
2371};
2372
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2373static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2374 { "MICBIAS1", NULL, "LDO2" },
2375 { "MICBIAS2", NULL, "LDO2" },
2376
2377 { "BST1 CBJ", NULL, "IN1P" },
2378 { "BST1 CBJ", NULL, "IN1N" },
2379 { "BST1 CBJ", NULL, "CBJ Power" },
2380
2381 { "BST2", NULL, "IN2P" },
2382 { "BST2", NULL, "IN2N" },
2383 { "BST2", NULL, "BST2 Power" },
2384
2385 { "RECMIX1L", "BST2 Switch", "BST2" },
2386 { "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" },
2387 { "RECMIX1L", NULL, "RECMIX1L Power" },
2388 { "RECMIX1R", "BST2 Switch", "BST2" },
2389 { "RECMIX1R", NULL, "RECMIX1R Power" },
2390
2391 { "ADC L", NULL, "RECMIX1L" },
2392 { "ADC R", NULL, "RECMIX1R" },
2393 { "ADC R", NULL, "ADC R Power" },
2394 { "ADC R", NULL, "ADC Clock" },
2395
2396 { "STO1 ADC L Mux", "ADC L", "ADC L" },
2397 { "STO1 ADC L Mux", "ADC R", "ADC R" },
2398 { "STO1 ADC L1", NULL, "STO1 ADC L Mux" },
2399
2400 { "STO1 ADC R Mux", "ADC L", "ADC L" },
2401 { "STO1 ADC R Mux", "ADC R", "ADC R" },
2402 { "STO1 ADC R1", NULL, "STO1 ADC R Mux" },
2403 { "STO1 ADC R2", NULL, "STO1 DAC MIXR" },
2404
2405 { "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" },
2406 { "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" },
2407 { "STO1 ADC MIXR", NULL, "STO1 ADC Filter" },
2408
2409 { "IF1 ADC1", NULL, "STO1 ADC MIXR" },
2410
2411 { "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" },
2412
2413 { "DAC L", NULL, "STO1 DAC MIXL" },
2414 { "DAC L", NULL, "LDO DAC" },
2415 { "DAC L", NULL, "DAC Clock" },
2416 { "DAC R", NULL, "STO1 DAC MIXR" },
2417 { "DAC R", NULL, "LDO DAC" },
2418 { "DAC R", NULL, "DAC Clock" },
2419
2420 { "HPO Playback", "Switch", "HP Amp" },
2421 { "HPOL", NULL, "HPO Playback" },
2422 { "HPOR", NULL, "HPO Playback" },
2423};
2424
2425static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = {
2426 { "I2S", NULL, "Pre Div Power" },
2427
2428 { "BST1", NULL, "IN1P" },
2429 { "BST1", NULL, "IN1N" },
2430 { "BST1", NULL, "RECMIX1L Power" },
2431
2432 { "ADC L", NULL, "BST1" },
2433
2434 { "STO1 ADC L1", NULL, "ADC L" },
2435
2436 { "DAC L Mux", "DAC L", "DAC L1" },
2437 { "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" },
2438 { "DAC R Mux", "DAC R", "DAC R1"},
2439 { "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" },
2440
2441 { "DAC L", NULL, "DAC L Mux" },
2442 { "DAC R", NULL, "DAC R Mux" },
2443
2444 { "HPOL", NULL, "HP Amp" },
2445 { "HPOR", NULL, "HP Amp" },
2446};
2447
2448static int rt5663_hw_params(struct snd_pcm_substream *substream,
2449 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2450{
2451 struct snd_soc_codec *codec = dai->codec;
2452 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2453 unsigned int val_len = 0;
2454 int pre_div;
2455
2456 rt5663->lrck = params_rate(params);
2457
2458 dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n",
2459 rt5663->lrck, rt5663->sysclk);
2460
2461 pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck);
2462 if (pre_div < 0) {
2463 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
2464 rt5663->lrck, dai->id);
2465 return -EINVAL;
2466 }
2467
2468 dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
2469
2470 switch (params_width(params)) {
2471 case 8:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2472 val_len = RT5663_I2S_DL_8;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2473 break;
2474 case 16:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2475 val_len = RT5663_I2S_DL_16;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2476 break;
2477 case 20:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2478 val_len = RT5663_I2S_DL_20;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2479 break;
2480 case 24:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2481 val_len = RT5663_I2S_DL_24;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2482 break;
2483 default:
2484 return -EINVAL;
2485 }
2486
2487 snd_soc_update_bits(codec, RT5663_I2S1_SDP,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2488 RT5663_I2S_DL_MASK, val_len);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2489
2490 snd_soc_update_bits(codec, RT5663_ADDA_CLK_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2491 RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2492
2493 return 0;
2494}
2495
2496static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2497{
2498 struct snd_soc_codec *codec = dai->codec;
2499 unsigned int reg_val = 0;
2500
2501 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2502 case SND_SOC_DAIFMT_CBM_CFM:
2503 break;
2504 case SND_SOC_DAIFMT_CBS_CFS:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2505 reg_val |= RT5663_I2S_MS_S;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2506 break;
2507 default:
2508 return -EINVAL;
2509 }
2510
2511 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2512 case SND_SOC_DAIFMT_NB_NF:
2513 break;
2514 case SND_SOC_DAIFMT_IB_NF:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2515 reg_val |= RT5663_I2S_BP_INV;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2516 break;
2517 default:
2518 return -EINVAL;
2519 }
2520
2521 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2522 case SND_SOC_DAIFMT_I2S:
2523 break;
2524 case SND_SOC_DAIFMT_LEFT_J:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2525 reg_val |= RT5663_I2S_DF_LEFT;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2526 break;
2527 case SND_SOC_DAIFMT_DSP_A:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2528 reg_val |= RT5663_I2S_DF_PCM_A;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2529 break;
2530 case SND_SOC_DAIFMT_DSP_B:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2531 reg_val |= RT5663_I2S_DF_PCM_B;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2532 break;
2533 default:
2534 return -EINVAL;
2535 }
2536
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2537 snd_soc_update_bits(codec, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK |
2538 RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2539
2540 return 0;
2541}
2542
2543static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2544 unsigned int freq, int dir)
2545{
2546 struct snd_soc_codec *codec = dai->codec;
2547 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2548 unsigned int reg_val = 0;
2549
2550 if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src)
2551 return 0;
2552
2553 switch (clk_id) {
2554 case RT5663_SCLK_S_MCLK:
2555 reg_val |= RT5663_SCLK_SRC_MCLK;
2556 break;
2557 case RT5663_SCLK_S_PLL1:
2558 reg_val |= RT5663_SCLK_SRC_PLL1;
2559 break;
2560 case RT5663_SCLK_S_RCCLK:
2561 reg_val |= RT5663_SCLK_SRC_RCCLK;
2562 break;
2563 default:
2564 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2565 return -EINVAL;
2566 }
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2567 snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2568 reg_val);
2569 rt5663->sysclk = freq;
2570 rt5663->sysclk_src = clk_id;
2571
2572 dev_dbg(codec->dev, "Sysclk is %dHz and clock id is %d\n",
2573 freq, clk_id);
2574
2575 return 0;
2576}
2577
2578static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2579 unsigned int freq_in, unsigned int freq_out)
2580{
2581 struct snd_soc_codec *codec = dai->codec;
2582 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2583 struct rl6231_pll_code pll_code;
2584 int ret;
2585 int mask, shift, val;
2586
2587 if (source == rt5663->pll_src && freq_in == rt5663->pll_in &&
2588 freq_out == rt5663->pll_out)
2589 return 0;
2590
2591 if (!freq_in || !freq_out) {
2592 dev_dbg(codec->dev, "PLL disabled\n");
2593
2594 rt5663->pll_in = 0;
2595 rt5663->pll_out = 0;
2596 snd_soc_update_bits(codec, RT5663_GLB_CLK,
2597 RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK);
2598 return 0;
2599 }
2600
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2601 switch (rt5663->codec_ver) {
2602 case CODEC_VER_1:
2603 mask = RT5663_V2_PLL1_SRC_MASK;
2604 shift = RT5663_V2_PLL1_SRC_SHIFT;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2605 break;
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2606 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2607 mask = RT5663_PLL1_SRC_MASK;
2608 shift = RT5663_PLL1_SRC_SHIFT;
2609 break;
2610 default:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2611 dev_err(codec->dev, "Unknown CODEC Version\n");
Arnd Bergmann56efaed2016-09-15 17:42:21 +0200[diff] [blame]2612 return -EINVAL;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2613 }
2614
2615 switch (source) {
2616 case RT5663_PLL1_S_MCLK:
2617 val = 0x0;
2618 break;
2619 case RT5663_PLL1_S_BCLK1:
2620 val = 0x1;
2621 break;
2622 default:
2623 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2624 return -EINVAL;
2625 }
2626 snd_soc_update_bits(codec, RT5663_GLB_CLK, mask, (val << shift));
2627
2628 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2629 if (ret < 0) {
2630 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2631 return ret;
2632 }
2633
2634 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp,
2635 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
2636 pll_code.k_code);
2637
2638 snd_soc_write(codec, RT5663_PLL_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2639 pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2640 snd_soc_write(codec, RT5663_PLL_2,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2641 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT |
2642 pll_code.m_bp << RT5663_PLL_M_BP_SHIFT);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2643
2644 rt5663->pll_in = freq_in;
2645 rt5663->pll_out = freq_out;
2646 rt5663->pll_src = source;
2647
2648 return 0;
2649}
2650
2651static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2652 unsigned int rx_mask, int slots, int slot_width)
2653{
2654 struct snd_soc_codec *codec = dai->codec;
2655 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2656 unsigned int val = 0, reg;
2657
2658 if (rx_mask || tx_mask)
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2659 val |= RT5663_TDM_MODE_TDM;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2660
2661 switch (slots) {
2662 case 4:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2663 val |= RT5663_TDM_IN_CH_4;
2664 val |= RT5663_TDM_OUT_CH_4;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2665 break;
2666 case 6:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2667 val |= RT5663_TDM_IN_CH_6;
2668 val |= RT5663_TDM_OUT_CH_6;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2669 break;
2670 case 8:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2671 val |= RT5663_TDM_IN_CH_8;
2672 val |= RT5663_TDM_OUT_CH_8;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2673 break;
2674 case 2:
2675 break;
2676 default:
2677 return -EINVAL;
2678 }
2679
2680 switch (slot_width) {
2681 case 20:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2682 val |= RT5663_TDM_IN_LEN_20;
2683 val |= RT5663_TDM_OUT_LEN_20;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2684 break;
2685 case 24:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2686 val |= RT5663_TDM_IN_LEN_24;
2687 val |= RT5663_TDM_OUT_LEN_24;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2688 break;
2689 case 32:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2690 val |= RT5663_TDM_IN_LEN_32;
2691 val |= RT5663_TDM_OUT_LEN_32;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2692 break;
2693 case 16:
2694 break;
2695 default:
2696 return -EINVAL;
2697 }
2698
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2699 switch (rt5663->codec_ver) {
2700 case CODEC_VER_1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2701 reg = RT5663_TDM_2;
2702 break;
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2703 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2704 reg = RT5663_TDM_1;
2705 break;
2706 default:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2707 dev_err(codec->dev, "Unknown CODEC Version\n");
Arnd Bergmann56efaed2016-09-15 17:42:21 +0200[diff] [blame]2708 return -EINVAL;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2709 }
2710
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2711 snd_soc_update_bits(codec, reg, RT5663_TDM_MODE_MASK |
2712 RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK |
2713 RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2714
2715 return 0;
2716}
2717
2718static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2719{
2720 struct snd_soc_codec *codec = dai->codec;
2721 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2722 unsigned int reg;
2723
2724 dev_dbg(codec->dev, "%s ratio = %d\n", __func__, ratio);
2725
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2726 if (rt5663->codec_ver == CODEC_VER_1)
2727 reg = RT5663_TDM_9;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2728 else
2729 reg = RT5663_TDM_5;
2730
2731 switch (ratio) {
2732 case 32:
2733 snd_soc_update_bits(codec, reg,
2734 RT5663_TDM_LENGTN_MASK,
2735 RT5663_TDM_LENGTN_16);
2736 break;
2737 case 40:
2738 snd_soc_update_bits(codec, reg,
2739 RT5663_TDM_LENGTN_MASK,
2740 RT5663_TDM_LENGTN_20);
2741 break;
2742 case 48:
2743 snd_soc_update_bits(codec, reg,
2744 RT5663_TDM_LENGTN_MASK,
2745 RT5663_TDM_LENGTN_24);
2746 break;
2747 case 64:
2748 snd_soc_update_bits(codec, reg,
2749 RT5663_TDM_LENGTN_MASK,
2750 RT5663_TDM_LENGTN_32);
2751 break;
2752 default:
2753 dev_err(codec->dev, "Invalid ratio!\n");
2754 return -EINVAL;
2755 }
2756
2757 return 0;
2758}
2759
2760static int rt5663_set_bias_level(struct snd_soc_codec *codec,
2761 enum snd_soc_bias_level level)
2762{
2763 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2764
2765 switch (level) {
2766 case SND_SOC_BIAS_ON:
2767 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2768 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
2769 RT5663_PWR_FV1 | RT5663_PWR_FV2);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2770 break;
2771
2772 case SND_SOC_BIAS_PREPARE:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2773 if (rt5663->codec_ver == CODEC_VER_1) {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2774 snd_soc_update_bits(codec, RT5663_DIG_MISC,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2775 RT5663_DIG_GATE_CTRL_MASK,
2776 RT5663_DIG_GATE_CTRL_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2777 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2778 RT5663_EN_ANA_CLK_DET_MASK |
2779 RT5663_PWR_CLK_DET_MASK,
2780 RT5663_EN_ANA_CLK_DET_AUTO |
2781 RT5663_PWR_CLK_DET_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2782 }
2783 break;
2784
2785 case SND_SOC_BIAS_STANDBY:
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2786 if (rt5663->codec_ver == CODEC_VER_1)
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2787 snd_soc_update_bits(codec, RT5663_DIG_MISC,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2788 RT5663_DIG_GATE_CTRL_MASK,
2789 RT5663_DIG_GATE_CTRL_DIS);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2790 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2791 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
2792 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK |
2793 RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 |
2794 RT5663_PWR_VREF2 | RT5663_PWR_MB);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2795 usleep_range(10000, 10005);
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2796 if (rt5663->codec_ver == CODEC_VER_1) {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2797 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2798 RT5663_EN_ANA_CLK_DET_MASK |
2799 RT5663_PWR_CLK_DET_MASK,
2800 RT5663_EN_ANA_CLK_DET_DIS |
2801 RT5663_PWR_CLK_DET_DIS);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2802 }
2803 break;
2804
2805 case SND_SOC_BIAS_OFF:
2806 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2807 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
2808 RT5663_PWR_FV1 | RT5663_PWR_FV2, 0x0);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2809 break;
2810
2811 default:
2812 break;
2813 }
2814
2815 return 0;
2816}
2817
2818static int rt5663_probe(struct snd_soc_codec *codec)
2819{
2820 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
2821 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2822
2823 rt5663->codec = codec;
2824
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2825 switch (rt5663->codec_ver) {
2826 case CODEC_VER_1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2827 snd_soc_dapm_new_controls(dapm,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2828 rt5663_v2_specific_dapm_widgets,
2829 ARRAY_SIZE(rt5663_v2_specific_dapm_widgets));
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2830 snd_soc_dapm_add_routes(dapm,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2831 rt5663_v2_specific_dapm_routes,
2832 ARRAY_SIZE(rt5663_v2_specific_dapm_routes));
2833 snd_soc_add_codec_controls(codec, rt5663_v2_specific_controls,
2834 ARRAY_SIZE(rt5663_v2_specific_controls));
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2835 break;
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2836 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2837 snd_soc_dapm_new_controls(dapm,
2838 rt5663_specific_dapm_widgets,
2839 ARRAY_SIZE(rt5663_specific_dapm_widgets));
2840 snd_soc_dapm_add_routes(dapm,
2841 rt5663_specific_dapm_routes,
2842 ARRAY_SIZE(rt5663_specific_dapm_routes));
2843 snd_soc_add_codec_controls(codec, rt5663_specific_controls,
2844 ARRAY_SIZE(rt5663_specific_controls));
2845 break;
2846 }
2847
2848 return 0;
2849}
2850
2851static int rt5663_remove(struct snd_soc_codec *codec)
2852{
2853 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2854
2855 regmap_write(rt5663->regmap, RT5663_RESET, 0);
2856
2857 return 0;
2858}
2859
2860#ifdef CONFIG_PM
2861static int rt5663_suspend(struct snd_soc_codec *codec)
2862{
2863 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2864
2865 regcache_cache_only(rt5663->regmap, true);
2866 regcache_mark_dirty(rt5663->regmap);
2867
2868 return 0;
2869}
2870
2871static int rt5663_resume(struct snd_soc_codec *codec)
2872{
2873 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2874
2875 regcache_cache_only(rt5663->regmap, false);
2876 regcache_sync(rt5663->regmap);
2877
Oder Chiou17616ce2017-06-12 11:02:17 +0800[diff] [blame]2878 rt5663_irq(0, rt5663);
2879
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2880 return 0;
2881}
2882#else
2883#define rt5663_suspend NULL
2884#define rt5663_resume NULL
2885#endif
2886
2887#define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2888#define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2889 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2890
Gustavo A. R. Silva6ccf3a62017-07-13 15:37:36 -0500[diff] [blame^]2891static const struct snd_soc_dai_ops rt5663_aif_dai_ops = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2892 .hw_params = rt5663_hw_params,
2893 .set_fmt = rt5663_set_dai_fmt,
2894 .set_sysclk = rt5663_set_dai_sysclk,
2895 .set_pll = rt5663_set_dai_pll,
2896 .set_tdm_slot = rt5663_set_tdm_slot,
2897 .set_bclk_ratio = rt5663_set_bclk_ratio,
2898};
2899
Wei Yongjun66d7c262016-09-17 01:34:09 +0000[diff] [blame]2900static struct snd_soc_dai_driver rt5663_dai[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2901 {
2902 .name = "rt5663-aif",
2903 .id = RT5663_AIF,
2904 .playback = {
2905 .stream_name = "AIF Playback",
2906 .channels_min = 1,
2907 .channels_max = 2,
2908 .rates = RT5663_STEREO_RATES,
2909 .formats = RT5663_FORMATS,
2910 },
2911 .capture = {
2912 .stream_name = "AIF Capture",
2913 .channels_min = 1,
2914 .channels_max = 2,
2915 .rates = RT5663_STEREO_RATES,
2916 .formats = RT5663_FORMATS,
2917 },
2918 .ops = &rt5663_aif_dai_ops,
2919 },
2920};
2921
2922static struct snd_soc_codec_driver soc_codec_dev_rt5663 = {
2923 .probe = rt5663_probe,
2924 .remove = rt5663_remove,
2925 .suspend = rt5663_suspend,
2926 .resume = rt5663_resume,
2927 .set_bias_level = rt5663_set_bias_level,
2928 .idle_bias_off = true,
2929 .component_driver = {
2930 .controls = rt5663_snd_controls,
2931 .num_controls = ARRAY_SIZE(rt5663_snd_controls),
2932 .dapm_widgets = rt5663_dapm_widgets,
2933 .num_dapm_widgets = ARRAY_SIZE(rt5663_dapm_widgets),
2934 .dapm_routes = rt5663_dapm_routes,
2935 .num_dapm_routes = ARRAY_SIZE(rt5663_dapm_routes),
2936 }
2937};
2938
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2939static const struct regmap_config rt5663_v2_regmap = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2940 .reg_bits = 16,
2941 .val_bits = 16,
2942 .use_single_rw = true,
2943 .max_register = 0x07fa,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2944 .volatile_reg = rt5663_v2_volatile_register,
2945 .readable_reg = rt5663_v2_readable_register,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2946 .cache_type = REGCACHE_RBTREE,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2947 .reg_defaults = rt5663_v2_reg,
2948 .num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2949};
2950
2951static const struct regmap_config rt5663_regmap = {
2952 .reg_bits = 16,
2953 .val_bits = 16,
2954 .use_single_rw = true,
2955 .max_register = 0x03f3,
2956 .volatile_reg = rt5663_volatile_register,
2957 .readable_reg = rt5663_readable_register,
2958 .cache_type = REGCACHE_RBTREE,
2959 .reg_defaults = rt5663_reg,
2960 .num_reg_defaults = ARRAY_SIZE(rt5663_reg),
2961};
2962
2963static const struct regmap_config temp_regmap = {
2964 .name = "nocache",
2965 .reg_bits = 16,
2966 .val_bits = 16,
2967 .use_single_rw = true,
2968 .max_register = 0x03f3,
2969 .cache_type = REGCACHE_NONE,
2970};
2971
2972static const struct i2c_device_id rt5663_i2c_id[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2973 { "rt5663", 0 },
2974 {}
2975};
2976MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
2977
2978#if defined(CONFIG_OF)
2979static const struct of_device_id rt5663_of_match[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2980 { .compatible = "realtek,rt5663", },
2981 {},
2982};
2983MODULE_DEVICE_TABLE(of, rt5663_of_match);
2984#endif
2985
2986#ifdef CONFIG_ACPI
2987static struct acpi_device_id rt5663_acpi_match[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2988 { "10EC5663", 0},
2989 {},
2990};
2991MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
2992#endif
2993
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2994static void rt5663_v2_calibrate(struct rt5663_priv *rt5663)
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2995{
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]2996 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
2997 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100);
2998 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040);
2999 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001);
3000 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3001 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3002 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3003 regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030);
3004 regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05);
3005 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3006 msleep(40);
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3007 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e);
3008 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321);
3009 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3010 msleep(500);
3011}
3012
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3013static void rt5663_calibrate(struct rt5663_priv *rt5663)
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3014{
3015 int value, count;
3016
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3017 regmap_write(rt5663->regmap, RT5663_RESET, 0x0000);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3018 msleep(20);
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3019 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_4, 0x00a1);
3020 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3021 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3022 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3023 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3024 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c);
3025 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324);
3026 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
3027 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b);
3028 msleep(30);
3029 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b);
3030 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8000);
3031 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x0008);
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3032 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
3033 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3034 regmap_write(rt5663->regmap, RT5663_CBJ_1, 0x8c10);
3035 regmap_write(rt5663->regmap, RT5663_IL_CMD_2, 0x00c1);
3036 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb880);
3037 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4110);
3038 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4118);
3039
3040 count = 0;
3041 while (true) {
3042 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &value);
3043 if (!(value & 0x80))
3044 usleep_range(10000, 10005);
3045 else
3046 break;
3047
Colin Ian King09b88522017-07-10 16:20:45 +0100[diff] [blame]3048 if (++count > 200)
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3049 break;
3050 }
3051
3052 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x0000);
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3053 regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3054 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0038);
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3055 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3056 regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
3057 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
3058 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003);
3059 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3060 regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3061 regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3062 regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000);
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3063 regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3064 regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xafaa);
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3065 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
3066 regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
3067 regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
3068 regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
3069 regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3070 regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3071 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
3072 regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
3073 regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
3074 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
3075 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3076 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x1111);
3077 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4402);
3078 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x3311);
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3079 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3080 regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06ce);
3081 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6800);
3082 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x1100);
3083 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0057);
3084 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe800);
3085
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3086 count = 0;
3087 while (true) {
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3088 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3089 if (value & 0x8000)
3090 usleep_range(10000, 10005);
3091 else
3092 break;
3093
3094 if (count > 200)
3095 return;
3096 count++;
3097 }
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3098
3099 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6200);
3100 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0059);
3101 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe200);
3102
3103 count = 0;
3104 while (true) {
3105 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3106 if (value & 0x8000)
3107 usleep_range(10000, 10005);
3108 else
3109 break;
3110
3111 if (count > 200)
3112 return;
3113 count++;
3114 }
3115
3116 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb8e0);
3117 usleep_range(10000, 10005);
3118 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0x003b);
3119 usleep_range(10000, 10005);
3120 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0000);
3121 usleep_range(10000, 10005);
3122 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x000b);
3123 usleep_range(10000, 10005);
3124 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0008);
3125 usleep_range(10000, 10005);
3126 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0000);
3127 usleep_range(10000, 10005);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3128}
3129
oder_chiou@realtek.com450f0f62017-07-10 11:14:56 +0800[diff] [blame]3130static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev)
3131{
3132 device_property_read_u32(dev, "realtek,dc_offset_l_manual",
3133 &rt5663->pdata.dc_offset_l_manual);
3134 device_property_read_u32(dev, "realtek,dc_offset_r_manual",
3135 &rt5663->pdata.dc_offset_r_manual);
3136
3137 return 0;
3138}
3139
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3140static int rt5663_i2c_probe(struct i2c_client *i2c,
3141 const struct i2c_device_id *id)
3142{
oder_chiou@realtek.com450f0f62017-07-10 11:14:56 +0800[diff] [blame]3143 struct rt5663_platform_data *pdata = dev_get_platdata(&i2c->dev);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3144 struct rt5663_priv *rt5663;
3145 int ret;
3146 unsigned int val;
3147 struct regmap *regmap;
3148
3149 rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv),
3150 GFP_KERNEL);
3151
3152 if (rt5663 == NULL)
3153 return -ENOMEM;
3154
3155 i2c_set_clientdata(i2c, rt5663);
3156
oder_chiou@realtek.com450f0f62017-07-10 11:14:56 +0800[diff] [blame]3157 if (pdata)
3158 rt5663->pdata = *pdata;
3159 else
3160 rt5663_parse_dp(rt5663, &i2c->dev);
3161
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3162 regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3163 if (IS_ERR(regmap)) {
3164 ret = PTR_ERR(regmap);
3165 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3166 ret);
3167 return ret;
3168 }
3169 regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3170 switch (val) {
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3171 case RT5663_DEVICE_ID_2:
3172 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap);
3173 rt5663->codec_ver = CODEC_VER_1;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3174 break;
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3175 case RT5663_DEVICE_ID_1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3176 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3177 rt5663->codec_ver = CODEC_VER_0;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3178 break;
3179 default:
3180 dev_err(&i2c->dev,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3181 "Device with ID register %#x is not rt5663\n",
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3182 val);
3183 return -ENODEV;
3184 }
3185
3186 if (IS_ERR(rt5663->regmap)) {
3187 ret = PTR_ERR(rt5663->regmap);
3188 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3189 ret);
3190 return ret;
3191 }
3192
3193 /* reset and calibrate */
3194 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3195 regcache_cache_bypass(rt5663->regmap, true);
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3196 switch (rt5663->codec_ver) {
3197 case CODEC_VER_1:
3198 rt5663_v2_calibrate(rt5663);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3199 break;
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3200 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3201 rt5663_calibrate(rt5663);
3202 break;
3203 default:
3204 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3205 }
3206 regcache_cache_bypass(rt5663->regmap, false);
3207 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3208 dev_dbg(&i2c->dev, "calibrate done\n");
3209
oder_chiou@realtek.com450f0f62017-07-10 11:14:56 +0800[diff] [blame]3210 switch (rt5663->codec_ver) {
3211 case CODEC_VER_1:
3212 break;
3213 case CODEC_VER_0:
3214 ret = regmap_register_patch(rt5663->regmap, rt5663_patch_list,
3215 ARRAY_SIZE(rt5663_patch_list));
3216 if (ret != 0)
3217 dev_warn(&i2c->dev,
3218 "Failed to apply regmap patch: %d\n", ret);
3219 break;
3220 default:
3221 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3222 }
3223
3224 if (rt5663->pdata.dc_offset_l_manual) {
3225 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
3226 rt5663->pdata.dc_offset_l_manual >> 16);
3227 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
3228 rt5663->pdata.dc_offset_l_manual & 0xffff);
3229 }
3230
3231 if (rt5663->pdata.dc_offset_r_manual) {
3232 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
3233 rt5663->pdata.dc_offset_r_manual >> 16);
3234 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
3235 rt5663->pdata.dc_offset_r_manual & 0xffff);
3236 }
3237
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3238 /* GPIO1 as IRQ */
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3239 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
3240 RT5663_GP1_PIN_IRQ);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3241 /* 4btn inline command debounce */
3242 regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3243 RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3244
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3245 switch (rt5663->codec_ver) {
3246 case CODEC_VER_1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3247 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3248 /* JD1 */
3249 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3250 RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK,
3251 RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3252 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3253 RT5663_PWR_JD1_MASK, RT5663_PWR_JD1);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3254 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3255 RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3256
3257 regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3258 RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3259 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3260 RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK |
3261 RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG |
3262 RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3263 /* Set GPIO4 and GPIO8 as input for combo jack */
3264 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3265 RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT);
3266 regmap_update_bits(rt5663->regmap, RT5663_GPIO_3,
3267 RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3268 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3269 RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK,
3270 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3271 break;
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3272 case CODEC_VER_0:
Jack Yu7e7e76b2016-10-03 10:43:27 +0800[diff] [blame]3273 regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC,
Bard Liao73444722016-10-21 11:02:28 +0800[diff] [blame]3274 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
Jack Yu7e7e76b2016-10-03 10:43:27 +0800[diff] [blame]3275 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
Oder Chiouaf2728e2017-06-06 14:59:54 +0800[diff] [blame]3276 RT5663_IRQ_MANUAL_MASK, RT5663_IRQ_MANUAL_EN);
Jack Yu7e7e76b2016-10-03 10:43:27 +0800[diff] [blame]3277 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3278 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
3279 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1,
3280 RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3281 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3282 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be);
3283 msleep(20);
3284 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be);
3285 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
Jack Yu7e7e76b2016-10-03 10:43:27 +0800[diff] [blame]3286 RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK,
3287 RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3288 /* DACREF LDO control */
3289 regmap_update_bits(rt5663->regmap, RT5663_DACREF_LDO, 0x3e0e,
3290 0x3a0a);
3291 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3292 RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON);
3293 regmap_update_bits(rt5663->regmap, RT5663_TDM_2,
3294 RT5663_DATA_SWAP_ADCDAT1_MASK,
3295 RT5663_DATA_SWAP_ADCDAT1_LL);
3296 break;
3297 default:
3298 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3299 }
3300
3301 INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work);
3302
3303 if (i2c->irq) {
3304 ret = request_irq(i2c->irq, rt5663_irq,
3305 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3306 | IRQF_ONESHOT, "rt5663", rt5663);
3307 if (ret)
3308 dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n",
3309 __func__, ret);
3310 }
3311
3312 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5663,
3313 rt5663_dai, ARRAY_SIZE(rt5663_dai));
3314
3315 if (ret) {
3316 if (i2c->irq)
3317 free_irq(i2c->irq, rt5663);
3318 }
3319
3320 return ret;
3321}
3322
3323static int rt5663_i2c_remove(struct i2c_client *i2c)
3324{
3325 struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c);
3326
3327 if (i2c->irq)
3328 free_irq(i2c->irq, rt5663);
3329
3330 snd_soc_unregister_codec(&i2c->dev);
3331
3332 return 0;
3333}
3334
Wei Yongjun66d7c262016-09-17 01:34:09 +0000[diff] [blame]3335static void rt5663_i2c_shutdown(struct i2c_client *client)
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3336{
3337 struct rt5663_priv *rt5663 = i2c_get_clientdata(client);
3338
3339 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3340}
3341
Wei Yongjun66d7c262016-09-17 01:34:09 +0000[diff] [blame]3342static struct i2c_driver rt5663_i2c_driver = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3343 .driver = {
3344 .name = "rt5663",
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3345 .acpi_match_table = ACPI_PTR(rt5663_acpi_match),
3346 .of_match_table = of_match_ptr(rt5663_of_match),
3347 },
3348 .probe = rt5663_i2c_probe,
3349 .remove = rt5663_i2c_remove,
3350 .shutdown = rt5663_i2c_shutdown,
3351 .id_table = rt5663_i2c_id,
3352};
3353module_i2c_driver(rt5663_i2c_driver);
3354
3355MODULE_DESCRIPTION("ASoC RT5663 driver");
3356MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
3357MODULE_LICENSE("GPL v2");