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git.odroid.com / yocto / kernel / common / 90bdbb46f41c9fa670d7b0709e0c8a92ad82bdfe / . / sound / soc / codecs / rt5677.c
blob: 4a0f3dfb2a4722ce44f604e9cdf46d88d7450ffb [file] [log] [blame]
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1/*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/fs.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/regmap.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/spi/spi.h>
Oder Chiou44caf762014-09-16 11:37:39 +0800[diff] [blame]22#include <linux/gpio.h>
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
30
Axel Lin30f14b42014-06-10 08:57:36 +0800[diff] [blame]31#include "rl6231.h"
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]32#include "rt5677.h"
33
34#define RT5677_DEVICE_ID 0x6327
35
36#define RT5677_PR_RANGE_BASE (0xff + 1)
37#define RT5677_PR_SPACING 0x100
38
39#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
40
41static const struct regmap_range_cfg rt5677_ranges[] = {
42 {
43 .name = "PR",
44 .range_min = RT5677_PR_BASE,
45 .range_max = RT5677_PR_BASE + 0xfd,
46 .selector_reg = RT5677_PRIV_INDEX,
47 .selector_mask = 0xff,
48 .selector_shift = 0x0,
49 .window_start = RT5677_PRIV_DATA,
50 .window_len = 0x1,
51 },
52};
53
54static const struct reg_default init_list[] = {
55 {RT5677_PR_BASE + 0x3d, 0x364d},
56 {RT5677_PR_BASE + 0x17, 0x4fc0},
57 {RT5677_PR_BASE + 0x13, 0x0312},
58 {RT5677_PR_BASE + 0x1e, 0x0000},
59 {RT5677_PR_BASE + 0x12, 0x0eaa},
60 {RT5677_PR_BASE + 0x14, 0x018a},
61};
62#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
63
64static const struct reg_default rt5677_reg[] = {
65 {RT5677_RESET , 0x0000},
66 {RT5677_LOUT1 , 0xa800},
67 {RT5677_IN1 , 0x0000},
68 {RT5677_MICBIAS , 0x0000},
69 {RT5677_SLIMBUS_PARAM , 0x0000},
70 {RT5677_SLIMBUS_RX , 0x0000},
71 {RT5677_SLIMBUS_CTRL , 0x0000},
72 {RT5677_SIDETONE_CTRL , 0x000b},
73 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
74 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
75 {RT5677_DAC4_DIG_VOL , 0xafaf},
76 {RT5677_DAC3_DIG_VOL , 0xafaf},
77 {RT5677_DAC1_DIG_VOL , 0xafaf},
78 {RT5677_DAC2_DIG_VOL , 0xafaf},
79 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
80 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
81 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
82 {RT5677_STO1_2_ADC_BST , 0x0000},
83 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
84 {RT5677_ADC_BST_CTRL2 , 0x0000},
85 {RT5677_STO3_4_ADC_BST , 0x0000},
86 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
87 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_STO4_ADC_MIXER , 0xd4c0},
89 {RT5677_STO3_ADC_MIXER , 0xd4c0},
90 {RT5677_STO2_ADC_MIXER , 0xd4c0},
91 {RT5677_STO1_ADC_MIXER , 0xd4c0},
92 {RT5677_MONO_ADC_MIXER , 0xd4d1},
93 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
94 {RT5677_STO1_DAC_MIXER , 0xaaaa},
95 {RT5677_MONO_DAC_MIXER , 0xaaaa},
96 {RT5677_DD1_MIXER , 0xaaaa},
97 {RT5677_DD2_MIXER , 0xaaaa},
98 {RT5677_IF3_DATA , 0x0000},
99 {RT5677_IF4_DATA , 0x0000},
100 {RT5677_PDM_OUT_CTRL , 0x8888},
101 {RT5677_PDM_DATA_CTRL1 , 0x0000},
102 {RT5677_PDM_DATA_CTRL2 , 0x0000},
103 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
104 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
105 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
106 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
107 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
108 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
109 {RT5677_TDM1_CTRL1 , 0x0300},
110 {RT5677_TDM1_CTRL2 , 0x0000},
111 {RT5677_TDM1_CTRL3 , 0x4000},
112 {RT5677_TDM1_CTRL4 , 0x0123},
113 {RT5677_TDM1_CTRL5 , 0x4567},
114 {RT5677_TDM2_CTRL1 , 0x0300},
115 {RT5677_TDM2_CTRL2 , 0x0000},
116 {RT5677_TDM2_CTRL3 , 0x4000},
117 {RT5677_TDM2_CTRL4 , 0x0123},
118 {RT5677_TDM2_CTRL5 , 0x4567},
119 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
120 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
121 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
122 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
123 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
124 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
125 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
126 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
127 {RT5677_DMIC_CTRL1 , 0x1505},
128 {RT5677_DMIC_CTRL2 , 0x0055},
129 {RT5677_HAP_GENE_CTRL1 , 0x0111},
130 {RT5677_HAP_GENE_CTRL2 , 0x0064},
131 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
132 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
133 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
134 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
135 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
136 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
137 {RT5677_HAP_GENE_CTRL9 , 0xf000},
138 {RT5677_HAP_GENE_CTRL10 , 0x0000},
139 {RT5677_PWR_DIG1 , 0x0000},
140 {RT5677_PWR_DIG2 , 0x0000},
141 {RT5677_PWR_ANLG1 , 0x0055},
142 {RT5677_PWR_ANLG2 , 0x0000},
143 {RT5677_PWR_DSP1 , 0x0001},
144 {RT5677_PWR_DSP_ST , 0x0000},
145 {RT5677_PWR_DSP2 , 0x0000},
146 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
147 {RT5677_PRIV_INDEX , 0x0000},
148 {RT5677_PRIV_DATA , 0x0000},
149 {RT5677_I2S4_SDP , 0x8000},
150 {RT5677_I2S1_SDP , 0x8000},
151 {RT5677_I2S2_SDP , 0x8000},
152 {RT5677_I2S3_SDP , 0x8000},
153 {RT5677_CLK_TREE_CTRL1 , 0x1111},
154 {RT5677_CLK_TREE_CTRL2 , 0x1111},
155 {RT5677_CLK_TREE_CTRL3 , 0x0000},
156 {RT5677_PLL1_CTRL1 , 0x0000},
157 {RT5677_PLL1_CTRL2 , 0x0000},
158 {RT5677_PLL2_CTRL1 , 0x0c60},
159 {RT5677_PLL2_CTRL2 , 0x2000},
160 {RT5677_GLB_CLK1 , 0x0000},
161 {RT5677_GLB_CLK2 , 0x0000},
162 {RT5677_ASRC_1 , 0x0000},
163 {RT5677_ASRC_2 , 0x0000},
164 {RT5677_ASRC_3 , 0x0000},
165 {RT5677_ASRC_4 , 0x0000},
166 {RT5677_ASRC_5 , 0x0000},
167 {RT5677_ASRC_6 , 0x0000},
168 {RT5677_ASRC_7 , 0x0000},
169 {RT5677_ASRC_8 , 0x0000},
170 {RT5677_ASRC_9 , 0x0000},
171 {RT5677_ASRC_10 , 0x0000},
172 {RT5677_ASRC_11 , 0x0000},
173 {RT5677_ASRC_12 , 0x0008},
174 {RT5677_ASRC_13 , 0x0000},
175 {RT5677_ASRC_14 , 0x0000},
176 {RT5677_ASRC_15 , 0x0000},
177 {RT5677_ASRC_16 , 0x0000},
178 {RT5677_ASRC_17 , 0x0000},
179 {RT5677_ASRC_18 , 0x0000},
180 {RT5677_ASRC_19 , 0x0000},
181 {RT5677_ASRC_20 , 0x0000},
182 {RT5677_ASRC_21 , 0x000c},
183 {RT5677_ASRC_22 , 0x0000},
184 {RT5677_ASRC_23 , 0x0000},
185 {RT5677_VAD_CTRL1 , 0x2184},
186 {RT5677_VAD_CTRL2 , 0x010a},
187 {RT5677_VAD_CTRL3 , 0x0aea},
188 {RT5677_VAD_CTRL4 , 0x000c},
189 {RT5677_VAD_CTRL5 , 0x0000},
190 {RT5677_DSP_INB_CTRL1 , 0x0000},
191 {RT5677_DSP_INB_CTRL2 , 0x0000},
192 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
193 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
194 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
195 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
196 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
197 {RT5677_ADC_EQ_CTRL1 , 0x6000},
198 {RT5677_ADC_EQ_CTRL2 , 0x0000},
199 {RT5677_EQ_CTRL1 , 0xc000},
200 {RT5677_EQ_CTRL2 , 0x0000},
201 {RT5677_EQ_CTRL3 , 0x0000},
202 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
203 {RT5677_JD_CTRL1 , 0x0000},
204 {RT5677_JD_CTRL2 , 0x0000},
205 {RT5677_JD_CTRL3 , 0x0000},
206 {RT5677_IRQ_CTRL1 , 0x0000},
207 {RT5677_IRQ_CTRL2 , 0x0000},
208 {RT5677_GPIO_ST , 0x0000},
209 {RT5677_GPIO_CTRL1 , 0x0000},
210 {RT5677_GPIO_CTRL2 , 0x0000},
211 {RT5677_GPIO_CTRL3 , 0x0000},
212 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
213 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
214 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
215 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
216 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
217 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
218 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
219 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
220 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
221 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
222 {RT5677_MB_DRC_CTRL1 , 0x0f20},
223 {RT5677_DRC1_CTRL1 , 0x001f},
224 {RT5677_DRC1_CTRL2 , 0x020c},
225 {RT5677_DRC1_CTRL3 , 0x1f00},
226 {RT5677_DRC1_CTRL4 , 0x0000},
227 {RT5677_DRC1_CTRL5 , 0x0000},
228 {RT5677_DRC1_CTRL6 , 0x0029},
229 {RT5677_DRC2_CTRL1 , 0x001f},
230 {RT5677_DRC2_CTRL2 , 0x020c},
231 {RT5677_DRC2_CTRL3 , 0x1f00},
232 {RT5677_DRC2_CTRL4 , 0x0000},
233 {RT5677_DRC2_CTRL5 , 0x0000},
234 {RT5677_DRC2_CTRL6 , 0x0029},
235 {RT5677_DRC1_HL_CTRL1 , 0x8000},
236 {RT5677_DRC1_HL_CTRL2 , 0x0200},
237 {RT5677_DRC2_HL_CTRL1 , 0x8000},
238 {RT5677_DRC2_HL_CTRL2 , 0x0200},
239 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
240 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
241 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
242 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
243 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
244 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
245 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
246 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
247 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
248 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
249 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
250 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
251 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
252 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
253 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
254 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
255 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
256 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
257 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
258 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
259 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
260 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
261 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
262 {RT5677_DIG_MISC , 0x0000},
263 {RT5677_GEN_CTRL1 , 0x0000},
264 {RT5677_GEN_CTRL2 , 0x0000},
265 {RT5677_VENDOR_ID , 0x0000},
266 {RT5677_VENDOR_ID1 , 0x10ec},
267 {RT5677_VENDOR_ID2 , 0x6327},
268};
269
270static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
271{
272 int i;
273
274 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
275 if (reg >= rt5677_ranges[i].range_min &&
276 reg <= rt5677_ranges[i].range_max) {
277 return true;
278 }
279 }
280
281 switch (reg) {
282 case RT5677_RESET:
283 case RT5677_SLIMBUS_PARAM:
284 case RT5677_PDM_DATA_CTRL1:
285 case RT5677_PDM_DATA_CTRL2:
286 case RT5677_PDM1_DATA_CTRL4:
287 case RT5677_PDM2_DATA_CTRL4:
288 case RT5677_I2C_MASTER_CTRL1:
289 case RT5677_I2C_MASTER_CTRL7:
290 case RT5677_I2C_MASTER_CTRL8:
291 case RT5677_HAP_GENE_CTRL2:
292 case RT5677_PWR_DSP_ST:
293 case RT5677_PRIV_DATA:
294 case RT5677_PLL1_CTRL2:
295 case RT5677_PLL2_CTRL2:
296 case RT5677_ASRC_22:
297 case RT5677_ASRC_23:
298 case RT5677_VAD_CTRL5:
299 case RT5677_ADC_EQ_CTRL1:
300 case RT5677_EQ_CTRL1:
301 case RT5677_IRQ_CTRL1:
302 case RT5677_IRQ_CTRL2:
303 case RT5677_GPIO_ST:
304 case RT5677_DSP_INB1_SRC_CTRL4:
305 case RT5677_DSP_INB2_SRC_CTRL4:
306 case RT5677_DSP_INB3_SRC_CTRL4:
307 case RT5677_DSP_OUTB1_SRC_CTRL4:
308 case RT5677_DSP_OUTB2_SRC_CTRL4:
309 case RT5677_VENDOR_ID:
310 case RT5677_VENDOR_ID1:
311 case RT5677_VENDOR_ID2:
312 return true;
313 default:
314 return false;
315 }
316}
317
318static bool rt5677_readable_register(struct device *dev, unsigned int reg)
319{
320 int i;
321
322 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
323 if (reg >= rt5677_ranges[i].range_min &&
324 reg <= rt5677_ranges[i].range_max) {
325 return true;
326 }
327 }
328
329 switch (reg) {
330 case RT5677_RESET:
331 case RT5677_LOUT1:
332 case RT5677_IN1:
333 case RT5677_MICBIAS:
334 case RT5677_SLIMBUS_PARAM:
335 case RT5677_SLIMBUS_RX:
336 case RT5677_SLIMBUS_CTRL:
337 case RT5677_SIDETONE_CTRL:
338 case RT5677_ANA_DAC1_2_3_SRC:
339 case RT5677_IF_DSP_DAC3_4_MIXER:
340 case RT5677_DAC4_DIG_VOL:
341 case RT5677_DAC3_DIG_VOL:
342 case RT5677_DAC1_DIG_VOL:
343 case RT5677_DAC2_DIG_VOL:
344 case RT5677_IF_DSP_DAC2_MIXER:
345 case RT5677_STO1_ADC_DIG_VOL:
346 case RT5677_MONO_ADC_DIG_VOL:
347 case RT5677_STO1_2_ADC_BST:
348 case RT5677_STO2_ADC_DIG_VOL:
349 case RT5677_ADC_BST_CTRL2:
350 case RT5677_STO3_4_ADC_BST:
351 case RT5677_STO3_ADC_DIG_VOL:
352 case RT5677_STO4_ADC_DIG_VOL:
353 case RT5677_STO4_ADC_MIXER:
354 case RT5677_STO3_ADC_MIXER:
355 case RT5677_STO2_ADC_MIXER:
356 case RT5677_STO1_ADC_MIXER:
357 case RT5677_MONO_ADC_MIXER:
358 case RT5677_ADC_IF_DSP_DAC1_MIXER:
359 case RT5677_STO1_DAC_MIXER:
360 case RT5677_MONO_DAC_MIXER:
361 case RT5677_DD1_MIXER:
362 case RT5677_DD2_MIXER:
363 case RT5677_IF3_DATA:
364 case RT5677_IF4_DATA:
365 case RT5677_PDM_OUT_CTRL:
366 case RT5677_PDM_DATA_CTRL1:
367 case RT5677_PDM_DATA_CTRL2:
368 case RT5677_PDM1_DATA_CTRL2:
369 case RT5677_PDM1_DATA_CTRL3:
370 case RT5677_PDM1_DATA_CTRL4:
371 case RT5677_PDM2_DATA_CTRL2:
372 case RT5677_PDM2_DATA_CTRL3:
373 case RT5677_PDM2_DATA_CTRL4:
374 case RT5677_TDM1_CTRL1:
375 case RT5677_TDM1_CTRL2:
376 case RT5677_TDM1_CTRL3:
377 case RT5677_TDM1_CTRL4:
378 case RT5677_TDM1_CTRL5:
379 case RT5677_TDM2_CTRL1:
380 case RT5677_TDM2_CTRL2:
381 case RT5677_TDM2_CTRL3:
382 case RT5677_TDM2_CTRL4:
383 case RT5677_TDM2_CTRL5:
384 case RT5677_I2C_MASTER_CTRL1:
385 case RT5677_I2C_MASTER_CTRL2:
386 case RT5677_I2C_MASTER_CTRL3:
387 case RT5677_I2C_MASTER_CTRL4:
388 case RT5677_I2C_MASTER_CTRL5:
389 case RT5677_I2C_MASTER_CTRL6:
390 case RT5677_I2C_MASTER_CTRL7:
391 case RT5677_I2C_MASTER_CTRL8:
392 case RT5677_DMIC_CTRL1:
393 case RT5677_DMIC_CTRL2:
394 case RT5677_HAP_GENE_CTRL1:
395 case RT5677_HAP_GENE_CTRL2:
396 case RT5677_HAP_GENE_CTRL3:
397 case RT5677_HAP_GENE_CTRL4:
398 case RT5677_HAP_GENE_CTRL5:
399 case RT5677_HAP_GENE_CTRL6:
400 case RT5677_HAP_GENE_CTRL7:
401 case RT5677_HAP_GENE_CTRL8:
402 case RT5677_HAP_GENE_CTRL9:
403 case RT5677_HAP_GENE_CTRL10:
404 case RT5677_PWR_DIG1:
405 case RT5677_PWR_DIG2:
406 case RT5677_PWR_ANLG1:
407 case RT5677_PWR_ANLG2:
408 case RT5677_PWR_DSP1:
409 case RT5677_PWR_DSP_ST:
410 case RT5677_PWR_DSP2:
411 case RT5677_ADC_DAC_HPF_CTRL1:
412 case RT5677_PRIV_INDEX:
413 case RT5677_PRIV_DATA:
414 case RT5677_I2S4_SDP:
415 case RT5677_I2S1_SDP:
416 case RT5677_I2S2_SDP:
417 case RT5677_I2S3_SDP:
418 case RT5677_CLK_TREE_CTRL1:
419 case RT5677_CLK_TREE_CTRL2:
420 case RT5677_CLK_TREE_CTRL3:
421 case RT5677_PLL1_CTRL1:
422 case RT5677_PLL1_CTRL2:
423 case RT5677_PLL2_CTRL1:
424 case RT5677_PLL2_CTRL2:
425 case RT5677_GLB_CLK1:
426 case RT5677_GLB_CLK2:
427 case RT5677_ASRC_1:
428 case RT5677_ASRC_2:
429 case RT5677_ASRC_3:
430 case RT5677_ASRC_4:
431 case RT5677_ASRC_5:
432 case RT5677_ASRC_6:
433 case RT5677_ASRC_7:
434 case RT5677_ASRC_8:
435 case RT5677_ASRC_9:
436 case RT5677_ASRC_10:
437 case RT5677_ASRC_11:
438 case RT5677_ASRC_12:
439 case RT5677_ASRC_13:
440 case RT5677_ASRC_14:
441 case RT5677_ASRC_15:
442 case RT5677_ASRC_16:
443 case RT5677_ASRC_17:
444 case RT5677_ASRC_18:
445 case RT5677_ASRC_19:
446 case RT5677_ASRC_20:
447 case RT5677_ASRC_21:
448 case RT5677_ASRC_22:
449 case RT5677_ASRC_23:
450 case RT5677_VAD_CTRL1:
451 case RT5677_VAD_CTRL2:
452 case RT5677_VAD_CTRL3:
453 case RT5677_VAD_CTRL4:
454 case RT5677_VAD_CTRL5:
455 case RT5677_DSP_INB_CTRL1:
456 case RT5677_DSP_INB_CTRL2:
457 case RT5677_DSP_IN_OUTB_CTRL:
458 case RT5677_DSP_OUTB0_1_DIG_VOL:
459 case RT5677_DSP_OUTB2_3_DIG_VOL:
460 case RT5677_DSP_OUTB4_5_DIG_VOL:
461 case RT5677_DSP_OUTB6_7_DIG_VOL:
462 case RT5677_ADC_EQ_CTRL1:
463 case RT5677_ADC_EQ_CTRL2:
464 case RT5677_EQ_CTRL1:
465 case RT5677_EQ_CTRL2:
466 case RT5677_EQ_CTRL3:
467 case RT5677_SOFT_VOL_ZERO_CROSS1:
468 case RT5677_JD_CTRL1:
469 case RT5677_JD_CTRL2:
470 case RT5677_JD_CTRL3:
471 case RT5677_IRQ_CTRL1:
472 case RT5677_IRQ_CTRL2:
473 case RT5677_GPIO_ST:
474 case RT5677_GPIO_CTRL1:
475 case RT5677_GPIO_CTRL2:
476 case RT5677_GPIO_CTRL3:
477 case RT5677_STO1_ADC_HI_FILTER1:
478 case RT5677_STO1_ADC_HI_FILTER2:
479 case RT5677_MONO_ADC_HI_FILTER1:
480 case RT5677_MONO_ADC_HI_FILTER2:
481 case RT5677_STO2_ADC_HI_FILTER1:
482 case RT5677_STO2_ADC_HI_FILTER2:
483 case RT5677_STO3_ADC_HI_FILTER1:
484 case RT5677_STO3_ADC_HI_FILTER2:
485 case RT5677_STO4_ADC_HI_FILTER1:
486 case RT5677_STO4_ADC_HI_FILTER2:
487 case RT5677_MB_DRC_CTRL1:
488 case RT5677_DRC1_CTRL1:
489 case RT5677_DRC1_CTRL2:
490 case RT5677_DRC1_CTRL3:
491 case RT5677_DRC1_CTRL4:
492 case RT5677_DRC1_CTRL5:
493 case RT5677_DRC1_CTRL6:
494 case RT5677_DRC2_CTRL1:
495 case RT5677_DRC2_CTRL2:
496 case RT5677_DRC2_CTRL3:
497 case RT5677_DRC2_CTRL4:
498 case RT5677_DRC2_CTRL5:
499 case RT5677_DRC2_CTRL6:
500 case RT5677_DRC1_HL_CTRL1:
501 case RT5677_DRC1_HL_CTRL2:
502 case RT5677_DRC2_HL_CTRL1:
503 case RT5677_DRC2_HL_CTRL2:
504 case RT5677_DSP_INB1_SRC_CTRL1:
505 case RT5677_DSP_INB1_SRC_CTRL2:
506 case RT5677_DSP_INB1_SRC_CTRL3:
507 case RT5677_DSP_INB1_SRC_CTRL4:
508 case RT5677_DSP_INB2_SRC_CTRL1:
509 case RT5677_DSP_INB2_SRC_CTRL2:
510 case RT5677_DSP_INB2_SRC_CTRL3:
511 case RT5677_DSP_INB2_SRC_CTRL4:
512 case RT5677_DSP_INB3_SRC_CTRL1:
513 case RT5677_DSP_INB3_SRC_CTRL2:
514 case RT5677_DSP_INB3_SRC_CTRL3:
515 case RT5677_DSP_INB3_SRC_CTRL4:
516 case RT5677_DSP_OUTB1_SRC_CTRL1:
517 case RT5677_DSP_OUTB1_SRC_CTRL2:
518 case RT5677_DSP_OUTB1_SRC_CTRL3:
519 case RT5677_DSP_OUTB1_SRC_CTRL4:
520 case RT5677_DSP_OUTB2_SRC_CTRL1:
521 case RT5677_DSP_OUTB2_SRC_CTRL2:
522 case RT5677_DSP_OUTB2_SRC_CTRL3:
523 case RT5677_DSP_OUTB2_SRC_CTRL4:
524 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
525 case RT5677_DSP_OUTB_45_MIXER_CTRL:
526 case RT5677_DSP_OUTB_67_MIXER_CTRL:
527 case RT5677_DIG_MISC:
528 case RT5677_GEN_CTRL1:
529 case RT5677_GEN_CTRL2:
530 case RT5677_VENDOR_ID:
531 case RT5677_VENDOR_ID1:
532 case RT5677_VENDOR_ID2:
533 return true;
534 default:
535 return false;
536 }
537}
538
539static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
540static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
541static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
542static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
543static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
Oder Chiou90bdbb42014-09-18 14:45:59 +0800[diff] [blame^]544static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]545
546/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
547static unsigned int bst_tlv[] = {
548 TLV_DB_RANGE_HEAD(7),
549 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
550 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
551 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
552 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
553 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
554 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
555 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
556};
557
558static const struct snd_kcontrol_new rt5677_snd_controls[] = {
559 /* OUTPUT Control */
560 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
561 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
562 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
563 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
564 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
565 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
566
567 /* DAC Digital Volume */
568 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
569 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
570 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
571 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
572 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
573 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
574 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
575 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
576
577 /* IN1/IN2 Control */
578 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
579 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
580
581 /* ADC Digital Volume Control */
582 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
583 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
584 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
585 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
586 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
587 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
588 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
589 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
590 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
591 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
592
593 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
594 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
595 adc_vol_tlv),
596 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
597 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
598 adc_vol_tlv),
599 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
600 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
601 adc_vol_tlv),
602 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
603 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
604 adc_vol_tlv),
605 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
606 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 127, 0,
607 adc_vol_tlv),
608
Oder Chiou90bdbb42014-09-18 14:45:59 +0800[diff] [blame^]609 /* Sidetone Control */
610 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
611 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
612
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]613 /* ADC Boost Volume Control */
Oder Chiou80220f22014-06-10 14:35:25 +0800[diff] [blame]614 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]615 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
616 adc_bst_tlv),
Oder Chiou80220f22014-06-10 14:35:25 +0800[diff] [blame]617 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]618 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
619 adc_bst_tlv),
Oder Chiou80220f22014-06-10 14:35:25 +0800[diff] [blame]620 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]621 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
622 adc_bst_tlv),
Oder Chiou80220f22014-06-10 14:35:25 +0800[diff] [blame]623 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]624 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
625 adc_bst_tlv),
Oder Chiou80220f22014-06-10 14:35:25 +0800[diff] [blame]626 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]627 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
628 adc_bst_tlv),
629};
630
631/**
632 * set_dmic_clk - Set parameter of dmic.
633 *
634 * @w: DAPM widget.
635 * @kcontrol: The kcontrol of this widget.
636 * @event: Event id.
637 *
638 * Choose dmic clock between 1MHz and 3MHz.
639 * It is better for clock to approximate 3MHz.
640 */
641static int set_dmic_clk(struct snd_soc_dapm_widget *w,
642 struct snd_kcontrol *kcontrol, int event)
643{
644 struct snd_soc_codec *codec = w->codec;
645 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
Axel Lin9a535812014-06-03 10:58:58 +0800[diff] [blame]646 int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]647
648 if (idx < 0)
649 dev_err(codec->dev, "Failed to set DMIC clock\n");
650 else
651 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
652 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
653 return idx;
654}
655
656static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
657 struct snd_soc_dapm_widget *sink)
658{
659 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec);
660 unsigned int val;
661
662 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
663 val &= RT5677_SCLK_SRC_MASK;
664 if (val == RT5677_SCLK_SRC_PLL1)
665 return 1;
666 else
667 return 0;
668}
669
670/* Digital Mixer */
671static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
672 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
673 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
674 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
675 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
676};
677
678static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
679 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
680 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
681 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
682 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
683};
684
685static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
686 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
687 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
688 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
689 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
690};
691
692static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
693 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
694 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
695 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
696 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
697};
698
699static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
700 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
701 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
702 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
703 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
704};
705
706static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
707 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
708 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
709 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
710 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
711};
712
713static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
714 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
715 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
716 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
717 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
718};
719
720static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
721 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
722 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
723 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
724 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
725};
726
727static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
728 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
729 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
730 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
731 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
732};
733
734static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
735 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
736 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
737 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
738 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
739};
740
741static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
742 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
743 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
744 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
745 RT5677_M_DAC1_L_SFT, 1, 1),
746};
747
748static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
749 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
750 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
751 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
752 RT5677_M_DAC1_R_SFT, 1, 1),
753};
754
755static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
756 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
757 RT5677_M_ST_DAC1_L_SFT, 1, 1),
758 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
759 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
760 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
761 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
762 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
763 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
764};
765
766static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
767 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
768 RT5677_M_ST_DAC1_R_SFT, 1, 1),
769 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
770 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
771 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
772 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
773 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
774 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
775};
776
777static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
778 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
779 RT5677_M_ST_DAC2_L_SFT, 1, 1),
780 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
781 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
782 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
783 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
784 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
785 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
786};
787
788static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
789 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
790 RT5677_M_ST_DAC2_R_SFT, 1, 1),
791 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
792 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
793 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
794 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
795 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
796 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
797};
798
799static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
800 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
801 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
802 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
803 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
804 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
805 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
806 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
807 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
808};
809
810static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
811 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
812 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
813 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
814 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
815 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
816 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
817 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
818 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
819};
820
821static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
822 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
823 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
824 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
825 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
826 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
827 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
828 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
829 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
830};
831
832static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
833 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
834 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
835 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
836 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
837 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
838 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
839 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
840 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
841};
842
843static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
844 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
845 RT5677_DSP_IB_01_H_SFT, 1, 1),
846 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
847 RT5677_DSP_IB_23_H_SFT, 1, 1),
848 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
849 RT5677_DSP_IB_45_H_SFT, 1, 1),
850 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
851 RT5677_DSP_IB_6_H_SFT, 1, 1),
852 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
853 RT5677_DSP_IB_7_H_SFT, 1, 1),
854 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
855 RT5677_DSP_IB_8_H_SFT, 1, 1),
856 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
857 RT5677_DSP_IB_9_H_SFT, 1, 1),
858};
859
860static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
861 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
862 RT5677_DSP_IB_01_L_SFT, 1, 1),
863 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
864 RT5677_DSP_IB_23_L_SFT, 1, 1),
865 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
866 RT5677_DSP_IB_45_L_SFT, 1, 1),
867 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
868 RT5677_DSP_IB_6_L_SFT, 1, 1),
869 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
870 RT5677_DSP_IB_7_L_SFT, 1, 1),
871 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
872 RT5677_DSP_IB_8_L_SFT, 1, 1),
873 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
874 RT5677_DSP_IB_9_L_SFT, 1, 1),
875};
876
877static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
878 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
879 RT5677_DSP_IB_01_H_SFT, 1, 1),
880 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
881 RT5677_DSP_IB_23_H_SFT, 1, 1),
882 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
883 RT5677_DSP_IB_45_H_SFT, 1, 1),
884 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
885 RT5677_DSP_IB_6_H_SFT, 1, 1),
886 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
887 RT5677_DSP_IB_7_H_SFT, 1, 1),
888 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
889 RT5677_DSP_IB_8_H_SFT, 1, 1),
890 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
891 RT5677_DSP_IB_9_H_SFT, 1, 1),
892};
893
894static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
895 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
896 RT5677_DSP_IB_01_L_SFT, 1, 1),
897 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
898 RT5677_DSP_IB_23_L_SFT, 1, 1),
899 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
900 RT5677_DSP_IB_45_L_SFT, 1, 1),
901 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
902 RT5677_DSP_IB_6_L_SFT, 1, 1),
903 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
904 RT5677_DSP_IB_7_L_SFT, 1, 1),
905 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
906 RT5677_DSP_IB_8_L_SFT, 1, 1),
907 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
908 RT5677_DSP_IB_9_L_SFT, 1, 1),
909};
910
911static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
912 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
913 RT5677_DSP_IB_01_H_SFT, 1, 1),
914 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
915 RT5677_DSP_IB_23_H_SFT, 1, 1),
916 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
917 RT5677_DSP_IB_45_H_SFT, 1, 1),
918 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
919 RT5677_DSP_IB_6_H_SFT, 1, 1),
920 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
921 RT5677_DSP_IB_7_H_SFT, 1, 1),
922 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
923 RT5677_DSP_IB_8_H_SFT, 1, 1),
924 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
925 RT5677_DSP_IB_9_H_SFT, 1, 1),
926};
927
928static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
929 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
930 RT5677_DSP_IB_01_L_SFT, 1, 1),
931 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
932 RT5677_DSP_IB_23_L_SFT, 1, 1),
933 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
934 RT5677_DSP_IB_45_L_SFT, 1, 1),
935 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
936 RT5677_DSP_IB_6_L_SFT, 1, 1),
937 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
938 RT5677_DSP_IB_7_L_SFT, 1, 1),
939 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
940 RT5677_DSP_IB_8_L_SFT, 1, 1),
941 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
942 RT5677_DSP_IB_9_L_SFT, 1, 1),
943};
944
945
946/* Mux */
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]947/* DAC1 L/R Source */ /* MX-29 [10:8] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]948static const char * const rt5677_dac1_src[] = {
949 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
950 "OB 01"
951};
952
953static SOC_ENUM_SINGLE_DECL(
954 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
955 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
956
957static const struct snd_kcontrol_new rt5677_dac1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]958 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]959
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]960/* ADDA1 L/R Source */ /* MX-29 [1:0] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]961static const char * const rt5677_adda1_src[] = {
962 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
963};
964
965static SOC_ENUM_SINGLE_DECL(
966 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
967 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
968
969static const struct snd_kcontrol_new rt5677_adda1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]970 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]971
972
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]973/*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]974static const char * const rt5677_dac2l_src[] = {
975 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
976 "OB 2",
977};
978
979static SOC_ENUM_SINGLE_DECL(
980 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
981 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
982
983static const struct snd_kcontrol_new rt5677_dac2_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]984 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]985
986static const char * const rt5677_dac2r_src[] = {
987 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
988 "OB 3", "Haptic Generator", "VAD ADC"
989};
990
991static SOC_ENUM_SINGLE_DECL(
992 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
993 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
994
995static const struct snd_kcontrol_new rt5677_dac2_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]996 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]997
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]998/*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]999static const char * const rt5677_dac3l_src[] = {
1000 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1001 "SLB DAC 4", "OB 4"
1002};
1003
1004static SOC_ENUM_SINGLE_DECL(
1005 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1006 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1007
1008static const struct snd_kcontrol_new rt5677_dac3_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1009 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1010
1011static const char * const rt5677_dac3r_src[] = {
1012 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1013 "SLB DAC 5", "OB 5"
1014};
1015
1016static SOC_ENUM_SINGLE_DECL(
1017 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1018 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1019
1020static const struct snd_kcontrol_new rt5677_dac3_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1021 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1022
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1023/*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1024static const char * const rt5677_dac4l_src[] = {
1025 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1026 "SLB DAC 6", "OB 6"
1027};
1028
1029static SOC_ENUM_SINGLE_DECL(
1030 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1031 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1032
1033static const struct snd_kcontrol_new rt5677_dac4_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1034 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1035
1036static const char * const rt5677_dac4r_src[] = {
1037 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1038 "SLB DAC 7", "OB 7"
1039};
1040
1041static SOC_ENUM_SINGLE_DECL(
1042 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1043 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1044
1045static const struct snd_kcontrol_new rt5677_dac4_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1046 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1047
1048/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1049static const char * const rt5677_iob_bypass_src[] = {
1050 "Bypass", "Pass SRC"
1051};
1052
1053static SOC_ENUM_SINGLE_DECL(
1054 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1055 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1056
1057static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1058 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1059
1060static SOC_ENUM_SINGLE_DECL(
1061 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1062 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1063
1064static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1065 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1066
1067static SOC_ENUM_SINGLE_DECL(
1068 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1069 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1070
1071static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1072 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1073
1074static SOC_ENUM_SINGLE_DECL(
1075 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1076 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1077
1078static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1079 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1080
1081static SOC_ENUM_SINGLE_DECL(
1082 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1083 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1084
1085static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1086 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1087
1088/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1089static const char * const rt5677_stereo_adc2_src[] = {
1090 "DD MIX1", "DMIC", "Stereo DAC MIX"
1091};
1092
1093static SOC_ENUM_SINGLE_DECL(
1094 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1095 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1096
1097static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1098 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1099
1100static SOC_ENUM_SINGLE_DECL(
1101 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1102 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1103
1104static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1105 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1106
1107static SOC_ENUM_SINGLE_DECL(
1108 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1109 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1110
1111static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1112 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1113
1114/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1115static const char * const rt5677_dmic_src[] = {
1116 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1117};
1118
1119static SOC_ENUM_SINGLE_DECL(
1120 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1121 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1122
1123static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1124 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1125
1126static SOC_ENUM_SINGLE_DECL(
1127 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1128 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1129
1130static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1131 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1132
1133static SOC_ENUM_SINGLE_DECL(
1134 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1135 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1136
1137static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1138 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1139
1140static SOC_ENUM_SINGLE_DECL(
1141 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1142 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1143
1144static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1145 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1146
1147static SOC_ENUM_SINGLE_DECL(
1148 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1149 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1150
1151static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1152 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1153
1154static SOC_ENUM_SINGLE_DECL(
1155 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1156 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1157
1158static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1159 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1160
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1161/* Stereo2 ADC Source */ /* MX-26 [0] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1162static const char * const rt5677_stereo2_adc_lr_src[] = {
1163 "L", "LR"
1164};
1165
1166static SOC_ENUM_SINGLE_DECL(
1167 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1168 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1169
1170static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1171 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1172
1173/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1174static const char * const rt5677_stereo_adc1_src[] = {
1175 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1176};
1177
1178static SOC_ENUM_SINGLE_DECL(
1179 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1180 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1181
1182static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1183 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1184
1185static SOC_ENUM_SINGLE_DECL(
1186 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1187 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1188
1189static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1190 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1191
1192static SOC_ENUM_SINGLE_DECL(
1193 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1194 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1195
1196static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1197 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1198
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1199/* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1200static const char * const rt5677_mono_adc2_l_src[] = {
1201 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1202};
1203
1204static SOC_ENUM_SINGLE_DECL(
1205 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1206 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1207
1208static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1209 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1210
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1211/* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1212static const char * const rt5677_mono_adc1_l_src[] = {
1213 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1214};
1215
1216static SOC_ENUM_SINGLE_DECL(
1217 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1218 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1219
1220static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1221 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1222
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1223/* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1224static const char * const rt5677_mono_adc2_r_src[] = {
1225 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1226};
1227
1228static SOC_ENUM_SINGLE_DECL(
1229 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1230 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1231
1232static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1233 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1234
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1235/* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1236static const char * const rt5677_mono_adc1_r_src[] = {
1237 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1238};
1239
1240static SOC_ENUM_SINGLE_DECL(
1241 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1242 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1243
1244static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1245 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1246
1247/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1248static const char * const rt5677_stereo4_adc2_src[] = {
1249 "DD MIX1", "DMIC", "DD MIX2"
1250};
1251
1252static SOC_ENUM_SINGLE_DECL(
1253 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1254 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1255
1256static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1257 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1258
1259
1260/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1261static const char * const rt5677_stereo4_adc1_src[] = {
1262 "DD MIX1", "ADC1/2", "DD MIX2"
1263};
1264
1265static SOC_ENUM_SINGLE_DECL(
1266 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1267 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1268
1269static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1270 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1271
1272/* InBound0/1 Source */ /* MX-A3 [14:12] */
1273static const char * const rt5677_inbound01_src[] = {
1274 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1275 "VAD ADC/DAC1 FS"
1276};
1277
1278static SOC_ENUM_SINGLE_DECL(
1279 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1280 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1281
1282static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1283 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1284
1285/* InBound2/3 Source */ /* MX-A3 [10:8] */
1286static const char * const rt5677_inbound23_src[] = {
1287 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1288 "DAC1 FS", "IF4 DAC"
1289};
1290
1291static SOC_ENUM_SINGLE_DECL(
1292 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1293 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1294
1295static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1296 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1297
1298/* InBound4/5 Source */ /* MX-A3 [6:4] */
1299static const char * const rt5677_inbound45_src[] = {
1300 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1301 "IF3 DAC"
1302};
1303
1304static SOC_ENUM_SINGLE_DECL(
1305 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1306 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1307
1308static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1309 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1310
1311/* InBound6 Source */ /* MX-A3 [2:0] */
1312static const char * const rt5677_inbound6_src[] = {
1313 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1314 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1315};
1316
1317static SOC_ENUM_SINGLE_DECL(
1318 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1319 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1320
1321static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1322 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1323
1324/* InBound7 Source */ /* MX-A4 [14:12] */
1325static const char * const rt5677_inbound7_src[] = {
1326 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1327 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1328};
1329
1330static SOC_ENUM_SINGLE_DECL(
1331 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1332 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1333
1334static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1335 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1336
1337/* InBound8 Source */ /* MX-A4 [10:8] */
1338static const char * const rt5677_inbound8_src[] = {
1339 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1340 "MONO ADC MIX L", "DACL1 FS"
1341};
1342
1343static SOC_ENUM_SINGLE_DECL(
1344 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1345 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1346
1347static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1348 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1349
1350/* InBound9 Source */ /* MX-A4 [6:4] */
1351static const char * const rt5677_inbound9_src[] = {
1352 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1353 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1354};
1355
1356static SOC_ENUM_SINGLE_DECL(
1357 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1358 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1359
1360static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1361 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1362
1363/* VAD Source */ /* MX-9F [6:4] */
1364static const char * const rt5677_vad_src[] = {
1365 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1366 "STO3 ADC MIX L"
1367};
1368
1369static SOC_ENUM_SINGLE_DECL(
1370 rt5677_vad_enum, RT5677_VAD_CTRL4,
1371 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1372
1373static const struct snd_kcontrol_new rt5677_vad_src_mux =
1374 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1375
1376/* Sidetone Source */ /* MX-13 [11:9] */
1377static const char * const rt5677_sidetone_src[] = {
1378 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1379};
1380
1381static SOC_ENUM_SINGLE_DECL(
1382 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1383 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1384
1385static const struct snd_kcontrol_new rt5677_sidetone_mux =
1386 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1387
1388/* DAC1/2 Source */ /* MX-15 [1:0] */
1389static const char * const rt5677_dac12_src[] = {
1390 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1391};
1392
1393static SOC_ENUM_SINGLE_DECL(
1394 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1395 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1396
1397static const struct snd_kcontrol_new rt5677_dac12_mux =
1398 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1399
1400/* DAC3 Source */ /* MX-15 [5:4] */
1401static const char * const rt5677_dac3_src[] = {
1402 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1403};
1404
1405static SOC_ENUM_SINGLE_DECL(
1406 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1407 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1408
1409static const struct snd_kcontrol_new rt5677_dac3_mux =
1410 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1411
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1412/* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1413static const char * const rt5677_pdm_src[] = {
1414 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1415};
1416
1417static SOC_ENUM_SINGLE_DECL(
1418 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1419 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1420
1421static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1422 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1423
1424static SOC_ENUM_SINGLE_DECL(
1425 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1426 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1427
1428static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1429 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1430
1431static SOC_ENUM_SINGLE_DECL(
1432 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1433 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1434
1435static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1436 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1437
1438static SOC_ENUM_SINGLE_DECL(
1439 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1440 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1441
1442static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1443 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1444
1445/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0]*/
1446static const char * const rt5677_if12_adc1_src[] = {
1447 "STO1 ADC MIX", "OB01", "VAD ADC"
1448};
1449
1450static SOC_ENUM_SINGLE_DECL(
1451 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
1452 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1453
1454static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1455 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1456
1457static SOC_ENUM_SINGLE_DECL(
1458 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1459 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1460
1461static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1462 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1463
1464static SOC_ENUM_SINGLE_DECL(
1465 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1466 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
1467
1468static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1469 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1470
1471/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
1472static const char * const rt5677_if12_adc2_src[] = {
1473 "STO2 ADC MIX", "OB23"
1474};
1475
1476static SOC_ENUM_SINGLE_DECL(
1477 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
1478 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
1479
1480static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1481 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1482
1483static SOC_ENUM_SINGLE_DECL(
1484 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
1485 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
1486
1487static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1488 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1489
1490static SOC_ENUM_SINGLE_DECL(
1491 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
1492 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
1493
1494static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1495 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1496
1497/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
1498static const char * const rt5677_if12_adc3_src[] = {
1499 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
1500};
1501
1502static SOC_ENUM_SINGLE_DECL(
1503 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
1504 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
1505
1506static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1507 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1508
1509static SOC_ENUM_SINGLE_DECL(
1510 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
1511 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
1512
1513static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1514 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1515
1516static SOC_ENUM_SINGLE_DECL(
1517 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
1518 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
1519
1520static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1521 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1522
1523/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
1524static const char * const rt5677_if12_adc4_src[] = {
1525 "STO4 ADC MIX", "OB67", "OB01"
1526};
1527
1528static SOC_ENUM_SINGLE_DECL(
1529 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
1530 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
1531
1532static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1533 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1534
1535static SOC_ENUM_SINGLE_DECL(
1536 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
1537 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
1538
1539static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1540 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1541
1542static SOC_ENUM_SINGLE_DECL(
1543 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
1544 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
1545
1546static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1547 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1548
1549/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4]*/
1550static const char * const rt5677_if34_adc_src[] = {
1551 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
1552 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
1553};
1554
1555static SOC_ENUM_SINGLE_DECL(
1556 rt5677_if3_adc_enum, RT5677_IF3_DATA,
1557 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
1558
1559static const struct snd_kcontrol_new rt5677_if3_adc_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1560 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1561
1562static SOC_ENUM_SINGLE_DECL(
1563 rt5677_if4_adc_enum, RT5677_IF4_DATA,
1564 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
1565
1566static const struct snd_kcontrol_new rt5677_if4_adc_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1567 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1568
1569static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
1570 struct snd_kcontrol *kcontrol, int event)
1571{
1572 struct snd_soc_codec *codec = w->codec;
1573 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1574
1575 switch (event) {
1576 case SND_SOC_DAPM_POST_PMU:
1577 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1578 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
1579 break;
1580
1581 case SND_SOC_DAPM_PRE_PMD:
1582 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1583 RT5677_PWR_BST1_P, 0);
1584 break;
1585
1586 default:
1587 return 0;
1588 }
1589
1590 return 0;
1591}
1592
1593static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
1594 struct snd_kcontrol *kcontrol, int event)
1595{
1596 struct snd_soc_codec *codec = w->codec;
1597 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1598
1599 switch (event) {
1600 case SND_SOC_DAPM_POST_PMU:
1601 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1602 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
1603 break;
1604
1605 case SND_SOC_DAPM_PRE_PMD:
1606 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1607 RT5677_PWR_BST2_P, 0);
1608 break;
1609
1610 default:
1611 return 0;
1612 }
1613
1614 return 0;
1615}
1616
1617static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
1618 struct snd_kcontrol *kcontrol, int event)
1619{
1620 struct snd_soc_codec *codec = w->codec;
1621 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1622
1623 switch (event) {
1624 case SND_SOC_DAPM_POST_PMU:
1625 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
1626 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
1627 break;
1628 default:
1629 return 0;
1630 }
1631
1632 return 0;
1633}
1634
1635static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
1636 struct snd_kcontrol *kcontrol, int event)
1637{
1638 struct snd_soc_codec *codec = w->codec;
1639 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1640
1641 switch (event) {
1642 case SND_SOC_DAPM_POST_PMU:
1643 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
1644 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
1645 break;
1646 default:
1647 return 0;
1648 }
1649
1650 return 0;
1651}
1652
1653static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
1654 struct snd_kcontrol *kcontrol, int event)
1655{
1656 struct snd_soc_codec *codec = w->codec;
1657 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1658
1659 switch (event) {
1660 case SND_SOC_DAPM_POST_PMU:
1661 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1662 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
1663 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
1664 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
1665 break;
Oder Chiouf58c3b92014-06-10 14:35:26 +0800[diff] [blame]1666
1667 case SND_SOC_DAPM_PRE_PMD:
1668 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1669 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
1670 RT5677_PWR_CLK_MB, 0);
1671 break;
1672
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1673 default:
1674 return 0;
1675 }
1676
1677 return 0;
1678}
1679
1680static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
1681 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
1682 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU),
1683 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
1684 0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU),
1685
1686 /* Input Side */
1687 /* micbias */
Oder Chiou3d0c03d2014-06-10 14:35:23 +0800[diff] [blame]1688 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
Oder Chiouf58c3b92014-06-10 14:35:26 +0800[diff] [blame]1689 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
1690 SND_SOC_DAPM_POST_PMU),
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1691
1692 /* Input Lines */
1693 SND_SOC_DAPM_INPUT("DMIC L1"),
1694 SND_SOC_DAPM_INPUT("DMIC R1"),
1695 SND_SOC_DAPM_INPUT("DMIC L2"),
1696 SND_SOC_DAPM_INPUT("DMIC R2"),
1697 SND_SOC_DAPM_INPUT("DMIC L3"),
1698 SND_SOC_DAPM_INPUT("DMIC R3"),
1699 SND_SOC_DAPM_INPUT("DMIC L4"),
1700 SND_SOC_DAPM_INPUT("DMIC R4"),
1701
1702 SND_SOC_DAPM_INPUT("IN1P"),
1703 SND_SOC_DAPM_INPUT("IN1N"),
1704 SND_SOC_DAPM_INPUT("IN2P"),
1705 SND_SOC_DAPM_INPUT("IN2N"),
1706
1707 SND_SOC_DAPM_INPUT("Haptic Generator"),
1708
Bard Liao2d15d972014-08-27 19:50:34 +0800[diff] [blame]1709 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1710 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1711 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1712 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1713
1714 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
1715 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
1716 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
1717 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
1718 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
1719 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
1720 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
1721 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1722
1723 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1724 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1725
1726 /* Boost */
1727 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
1728 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
1729 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1730 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
1731 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
1732 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1733
1734 /* ADCs */
1735 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
1736 0, 0),
1737 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
1738 0, 0),
1739 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
1740
1741 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
1742 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
1743 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
1744 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
1745 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
1746 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
1747 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
1748 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
1749
1750 /* ADC Mux */
1751 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1752 &rt5677_sto1_dmic_mux),
1753 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1754 &rt5677_sto1_adc1_mux),
1755 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1756 &rt5677_sto1_adc2_mux),
1757 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
1758 &rt5677_sto2_dmic_mux),
1759 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1760 &rt5677_sto2_adc1_mux),
1761 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1762 &rt5677_sto2_adc2_mux),
1763 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
1764 &rt5677_sto2_adc_lr_mux),
1765 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
1766 &rt5677_sto3_dmic_mux),
1767 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1768 &rt5677_sto3_adc1_mux),
1769 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1770 &rt5677_sto3_adc2_mux),
1771 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
1772 &rt5677_sto4_dmic_mux),
1773 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1774 &rt5677_sto4_adc1_mux),
1775 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1776 &rt5677_sto4_adc2_mux),
1777 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1778 &rt5677_mono_dmic_l_mux),
1779 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1780 &rt5677_mono_dmic_r_mux),
1781 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
1782 &rt5677_mono_adc2_l_mux),
1783 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
1784 &rt5677_mono_adc1_l_mux),
1785 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
1786 &rt5677_mono_adc1_r_mux),
1787 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
1788 &rt5677_mono_adc2_r_mux),
1789
1790 /* ADC Mixer */
1791 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
1792 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
1793 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
1794 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
1795 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
1796 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
1797 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
1798 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
1799 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1800 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
1801 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1802 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
1803 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
1804 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
1805 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
1806 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
1807 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
1808 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
1809 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
1810 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
1811 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
1812 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
1813 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
1814 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
1815 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
1816 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1817 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1818 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
1819 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
1820 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1821 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1822 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
1823
1824 /* ADC PGA */
1825 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1826 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1827 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1828 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1829 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1830 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1831 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1832 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1833 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1834 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1835 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1836 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1837 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1838 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1839 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1840 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1841 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1842 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1843
1844 /* DSP */
1845 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
1846 &rt5677_ib9_src_mux),
1847 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
1848 &rt5677_ib8_src_mux),
1849 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
1850 &rt5677_ib7_src_mux),
1851 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
1852 &rt5677_ib6_src_mux),
1853 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
1854 &rt5677_ib45_src_mux),
1855 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
1856 &rt5677_ib23_src_mux),
1857 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
1858 &rt5677_ib01_src_mux),
1859 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
1860 &rt5677_ib45_bypass_src_mux),
1861 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
1862 &rt5677_ib23_bypass_src_mux),
1863 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
1864 &rt5677_ib01_bypass_src_mux),
1865 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
1866 &rt5677_ob23_bypass_src_mux),
1867 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
1868 &rt5677_ob01_bypass_src_mux),
1869
1870 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
1871 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
1872
1873 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
1874 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
1875 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
1876 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
1877 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
1878 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
1879
1880 /* Digital Interface */
1881 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
1882 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
1883 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1884 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1885 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1886 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1887 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1888 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1889 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1890 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1891 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1892 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1893 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1894 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1895 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1896 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1897 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1898 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1899
1900 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
1901 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
1902 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1903 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1904 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1905 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1906 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1907 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1908 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1909 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1910 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1911 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1912 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1913 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1914 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1915 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1916 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1917 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1918
1919 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
1920 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
1921 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1922 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1923 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1924 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1925 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1926 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1927
1928 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
1929 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
1930 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1931 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1932 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1933 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1934 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1935 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1936
1937 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
1938 RT5677_PWR_SLB_BIT, 0, NULL, 0),
1939 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1940 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1941 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1942 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1943 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1944 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1945 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1946 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1947 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1948 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1949 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1950 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1951 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1952 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1953 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1954 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1955
1956 /* Digital Interface Select */
1957 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1958 &rt5677_if1_adc1_mux),
1959 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1960 &rt5677_if1_adc2_mux),
1961 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
1962 &rt5677_if1_adc3_mux),
1963 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
1964 &rt5677_if1_adc4_mux),
1965 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1966 &rt5677_if2_adc1_mux),
1967 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1968 &rt5677_if2_adc2_mux),
1969 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
1970 &rt5677_if2_adc3_mux),
1971 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
1972 &rt5677_if2_adc4_mux),
1973 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
1974 &rt5677_if3_adc_mux),
1975 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
1976 &rt5677_if4_adc_mux),
1977 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
1978 &rt5677_slb_adc1_mux),
1979 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
1980 &rt5677_slb_adc2_mux),
1981 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
1982 &rt5677_slb_adc3_mux),
1983 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
1984 &rt5677_slb_adc4_mux),
1985
1986 /* Audio Interface */
1987 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1988 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1989 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1990 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1991 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1992 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1993 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
1994 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
1995 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
1996 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
1997
1998 /* Sidetone Mux */
1999 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
2000 &rt5677_sidetone_mux),
Oder Chiou90bdbb42014-09-18 14:45:59 +0800[diff] [blame^]2001 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
2002 RT5677_ST_EN_SFT, 0, NULL, 0),
2003
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2004 /* VAD Mux*/
2005 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
2006 &rt5677_vad_src_mux),
2007
2008 /* Tensilica DSP */
2009 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2010 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2011 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2012 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2013 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2014 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2015 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2016 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2017 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2018 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2019 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2020 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2021 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2022
2023 /* Output Side */
2024 /* DAC mixer before sound effect */
2025 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2026 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2027 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2028 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2029 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2030
2031 /* DAC Mux */
2032 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2033 &rt5677_dac1_mux),
2034 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2035 &rt5677_adda1_mux),
2036 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2037 &rt5677_dac12_mux),
2038 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2039 &rt5677_dac3_mux),
2040
2041 /* DAC2 channel Mux */
2042 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2043 &rt5677_dac2_l_mux),
2044 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2045 &rt5677_dac2_r_mux),
2046
2047 /* DAC3 channel Mux */
2048 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2049 &rt5677_dac3_l_mux),
2050 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2051 &rt5677_dac3_r_mux),
2052
2053 /* DAC4 channel Mux */
2054 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2055 &rt5677_dac4_l_mux),
2056 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2057 &rt5677_dac4_r_mux),
2058
2059 /* DAC Mixer */
2060 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
2061 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
2062 SND_SOC_DAPM_SUPPLY("dac mono left filter", RT5677_PWR_DIG2,
2063 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
2064 SND_SOC_DAPM_SUPPLY("dac mono right filter", RT5677_PWR_DIG2,
2065 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
2066
2067 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2068 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
2069 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2070 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
2071 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2072 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
2073 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2074 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
2075 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
2076 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
2077 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
2078 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
2079 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
2080 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
2081 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
2082 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
2083 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2084 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2085 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2086 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2087
2088 /* DACs */
2089 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
2090 RT5677_PWR_DAC1_BIT, 0),
2091 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
2092 RT5677_PWR_DAC2_BIT, 0),
2093 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
2094 RT5677_PWR_DAC3_BIT, 0),
2095
2096 /* PDM */
2097 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
2098 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
2099 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
2100 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
2101
2102 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
2103 1, &rt5677_pdm1_l_mux),
2104 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
2105 1, &rt5677_pdm1_r_mux),
2106 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
2107 1, &rt5677_pdm2_l_mux),
2108 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
2109 1, &rt5677_pdm2_r_mux),
2110
2111 SND_SOC_DAPM_PGA_S("LOUT1 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
2112 0, NULL, 0),
2113 SND_SOC_DAPM_PGA_S("LOUT2 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
2114 0, NULL, 0),
2115 SND_SOC_DAPM_PGA_S("LOUT3 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
2116 0, NULL, 0),
2117
2118 /* Output Lines */
2119 SND_SOC_DAPM_OUTPUT("LOUT1"),
2120 SND_SOC_DAPM_OUTPUT("LOUT2"),
2121 SND_SOC_DAPM_OUTPUT("LOUT3"),
2122 SND_SOC_DAPM_OUTPUT("PDM1L"),
2123 SND_SOC_DAPM_OUTPUT("PDM1R"),
2124 SND_SOC_DAPM_OUTPUT("PDM2L"),
2125 SND_SOC_DAPM_OUTPUT("PDM2R"),
2126};
2127
2128static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2129 { "DMIC1", NULL, "DMIC L1" },
2130 { "DMIC1", NULL, "DMIC R1" },
2131 { "DMIC2", NULL, "DMIC L2" },
2132 { "DMIC2", NULL, "DMIC R2" },
2133 { "DMIC3", NULL, "DMIC L3" },
2134 { "DMIC3", NULL, "DMIC R3" },
2135 { "DMIC4", NULL, "DMIC L4" },
2136 { "DMIC4", NULL, "DMIC R4" },
2137
2138 { "DMIC L1", NULL, "DMIC CLK" },
2139 { "DMIC R1", NULL, "DMIC CLK" },
2140 { "DMIC L2", NULL, "DMIC CLK" },
2141 { "DMIC R2", NULL, "DMIC CLK" },
2142 { "DMIC L3", NULL, "DMIC CLK" },
2143 { "DMIC R3", NULL, "DMIC CLK" },
2144 { "DMIC L4", NULL, "DMIC CLK" },
2145 { "DMIC R4", NULL, "DMIC CLK" },
2146
Bard Liao2d15d972014-08-27 19:50:34 +0800[diff] [blame]2147 { "DMIC L1", NULL, "DMIC1 power" },
2148 { "DMIC R1", NULL, "DMIC1 power" },
2149 { "DMIC L3", NULL, "DMIC3 power" },
2150 { "DMIC R3", NULL, "DMIC3 power" },
2151 { "DMIC L4", NULL, "DMIC4 power" },
2152 { "DMIC R4", NULL, "DMIC4 power" },
2153
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2154 { "BST1", NULL, "IN1P" },
2155 { "BST1", NULL, "IN1N" },
2156 { "BST2", NULL, "IN2P" },
2157 { "BST2", NULL, "IN2N" },
2158
2159 { "IN1P", NULL, "micbias1" },
2160 { "IN1N", NULL, "micbias1" },
2161 { "IN2P", NULL, "micbias1" },
2162 { "IN2N", NULL, "micbias1" },
2163
2164 { "ADC 1", NULL, "BST1" },
2165 { "ADC 1", NULL, "ADC 1 power" },
2166 { "ADC 1", NULL, "ADC1 clock" },
2167 { "ADC 2", NULL, "BST2" },
2168 { "ADC 2", NULL, "ADC 2 power" },
2169 { "ADC 2", NULL, "ADC2 clock" },
2170
2171 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2172 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2173 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
2174 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
2175
2176 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
2177 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
2178 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
2179 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
2180
2181 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
2182 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
2183 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
2184 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
2185
2186 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
2187 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
2188 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
2189 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
2190
2191 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
2192 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
2193 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
2194 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
2195
2196 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
2197 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
2198 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
2199 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
2200
2201 { "ADC 1_2", NULL, "ADC 1" },
2202 { "ADC 1_2", NULL, "ADC 2" },
2203
2204 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2205 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2206 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2207
2208 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2209 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2210 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2211
2212 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2213 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2214 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2215
2216 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2217 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2218 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2219
2220 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2221 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2222 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2223
2224 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2225 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2226 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2227
2228 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2229 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2230 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
2231
2232 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2233 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2234 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
2235
2236 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
2237 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
2238 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2239
2240 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
2241 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
2242 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2243
2244 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
2245 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
2246 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2247
2248 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
2249 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
2250 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2251
2252 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2253 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2254 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2255 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2256
2257 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2258 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2259 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2260
2261 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2262 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2263 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2264
2265 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
2266 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
2267
2268 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2269 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2270 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2271 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2272
2273 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
2274 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
2275
2276 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
2277 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
2278
2279 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
2280 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
2281 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2282
2283 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
2284 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
2285 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2286
2287 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
2288 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
2289
2290 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2291 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2292 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2293 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2294
2295 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
2296 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
2297 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2298
2299 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
2300 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
2301 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2302
2303 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
2304 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
2305
2306 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2307 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2308 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2309 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2310
2311 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
2312 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
2313 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2314
2315 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
2316 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
2317 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2318
2319 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
2320 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
2321
2322 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
2323 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
2324 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2325 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2326
2327 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
2328 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
2329 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2330 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2331
2332 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
2333 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
2334
2335 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2336 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2337 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2338 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2339 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2340
2341 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2342 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2343 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2344
2345 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2346 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2347
2348 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2349 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2350 { "IF1 ADC3 Mux", "OB45", "OB45" },
2351
2352 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2353 { "IF1 ADC4 Mux", "OB67", "OB67" },
2354 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2355
2356 { "AIF1TX", NULL, "I2S1" },
2357 { "AIF1TX", NULL, "IF1 ADC1 Mux" },
2358 { "AIF1TX", NULL, "IF1 ADC2 Mux" },
2359 { "AIF1TX", NULL, "IF1 ADC3 Mux" },
2360 { "AIF1TX", NULL, "IF1 ADC4 Mux" },
2361
2362 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2363 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2364 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2365
2366 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2367 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2368
2369 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2370 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2371 { "IF2 ADC3 Mux", "OB45", "OB45" },
2372
2373 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2374 { "IF2 ADC4 Mux", "OB67", "OB67" },
2375 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2376
2377 { "AIF2TX", NULL, "I2S2" },
2378 { "AIF2TX", NULL, "IF2 ADC1 Mux" },
2379 { "AIF2TX", NULL, "IF2 ADC2 Mux" },
2380 { "AIF2TX", NULL, "IF2 ADC3 Mux" },
2381 { "AIF2TX", NULL, "IF2 ADC4 Mux" },
2382
2383 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2384 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2385 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2386 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2387 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2388 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
2389 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
2390 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2391
2392 { "AIF3TX", NULL, "I2S3" },
2393 { "AIF3TX", NULL, "IF3 ADC Mux" },
2394
2395 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2396 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2397 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2398 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2399 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2400 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
2401 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
2402 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2403
2404 { "AIF4TX", NULL, "I2S4" },
2405 { "AIF4TX", NULL, "IF4 ADC Mux" },
2406
2407 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2408 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2409 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2410
2411 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2412 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2413
2414 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2415 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2416 { "SLB ADC3 Mux", "OB45", "OB45" },
2417
2418 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2419 { "SLB ADC4 Mux", "OB67", "OB67" },
2420 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2421
2422 { "SLBTX", NULL, "SLB" },
2423 { "SLBTX", NULL, "SLB ADC1 Mux" },
2424 { "SLBTX", NULL, "SLB ADC2 Mux" },
2425 { "SLBTX", NULL, "SLB ADC3 Mux" },
2426 { "SLBTX", NULL, "SLB ADC4 Mux" },
2427
2428 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
2429 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
2430 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
2431 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2432 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
2433
2434 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
2435 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
2436
2437 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
2438 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
2439 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
2440 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2441 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
2442 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
2443
2444 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
2445 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
2446
2447 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
2448 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
2449 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
2450 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2451 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
2452
2453 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
2454 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
2455
2456 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" },
2457 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" },
2458 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
2459 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2460 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
2461 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2462 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2463 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2464
2465 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" },
2466 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" },
2467 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
2468 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2469 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
2470 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2471 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2472 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2473
2474 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2475 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2476 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2477 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2478 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2479 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
2480
2481 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2482 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2483 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2484 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2485 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2486 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
2487 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
2488
2489 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2490 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2491 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2492 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
2493 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
2494 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
2495 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
2496
2497 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2498 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2499 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2500 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
2501 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
2502 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
2503 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
2504
2505 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2506 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2507 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2508 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
2509 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
2510 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
2511 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
2512
2513 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2514 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2515 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2516 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
2517 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
2518 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
2519 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
2520
2521 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2522 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2523 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2524 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
2525 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
2526 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
2527 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
2528
2529 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2530 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2531 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2532 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
2533 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
2534 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
2535 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
2536
2537 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
2538 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
2539 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
2540 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
2541
2542 { "OutBound2", NULL, "OB23 Bypass Mux" },
2543 { "OutBound3", NULL, "OB23 Bypass Mux" },
2544 { "OutBound4", NULL, "OB4 MIX" },
2545 { "OutBound5", NULL, "OB5 MIX" },
2546 { "OutBound6", NULL, "OB6 MIX" },
2547 { "OutBound7", NULL, "OB7 MIX" },
2548
2549 { "OB45", NULL, "OutBound4" },
2550 { "OB45", NULL, "OutBound5" },
2551 { "OB67", NULL, "OutBound6" },
2552 { "OB67", NULL, "OutBound7" },
2553
2554 { "IF1 DAC0", NULL, "AIF1RX" },
2555 { "IF1 DAC1", NULL, "AIF1RX" },
2556 { "IF1 DAC2", NULL, "AIF1RX" },
2557 { "IF1 DAC3", NULL, "AIF1RX" },
2558 { "IF1 DAC4", NULL, "AIF1RX" },
2559 { "IF1 DAC5", NULL, "AIF1RX" },
2560 { "IF1 DAC6", NULL, "AIF1RX" },
2561 { "IF1 DAC7", NULL, "AIF1RX" },
2562 { "IF1 DAC0", NULL, "I2S1" },
2563 { "IF1 DAC1", NULL, "I2S1" },
2564 { "IF1 DAC2", NULL, "I2S1" },
2565 { "IF1 DAC3", NULL, "I2S1" },
2566 { "IF1 DAC4", NULL, "I2S1" },
2567 { "IF1 DAC5", NULL, "I2S1" },
2568 { "IF1 DAC6", NULL, "I2S1" },
2569 { "IF1 DAC7", NULL, "I2S1" },
2570
2571 { "IF1 DAC01", NULL, "IF1 DAC0" },
2572 { "IF1 DAC01", NULL, "IF1 DAC1" },
2573 { "IF1 DAC23", NULL, "IF1 DAC2" },
2574 { "IF1 DAC23", NULL, "IF1 DAC3" },
2575 { "IF1 DAC45", NULL, "IF1 DAC4" },
2576 { "IF1 DAC45", NULL, "IF1 DAC5" },
2577 { "IF1 DAC67", NULL, "IF1 DAC6" },
2578 { "IF1 DAC67", NULL, "IF1 DAC7" },
2579
2580 { "IF2 DAC0", NULL, "AIF2RX" },
2581 { "IF2 DAC1", NULL, "AIF2RX" },
2582 { "IF2 DAC2", NULL, "AIF2RX" },
2583 { "IF2 DAC3", NULL, "AIF2RX" },
2584 { "IF2 DAC4", NULL, "AIF2RX" },
2585 { "IF2 DAC5", NULL, "AIF2RX" },
2586 { "IF2 DAC6", NULL, "AIF2RX" },
2587 { "IF2 DAC7", NULL, "AIF2RX" },
2588 { "IF2 DAC0", NULL, "I2S2" },
2589 { "IF2 DAC1", NULL, "I2S2" },
2590 { "IF2 DAC2", NULL, "I2S2" },
2591 { "IF2 DAC3", NULL, "I2S2" },
2592 { "IF2 DAC4", NULL, "I2S2" },
2593 { "IF2 DAC5", NULL, "I2S2" },
2594 { "IF2 DAC6", NULL, "I2S2" },
2595 { "IF2 DAC7", NULL, "I2S2" },
2596
2597 { "IF2 DAC01", NULL, "IF2 DAC0" },
2598 { "IF2 DAC01", NULL, "IF2 DAC1" },
2599 { "IF2 DAC23", NULL, "IF2 DAC2" },
2600 { "IF2 DAC23", NULL, "IF2 DAC3" },
2601 { "IF2 DAC45", NULL, "IF2 DAC4" },
2602 { "IF2 DAC45", NULL, "IF2 DAC5" },
2603 { "IF2 DAC67", NULL, "IF2 DAC6" },
2604 { "IF2 DAC67", NULL, "IF2 DAC7" },
2605
2606 { "IF3 DAC", NULL, "AIF3RX" },
2607 { "IF3 DAC", NULL, "I2S3" },
2608
2609 { "IF4 DAC", NULL, "AIF4RX" },
2610 { "IF4 DAC", NULL, "I2S4" },
2611
2612 { "IF3 DAC L", NULL, "IF3 DAC" },
2613 { "IF3 DAC R", NULL, "IF3 DAC" },
2614
2615 { "IF4 DAC L", NULL, "IF4 DAC" },
2616 { "IF4 DAC R", NULL, "IF4 DAC" },
2617
2618 { "SLB DAC0", NULL, "SLBRX" },
2619 { "SLB DAC1", NULL, "SLBRX" },
2620 { "SLB DAC2", NULL, "SLBRX" },
2621 { "SLB DAC3", NULL, "SLBRX" },
2622 { "SLB DAC4", NULL, "SLBRX" },
2623 { "SLB DAC5", NULL, "SLBRX" },
2624 { "SLB DAC6", NULL, "SLBRX" },
2625 { "SLB DAC7", NULL, "SLBRX" },
2626 { "SLB DAC0", NULL, "SLB" },
2627 { "SLB DAC1", NULL, "SLB" },
2628 { "SLB DAC2", NULL, "SLB" },
2629 { "SLB DAC3", NULL, "SLB" },
2630 { "SLB DAC4", NULL, "SLB" },
2631 { "SLB DAC5", NULL, "SLB" },
2632 { "SLB DAC6", NULL, "SLB" },
2633 { "SLB DAC7", NULL, "SLB" },
2634
2635 { "SLB DAC01", NULL, "SLB DAC0" },
2636 { "SLB DAC01", NULL, "SLB DAC1" },
2637 { "SLB DAC23", NULL, "SLB DAC2" },
2638 { "SLB DAC23", NULL, "SLB DAC3" },
2639 { "SLB DAC45", NULL, "SLB DAC4" },
2640 { "SLB DAC45", NULL, "SLB DAC5" },
2641 { "SLB DAC67", NULL, "SLB DAC6" },
2642 { "SLB DAC67", NULL, "SLB DAC7" },
2643
2644 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2645 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2646 { "ADDA1 Mux", "OB 67", "OB67" },
2647
2648 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
2649 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
2650 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
2651 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
2652 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
2653 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
2654
2655 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
2656 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
2657 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2658 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
2659 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
2660 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2661
2662 { "DAC1 FS", NULL, "DAC1 MIXL" },
2663 { "DAC1 FS", NULL, "DAC1 MIXR" },
2664
2665 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" },
2666 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" },
2667 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
2668 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
2669 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
2670 { "DAC2 L Mux", "OB 2", "OutBound2" },
2671
2672 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" },
2673 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" },
2674 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
2675 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
2676 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
2677 { "DAC2 R Mux", "OB 3", "OutBound3" },
2678 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
2679 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
2680
2681 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" },
2682 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" },
2683 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
2684 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
2685 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
2686 { "DAC3 L Mux", "OB 4", "OutBound4" },
2687
2688 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" },
2689 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" },
2690 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
2691 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
2692 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
2693 { "DAC3 R Mux", "OB 5", "OutBound5" },
2694
2695 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" },
2696 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" },
2697 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
2698 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
2699 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
2700 { "DAC4 L Mux", "OB 6", "OutBound6" },
2701
2702 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" },
2703 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" },
2704 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
2705 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
2706 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
2707 { "DAC4 R Mux", "OB 7", "OutBound7" },
2708
2709 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
2710 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
2711 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
2712 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
2713 { "Sidetone Mux", "ADC1", "ADC 1" },
2714 { "Sidetone Mux", "ADC2", "ADC 2" },
Oder Chiou90bdbb42014-09-18 14:45:59 +0800[diff] [blame^]2715 { "Sidetone Mux", NULL, "Sidetone Power" },
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2716
2717 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
2718 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
2719 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
2720 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
2721 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2722 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
2723 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
2724 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
2725 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
2726 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2727
2728 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
2729 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
2730 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
2731 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
2732 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2733 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
2734 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
2735 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
2736 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
2737 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2738
2739 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2740 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
2741 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
2742 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
2743 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2744 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
2745 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
2746 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
2747
2748 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2749 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
2750 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
2751 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
2752 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2753 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
2754 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
2755 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
2756
2757 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
2758 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
2759 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
2760 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
2761 { "DD1 MIX", NULL, "DD1 MIXL" },
2762 { "DD1 MIX", NULL, "DD1 MIXR" },
2763 { "DD2 MIX", NULL, "DD2 MIXL" },
2764 { "DD2 MIX", NULL, "DD2 MIXR" },
2765
2766 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
2767 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
2768 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
2769 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
2770
2771 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2772 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2773 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
2774 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
2775
2776 { "DAC 1", NULL, "DAC12 SRC Mux" },
2777 { "DAC 1", NULL, "PLL1", is_sys_clk_from_pll },
2778 { "DAC 2", NULL, "DAC12 SRC Mux" },
2779 { "DAC 2", NULL, "PLL1", is_sys_clk_from_pll },
2780 { "DAC 3", NULL, "DAC3 SRC Mux" },
2781 { "DAC 3", NULL, "PLL1", is_sys_clk_from_pll },
2782
2783 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
2784 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
2785 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
2786 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
2787 { "PDM1 L Mux", NULL, "PDM1 Power" },
2788 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
2789 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
2790 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
2791 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
2792 { "PDM1 R Mux", NULL, "PDM1 Power" },
2793 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
2794 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
2795 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
2796 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
2797 { "PDM2 L Mux", NULL, "PDM2 Power" },
2798 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
2799 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
2800 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
2801 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
2802 { "PDM2 R Mux", NULL, "PDM2 Power" },
2803
2804 { "LOUT1 amp", NULL, "DAC 1" },
2805 { "LOUT2 amp", NULL, "DAC 2" },
2806 { "LOUT3 amp", NULL, "DAC 3" },
2807
2808 { "LOUT1", NULL, "LOUT1 amp" },
2809 { "LOUT2", NULL, "LOUT2 amp" },
2810 { "LOUT3", NULL, "LOUT3 amp" },
2811
2812 { "PDM1L", NULL, "PDM1 L Mux" },
2813 { "PDM1R", NULL, "PDM1 R Mux" },
2814 { "PDM2L", NULL, "PDM2 L Mux" },
2815 { "PDM2R", NULL, "PDM2 R Mux" },
2816};
2817
Bard Liao2d15d972014-08-27 19:50:34 +0800[diff] [blame]2818static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
2819 { "DMIC L2", NULL, "DMIC1 power" },
2820 { "DMIC R2", NULL, "DMIC1 power" },
2821};
2822
2823static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
2824 { "DMIC L2", NULL, "DMIC2 power" },
2825 { "DMIC R2", NULL, "DMIC2 power" },
2826};
2827
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2828static int rt5677_hw_params(struct snd_pcm_substream *substream,
2829 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2830{
2831 struct snd_soc_codec *codec = dai->codec;
2832 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2833 unsigned int val_len = 0, val_clk, mask_clk;
2834 int pre_div, bclk_ms, frame_size;
2835
2836 rt5677->lrck[dai->id] = params_rate(params);
Axel Lin30f14b42014-06-10 08:57:36 +0800[diff] [blame]2837 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2838 if (pre_div < 0) {
2839 dev_err(codec->dev, "Unsupported clock setting\n");
2840 return -EINVAL;
2841 }
2842 frame_size = snd_soc_params_to_frame_size(params);
2843 if (frame_size < 0) {
2844 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2845 return -EINVAL;
2846 }
2847 bclk_ms = frame_size > 32;
2848 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
2849
2850 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2851 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
2852 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2853 bclk_ms, pre_div, dai->id);
2854
2855 switch (params_width(params)) {
2856 case 16:
2857 break;
2858 case 20:
2859 val_len |= RT5677_I2S_DL_20;
2860 break;
2861 case 24:
2862 val_len |= RT5677_I2S_DL_24;
2863 break;
2864 case 8:
2865 val_len |= RT5677_I2S_DL_8;
2866 break;
2867 default:
2868 return -EINVAL;
2869 }
2870
2871 switch (dai->id) {
2872 case RT5677_AIF1:
2873 mask_clk = RT5677_I2S_PD1_MASK;
2874 val_clk = pre_div << RT5677_I2S_PD1_SFT;
2875 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
2876 RT5677_I2S_DL_MASK, val_len);
2877 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2878 mask_clk, val_clk);
2879 break;
2880 case RT5677_AIF2:
2881 mask_clk = RT5677_I2S_PD2_MASK;
2882 val_clk = pre_div << RT5677_I2S_PD2_SFT;
2883 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
2884 RT5677_I2S_DL_MASK, val_len);
2885 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2886 mask_clk, val_clk);
2887 break;
2888 case RT5677_AIF3:
2889 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
2890 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
2891 pre_div << RT5677_I2S_PD3_SFT;
2892 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
2893 RT5677_I2S_DL_MASK, val_len);
2894 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2895 mask_clk, val_clk);
2896 break;
2897 case RT5677_AIF4:
2898 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
2899 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
2900 pre_div << RT5677_I2S_PD4_SFT;
2901 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
2902 RT5677_I2S_DL_MASK, val_len);
2903 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2904 mask_clk, val_clk);
2905 break;
2906 default:
2907 break;
2908 }
2909
2910 return 0;
2911}
2912
2913static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2914{
2915 struct snd_soc_codec *codec = dai->codec;
2916 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2917 unsigned int reg_val = 0;
2918
2919 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2920 case SND_SOC_DAIFMT_CBM_CFM:
2921 rt5677->master[dai->id] = 1;
2922 break;
2923 case SND_SOC_DAIFMT_CBS_CFS:
2924 reg_val |= RT5677_I2S_MS_S;
2925 rt5677->master[dai->id] = 0;
2926 break;
2927 default:
2928 return -EINVAL;
2929 }
2930
2931 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2932 case SND_SOC_DAIFMT_NB_NF:
2933 break;
2934 case SND_SOC_DAIFMT_IB_NF:
2935 reg_val |= RT5677_I2S_BP_INV;
2936 break;
2937 default:
2938 return -EINVAL;
2939 }
2940
2941 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2942 case SND_SOC_DAIFMT_I2S:
2943 break;
2944 case SND_SOC_DAIFMT_LEFT_J:
2945 reg_val |= RT5677_I2S_DF_LEFT;
2946 break;
2947 case SND_SOC_DAIFMT_DSP_A:
2948 reg_val |= RT5677_I2S_DF_PCM_A;
2949 break;
2950 case SND_SOC_DAIFMT_DSP_B:
2951 reg_val |= RT5677_I2S_DF_PCM_B;
2952 break;
2953 default:
2954 return -EINVAL;
2955 }
2956
2957 switch (dai->id) {
2958 case RT5677_AIF1:
2959 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
2960 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2961 RT5677_I2S_DF_MASK, reg_val);
2962 break;
2963 case RT5677_AIF2:
2964 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
2965 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2966 RT5677_I2S_DF_MASK, reg_val);
2967 break;
2968 case RT5677_AIF3:
2969 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
2970 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2971 RT5677_I2S_DF_MASK, reg_val);
2972 break;
2973 case RT5677_AIF4:
2974 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
2975 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2976 RT5677_I2S_DF_MASK, reg_val);
2977 break;
2978 default:
2979 break;
2980 }
2981
2982
2983 return 0;
2984}
2985
2986static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
2987 int clk_id, unsigned int freq, int dir)
2988{
2989 struct snd_soc_codec *codec = dai->codec;
2990 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2991 unsigned int reg_val = 0;
2992
2993 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
2994 return 0;
2995
2996 switch (clk_id) {
2997 case RT5677_SCLK_S_MCLK:
2998 reg_val |= RT5677_SCLK_SRC_MCLK;
2999 break;
3000 case RT5677_SCLK_S_PLL1:
3001 reg_val |= RT5677_SCLK_SRC_PLL1;
3002 break;
3003 case RT5677_SCLK_S_RCCLK:
3004 reg_val |= RT5677_SCLK_SRC_RCCLK;
3005 break;
3006 default:
3007 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
3008 return -EINVAL;
3009 }
3010 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3011 RT5677_SCLK_SRC_MASK, reg_val);
3012 rt5677->sysclk = freq;
3013 rt5677->sysclk_src = clk_id;
3014
3015 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
3016
3017 return 0;
3018}
3019
3020/**
3021 * rt5677_pll_calc - Calcualte PLL M/N/K code.
3022 * @freq_in: external clock provided to codec.
3023 * @freq_out: target clock which codec works on.
3024 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
3025 *
3026 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
3027 *
3028 * Returns 0 for success or negative error code.
3029 */
3030static int rt5677_pll_calc(const unsigned int freq_in,
Axel Lin099d3342014-06-17 12:41:31 +0800[diff] [blame]3031 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3032{
Axel Lin099d3342014-06-17 12:41:31 +0800[diff] [blame]3033 if (RT5677_PLL_INP_MIN > freq_in)
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3034 return -EINVAL;
3035
Axel Lin099d3342014-06-17 12:41:31 +0800[diff] [blame]3036 return rl6231_pll_calc(freq_in, freq_out, pll_code);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3037}
3038
3039static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
3040 unsigned int freq_in, unsigned int freq_out)
3041{
3042 struct snd_soc_codec *codec = dai->codec;
3043 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
Axel Lin099d3342014-06-17 12:41:31 +0800[diff] [blame]3044 struct rl6231_pll_code pll_code;
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3045 int ret;
3046
3047 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
3048 freq_out == rt5677->pll_out)
3049 return 0;
3050
3051 if (!freq_in || !freq_out) {
3052 dev_dbg(codec->dev, "PLL disabled\n");
3053
3054 rt5677->pll_in = 0;
3055 rt5677->pll_out = 0;
3056 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3057 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
3058 return 0;
3059 }
3060
3061 switch (source) {
3062 case RT5677_PLL1_S_MCLK:
3063 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3064 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
3065 break;
3066 case RT5677_PLL1_S_BCLK1:
3067 case RT5677_PLL1_S_BCLK2:
3068 case RT5677_PLL1_S_BCLK3:
3069 case RT5677_PLL1_S_BCLK4:
3070 switch (dai->id) {
3071 case RT5677_AIF1:
3072 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3073 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
3074 break;
3075 case RT5677_AIF2:
3076 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3077 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
3078 break;
3079 case RT5677_AIF3:
3080 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3081 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
3082 break;
3083 case RT5677_AIF4:
3084 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3085 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
3086 break;
3087 default:
3088 break;
3089 }
3090 break;
3091 default:
3092 dev_err(codec->dev, "Unknown PLL source %d\n", source);
3093 return -EINVAL;
3094 }
3095
3096 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
3097 if (ret < 0) {
3098 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
3099 return ret;
3100 }
3101
Axel Lin099d3342014-06-17 12:41:31 +0800[diff] [blame]3102 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
3103 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
3104 pll_code.n_code, pll_code.k_code);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3105
3106 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
Axel Lin099d3342014-06-17 12:41:31 +0800[diff] [blame]3107 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3108 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
3109 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
3110 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
3111
3112 rt5677->pll_in = freq_in;
3113 rt5677->pll_out = freq_out;
3114 rt5677->pll_src = source;
3115
3116 return 0;
3117}
3118
Oder Chiou48561af2014-09-17 15:12:33 +0800[diff] [blame]3119static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
3120 unsigned int rx_mask, int slots, int slot_width)
3121{
3122 struct snd_soc_codec *codec = dai->codec;
3123 unsigned int val = 0;
3124
3125 if (rx_mask || tx_mask)
3126 val |= (1 << 12);
3127
3128 switch (slots) {
3129 case 4:
3130 val |= (1 << 10);
3131 break;
3132 case 6:
3133 val |= (2 << 10);
3134 break;
3135 case 8:
3136 val |= (3 << 10);
3137 break;
3138 case 2:
3139 default:
3140 break;
3141 }
3142
3143 switch (slot_width) {
3144 case 20:
3145 val |= (1 << 8);
3146 break;
3147 case 24:
3148 val |= (2 << 8);
3149 break;
3150 case 32:
3151 val |= (3 << 8);
3152 break;
3153 case 16:
3154 default:
3155 break;
3156 }
3157
3158 switch (dai->id) {
3159 case RT5677_AIF1:
3160 snd_soc_update_bits(codec, RT5677_TDM1_CTRL1, 0x1f00, val);
3161 break;
3162 case RT5677_AIF2:
3163 snd_soc_update_bits(codec, RT5677_TDM2_CTRL1, 0x1f00, val);
3164 break;
3165 default:
3166 break;
3167 }
3168
3169 return 0;
3170}
3171
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3172static int rt5677_set_bias_level(struct snd_soc_codec *codec,
3173 enum snd_soc_bias_level level)
3174{
3175 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3176
3177 switch (level) {
3178 case SND_SOC_BIAS_ON:
3179 break;
3180
3181 case SND_SOC_BIAS_PREPARE:
3182 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
3183 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3184 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
3185 0x0055);
3186 regmap_update_bits(rt5677->regmap,
3187 RT5677_PR_BASE + RT5677_BIAS_CUR4,
3188 0x0f00, 0x0f00);
3189 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3190 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3191 RT5677_PWR_BG | RT5677_PWR_VREF2,
3192 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3193 RT5677_PWR_BG | RT5677_PWR_VREF2);
3194 mdelay(20);
3195 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3196 RT5677_PWR_FV1 | RT5677_PWR_FV2,
3197 RT5677_PWR_FV1 | RT5677_PWR_FV2);
3198 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
3199 RT5677_PWR_CORE, RT5677_PWR_CORE);
3200 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
3201 0x1, 0x1);
3202 }
3203 break;
3204
3205 case SND_SOC_BIAS_STANDBY:
3206 break;
3207
3208 case SND_SOC_BIAS_OFF:
3209 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
3210 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
3211 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
Oder Chiouf18803a2014-07-07 15:37:00 +0800[diff] [blame]3212 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3213 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
3214 regmap_update_bits(rt5677->regmap,
3215 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
3216 break;
3217
3218 default:
3219 break;
3220 }
3221 codec->dapm.bias_level = level;
3222
3223 return 0;
3224}
3225
Oder Chiou44caf762014-09-16 11:37:39 +0800[diff] [blame]3226#ifdef CONFIG_GPIOLIB
3227static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
3228{
3229 return container_of(chip, struct rt5677_priv, gpio_chip);
3230}
3231
3232static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3233{
3234 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3235
3236 switch (offset) {
3237 case RT5677_GPIO1 ... RT5677_GPIO5:
3238 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3239 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
3240 break;
3241
3242 case RT5677_GPIO6:
3243 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
3244 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
3245 break;
3246
3247 default:
3248 break;
3249 }
3250}
3251
3252static int rt5677_gpio_direction_out(struct gpio_chip *chip,
3253 unsigned offset, int value)
3254{
3255 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3256
3257 switch (offset) {
3258 case RT5677_GPIO1 ... RT5677_GPIO5:
3259 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3260 0x3 << (offset * 3 + 1),
3261 (0x2 | !!value) << (offset * 3 + 1));
3262 break;
3263
3264 case RT5677_GPIO6:
3265 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
3266 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
3267 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
3268 break;
3269
3270 default:
3271 break;
3272 }
3273
3274 return 0;
3275}
3276
3277static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
3278{
3279 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3280 int value, ret;
3281
3282 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
3283 if (ret < 0)
3284 return ret;
3285
3286 return (value & (0x1 << offset)) >> offset;
3287}
3288
3289static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
3290{
3291 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3292
3293 switch (offset) {
3294 case RT5677_GPIO1 ... RT5677_GPIO5:
3295 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3296 0x1 << (offset * 3 + 2), 0x0);
3297 break;
3298
3299 case RT5677_GPIO6:
3300 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
3301 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
3302 break;
3303
3304 default:
3305 break;
3306 }
3307
3308 return 0;
3309}
3310
3311static struct gpio_chip rt5677_template_chip = {
3312 .label = "rt5677",
3313 .owner = THIS_MODULE,
3314 .direction_output = rt5677_gpio_direction_out,
3315 .set = rt5677_gpio_set,
3316 .direction_input = rt5677_gpio_direction_in,
3317 .get = rt5677_gpio_get,
3318 .can_sleep = 1,
3319};
3320
3321static void rt5677_init_gpio(struct i2c_client *i2c)
3322{
3323 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
3324 int ret;
3325
3326 rt5677->gpio_chip = rt5677_template_chip;
3327 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
3328 rt5677->gpio_chip.dev = &i2c->dev;
3329 rt5677->gpio_chip.base = -1;
3330
3331 ret = gpiochip_add(&rt5677->gpio_chip);
3332 if (ret != 0)
3333 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
3334}
3335
3336static void rt5677_free_gpio(struct i2c_client *i2c)
3337{
3338 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
3339 int ret;
3340
3341 ret = gpiochip_remove(&rt5677->gpio_chip);
3342 if (ret != 0)
3343 dev_err(&i2c->dev, "Failed to remove GPIOs: %d\n", ret);
3344}
3345#else
3346static void rt5677_init_gpio(struct i2c_client *i2c)
3347{
3348}
3349
3350static void rt5677_free_gpio(struct i2c_client *i2c)
3351{
3352}
3353#endif
3354
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3355static int rt5677_probe(struct snd_soc_codec *codec)
3356{
3357 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3358
3359 rt5677->codec = codec;
3360
Bard Liao2d15d972014-08-27 19:50:34 +0800[diff] [blame]3361 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
3362 snd_soc_dapm_add_routes(&codec->dapm,
3363 rt5677_dmic2_clk_2,
3364 ARRAY_SIZE(rt5677_dmic2_clk_2));
3365 } else { /*use dmic1 clock by default*/
3366 snd_soc_dapm_add_routes(&codec->dapm,
3367 rt5677_dmic2_clk_1,
3368 ARRAY_SIZE(rt5677_dmic2_clk_1));
3369 }
3370
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3371 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
3372
3373 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
3374 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
3375
3376 return 0;
3377}
3378
3379static int rt5677_remove(struct snd_soc_codec *codec)
3380{
3381 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3382
3383 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
3384
3385 return 0;
3386}
3387
3388#ifdef CONFIG_PM
3389static int rt5677_suspend(struct snd_soc_codec *codec)
3390{
3391 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3392
3393 regcache_cache_only(rt5677->regmap, true);
3394 regcache_mark_dirty(rt5677->regmap);
3395
3396 return 0;
3397}
3398
3399static int rt5677_resume(struct snd_soc_codec *codec)
3400{
3401 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3402
3403 regcache_cache_only(rt5677->regmap, false);
3404 regcache_sync(rt5677->regmap);
3405
3406 return 0;
3407}
3408#else
3409#define rt5677_suspend NULL
3410#define rt5677_resume NULL
3411#endif
3412
3413#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3414#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3415 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3416
3417static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
3418 .hw_params = rt5677_hw_params,
3419 .set_fmt = rt5677_set_dai_fmt,
3420 .set_sysclk = rt5677_set_dai_sysclk,
3421 .set_pll = rt5677_set_dai_pll,
Oder Chiou48561af2014-09-17 15:12:33 +0800[diff] [blame]3422 .set_tdm_slot = rt5677_set_tdm_slot,
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3423};
3424
3425static struct snd_soc_dai_driver rt5677_dai[] = {
3426 {
3427 .name = "rt5677-aif1",
3428 .id = RT5677_AIF1,
3429 .playback = {
3430 .stream_name = "AIF1 Playback",
3431 .channels_min = 1,
3432 .channels_max = 2,
3433 .rates = RT5677_STEREO_RATES,
3434 .formats = RT5677_FORMATS,
3435 },
3436 .capture = {
3437 .stream_name = "AIF1 Capture",
3438 .channels_min = 1,
3439 .channels_max = 2,
3440 .rates = RT5677_STEREO_RATES,
3441 .formats = RT5677_FORMATS,
3442 },
3443 .ops = &rt5677_aif_dai_ops,
3444 },
3445 {
3446 .name = "rt5677-aif2",
3447 .id = RT5677_AIF2,
3448 .playback = {
3449 .stream_name = "AIF2 Playback",
3450 .channels_min = 1,
3451 .channels_max = 2,
3452 .rates = RT5677_STEREO_RATES,
3453 .formats = RT5677_FORMATS,
3454 },
3455 .capture = {
3456 .stream_name = "AIF2 Capture",
3457 .channels_min = 1,
3458 .channels_max = 2,
3459 .rates = RT5677_STEREO_RATES,
3460 .formats = RT5677_FORMATS,
3461 },
3462 .ops = &rt5677_aif_dai_ops,
3463 },
3464 {
3465 .name = "rt5677-aif3",
3466 .id = RT5677_AIF3,
3467 .playback = {
3468 .stream_name = "AIF3 Playback",
3469 .channels_min = 1,
3470 .channels_max = 2,
3471 .rates = RT5677_STEREO_RATES,
3472 .formats = RT5677_FORMATS,
3473 },
3474 .capture = {
3475 .stream_name = "AIF3 Capture",
3476 .channels_min = 1,
3477 .channels_max = 2,
3478 .rates = RT5677_STEREO_RATES,
3479 .formats = RT5677_FORMATS,
3480 },
3481 .ops = &rt5677_aif_dai_ops,
3482 },
3483 {
3484 .name = "rt5677-aif4",
3485 .id = RT5677_AIF4,
3486 .playback = {
3487 .stream_name = "AIF4 Playback",
3488 .channels_min = 1,
3489 .channels_max = 2,
3490 .rates = RT5677_STEREO_RATES,
3491 .formats = RT5677_FORMATS,
3492 },
3493 .capture = {
3494 .stream_name = "AIF4 Capture",
3495 .channels_min = 1,
3496 .channels_max = 2,
3497 .rates = RT5677_STEREO_RATES,
3498 .formats = RT5677_FORMATS,
3499 },
3500 .ops = &rt5677_aif_dai_ops,
3501 },
3502 {
3503 .name = "rt5677-slimbus",
3504 .id = RT5677_AIF5,
3505 .playback = {
3506 .stream_name = "SLIMBus Playback",
3507 .channels_min = 1,
3508 .channels_max = 2,
3509 .rates = RT5677_STEREO_RATES,
3510 .formats = RT5677_FORMATS,
3511 },
3512 .capture = {
3513 .stream_name = "SLIMBus Capture",
3514 .channels_min = 1,
3515 .channels_max = 2,
3516 .rates = RT5677_STEREO_RATES,
3517 .formats = RT5677_FORMATS,
3518 },
3519 .ops = &rt5677_aif_dai_ops,
3520 },
3521};
3522
3523static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
3524 .probe = rt5677_probe,
3525 .remove = rt5677_remove,
3526 .suspend = rt5677_suspend,
3527 .resume = rt5677_resume,
3528 .set_bias_level = rt5677_set_bias_level,
3529 .idle_bias_off = true,
3530 .controls = rt5677_snd_controls,
3531 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
3532 .dapm_widgets = rt5677_dapm_widgets,
3533 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
3534 .dapm_routes = rt5677_dapm_routes,
3535 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
3536};
3537
3538static const struct regmap_config rt5677_regmap = {
3539 .reg_bits = 8,
3540 .val_bits = 16,
3541
3542 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
3543 RT5677_PR_SPACING),
3544
3545 .volatile_reg = rt5677_volatile_register,
3546 .readable_reg = rt5677_readable_register,
3547
3548 .cache_type = REGCACHE_RBTREE,
3549 .reg_defaults = rt5677_reg,
3550 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
3551 .ranges = rt5677_ranges,
3552 .num_ranges = ARRAY_SIZE(rt5677_ranges),
3553};
3554
3555static const struct i2c_device_id rt5677_i2c_id[] = {
3556 { "rt5677", 0 },
3557 { }
3558};
3559MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
3560
3561static int rt5677_i2c_probe(struct i2c_client *i2c,
3562 const struct i2c_device_id *id)
3563{
3564 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
3565 struct rt5677_priv *rt5677;
3566 int ret;
3567 unsigned int val;
3568
3569 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
3570 GFP_KERNEL);
3571 if (rt5677 == NULL)
3572 return -ENOMEM;
3573
3574 i2c_set_clientdata(i2c, rt5677);
3575
3576 if (pdata)
3577 rt5677->pdata = *pdata;
3578
3579 rt5677->regmap = devm_regmap_init_i2c(i2c, &rt5677_regmap);
3580 if (IS_ERR(rt5677->regmap)) {
3581 ret = PTR_ERR(rt5677->regmap);
3582 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3583 ret);
3584 return ret;
3585 }
3586
3587 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
3588 if (val != RT5677_DEVICE_ID) {
3589 dev_err(&i2c->dev,
3590 "Device with ID register %x is not rt5677\n", val);
3591 return -ENODEV;
3592 }
3593
3594 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
3595
3596 ret = regmap_register_patch(rt5677->regmap, init_list,
3597 ARRAY_SIZE(init_list));
3598 if (ret != 0)
3599 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3600
3601 if (rt5677->pdata.in1_diff)
3602 regmap_update_bits(rt5677->regmap, RT5677_IN1,
3603 RT5677_IN_DF1, RT5677_IN_DF1);
3604
3605 if (rt5677->pdata.in2_diff)
3606 regmap_update_bits(rt5677->regmap, RT5677_IN1,
3607 RT5677_IN_DF2, RT5677_IN_DF2);
3608
Bard Liao2d15d972014-08-27 19:50:34 +0800[diff] [blame]3609 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
3610 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
3611 RT5677_GPIO5_FUNC_MASK,
3612 RT5677_GPIO5_FUNC_DMIC);
3613 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3614 RT5677_GPIO5_DIR_MASK,
3615 RT5677_GPIO5_DIR_OUT);
3616 }
3617
Oder Chiou44caf762014-09-16 11:37:39 +0800[diff] [blame]3618 rt5677_init_gpio(i2c);
3619
Axel Lind0bdcb92014-06-10 11:37:24 +0800[diff] [blame]3620 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
3621 rt5677_dai, ARRAY_SIZE(rt5677_dai));
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3622}
3623
3624static int rt5677_i2c_remove(struct i2c_client *i2c)
3625{
3626 snd_soc_unregister_codec(&i2c->dev);
Oder Chiou44caf762014-09-16 11:37:39 +0800[diff] [blame]3627 rt5677_free_gpio(i2c);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3628
3629 return 0;
3630}
3631
3632static struct i2c_driver rt5677_i2c_driver = {
3633 .driver = {
3634 .name = "rt5677",
3635 .owner = THIS_MODULE,
3636 },
3637 .probe = rt5677_i2c_probe,
3638 .remove = rt5677_i2c_remove,
3639 .id_table = rt5677_i2c_id,
3640};
Axel Linc8cfbec82014-06-03 10:56:41 +0800[diff] [blame]3641module_i2c_driver(rt5677_i2c_driver);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3642
3643MODULE_DESCRIPTION("ASoC RT5677 driver");
3644MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
3645MODULE_LICENSE("GPL v2");