Thomas Gleixner | 28a2775 | 2018-04-29 15:01:37 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | #ifndef _ASM_X86_SPECCTRL_H_ |
| 3 | #define _ASM_X86_SPECCTRL_H_ |
| 4 | |
Thomas Gleixner | 885f82b | 2018-04-29 15:21:42 +0200 | [diff] [blame] | 5 | #include <linux/thread_info.h> |
Thomas Gleixner | 28a2775 | 2018-04-29 15:01:37 +0200 | [diff] [blame] | 6 | #include <asm/nospec-branch.h> |
| 7 | |
| 8 | /* |
| 9 | * On VMENTER we must preserve whatever view of the SPEC_CTRL MSR |
| 10 | * the guest has, while on VMEXIT we restore the host view. This |
| 11 | * would be easier if SPEC_CTRL were architecturally maskable or |
| 12 | * shadowable for guests but this is not (currently) the case. |
| 13 | * Takes the guest view of SPEC_CTRL MSR as a parameter. |
| 14 | */ |
| 15 | extern void x86_spec_ctrl_set_guest(u64); |
| 16 | extern void x86_spec_ctrl_restore_host(u64); |
| 17 | |
| 18 | /* AMD specific Speculative Store Bypass MSR data */ |
| 19 | extern u64 x86_amd_ls_cfg_base; |
Konrad Rzeszutek Wilk | 9f65fb2 | 2018-05-09 21:41:38 +0200 | [diff] [blame^] | 20 | extern u64 x86_amd_ls_cfg_ssbd_mask; |
Thomas Gleixner | 28a2775 | 2018-04-29 15:01:37 +0200 | [diff] [blame] | 21 | |
Thomas Gleixner | 885f82b | 2018-04-29 15:21:42 +0200 | [diff] [blame] | 22 | /* The Intel SPEC CTRL MSR base value cache */ |
| 23 | extern u64 x86_spec_ctrl_base; |
| 24 | |
Konrad Rzeszutek Wilk | 9f65fb2 | 2018-05-09 21:41:38 +0200 | [diff] [blame^] | 25 | static inline u64 ssbd_tif_to_spec_ctrl(u64 tifn) |
Thomas Gleixner | 885f82b | 2018-04-29 15:21:42 +0200 | [diff] [blame] | 26 | { |
Konrad Rzeszutek Wilk | 9f65fb2 | 2018-05-09 21:41:38 +0200 | [diff] [blame^] | 27 | BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT); |
| 28 | return (tifn & _TIF_SSBD) >> (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT); |
Thomas Gleixner | 885f82b | 2018-04-29 15:21:42 +0200 | [diff] [blame] | 29 | } |
| 30 | |
Konrad Rzeszutek Wilk | 9f65fb2 | 2018-05-09 21:41:38 +0200 | [diff] [blame^] | 31 | static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn) |
Thomas Gleixner | 885f82b | 2018-04-29 15:21:42 +0200 | [diff] [blame] | 32 | { |
Konrad Rzeszutek Wilk | 9f65fb2 | 2018-05-09 21:41:38 +0200 | [diff] [blame^] | 33 | return (tifn & _TIF_SSBD) ? x86_amd_ls_cfg_ssbd_mask : 0ULL; |
Thomas Gleixner | 885f82b | 2018-04-29 15:21:42 +0200 | [diff] [blame] | 34 | } |
| 35 | |
| 36 | extern void speculative_store_bypass_update(void); |
| 37 | |
Thomas Gleixner | 28a2775 | 2018-04-29 15:01:37 +0200 | [diff] [blame] | 38 | #endif |