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Thomas Gleixner28a27752018-04-29 15:01:37 +02001/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_SPECCTRL_H_
3#define _ASM_X86_SPECCTRL_H_
4
Thomas Gleixner885f82b2018-04-29 15:21:42 +02005#include <linux/thread_info.h>
Thomas Gleixner28a27752018-04-29 15:01:37 +02006#include <asm/nospec-branch.h>
7
8/*
9 * On VMENTER we must preserve whatever view of the SPEC_CTRL MSR
10 * the guest has, while on VMEXIT we restore the host view. This
11 * would be easier if SPEC_CTRL were architecturally maskable or
12 * shadowable for guests but this is not (currently) the case.
13 * Takes the guest view of SPEC_CTRL MSR as a parameter.
14 */
15extern void x86_spec_ctrl_set_guest(u64);
16extern void x86_spec_ctrl_restore_host(u64);
17
18/* AMD specific Speculative Store Bypass MSR data */
19extern u64 x86_amd_ls_cfg_base;
Konrad Rzeszutek Wilk9f65fb22018-05-09 21:41:38 +020020extern u64 x86_amd_ls_cfg_ssbd_mask;
Thomas Gleixner28a27752018-04-29 15:01:37 +020021
Thomas Gleixner885f82b2018-04-29 15:21:42 +020022/* The Intel SPEC CTRL MSR base value cache */
23extern u64 x86_spec_ctrl_base;
24
Konrad Rzeszutek Wilk9f65fb22018-05-09 21:41:38 +020025static inline u64 ssbd_tif_to_spec_ctrl(u64 tifn)
Thomas Gleixner885f82b2018-04-29 15:21:42 +020026{
Konrad Rzeszutek Wilk9f65fb22018-05-09 21:41:38 +020027 BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT);
28 return (tifn & _TIF_SSBD) >> (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT);
Thomas Gleixner885f82b2018-04-29 15:21:42 +020029}
30
Konrad Rzeszutek Wilk9f65fb22018-05-09 21:41:38 +020031static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn)
Thomas Gleixner885f82b2018-04-29 15:21:42 +020032{
Konrad Rzeszutek Wilk9f65fb22018-05-09 21:41:38 +020033 return (tifn & _TIF_SSBD) ? x86_amd_ls_cfg_ssbd_mask : 0ULL;
Thomas Gleixner885f82b2018-04-29 15:21:42 +020034}
35
36extern void speculative_store_bypass_update(void);
37
Thomas Gleixner28a27752018-04-29 15:01:37 +020038#endif