Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1 | /* |
| 2 | * NAND Flash Controller Device Driver |
| 3 | * Copyright © 2009-2010, Intel Corporation and its suppliers. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2, as published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
| 15 | * this program; if not, write to the Free Software Foundation, Inc., |
| 16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 17 | * |
| 18 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/delay.h> |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 21 | #include <linux/dma-mapping.h> |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 22 | #include <linux/wait.h> |
| 23 | #include <linux/mutex.h> |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 24 | #include <linux/mtd/mtd.h> |
| 25 | #include <linux/module.h> |
| 26 | |
| 27 | #include "denali.h" |
| 28 | |
| 29 | MODULE_LICENSE("GPL"); |
| 30 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 31 | /* |
| 32 | * We define a module parameter that allows the user to override |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 33 | * the hardware and decide what timing mode should be used. |
| 34 | */ |
| 35 | #define NAND_DEFAULT_TIMINGS -1 |
| 36 | |
| 37 | static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; |
| 38 | module_param(onfi_timing_mode, int, S_IRUGO); |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 39 | MODULE_PARM_DESC(onfi_timing_mode, |
| 40 | "Overrides default ONFI setting. -1 indicates use default timings"); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 41 | |
| 42 | #define DENALI_NAND_NAME "denali-nand" |
| 43 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 44 | /* |
| 45 | * We define a macro here that combines all interrupts this driver uses into |
| 46 | * a single constant value, for convenience. |
| 47 | */ |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 48 | #define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \ |
| 49 | INTR_STATUS__ECC_TRANSACTION_DONE | \ |
| 50 | INTR_STATUS__ECC_ERR | \ |
| 51 | INTR_STATUS__PROGRAM_FAIL | \ |
| 52 | INTR_STATUS__LOAD_COMP | \ |
| 53 | INTR_STATUS__PROGRAM_COMP | \ |
| 54 | INTR_STATUS__TIME_OUT | \ |
| 55 | INTR_STATUS__ERASE_FAIL | \ |
| 56 | INTR_STATUS__RST_COMP | \ |
| 57 | INTR_STATUS__ERASE_COMP) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 58 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 59 | /* |
| 60 | * indicates whether or not the internal value for the flash bank is |
| 61 | * valid or not |
| 62 | */ |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 63 | #define CHIP_SELECT_INVALID -1 |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 64 | |
| 65 | #define SUPPORT_8BITECC 1 |
| 66 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 67 | /* |
| 68 | * This macro divides two integers and rounds fractional values up |
| 69 | * to the nearest integer value. |
| 70 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 71 | #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y))) |
| 72 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 73 | /* |
| 74 | * this macro allows us to convert from an MTD structure to our own |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 75 | * device context (denali) structure. |
| 76 | */ |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 77 | static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) |
| 78 | { |
| 79 | return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); |
| 80 | } |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 81 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 82 | /* |
| 83 | * These constants are defined by the driver to enable common driver |
| 84 | * configuration options. |
| 85 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 86 | #define SPARE_ACCESS 0x41 |
| 87 | #define MAIN_ACCESS 0x42 |
| 88 | #define MAIN_SPARE_ACCESS 0x43 |
Masahiro Yamada | 2902330 | 2014-07-11 11:14:05 +0900 | [diff] [blame] | 89 | #define PIPELINE_ACCESS 0x2000 |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 90 | |
| 91 | #define DENALI_READ 0 |
| 92 | #define DENALI_WRITE 0x100 |
| 93 | |
| 94 | /* types of device accesses. We can issue commands and get status */ |
| 95 | #define COMMAND_CYCLE 0 |
| 96 | #define ADDR_CYCLE 1 |
| 97 | #define STATUS_CYCLE 2 |
| 98 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 99 | /* |
| 100 | * this is a helper macro that allows us to |
| 101 | * format the bank into the proper bits for the controller |
| 102 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 103 | #define BANK(x) ((x) << 24) |
| 104 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 105 | /* forward declarations */ |
| 106 | static void clear_interrupts(struct denali_nand_info *denali); |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 107 | static uint32_t wait_for_irq(struct denali_nand_info *denali, |
| 108 | uint32_t irq_mask); |
| 109 | static void denali_irq_enable(struct denali_nand_info *denali, |
| 110 | uint32_t int_mask); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 111 | static uint32_t read_interrupt_status(struct denali_nand_info *denali); |
| 112 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 113 | /* |
| 114 | * Certain operations for the denali NAND controller use an indexed mode to |
| 115 | * read/write data. The operation is performed by writing the address value |
| 116 | * of the command to the device memory followed by the data. This function |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 117 | * abstracts this common operation. |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 118 | */ |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 119 | static void index_addr(struct denali_nand_info *denali, |
| 120 | uint32_t address, uint32_t data) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 121 | { |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 122 | iowrite32(address, denali->flash_mem); |
| 123 | iowrite32(data, denali->flash_mem + 0x10); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 124 | } |
| 125 | |
| 126 | /* Perform an indexed read of the device */ |
| 127 | static void index_addr_read_data(struct denali_nand_info *denali, |
| 128 | uint32_t address, uint32_t *pdata) |
| 129 | { |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 130 | iowrite32(address, denali->flash_mem); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 131 | *pdata = ioread32(denali->flash_mem + 0x10); |
| 132 | } |
| 133 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 134 | /* |
| 135 | * We need to buffer some data for some of the NAND core routines. |
| 136 | * The operations manage buffering that data. |
| 137 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 138 | static void reset_buf(struct denali_nand_info *denali) |
| 139 | { |
| 140 | denali->buf.head = denali->buf.tail = 0; |
| 141 | } |
| 142 | |
| 143 | static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte) |
| 144 | { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 145 | denali->buf.buf[denali->buf.tail++] = byte; |
| 146 | } |
| 147 | |
| 148 | /* reads the status of the device */ |
| 149 | static void read_status(struct denali_nand_info *denali) |
| 150 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 151 | uint32_t cmd; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 152 | |
| 153 | /* initialize the data buffer to store status */ |
| 154 | reset_buf(denali); |
| 155 | |
Chuanxiao Dong | f0bc0c7 | 2010-08-11 17:14:59 +0800 | [diff] [blame] | 156 | cmd = ioread32(denali->flash_reg + WRITE_PROTECT); |
| 157 | if (cmd) |
| 158 | write_byte_to_buf(denali, NAND_STATUS_WP); |
| 159 | else |
| 160 | write_byte_to_buf(denali, 0); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 161 | } |
| 162 | |
| 163 | /* resets a specific device connected to the core */ |
| 164 | static void reset_bank(struct denali_nand_info *denali) |
| 165 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 166 | uint32_t irq_status; |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 167 | uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 168 | |
| 169 | clear_interrupts(denali); |
| 170 | |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 171 | iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 172 | |
| 173 | irq_status = wait_for_irq(denali, irq_mask); |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 174 | |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 175 | if (irq_status & INTR_STATUS__TIME_OUT) |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 176 | dev_err(denali->dev, "reset bank failed.\n"); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | /* Reset the flash controller */ |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 180 | static uint16_t denali_nand_reset(struct denali_nand_info *denali) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 181 | { |
Masahiro Yamada | 93e3c8a | 2014-09-09 11:01:54 +0900 | [diff] [blame] | 182 | int i; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 183 | |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 184 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 185 | __FILE__, __LINE__, __func__); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 186 | |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 187 | for (i = 0; i < denali->max_banks; i++) |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 188 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
| 189 | denali->flash_reg + INTR_STATUS(i)); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 190 | |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 191 | for (i = 0; i < denali->max_banks; i++) { |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 192 | iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 193 | while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 194 | (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT))) |
Chuanxiao Dong | 628bfd41 | 2010-08-11 17:53:29 +0800 | [diff] [blame] | 195 | cpu_relax(); |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 196 | if (ioread32(denali->flash_reg + INTR_STATUS(i)) & |
| 197 | INTR_STATUS__TIME_OUT) |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 198 | dev_dbg(denali->dev, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 199 | "NAND Reset operation timed out on bank %d\n", i); |
| 200 | } |
| 201 | |
Jamie Iles | c89eeda | 2011-05-06 15:28:57 +0100 | [diff] [blame] | 202 | for (i = 0; i < denali->max_banks; i++) |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 203 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 204 | denali->flash_reg + INTR_STATUS(i)); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 205 | |
| 206 | return PASS; |
| 207 | } |
| 208 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 209 | /* |
| 210 | * this routine calculates the ONFI timing values for a given mode and |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 211 | * programs the clocking register accordingly. The mode is determined by |
| 212 | * the get_onfi_nand_para routine. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 213 | */ |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 214 | static void nand_onfi_timing_set(struct denali_nand_info *denali, |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 215 | uint16_t mode) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 216 | { |
| 217 | uint16_t Trea[6] = {40, 30, 25, 20, 20, 16}; |
| 218 | uint16_t Trp[6] = {50, 25, 17, 15, 12, 10}; |
| 219 | uint16_t Treh[6] = {30, 15, 15, 10, 10, 7}; |
| 220 | uint16_t Trc[6] = {100, 50, 35, 30, 25, 20}; |
| 221 | uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15}; |
| 222 | uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5}; |
| 223 | uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25}; |
| 224 | uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70}; |
| 225 | uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100}; |
| 226 | uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100}; |
| 227 | uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60}; |
| 228 | uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15}; |
| 229 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 230 | uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid; |
| 231 | uint16_t dv_window = 0; |
| 232 | uint16_t en_lo, en_hi; |
| 233 | uint16_t acc_clks; |
| 234 | uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; |
| 235 | |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 236 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 237 | __FILE__, __LINE__, __func__); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 238 | |
| 239 | en_lo = CEIL_DIV(Trp[mode], CLK_X); |
| 240 | en_hi = CEIL_DIV(Treh[mode], CLK_X); |
| 241 | #if ONFI_BLOOM_TIME |
| 242 | if ((en_hi * CLK_X) < (Treh[mode] + 2)) |
| 243 | en_hi++; |
| 244 | #endif |
| 245 | |
| 246 | if ((en_lo + en_hi) * CLK_X < Trc[mode]) |
| 247 | en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X); |
| 248 | |
| 249 | if ((en_lo + en_hi) < CLK_MULTI) |
| 250 | en_lo += CLK_MULTI - en_lo - en_hi; |
| 251 | |
| 252 | while (dv_window < 8) { |
| 253 | data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode]; |
| 254 | |
| 255 | data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode]; |
| 256 | |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 257 | data_invalid = data_invalid_rhoh < data_invalid_rloh ? |
| 258 | data_invalid_rhoh : data_invalid_rloh; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 259 | |
| 260 | dv_window = data_invalid - Trea[mode]; |
| 261 | |
| 262 | if (dv_window < 8) |
| 263 | en_lo++; |
| 264 | } |
| 265 | |
| 266 | acc_clks = CEIL_DIV(Trea[mode], CLK_X); |
| 267 | |
Masahiro Yamada | 7d14ecd | 2014-09-16 20:04:24 +0900 | [diff] [blame] | 268 | while (acc_clks * CLK_X - Trea[mode] < 3) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 269 | acc_clks++; |
| 270 | |
Masahiro Yamada | 7d14ecd | 2014-09-16 20:04:24 +0900 | [diff] [blame] | 271 | if (data_invalid - acc_clks * CLK_X < 2) |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 272 | dev_warn(denali->dev, "%s, Line %d: Warning!\n", |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 273 | __FILE__, __LINE__); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 274 | |
| 275 | addr_2_data = CEIL_DIV(Tadl[mode], CLK_X); |
| 276 | re_2_we = CEIL_DIV(Trhw[mode], CLK_X); |
| 277 | re_2_re = CEIL_DIV(Trhz[mode], CLK_X); |
| 278 | we_2_re = CEIL_DIV(Twhr[mode], CLK_X); |
| 279 | cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 280 | if (cs_cnt == 0) |
| 281 | cs_cnt = 1; |
| 282 | |
| 283 | if (Tcea[mode]) { |
Masahiro Yamada | 7d14ecd | 2014-09-16 20:04:24 +0900 | [diff] [blame] | 284 | while (cs_cnt * CLK_X + Trea[mode] < Tcea[mode]) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 285 | cs_cnt++; |
| 286 | } |
| 287 | |
| 288 | #if MODE5_WORKAROUND |
| 289 | if (mode == 5) |
| 290 | acc_clks = 5; |
| 291 | #endif |
| 292 | |
| 293 | /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */ |
Masahiro Yamada | 7d14ecd | 2014-09-16 20:04:24 +0900 | [diff] [blame] | 294 | if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 && |
| 295 | ioread32(denali->flash_reg + DEVICE_ID) == 0x88) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 296 | acc_clks = 6; |
| 297 | |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 298 | iowrite32(acc_clks, denali->flash_reg + ACC_CLKS); |
| 299 | iowrite32(re_2_we, denali->flash_reg + RE_2_WE); |
| 300 | iowrite32(re_2_re, denali->flash_reg + RE_2_RE); |
| 301 | iowrite32(we_2_re, denali->flash_reg + WE_2_RE); |
| 302 | iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA); |
| 303 | iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT); |
| 304 | iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT); |
| 305 | iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 306 | } |
| 307 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 308 | /* queries the NAND device to see what ONFI modes it supports. */ |
| 309 | static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) |
| 310 | { |
| 311 | int i; |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 312 | |
| 313 | /* |
| 314 | * we needn't to do a reset here because driver has already |
Chuanxiao Dong | 4c03bbd | 2010-08-06 15:45:19 +0800 | [diff] [blame] | 315 | * reset all the banks before |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 316 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 317 | if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
| 318 | ONFI_TIMING_MODE__VALUE)) |
| 319 | return FAIL; |
| 320 | |
| 321 | for (i = 5; i > 0; i--) { |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 322 | if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
| 323 | (0x01 << i)) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 324 | break; |
| 325 | } |
| 326 | |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 327 | nand_onfi_timing_set(denali, i); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 328 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 329 | /* |
| 330 | * By now, all the ONFI devices we know support the page cache |
| 331 | * rw feature. So here we enable the pipeline_rw_ahead feature |
| 332 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 333 | /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */ |
| 334 | /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */ |
| 335 | |
| 336 | return PASS; |
| 337 | } |
| 338 | |
Chuanxiao Dong | 4c03bbd | 2010-08-06 15:45:19 +0800 | [diff] [blame] | 339 | static void get_samsung_nand_para(struct denali_nand_info *denali, |
| 340 | uint8_t device_id) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 341 | { |
Chuanxiao Dong | 4c03bbd | 2010-08-06 15:45:19 +0800 | [diff] [blame] | 342 | if (device_id == 0xd3) { /* Samsung K9WAG08U1A */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 343 | /* Set timing register values according to datasheet */ |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 344 | iowrite32(5, denali->flash_reg + ACC_CLKS); |
| 345 | iowrite32(20, denali->flash_reg + RE_2_WE); |
| 346 | iowrite32(12, denali->flash_reg + WE_2_RE); |
| 347 | iowrite32(14, denali->flash_reg + ADDR_2_DATA); |
| 348 | iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT); |
| 349 | iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT); |
| 350 | iowrite32(2, denali->flash_reg + CS_SETUP_CNT); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 351 | } |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 352 | } |
| 353 | |
| 354 | static void get_toshiba_nand_para(struct denali_nand_info *denali) |
| 355 | { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 356 | uint32_t tmp; |
| 357 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 358 | /* |
| 359 | * Workaround to fix a controller bug which reports a wrong |
| 360 | * spare area size for some kind of Toshiba NAND device |
| 361 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 362 | if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && |
| 363 | (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 364 | iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 365 | tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) * |
| 366 | ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 367 | iowrite32(tmp, |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 368 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 369 | #if SUPPORT_15BITECC |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 370 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 371 | #elif SUPPORT_8BITECC |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 372 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 373 | #endif |
| 374 | } |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 375 | } |
| 376 | |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 377 | static void get_hynix_nand_para(struct denali_nand_info *denali, |
| 378 | uint8_t device_id) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 379 | { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 380 | uint32_t main_size, spare_size; |
| 381 | |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 382 | switch (device_id) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 383 | case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */ |
| 384 | case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */ |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 385 | iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK); |
| 386 | iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); |
| 387 | iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 388 | main_size = 4096 * |
| 389 | ioread32(denali->flash_reg + DEVICES_CONNECTED); |
| 390 | spare_size = 224 * |
| 391 | ioread32(denali->flash_reg + DEVICES_CONNECTED); |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 392 | iowrite32(main_size, |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 393 | denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 394 | iowrite32(spare_size, |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 395 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 396 | iowrite32(0, denali->flash_reg + DEVICE_WIDTH); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 397 | #if SUPPORT_15BITECC |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 398 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 399 | #elif SUPPORT_8BITECC |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 400 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 401 | #endif |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 402 | break; |
| 403 | default: |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 404 | dev_warn(denali->dev, |
Masahiro Yamada | 789ccf1 | 2016-11-09 13:35:24 +0900 | [diff] [blame] | 405 | "Unknown Hynix NAND (Device ID: 0x%x).\n" |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 406 | "Will use default parameter values instead.\n", |
| 407 | device_id); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 408 | } |
| 409 | } |
| 410 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 411 | /* |
| 412 | * determines how many NAND chips are connected to the controller. Note for |
Chuanxiao Dong | b292c34 | 2010-08-11 17:46:00 +0800 | [diff] [blame] | 413 | * Intel CE4100 devices we don't support more than one device. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 414 | */ |
| 415 | static void find_valid_banks(struct denali_nand_info *denali) |
| 416 | { |
Jamie Iles | c89eeda | 2011-05-06 15:28:57 +0100 | [diff] [blame] | 417 | uint32_t id[denali->max_banks]; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 418 | int i; |
| 419 | |
| 420 | denali->total_used_banks = 1; |
Jamie Iles | c89eeda | 2011-05-06 15:28:57 +0100 | [diff] [blame] | 421 | for (i = 0; i < denali->max_banks; i++) { |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 422 | index_addr(denali, MODE_11 | (i << 24) | 0, 0x90); |
| 423 | index_addr(denali, MODE_11 | (i << 24) | 1, 0); |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 424 | index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 425 | |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 426 | dev_dbg(denali->dev, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 427 | "Return 1st ID for bank[%d]: %x\n", i, id[i]); |
| 428 | |
| 429 | if (i == 0) { |
| 430 | if (!(id[i] & 0x0ff)) |
| 431 | break; /* WTF? */ |
| 432 | } else { |
| 433 | if ((id[i] & 0x0ff) == (id[0] & 0x0ff)) |
| 434 | denali->total_used_banks++; |
| 435 | else |
| 436 | break; |
| 437 | } |
| 438 | } |
| 439 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 440 | if (denali->platform == INTEL_CE4100) { |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 441 | /* |
| 442 | * Platform limitations of the CE4100 device limit |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 443 | * users to a single chip solution for NAND. |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 444 | * Multichip support is not enabled. |
| 445 | */ |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 446 | if (denali->total_used_banks != 1) { |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 447 | dev_err(denali->dev, |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 448 | "Sorry, Intel CE4100 only supports a single NAND device.\n"); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 449 | BUG(); |
| 450 | } |
| 451 | } |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 452 | dev_dbg(denali->dev, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 453 | "denali->total_used_banks: %d\n", denali->total_used_banks); |
| 454 | } |
| 455 | |
Jamie Iles | c89eeda | 2011-05-06 15:28:57 +0100 | [diff] [blame] | 456 | /* |
| 457 | * Use the configuration feature register to determine the maximum number of |
| 458 | * banks that the hardware supports. |
| 459 | */ |
| 460 | static void detect_max_banks(struct denali_nand_info *denali) |
| 461 | { |
| 462 | uint32_t features = ioread32(denali->flash_reg + FEATURES); |
Graham Moore | 271707b | 2015-07-21 09:39:31 -0500 | [diff] [blame] | 463 | /* |
| 464 | * Read the revision register, so we can calculate the max_banks |
| 465 | * properly: the encoding changed from rev 5.0 to 5.1 |
| 466 | */ |
| 467 | u32 revision = MAKE_COMPARABLE_REVISION( |
| 468 | ioread32(denali->flash_reg + REVISION)); |
Jamie Iles | c89eeda | 2011-05-06 15:28:57 +0100 | [diff] [blame] | 469 | |
Graham Moore | 271707b | 2015-07-21 09:39:31 -0500 | [diff] [blame] | 470 | if (revision < REVISION_5_1) |
| 471 | denali->max_banks = 2 << (features & FEATURES__N_BANKS); |
| 472 | else |
| 473 | denali->max_banks = 1 << (features & FEATURES__N_BANKS); |
Jamie Iles | c89eeda | 2011-05-06 15:28:57 +0100 | [diff] [blame] | 474 | } |
| 475 | |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 476 | static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 477 | { |
| 478 | uint16_t status = PASS; |
grmoore@altera.com | d68a5c3 | 2014-06-23 14:21:10 -0500 | [diff] [blame] | 479 | uint32_t id_bytes[8], addr; |
Masahiro Yamada | 93e3c8a | 2014-09-09 11:01:54 +0900 | [diff] [blame] | 480 | uint8_t maf_id, device_id; |
| 481 | int i; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 482 | |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 483 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
Chuanxiao Dong | 7cfffac | 2010-08-10 00:16:51 +0800 | [diff] [blame] | 484 | __FILE__, __LINE__, __func__); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 485 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 486 | /* |
| 487 | * Use read id method to get device ID and other params. |
| 488 | * For some NAND chips, controller can't report the correct |
| 489 | * device ID by reading from DEVICE_ID register |
| 490 | */ |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 491 | addr = MODE_11 | BANK(denali->flash_bank); |
| 492 | index_addr(denali, addr | 0, 0x90); |
| 493 | index_addr(denali, addr | 1, 0); |
grmoore@altera.com | d68a5c3 | 2014-06-23 14:21:10 -0500 | [diff] [blame] | 494 | for (i = 0; i < 8; i++) |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 495 | index_addr_read_data(denali, addr | 2, &id_bytes[i]); |
| 496 | maf_id = id_bytes[0]; |
| 497 | device_id = id_bytes[1]; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 498 | |
| 499 | if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & |
| 500 | ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ |
| 501 | if (FAIL == get_onfi_nand_para(denali)) |
| 502 | return FAIL; |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 503 | } else if (maf_id == 0xEC) { /* Samsung NAND */ |
Chuanxiao Dong | 4c03bbd | 2010-08-06 15:45:19 +0800 | [diff] [blame] | 504 | get_samsung_nand_para(denali, device_id); |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 505 | } else if (maf_id == 0x98) { /* Toshiba NAND */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 506 | get_toshiba_nand_para(denali); |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 507 | } else if (maf_id == 0xAD) { /* Hynix NAND */ |
| 508 | get_hynix_nand_para(denali, device_id); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 509 | } |
| 510 | |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 511 | dev_info(denali->dev, |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 512 | "Dump timing register values:\n" |
Chuanxiao Dong | 7cfffac | 2010-08-10 00:16:51 +0800 | [diff] [blame] | 513 | "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" |
| 514 | "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 515 | "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", |
| 516 | ioread32(denali->flash_reg + ACC_CLKS), |
| 517 | ioread32(denali->flash_reg + RE_2_WE), |
Chuanxiao Dong | 7cfffac | 2010-08-10 00:16:51 +0800 | [diff] [blame] | 518 | ioread32(denali->flash_reg + RE_2_RE), |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 519 | ioread32(denali->flash_reg + WE_2_RE), |
| 520 | ioread32(denali->flash_reg + ADDR_2_DATA), |
| 521 | ioread32(denali->flash_reg + RDWR_EN_LO_CNT), |
| 522 | ioread32(denali->flash_reg + RDWR_EN_HI_CNT), |
| 523 | ioread32(denali->flash_reg + CS_SETUP_CNT)); |
| 524 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 525 | find_valid_banks(denali); |
| 526 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 527 | /* |
| 528 | * If the user specified to override the default timings |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 529 | * with a specific ONFI mode, we apply those changes here. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 530 | */ |
| 531 | if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 532 | nand_onfi_timing_set(denali, onfi_timing_mode); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 533 | |
| 534 | return status; |
| 535 | } |
| 536 | |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 537 | static void denali_set_intr_modes(struct denali_nand_info *denali, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 538 | uint16_t INT_ENABLE) |
| 539 | { |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 540 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 541 | __FILE__, __LINE__, __func__); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 542 | |
| 543 | if (INT_ENABLE) |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 544 | iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 545 | else |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 546 | iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 547 | } |
| 548 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 549 | /* |
| 550 | * validation function to verify that the controlling software is making |
Chuanxiao Dong | b292c34 | 2010-08-11 17:46:00 +0800 | [diff] [blame] | 551 | * a valid request |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 552 | */ |
| 553 | static inline bool is_flash_bank_valid(int flash_bank) |
| 554 | { |
Masahiro Yamada | 7d14ecd | 2014-09-16 20:04:24 +0900 | [diff] [blame] | 555 | return flash_bank >= 0 && flash_bank < 4; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 556 | } |
| 557 | |
| 558 | static void denali_irq_init(struct denali_nand_info *denali) |
| 559 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 560 | uint32_t int_mask; |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 561 | int i; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 562 | |
| 563 | /* Disable global interrupts */ |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 564 | denali_set_intr_modes(denali, false); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 565 | |
| 566 | int_mask = DENALI_IRQ_ALL; |
| 567 | |
| 568 | /* Clear all status bits */ |
Jamie Iles | c89eeda | 2011-05-06 15:28:57 +0100 | [diff] [blame] | 569 | for (i = 0; i < denali->max_banks; ++i) |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 570 | iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i)); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 571 | |
| 572 | denali_irq_enable(denali, int_mask); |
| 573 | } |
| 574 | |
| 575 | static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali) |
| 576 | { |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 577 | denali_set_intr_modes(denali, false); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 578 | } |
| 579 | |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 580 | static void denali_irq_enable(struct denali_nand_info *denali, |
| 581 | uint32_t int_mask) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 582 | { |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 583 | int i; |
| 584 | |
Jamie Iles | c89eeda | 2011-05-06 15:28:57 +0100 | [diff] [blame] | 585 | for (i = 0; i < denali->max_banks; ++i) |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 586 | iowrite32(int_mask, denali->flash_reg + INTR_EN(i)); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 587 | } |
| 588 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 589 | /* |
| 590 | * This function only returns when an interrupt that this driver cares about |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 591 | * occurs. This is to reduce the overhead of servicing interrupts |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 592 | */ |
| 593 | static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) |
| 594 | { |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 595 | return read_interrupt_status(denali) & DENALI_IRQ_ALL; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 596 | } |
| 597 | |
| 598 | /* Interrupts are cleared by writing a 1 to the appropriate status bit */ |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 599 | static inline void clear_interrupt(struct denali_nand_info *denali, |
| 600 | uint32_t irq_mask) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 601 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 602 | uint32_t intr_status_reg; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 603 | |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 604 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 605 | |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 606 | iowrite32(irq_mask, denali->flash_reg + intr_status_reg); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 607 | } |
| 608 | |
| 609 | static void clear_interrupts(struct denali_nand_info *denali) |
| 610 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 611 | uint32_t status; |
| 612 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 613 | spin_lock_irq(&denali->irq_lock); |
| 614 | |
| 615 | status = read_interrupt_status(denali); |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 616 | clear_interrupt(denali, status); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 617 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 618 | denali->irq_status = 0x0; |
| 619 | spin_unlock_irq(&denali->irq_lock); |
| 620 | } |
| 621 | |
| 622 | static uint32_t read_interrupt_status(struct denali_nand_info *denali) |
| 623 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 624 | uint32_t intr_status_reg; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 625 | |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 626 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 627 | |
| 628 | return ioread32(denali->flash_reg + intr_status_reg); |
| 629 | } |
| 630 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 631 | /* |
| 632 | * This is the interrupt service routine. It handles all interrupts |
| 633 | * sent to this device. Note that on CE4100, this is a shared interrupt. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 634 | */ |
| 635 | static irqreturn_t denali_isr(int irq, void *dev_id) |
| 636 | { |
| 637 | struct denali_nand_info *denali = dev_id; |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 638 | uint32_t irq_status; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 639 | irqreturn_t result = IRQ_NONE; |
| 640 | |
| 641 | spin_lock(&denali->irq_lock); |
| 642 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 643 | /* check to see if a valid NAND chip has been selected. */ |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 644 | if (is_flash_bank_valid(denali->flash_bank)) { |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 645 | /* |
| 646 | * check to see if controller generated the interrupt, |
| 647 | * since this is a shared interrupt |
| 648 | */ |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 649 | irq_status = denali_irq_detected(denali); |
| 650 | if (irq_status != 0) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 651 | /* handle interrupt */ |
| 652 | /* first acknowledge it */ |
| 653 | clear_interrupt(denali, irq_status); |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 654 | /* |
| 655 | * store the status in the device context for someone |
| 656 | * to read |
| 657 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 658 | denali->irq_status |= irq_status; |
| 659 | /* notify anyone who cares that it happened */ |
| 660 | complete(&denali->complete); |
| 661 | /* tell the OS that we've handled this */ |
| 662 | result = IRQ_HANDLED; |
| 663 | } |
| 664 | } |
| 665 | spin_unlock(&denali->irq_lock); |
| 666 | return result; |
| 667 | } |
| 668 | #define BANK(x) ((x) << 24) |
| 669 | |
| 670 | static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) |
| 671 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 672 | unsigned long comp_res; |
| 673 | uint32_t intr_status; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 674 | unsigned long timeout = msecs_to_jiffies(1000); |
| 675 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 676 | do { |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 677 | comp_res = |
| 678 | wait_for_completion_timeout(&denali->complete, timeout); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 679 | spin_lock_irq(&denali->irq_lock); |
| 680 | intr_status = denali->irq_status; |
| 681 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 682 | if (intr_status & irq_mask) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 683 | denali->irq_status &= ~irq_mask; |
| 684 | spin_unlock_irq(&denali->irq_lock); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 685 | /* our interrupt was detected */ |
| 686 | break; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 687 | } |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 688 | |
| 689 | /* |
| 690 | * these are not the interrupts you are looking for - |
| 691 | * need to wait again |
| 692 | */ |
| 693 | spin_unlock_irq(&denali->irq_lock); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 694 | } while (comp_res != 0); |
| 695 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 696 | if (comp_res == 0) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 697 | /* timeout */ |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 698 | pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n", |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 699 | intr_status, irq_mask); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 700 | |
| 701 | intr_status = 0; |
| 702 | } |
| 703 | return intr_status; |
| 704 | } |
| 705 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 706 | /* |
| 707 | * This helper function setups the registers for ECC and whether or not |
| 708 | * the spare area will be transferred. |
| 709 | */ |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 710 | static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 711 | bool transfer_spare) |
| 712 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 713 | int ecc_en_flag, transfer_spare_flag; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 714 | |
| 715 | /* set ECC, transfer spare bits if needed */ |
| 716 | ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; |
| 717 | transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0; |
| 718 | |
| 719 | /* Enable spare area/ECC per user's request. */ |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 720 | iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE); |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 721 | iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 722 | } |
| 723 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 724 | /* |
| 725 | * sends a pipeline command operation to the controller. See the Denali NAND |
Chuanxiao Dong | b292c34 | 2010-08-11 17:46:00 +0800 | [diff] [blame] | 726 | * controller's user guide for more information (section 4.2.3.6). |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 727 | */ |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 728 | static int denali_send_pipeline_cmd(struct denali_nand_info *denali, |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 729 | bool ecc_en, bool transfer_spare, |
| 730 | int access_type, int op) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 731 | { |
| 732 | int status = PASS; |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 733 | uint32_t page_count = 1; |
| 734 | uint32_t addr, cmd, irq_status, irq_mask; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 735 | |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 736 | if (op == DENALI_READ) |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 737 | irq_mask = INTR_STATUS__LOAD_COMP; |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 738 | else if (op == DENALI_WRITE) |
| 739 | irq_mask = 0; |
| 740 | else |
| 741 | BUG(); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 742 | |
| 743 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); |
| 744 | |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 745 | clear_interrupts(denali); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 746 | |
| 747 | addr = BANK(denali->flash_bank) | denali->page; |
| 748 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 749 | if (op == DENALI_WRITE && access_type != SPARE_ACCESS) { |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 750 | cmd = MODE_01 | addr; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 751 | iowrite32(cmd, denali->flash_mem); |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 752 | } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 753 | /* read spare area */ |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 754 | cmd = MODE_10 | addr; |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 755 | index_addr(denali, cmd, access_type); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 756 | |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 757 | cmd = MODE_01 | addr; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 758 | iowrite32(cmd, denali->flash_mem); |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 759 | } else if (op == DENALI_READ) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 760 | /* setup page read request for access type */ |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 761 | cmd = MODE_10 | addr; |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 762 | index_addr(denali, cmd, access_type); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 763 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 764 | /* |
| 765 | * page 33 of the NAND controller spec indicates we should not |
| 766 | * use the pipeline commands in Spare area only mode. |
| 767 | * So we don't. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 768 | */ |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 769 | if (access_type == SPARE_ACCESS) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 770 | cmd = MODE_01 | addr; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 771 | iowrite32(cmd, denali->flash_mem); |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 772 | } else { |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 773 | index_addr(denali, cmd, |
Masahiro Yamada | 2902330 | 2014-07-11 11:14:05 +0900 | [diff] [blame] | 774 | PIPELINE_ACCESS | op | page_count); |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 775 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 776 | /* |
| 777 | * wait for command to be accepted |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 778 | * can always use status0 bit as the |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 779 | * mask is identical for each bank. |
| 780 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 781 | irq_status = wait_for_irq(denali, irq_mask); |
| 782 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 783 | if (irq_status == 0) { |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 784 | dev_err(denali->dev, |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 785 | "cmd, page, addr on timeout (0x%x, 0x%x, 0x%x)\n", |
| 786 | cmd, denali->page, addr); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 787 | status = FAIL; |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 788 | } else { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 789 | cmd = MODE_01 | addr; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 790 | iowrite32(cmd, denali->flash_mem); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 791 | } |
| 792 | } |
| 793 | } |
| 794 | return status; |
| 795 | } |
| 796 | |
| 797 | /* helper function that simply writes a buffer to the flash */ |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 798 | static int write_data_to_flash_mem(struct denali_nand_info *denali, |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 799 | const uint8_t *buf, int len) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 800 | { |
Masahiro Yamada | 93e3c8a | 2014-09-09 11:01:54 +0900 | [diff] [blame] | 801 | uint32_t *buf32; |
| 802 | int i; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 803 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 804 | /* |
| 805 | * verify that the len is a multiple of 4. |
| 806 | * see comment in read_data_from_flash_mem() |
| 807 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 808 | BUG_ON((len % 4) != 0); |
| 809 | |
| 810 | /* write the data to the flash memory */ |
| 811 | buf32 = (uint32_t *)buf; |
| 812 | for (i = 0; i < len / 4; i++) |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 813 | iowrite32(*buf32++, denali->flash_mem + 0x10); |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 814 | return i * 4; /* intent is to return the number of bytes read */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 815 | } |
| 816 | |
| 817 | /* helper function that simply reads a buffer from the flash */ |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 818 | static int read_data_from_flash_mem(struct denali_nand_info *denali, |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 819 | uint8_t *buf, int len) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 820 | { |
Masahiro Yamada | 93e3c8a | 2014-09-09 11:01:54 +0900 | [diff] [blame] | 821 | uint32_t *buf32; |
| 822 | int i; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 823 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 824 | /* |
| 825 | * we assume that len will be a multiple of 4, if not it would be nice |
| 826 | * to know about it ASAP rather than have random failures... |
| 827 | * This assumption is based on the fact that this function is designed |
| 828 | * to be used to read flash pages, which are typically multiples of 4. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 829 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 830 | BUG_ON((len % 4) != 0); |
| 831 | |
| 832 | /* transfer the data from the flash */ |
| 833 | buf32 = (uint32_t *)buf; |
| 834 | for (i = 0; i < len / 4; i++) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 835 | *buf32++ = ioread32(denali->flash_mem + 0x10); |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 836 | return i * 4; /* intent is to return the number of bytes read */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 837 | } |
| 838 | |
| 839 | /* writes OOB data to the device */ |
| 840 | static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) |
| 841 | { |
| 842 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 843 | uint32_t irq_status; |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 844 | uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | |
| 845 | INTR_STATUS__PROGRAM_FAIL; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 846 | int status = 0; |
| 847 | |
| 848 | denali->page = page; |
| 849 | |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 850 | if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS, |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 851 | DENALI_WRITE) == PASS) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 852 | write_data_to_flash_mem(denali, buf, mtd->oobsize); |
| 853 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 854 | /* wait for operation to complete */ |
| 855 | irq_status = wait_for_irq(denali, irq_mask); |
| 856 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 857 | if (irq_status == 0) { |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 858 | dev_err(denali->dev, "OOB write failed\n"); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 859 | status = -EIO; |
| 860 | } |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 861 | } else { |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 862 | dev_err(denali->dev, "unable to send pipeline command\n"); |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 863 | status = -EIO; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 864 | } |
| 865 | return status; |
| 866 | } |
| 867 | |
| 868 | /* reads OOB data from the device */ |
| 869 | static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) |
| 870 | { |
| 871 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 872 | uint32_t irq_mask = INTR_STATUS__LOAD_COMP; |
| 873 | uint32_t irq_status, addr, cmd; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 874 | |
| 875 | denali->page = page; |
| 876 | |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 877 | if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 878 | DENALI_READ) == PASS) { |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 879 | read_data_from_flash_mem(denali, buf, mtd->oobsize); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 880 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 881 | /* |
| 882 | * wait for command to be accepted |
| 883 | * can always use status0 bit as the |
| 884 | * mask is identical for each bank. |
| 885 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 886 | irq_status = wait_for_irq(denali, irq_mask); |
| 887 | |
| 888 | if (irq_status == 0) |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 889 | dev_err(denali->dev, "page on OOB timeout %d\n", |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 890 | denali->page); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 891 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 892 | /* |
| 893 | * We set the device back to MAIN_ACCESS here as I observed |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 894 | * instability with the controller if you do a block erase |
| 895 | * and the last transaction was a SPARE_ACCESS. Block erase |
| 896 | * is reliable (according to the MTD test infrastructure) |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 897 | * if you are in MAIN_ACCESS. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 898 | */ |
| 899 | addr = BANK(denali->flash_bank) | denali->page; |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 900 | cmd = MODE_10 | addr; |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 901 | index_addr(denali, cmd, MAIN_ACCESS); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 902 | } |
| 903 | } |
| 904 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 905 | /* |
| 906 | * this function examines buffers to see if they contain data that |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 907 | * indicate that the buffer is part of an erased region of flash. |
| 908 | */ |
Rashika Kheria | 919193c | 2013-12-13 12:46:04 +0530 | [diff] [blame] | 909 | static bool is_erased(uint8_t *buf, int len) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 910 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 911 | int i; |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 912 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 913 | for (i = 0; i < len; i++) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 914 | if (buf[i] != 0xFF) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 915 | return false; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 916 | return true; |
| 917 | } |
| 918 | #define ECC_SECTOR_SIZE 512 |
| 919 | |
| 920 | #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12) |
| 921 | #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET)) |
| 922 | #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK) |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 923 | #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE)) |
| 924 | #define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 925 | #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO) |
| 926 | |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 927 | static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 928 | uint32_t irq_status, unsigned int *max_bitflips) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 929 | { |
| 930 | bool check_erased_page = false; |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 931 | unsigned int bitflips = 0; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 932 | |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 933 | if (irq_status & INTR_STATUS__ECC_ERR) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 934 | /* read the ECC errors. we'll ignore them for now */ |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 935 | uint32_t err_address, err_correction_info, err_byte, |
| 936 | err_sector, err_device, err_correction_value; |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 937 | denali_set_intr_modes(denali, false); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 938 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 939 | do { |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 940 | err_address = ioread32(denali->flash_reg + |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 941 | ECC_ERROR_ADDRESS); |
| 942 | err_sector = ECC_SECTOR(err_address); |
| 943 | err_byte = ECC_BYTE(err_address); |
| 944 | |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 945 | err_correction_info = ioread32(denali->flash_reg + |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 946 | ERR_CORRECTION_INFO); |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 947 | err_correction_value = |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 948 | ECC_CORRECTION_VALUE(err_correction_info); |
| 949 | err_device = ECC_ERR_DEVICE(err_correction_info); |
| 950 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 951 | if (ECC_ERROR_CORRECTABLE(err_correction_info)) { |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 952 | /* |
| 953 | * If err_byte is larger than ECC_SECTOR_SIZE, |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 954 | * means error happened in OOB, so we ignore |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 955 | * it. It's no need for us to correct it |
| 956 | * err_device is represented the NAND error |
| 957 | * bits are happened in if there are more |
| 958 | * than one NAND connected. |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 959 | */ |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 960 | if (err_byte < ECC_SECTOR_SIZE) { |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 961 | struct mtd_info *mtd = |
| 962 | nand_to_mtd(&denali->nand); |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 963 | int offset; |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 964 | |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 965 | offset = (err_sector * |
| 966 | ECC_SECTOR_SIZE + |
| 967 | err_byte) * |
| 968 | denali->devnum + |
| 969 | err_device; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 970 | /* correct the ECC error */ |
| 971 | buf[offset] ^= err_correction_value; |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 972 | mtd->ecc_stats.corrected++; |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 973 | bitflips++; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 974 | } |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 975 | } else { |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 976 | /* |
| 977 | * if the error is not correctable, need to |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 978 | * look at the page to see if it is an erased |
| 979 | * page. if so, then it's not a real ECC error |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 980 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 981 | check_erased_page = true; |
| 982 | } |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 983 | } while (!ECC_LAST_ERR(err_correction_info)); |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 984 | /* |
| 985 | * Once handle all ecc errors, controller will triger |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 986 | * a ECC_TRANSACTION_DONE interrupt, so here just wait |
| 987 | * for a while for this interrupt |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 988 | */ |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 989 | while (!(read_interrupt_status(denali) & |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 990 | INTR_STATUS__ECC_TRANSACTION_DONE)) |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 991 | cpu_relax(); |
| 992 | clear_interrupts(denali); |
| 993 | denali_set_intr_modes(denali, true); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 994 | } |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 995 | *max_bitflips = bitflips; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 996 | return check_erased_page; |
| 997 | } |
| 998 | |
| 999 | /* programs the controller to either enable/disable DMA transfers */ |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1000 | static void denali_enable_dma(struct denali_nand_info *denali, bool en) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1001 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 1002 | iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1003 | ioread32(denali->flash_reg + DMA_ENABLE); |
| 1004 | } |
| 1005 | |
| 1006 | /* setups the HW to perform the data DMA */ |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1007 | static void denali_setup_dma(struct denali_nand_info *denali, int op) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1008 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 1009 | uint32_t mode; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1010 | const int page_count = 1; |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 1011 | uint32_t addr = denali->buf.dma_buf; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1012 | |
| 1013 | mode = MODE_10 | BANK(denali->flash_bank); |
| 1014 | |
| 1015 | /* DMA is a four step process */ |
| 1016 | |
| 1017 | /* 1. setup transfer type and # of pages */ |
| 1018 | index_addr(denali, mode | denali->page, 0x2000 | op | page_count); |
| 1019 | |
| 1020 | /* 2. set memory high address bits 23:8 */ |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 1021 | index_addr(denali, mode | ((addr >> 16) << 8), 0x2200); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1022 | |
| 1023 | /* 3. set memory low address bits 23:8 */ |
Graham Moore | 7c272ac | 2015-01-09 09:32:35 -0600 | [diff] [blame] | 1024 | index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1025 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1026 | /* 4. interrupt when complete, burst len = 64 bytes */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1027 | index_addr(denali, mode | 0x14000, 0x2400); |
| 1028 | } |
| 1029 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1030 | /* |
| 1031 | * writes a page. user specifies type, and this function handles the |
| 1032 | * configuration details. |
| 1033 | */ |
Josh Wu | fdbad98d | 2012-06-25 18:07:45 +0800 | [diff] [blame] | 1034 | static int write_page(struct mtd_info *mtd, struct nand_chip *chip, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1035 | const uint8_t *buf, bool raw_xfer) |
| 1036 | { |
| 1037 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1038 | dma_addr_t addr = denali->buf.dma_buf; |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 1039 | size_t size = mtd->writesize + mtd->oobsize; |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 1040 | uint32_t irq_status; |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 1041 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP | |
| 1042 | INTR_STATUS__PROGRAM_FAIL; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1043 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1044 | /* |
| 1045 | * if it is a raw xfer, we want to disable ecc and send the spare area. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1046 | * !raw_xfer - enable ecc |
| 1047 | * raw_xfer - transfer spare |
| 1048 | */ |
| 1049 | setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer); |
| 1050 | |
| 1051 | /* copy buffer into DMA buffer */ |
| 1052 | memcpy(denali->buf.buf, buf, mtd->writesize); |
| 1053 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1054 | if (raw_xfer) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1055 | /* transfer the data to the spare area */ |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1056 | memcpy(denali->buf.buf + mtd->writesize, |
| 1057 | chip->oob_poi, |
| 1058 | mtd->oobsize); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1059 | } |
| 1060 | |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 1061 | dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1062 | |
| 1063 | clear_interrupts(denali); |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1064 | denali_enable_dma(denali, true); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1065 | |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1066 | denali_setup_dma(denali, DENALI_WRITE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1067 | |
| 1068 | /* wait for operation to complete */ |
| 1069 | irq_status = wait_for_irq(denali, irq_mask); |
| 1070 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1071 | if (irq_status == 0) { |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 1072 | dev_err(denali->dev, "timeout on write_page (type = %d)\n", |
| 1073 | raw_xfer); |
Brian Norris | c115add | 2014-07-21 19:07:31 -0700 | [diff] [blame] | 1074 | denali->status = NAND_STATUS_FAIL; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1075 | } |
| 1076 | |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1077 | denali_enable_dma(denali, false); |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 1078 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE); |
Josh Wu | fdbad98d | 2012-06-25 18:07:45 +0800 | [diff] [blame] | 1079 | |
| 1080 | return 0; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1081 | } |
| 1082 | |
| 1083 | /* NAND core entry points */ |
| 1084 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1085 | /* |
| 1086 | * this is the callback that the NAND core calls to write a page. Since |
Chuanxiao Dong | b292c34 | 2010-08-11 17:46:00 +0800 | [diff] [blame] | 1087 | * writing a page with ECC or without is similar, all the work is done |
| 1088 | * by write_page above. |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1089 | */ |
Josh Wu | fdbad98d | 2012-06-25 18:07:45 +0800 | [diff] [blame] | 1090 | static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
Boris BREZILLON | 45aaeff | 2015-10-13 11:22:18 +0200 | [diff] [blame] | 1091 | const uint8_t *buf, int oob_required, int page) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1092 | { |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1093 | /* |
| 1094 | * for regular page writes, we let HW handle all the ECC |
| 1095 | * data written to the device. |
| 1096 | */ |
Josh Wu | fdbad98d | 2012-06-25 18:07:45 +0800 | [diff] [blame] | 1097 | return write_page(mtd, chip, buf, false); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1098 | } |
| 1099 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1100 | /* |
| 1101 | * This is the callback that the NAND core calls to write a page without ECC. |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1102 | * raw access is similar to ECC page writes, so all the work is done in the |
Chuanxiao Dong | b292c34 | 2010-08-11 17:46:00 +0800 | [diff] [blame] | 1103 | * write_page() function above. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1104 | */ |
Josh Wu | fdbad98d | 2012-06-25 18:07:45 +0800 | [diff] [blame] | 1105 | static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
Boris BREZILLON | 45aaeff | 2015-10-13 11:22:18 +0200 | [diff] [blame] | 1106 | const uint8_t *buf, int oob_required, |
| 1107 | int page) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1108 | { |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1109 | /* |
| 1110 | * for raw page writes, we want to disable ECC and simply write |
| 1111 | * whatever data is in the buffer. |
| 1112 | */ |
Josh Wu | fdbad98d | 2012-06-25 18:07:45 +0800 | [diff] [blame] | 1113 | return write_page(mtd, chip, buf, true); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1114 | } |
| 1115 | |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1116 | static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1117 | int page) |
| 1118 | { |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1119 | return write_oob_data(mtd, chip->oob_poi, page); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1120 | } |
| 1121 | |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1122 | static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, |
Shmulik Ladkani | 5c2ffb1 | 2012-05-09 13:06:35 +0300 | [diff] [blame] | 1123 | int page) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1124 | { |
| 1125 | read_oob_data(mtd, chip->oob_poi, page); |
| 1126 | |
Shmulik Ladkani | 5c2ffb1 | 2012-05-09 13:06:35 +0300 | [diff] [blame] | 1127 | return 0; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1128 | } |
| 1129 | |
| 1130 | static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, |
Brian Norris | 1fbb938 | 2012-05-02 10:14:55 -0700 | [diff] [blame] | 1131 | uint8_t *buf, int oob_required, int page) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1132 | { |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 1133 | unsigned int max_bitflips; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1134 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1135 | |
| 1136 | dma_addr_t addr = denali->buf.dma_buf; |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 1137 | size_t size = mtd->writesize + mtd->oobsize; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1138 | |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 1139 | uint32_t irq_status; |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 1140 | uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE | |
| 1141 | INTR_STATUS__ECC_ERR; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1142 | bool check_erased_page = false; |
| 1143 | |
Chuanxiao Dong | 7d8a26f | 2010-08-11 18:19:23 +0800 | [diff] [blame] | 1144 | if (page != denali->page) { |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 1145 | dev_err(denali->dev, |
| 1146 | "IN %s: page %d is not equal to denali->page %d", |
| 1147 | __func__, page, denali->page); |
Chuanxiao Dong | 7d8a26f | 2010-08-11 18:19:23 +0800 | [diff] [blame] | 1148 | BUG(); |
| 1149 | } |
| 1150 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1151 | setup_ecc_for_xfer(denali, true, false); |
| 1152 | |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1153 | denali_enable_dma(denali, true); |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 1154 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1155 | |
| 1156 | clear_interrupts(denali); |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1157 | denali_setup_dma(denali, DENALI_READ); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1158 | |
| 1159 | /* wait for operation to complete */ |
| 1160 | irq_status = wait_for_irq(denali, irq_mask); |
| 1161 | |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 1162 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1163 | |
| 1164 | memcpy(buf, denali->buf.buf, mtd->writesize); |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1165 | |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 1166 | check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips); |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1167 | denali_enable_dma(denali, false); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1168 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1169 | if (check_erased_page) { |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 1170 | read_oob_data(mtd, chip->oob_poi, denali->page); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1171 | |
| 1172 | /* check ECC failures that may have occurred on erased pages */ |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1173 | if (check_erased_page) { |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 1174 | if (!is_erased(buf, mtd->writesize)) |
| 1175 | mtd->ecc_stats.failed++; |
| 1176 | if (!is_erased(buf, mtd->oobsize)) |
| 1177 | mtd->ecc_stats.failed++; |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1178 | } |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1179 | } |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 1180 | return max_bitflips; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1181 | } |
| 1182 | |
| 1183 | static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
Brian Norris | 1fbb938 | 2012-05-02 10:14:55 -0700 | [diff] [blame] | 1184 | uint8_t *buf, int oob_required, int page) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1185 | { |
| 1186 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1187 | dma_addr_t addr = denali->buf.dma_buf; |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 1188 | size_t size = mtd->writesize + mtd->oobsize; |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 1189 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1190 | |
Chuanxiao Dong | 7d8a26f | 2010-08-11 18:19:23 +0800 | [diff] [blame] | 1191 | if (page != denali->page) { |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 1192 | dev_err(denali->dev, |
| 1193 | "IN %s: page %d is not equal to denali->page %d", |
| 1194 | __func__, page, denali->page); |
Chuanxiao Dong | 7d8a26f | 2010-08-11 18:19:23 +0800 | [diff] [blame] | 1195 | BUG(); |
| 1196 | } |
| 1197 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1198 | setup_ecc_for_xfer(denali, false, true); |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1199 | denali_enable_dma(denali, true); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1200 | |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 1201 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1202 | |
| 1203 | clear_interrupts(denali); |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1204 | denali_setup_dma(denali, DENALI_READ); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1205 | |
| 1206 | /* wait for operation to complete */ |
Brian Norris | ba5f2bc | 2014-09-19 09:37:19 -0700 | [diff] [blame] | 1207 | wait_for_irq(denali, irq_mask); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1208 | |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 1209 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1210 | |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1211 | denali_enable_dma(denali, false); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1212 | |
| 1213 | memcpy(buf, denali->buf.buf, mtd->writesize); |
| 1214 | memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize); |
| 1215 | |
| 1216 | return 0; |
| 1217 | } |
| 1218 | |
| 1219 | static uint8_t denali_read_byte(struct mtd_info *mtd) |
| 1220 | { |
| 1221 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1222 | uint8_t result = 0xff; |
| 1223 | |
| 1224 | if (denali->buf.head < denali->buf.tail) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1225 | result = denali->buf.buf[denali->buf.head++]; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1226 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1227 | return result; |
| 1228 | } |
| 1229 | |
| 1230 | static void denali_select_chip(struct mtd_info *mtd, int chip) |
| 1231 | { |
| 1232 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
Chuanxiao Dong | 7cfffac | 2010-08-10 00:16:51 +0800 | [diff] [blame] | 1233 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1234 | spin_lock_irq(&denali->irq_lock); |
| 1235 | denali->flash_bank = chip; |
| 1236 | spin_unlock_irq(&denali->irq_lock); |
| 1237 | } |
| 1238 | |
| 1239 | static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) |
| 1240 | { |
| 1241 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1242 | int status = denali->status; |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 1243 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1244 | denali->status = 0; |
| 1245 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1246 | return status; |
| 1247 | } |
| 1248 | |
Brian Norris | 49c50b9 | 2014-05-06 16:02:19 -0700 | [diff] [blame] | 1249 | static int denali_erase(struct mtd_info *mtd, int page) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1250 | { |
| 1251 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1252 | |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 1253 | uint32_t cmd, irq_status; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1254 | |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1255 | clear_interrupts(denali); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1256 | |
| 1257 | /* setup page read request for access type */ |
| 1258 | cmd = MODE_10 | BANK(denali->flash_bank) | page; |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 1259 | index_addr(denali, cmd, 0x1); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1260 | |
| 1261 | /* wait for erase to complete or failure to occur */ |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 1262 | irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | |
| 1263 | INTR_STATUS__ERASE_FAIL); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1264 | |
Masahiro Yamada | 7d14ecd | 2014-09-16 20:04:24 +0900 | [diff] [blame] | 1265 | return irq_status & INTR_STATUS__ERASE_FAIL ? NAND_STATUS_FAIL : PASS; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1266 | } |
| 1267 | |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1268 | static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1269 | int page) |
| 1270 | { |
| 1271 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 1272 | uint32_t addr, id; |
| 1273 | int i; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1274 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1275 | switch (cmd) { |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 1276 | case NAND_CMD_PAGEPROG: |
| 1277 | break; |
| 1278 | case NAND_CMD_STATUS: |
| 1279 | read_status(denali); |
| 1280 | break; |
| 1281 | case NAND_CMD_READID: |
Florian Fainelli | 42af8b5 | 2010-08-30 18:32:20 +0200 | [diff] [blame] | 1282 | case NAND_CMD_PARAM: |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 1283 | reset_buf(denali); |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1284 | /* |
| 1285 | * sometimes ManufactureId read from register is not right |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 1286 | * e.g. some of Micron MT29F32G08QAA MLC NAND chips |
| 1287 | * So here we send READID cmd to NAND insteand |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1288 | */ |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 1289 | addr = MODE_11 | BANK(denali->flash_bank); |
| 1290 | index_addr(denali, addr | 0, 0x90); |
Enrico Jorns | 9c07d09 | 2015-09-18 10:02:41 +0200 | [diff] [blame] | 1291 | index_addr(denali, addr | 1, col); |
grmoore@altera.com | d68a5c3 | 2014-06-23 14:21:10 -0500 | [diff] [blame] | 1292 | for (i = 0; i < 8; i++) { |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 1293 | index_addr_read_data(denali, addr | 2, &id); |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 1294 | write_byte_to_buf(denali, id); |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 1295 | } |
| 1296 | break; |
| 1297 | case NAND_CMD_READ0: |
| 1298 | case NAND_CMD_SEQIN: |
| 1299 | denali->page = page; |
| 1300 | break; |
| 1301 | case NAND_CMD_RESET: |
| 1302 | reset_bank(denali); |
| 1303 | break; |
| 1304 | case NAND_CMD_READOOB: |
| 1305 | /* TODO: Read OOB data */ |
| 1306 | break; |
| 1307 | default: |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1308 | pr_err(": unsupported command received 0x%x\n", cmd); |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 1309 | break; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1310 | } |
| 1311 | } |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1312 | /* end NAND core entry points */ |
| 1313 | |
| 1314 | /* Initialization code to bring the device up to a known good state */ |
| 1315 | static void denali_hw_init(struct denali_nand_info *denali) |
| 1316 | { |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1317 | /* |
| 1318 | * tell driver how many bit controller will skip before |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1319 | * writing ECC code in OOB, this register may be already |
| 1320 | * set by firmware. So we read this value out. |
| 1321 | * if this value is 0, just let it be. |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1322 | */ |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1323 | denali->bbtskipbytes = ioread32(denali->flash_reg + |
| 1324 | SPARE_AREA_SKIP_BYTES); |
Jamie Iles | bc27ede | 2011-06-06 17:11:34 +0100 | [diff] [blame] | 1325 | detect_max_banks(denali); |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 1326 | denali_nand_reset(denali); |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 1327 | iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED); |
| 1328 | iowrite32(CHIP_EN_DONT_CARE__FLAG, |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 1329 | denali->flash_reg + CHIP_ENABLE_DONT_CARE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1330 | |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 1331 | iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1332 | |
| 1333 | /* Should set value for these registers when init */ |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 1334 | iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES); |
| 1335 | iowrite32(1, denali->flash_reg + ECC_ENABLE); |
Chuanxiao Dong | 5eab6aaa | 2010-08-12 10:07:18 +0800 | [diff] [blame] | 1336 | denali_nand_timing_set(denali); |
| 1337 | denali_irq_init(denali); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1338 | } |
| 1339 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1340 | /* |
| 1341 | * Althogh controller spec said SLC ECC is forceb to be 4bit, |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1342 | * but denali controller in MRST only support 15bit and 8bit ECC |
| 1343 | * correction |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1344 | */ |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1345 | #define ECC_8BITS 14 |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1346 | #define ECC_15BITS 26 |
Boris Brezillon | 14fad62 | 2016-02-03 20:00:11 +0100 | [diff] [blame] | 1347 | |
| 1348 | static int denali_ooblayout_ecc(struct mtd_info *mtd, int section, |
| 1349 | struct mtd_oob_region *oobregion) |
| 1350 | { |
| 1351 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1352 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 1353 | |
| 1354 | if (section) |
| 1355 | return -ERANGE; |
| 1356 | |
| 1357 | oobregion->offset = denali->bbtskipbytes; |
| 1358 | oobregion->length = chip->ecc.total; |
| 1359 | |
| 1360 | return 0; |
| 1361 | } |
| 1362 | |
| 1363 | static int denali_ooblayout_free(struct mtd_info *mtd, int section, |
| 1364 | struct mtd_oob_region *oobregion) |
| 1365 | { |
| 1366 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1367 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 1368 | |
| 1369 | if (section) |
| 1370 | return -ERANGE; |
| 1371 | |
| 1372 | oobregion->offset = chip->ecc.total + denali->bbtskipbytes; |
| 1373 | oobregion->length = mtd->oobsize - oobregion->offset; |
| 1374 | |
| 1375 | return 0; |
| 1376 | } |
| 1377 | |
| 1378 | static const struct mtd_ooblayout_ops denali_ooblayout_ops = { |
| 1379 | .ecc = denali_ooblayout_ecc, |
| 1380 | .free = denali_ooblayout_free, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1381 | }; |
| 1382 | |
| 1383 | static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; |
| 1384 | static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; |
| 1385 | |
| 1386 | static struct nand_bbt_descr bbt_main_descr = { |
| 1387 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
| 1388 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, |
| 1389 | .offs = 8, |
| 1390 | .len = 4, |
| 1391 | .veroffs = 12, |
| 1392 | .maxblocks = 4, |
| 1393 | .pattern = bbt_pattern, |
| 1394 | }; |
| 1395 | |
| 1396 | static struct nand_bbt_descr bbt_mirror_descr = { |
| 1397 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
| 1398 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, |
| 1399 | .offs = 8, |
| 1400 | .len = 4, |
| 1401 | .veroffs = 12, |
| 1402 | .maxblocks = 4, |
| 1403 | .pattern = mirror_pattern, |
| 1404 | }; |
| 1405 | |
Uwe Kleine-König | 421f91d | 2010-06-11 12:17:00 +0200 | [diff] [blame] | 1406 | /* initialize driver data structures */ |
Brian Norris | 8c51943 | 2013-08-10 22:57:30 -0700 | [diff] [blame] | 1407 | static void denali_drv_init(struct denali_nand_info *denali) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1408 | { |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1409 | /* |
| 1410 | * the completion object will be used to notify |
| 1411 | * the callee that the interrupt is done |
| 1412 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1413 | init_completion(&denali->complete); |
| 1414 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1415 | /* |
| 1416 | * the spinlock will be used to synchronize the ISR with any |
| 1417 | * element that might be access shared data (interrupt status) |
| 1418 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1419 | spin_lock_init(&denali->irq_lock); |
| 1420 | |
| 1421 | /* indicate that MTD has not selected a valid bank yet */ |
| 1422 | denali->flash_bank = CHIP_SELECT_INVALID; |
| 1423 | |
| 1424 | /* initialize our irq_status variable to indicate no interrupts */ |
| 1425 | denali->irq_status = 0; |
| 1426 | } |
| 1427 | |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1428 | int denali_init(struct denali_nand_info *denali) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1429 | { |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 1430 | struct mtd_info *mtd = nand_to_mtd(&denali->nand); |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1431 | int ret; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1432 | |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1433 | if (denali->platform == INTEL_CE4100) { |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1434 | /* |
| 1435 | * Due to a silicon limitation, we can only support |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1436 | * ONFI timing mode 1 and below. |
| 1437 | */ |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1438 | if (onfi_timing_mode < -1 || onfi_timing_mode > 1) { |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1439 | pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n"); |
| 1440 | return -EINVAL; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1441 | } |
| 1442 | } |
| 1443 | |
Huang Shijie | e07caa3 | 2013-12-21 00:02:28 +0800 | [diff] [blame] | 1444 | /* allocate a temporary buffer for nand_scan_ident() */ |
| 1445 | denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE, |
| 1446 | GFP_DMA | GFP_KERNEL); |
| 1447 | if (!denali->buf.buf) |
| 1448 | return -ENOMEM; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1449 | |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 1450 | mtd->dev.parent = denali->dev; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1451 | denali_hw_init(denali); |
| 1452 | denali_drv_init(denali); |
| 1453 | |
Masahiro Yamada | 7ebb8d0 | 2016-11-09 13:35:27 +0900 | [diff] [blame] | 1454 | /* Request IRQ after all the hardware initialization is finished */ |
| 1455 | ret = devm_request_irq(denali->dev, denali->irq, denali_isr, |
| 1456 | IRQF_SHARED, DENALI_NAND_NAME, denali); |
| 1457 | if (ret) { |
Masahiro Yamada | 789ccf1 | 2016-11-09 13:35:24 +0900 | [diff] [blame] | 1458 | dev_err(denali->dev, "Unable to request IRQ\n"); |
Masahiro Yamada | 7ebb8d0 | 2016-11-09 13:35:27 +0900 | [diff] [blame] | 1459 | return ret; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1460 | } |
| 1461 | |
| 1462 | /* now that our ISR is registered, we can enable interrupts */ |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 1463 | denali_set_intr_modes(denali, true); |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 1464 | mtd->name = "denali-nand"; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1465 | |
| 1466 | /* register the driver with the NAND core subsystem */ |
| 1467 | denali->nand.select_chip = denali_select_chip; |
| 1468 | denali->nand.cmdfunc = denali_cmdfunc; |
| 1469 | denali->nand.read_byte = denali_read_byte; |
| 1470 | denali->nand.waitfunc = denali_waitfunc; |
| 1471 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1472 | /* |
| 1473 | * scan for NAND devices attached to the controller |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1474 | * this is the first stage in a two step process to register |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1475 | * with the nand subsystem |
| 1476 | */ |
Masahiro Yamada | a227d4e | 2016-11-09 13:35:28 +0900 | [diff] [blame^] | 1477 | ret = nand_scan_ident(mtd, denali->max_banks, NULL); |
| 1478 | if (ret) |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1479 | goto failed_req_irq; |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1480 | |
Huang Shijie | e07caa3 | 2013-12-21 00:02:28 +0800 | [diff] [blame] | 1481 | /* allocate the right size buffer now */ |
| 1482 | devm_kfree(denali->dev, denali->buf.buf); |
| 1483 | denali->buf.buf = devm_kzalloc(denali->dev, |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 1484 | mtd->writesize + mtd->oobsize, |
Huang Shijie | e07caa3 | 2013-12-21 00:02:28 +0800 | [diff] [blame] | 1485 | GFP_KERNEL); |
| 1486 | if (!denali->buf.buf) { |
| 1487 | ret = -ENOMEM; |
| 1488 | goto failed_req_irq; |
| 1489 | } |
| 1490 | |
| 1491 | /* Is 32-bit DMA supported? */ |
| 1492 | ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32)); |
| 1493 | if (ret) { |
Masahiro Yamada | 789ccf1 | 2016-11-09 13:35:24 +0900 | [diff] [blame] | 1494 | dev_err(denali->dev, "No usable DMA configuration\n"); |
Huang Shijie | e07caa3 | 2013-12-21 00:02:28 +0800 | [diff] [blame] | 1495 | goto failed_req_irq; |
| 1496 | } |
| 1497 | |
| 1498 | denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf, |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 1499 | mtd->writesize + mtd->oobsize, |
Huang Shijie | e07caa3 | 2013-12-21 00:02:28 +0800 | [diff] [blame] | 1500 | DMA_BIDIRECTIONAL); |
| 1501 | if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) { |
Masahiro Yamada | 789ccf1 | 2016-11-09 13:35:24 +0900 | [diff] [blame] | 1502 | dev_err(denali->dev, "Failed to map DMA buffer\n"); |
Huang Shijie | e07caa3 | 2013-12-21 00:02:28 +0800 | [diff] [blame] | 1503 | ret = -EIO; |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1504 | goto failed_req_irq; |
Chuanxiao.Dong | 66406524 | 2010-08-06 18:48:21 +0800 | [diff] [blame] | 1505 | } |
| 1506 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1507 | /* |
| 1508 | * support for multi nand |
| 1509 | * MTD known nothing about multi nand, so we should tell it |
| 1510 | * the real pagesize and anything necessery |
Chuanxiao Dong | 08b9ab9 | 2010-08-06 18:19:09 +0800 | [diff] [blame] | 1511 | */ |
| 1512 | denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); |
| 1513 | denali->nand.chipsize <<= (denali->devnum - 1); |
| 1514 | denali->nand.page_shift += (denali->devnum - 1); |
| 1515 | denali->nand.pagemask = (denali->nand.chipsize >> |
| 1516 | denali->nand.page_shift) - 1; |
| 1517 | denali->nand.bbt_erase_shift += (denali->devnum - 1); |
| 1518 | denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift; |
| 1519 | denali->nand.chip_shift += (denali->devnum - 1); |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 1520 | mtd->writesize <<= (denali->devnum - 1); |
| 1521 | mtd->oobsize <<= (denali->devnum - 1); |
| 1522 | mtd->erasesize <<= (denali->devnum - 1); |
| 1523 | mtd->size = denali->nand.numchips * denali->nand.chipsize; |
Chuanxiao Dong | 08b9ab9 | 2010-08-06 18:19:09 +0800 | [diff] [blame] | 1524 | denali->bbtskipbytes *= denali->devnum; |
| 1525 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1526 | /* |
| 1527 | * second stage of the NAND scan |
Chuanxiao | 5bac3acf | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1528 | * this stage requires information regarding ECC and |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1529 | * bad block management. |
| 1530 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1531 | |
| 1532 | /* Bad block management */ |
| 1533 | denali->nand.bbt_td = &bbt_main_descr; |
| 1534 | denali->nand.bbt_md = &bbt_mirror_descr; |
| 1535 | |
| 1536 | /* skip the scan for now until we have OOB read and write support */ |
Brian Norris | bb9ebd4e | 2011-05-31 16:31:23 -0700 | [diff] [blame] | 1537 | denali->nand.bbt_options |= NAND_BBT_USE_FLASH; |
Brian Norris | a40f734 | 2011-05-31 16:31:22 -0700 | [diff] [blame] | 1538 | denali->nand.options |= NAND_SKIP_BBTSCAN; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1539 | denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; |
| 1540 | |
Graham Moore | d99d728 | 2015-01-14 09:38:50 -0600 | [diff] [blame] | 1541 | /* no subpage writes on denali */ |
| 1542 | denali->nand.options |= NAND_NO_SUBPAGE_WRITE; |
| 1543 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1544 | /* |
| 1545 | * Denali Controller only support 15bit and 8bit ECC in MRST, |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1546 | * so just let controller do 15bit ECC for MLC and 8bit ECC for |
| 1547 | * SLC if possible. |
| 1548 | * */ |
Huang Shijie | 1d0ed69 | 2013-09-25 14:58:10 +0800 | [diff] [blame] | 1549 | if (!nand_is_slc(&denali->nand) && |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 1550 | (mtd->oobsize > (denali->bbtskipbytes + |
| 1551 | ECC_15BITS * (mtd->writesize / |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1552 | ECC_SECTOR_SIZE)))) { |
| 1553 | /* if MLC OOB size is large enough, use 15bit ECC*/ |
Mike Dunn | 6a918ba | 2012-03-11 14:21:11 -0700 | [diff] [blame] | 1554 | denali->nand.ecc.strength = 15; |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1555 | denali->nand.ecc.bytes = ECC_15BITS; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 1556 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 1557 | } else if (mtd->oobsize < (denali->bbtskipbytes + |
| 1558 | ECC_8BITS * (mtd->writesize / |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1559 | ECC_SECTOR_SIZE))) { |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 1560 | pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes"); |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1561 | goto failed_req_irq; |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1562 | } else { |
Mike Dunn | 6a918ba | 2012-03-11 14:21:11 -0700 | [diff] [blame] | 1563 | denali->nand.ecc.strength = 8; |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1564 | denali->nand.ecc.bytes = ECC_8BITS; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 1565 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1566 | } |
| 1567 | |
Boris Brezillon | 14fad62 | 2016-02-03 20:00:11 +0100 | [diff] [blame] | 1568 | mtd_set_ooblayout(mtd, &denali_ooblayout_ops); |
Chuanxiao Dong | 08b9ab9 | 2010-08-06 18:19:09 +0800 | [diff] [blame] | 1569 | denali->nand.ecc.bytes *= denali->devnum; |
Mike Dunn | 6a918ba | 2012-03-11 14:21:11 -0700 | [diff] [blame] | 1570 | denali->nand.ecc.strength *= denali->devnum; |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1571 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1572 | /* override the default read operations */ |
Chuanxiao Dong | 08b9ab9 | 2010-08-06 18:19:09 +0800 | [diff] [blame] | 1573 | denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1574 | denali->nand.ecc.read_page = denali_read_page; |
| 1575 | denali->nand.ecc.read_page_raw = denali_read_page_raw; |
| 1576 | denali->nand.ecc.write_page = denali_write_page; |
| 1577 | denali->nand.ecc.write_page_raw = denali_write_page_raw; |
| 1578 | denali->nand.ecc.read_oob = denali_read_oob; |
| 1579 | denali->nand.ecc.write_oob = denali_write_oob; |
Brian Norris | 49c50b9 | 2014-05-06 16:02:19 -0700 | [diff] [blame] | 1580 | denali->nand.erase = denali_erase; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1581 | |
Masahiro Yamada | a227d4e | 2016-11-09 13:35:28 +0900 | [diff] [blame^] | 1582 | ret = nand_scan_tail(mtd); |
| 1583 | if (ret) |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1584 | goto failed_req_irq; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1585 | |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 1586 | ret = mtd_device_register(mtd, NULL, 0); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1587 | if (ret) { |
Masahiro Yamada | 789ccf1 | 2016-11-09 13:35:24 +0900 | [diff] [blame] | 1588 | dev_err(denali->dev, "Failed to register MTD: %d\n", ret); |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1589 | goto failed_req_irq; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1590 | } |
| 1591 | return 0; |
| 1592 | |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1593 | failed_req_irq: |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1594 | denali_irq_cleanup(denali->irq, denali); |
| 1595 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1596 | return ret; |
| 1597 | } |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1598 | EXPORT_SYMBOL(denali_init); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1599 | |
| 1600 | /* driver exit point */ |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1601 | void denali_remove(struct denali_nand_info *denali) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1602 | { |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 1603 | struct mtd_info *mtd = nand_to_mtd(&denali->nand); |
Boris BREZILLON | 320092a | 2015-12-11 15:02:34 +0100 | [diff] [blame] | 1604 | /* |
| 1605 | * Pre-compute DMA buffer size to avoid any problems in case |
| 1606 | * nand_release() ever changes in a way that mtd->writesize and |
| 1607 | * mtd->oobsize are not reliable after this call. |
| 1608 | */ |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 1609 | int bufsize = mtd->writesize + mtd->oobsize; |
Boris BREZILLON | 320092a | 2015-12-11 15:02:34 +0100 | [diff] [blame] | 1610 | |
Boris BREZILLON | 442f201b | 2015-12-11 15:06:00 +0100 | [diff] [blame] | 1611 | nand_release(mtd); |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1612 | denali_irq_cleanup(denali->irq, denali); |
Boris BREZILLON | 320092a | 2015-12-11 15:02:34 +0100 | [diff] [blame] | 1613 | dma_unmap_single(denali->dev, denali->buf.dma_buf, bufsize, |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 1614 | DMA_BIDIRECTIONAL); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1615 | } |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1616 | EXPORT_SYMBOL(denali_remove); |