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Jason Robertsce082592010-05-13 15:57:33 +01001/*
2 * NAND Flash Controller Device Driver
3 * Copyright © 2009-2010, Intel Corporation and its suppliers.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
Jason Robertsce082592010-05-13 15:57:33 +010019#include <linux/interrupt.h>
20#include <linux/delay.h>
Jamie Iles84457942011-05-06 15:28:55 +010021#include <linux/dma-mapping.h>
Jason Robertsce082592010-05-13 15:57:33 +010022#include <linux/wait.h>
23#include <linux/mutex.h>
Jason Robertsce082592010-05-13 15:57:33 +010024#include <linux/mtd/mtd.h>
25#include <linux/module.h>
26
27#include "denali.h"
28
29MODULE_LICENSE("GPL");
30
Masahiro Yamada43914a22014-09-09 11:01:51 +090031/*
32 * We define a module parameter that allows the user to override
Jason Robertsce082592010-05-13 15:57:33 +010033 * the hardware and decide what timing mode should be used.
34 */
35#define NAND_DEFAULT_TIMINGS -1
36
37static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
38module_param(onfi_timing_mode, int, S_IRUGO);
Masahiro Yamada81254502014-09-16 20:04:25 +090039MODULE_PARM_DESC(onfi_timing_mode,
40 "Overrides default ONFI setting. -1 indicates use default timings");
Jason Robertsce082592010-05-13 15:57:33 +010041
42#define DENALI_NAND_NAME "denali-nand"
43
Masahiro Yamada43914a22014-09-09 11:01:51 +090044/*
45 * We define a macro here that combines all interrupts this driver uses into
46 * a single constant value, for convenience.
47 */
Jamie Iles9589bf52011-05-06 15:28:56 +010048#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
49 INTR_STATUS__ECC_TRANSACTION_DONE | \
50 INTR_STATUS__ECC_ERR | \
51 INTR_STATUS__PROGRAM_FAIL | \
52 INTR_STATUS__LOAD_COMP | \
53 INTR_STATUS__PROGRAM_COMP | \
54 INTR_STATUS__TIME_OUT | \
55 INTR_STATUS__ERASE_FAIL | \
56 INTR_STATUS__RST_COMP | \
57 INTR_STATUS__ERASE_COMP)
Jason Robertsce082592010-05-13 15:57:33 +010058
Masahiro Yamada43914a22014-09-09 11:01:51 +090059/*
60 * indicates whether or not the internal value for the flash bank is
61 * valid or not
62 */
Chuanxiao5bac3acf2010-08-05 23:06:04 +080063#define CHIP_SELECT_INVALID -1
Jason Robertsce082592010-05-13 15:57:33 +010064
65#define SUPPORT_8BITECC 1
66
Masahiro Yamada43914a22014-09-09 11:01:51 +090067/*
68 * This macro divides two integers and rounds fractional values up
69 * to the nearest integer value.
70 */
Jason Robertsce082592010-05-13 15:57:33 +010071#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
72
Masahiro Yamada43914a22014-09-09 11:01:51 +090073/*
74 * this macro allows us to convert from an MTD structure to our own
Jason Robertsce082592010-05-13 15:57:33 +010075 * device context (denali) structure.
76 */
Boris BREZILLON442f201b2015-12-11 15:06:00 +010077static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
78{
79 return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
80}
Jason Robertsce082592010-05-13 15:57:33 +010081
Masahiro Yamada43914a22014-09-09 11:01:51 +090082/*
83 * These constants are defined by the driver to enable common driver
84 * configuration options.
85 */
Jason Robertsce082592010-05-13 15:57:33 +010086#define SPARE_ACCESS 0x41
87#define MAIN_ACCESS 0x42
88#define MAIN_SPARE_ACCESS 0x43
Masahiro Yamada29023302014-07-11 11:14:05 +090089#define PIPELINE_ACCESS 0x2000
Jason Robertsce082592010-05-13 15:57:33 +010090
91#define DENALI_READ 0
92#define DENALI_WRITE 0x100
93
94/* types of device accesses. We can issue commands and get status */
95#define COMMAND_CYCLE 0
96#define ADDR_CYCLE 1
97#define STATUS_CYCLE 2
98
Masahiro Yamada43914a22014-09-09 11:01:51 +090099/*
100 * this is a helper macro that allows us to
101 * format the bank into the proper bits for the controller
102 */
Jason Robertsce082592010-05-13 15:57:33 +0100103#define BANK(x) ((x) << 24)
104
Jason Robertsce082592010-05-13 15:57:33 +0100105/* forward declarations */
106static void clear_interrupts(struct denali_nand_info *denali);
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800107static uint32_t wait_for_irq(struct denali_nand_info *denali,
108 uint32_t irq_mask);
109static void denali_irq_enable(struct denali_nand_info *denali,
110 uint32_t int_mask);
Jason Robertsce082592010-05-13 15:57:33 +0100111static uint32_t read_interrupt_status(struct denali_nand_info *denali);
112
Masahiro Yamada43914a22014-09-09 11:01:51 +0900113/*
114 * Certain operations for the denali NAND controller use an indexed mode to
115 * read/write data. The operation is performed by writing the address value
116 * of the command to the device memory followed by the data. This function
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800117 * abstracts this common operation.
Masahiro Yamada43914a22014-09-09 11:01:51 +0900118 */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800119static void index_addr(struct denali_nand_info *denali,
120 uint32_t address, uint32_t data)
Jason Robertsce082592010-05-13 15:57:33 +0100121{
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800122 iowrite32(address, denali->flash_mem);
123 iowrite32(data, denali->flash_mem + 0x10);
Jason Robertsce082592010-05-13 15:57:33 +0100124}
125
126/* Perform an indexed read of the device */
127static void index_addr_read_data(struct denali_nand_info *denali,
128 uint32_t address, uint32_t *pdata)
129{
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800130 iowrite32(address, denali->flash_mem);
Jason Robertsce082592010-05-13 15:57:33 +0100131 *pdata = ioread32(denali->flash_mem + 0x10);
132}
133
Masahiro Yamada43914a22014-09-09 11:01:51 +0900134/*
135 * We need to buffer some data for some of the NAND core routines.
136 * The operations manage buffering that data.
137 */
Jason Robertsce082592010-05-13 15:57:33 +0100138static void reset_buf(struct denali_nand_info *denali)
139{
140 denali->buf.head = denali->buf.tail = 0;
141}
142
143static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
144{
Jason Robertsce082592010-05-13 15:57:33 +0100145 denali->buf.buf[denali->buf.tail++] = byte;
146}
147
148/* reads the status of the device */
149static void read_status(struct denali_nand_info *denali)
150{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900151 uint32_t cmd;
Jason Robertsce082592010-05-13 15:57:33 +0100152
153 /* initialize the data buffer to store status */
154 reset_buf(denali);
155
Chuanxiao Dongf0bc0c72010-08-11 17:14:59 +0800156 cmd = ioread32(denali->flash_reg + WRITE_PROTECT);
157 if (cmd)
158 write_byte_to_buf(denali, NAND_STATUS_WP);
159 else
160 write_byte_to_buf(denali, 0);
Jason Robertsce082592010-05-13 15:57:33 +0100161}
162
163/* resets a specific device connected to the core */
164static void reset_bank(struct denali_nand_info *denali)
165{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900166 uint32_t irq_status;
Masahiro Yamada81254502014-09-16 20:04:25 +0900167 uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT;
Jason Robertsce082592010-05-13 15:57:33 +0100168
169 clear_interrupts(denali);
170
Jamie Iles9589bf52011-05-06 15:28:56 +0100171 iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
Jason Robertsce082592010-05-13 15:57:33 +0100172
173 irq_status = wait_for_irq(denali, irq_mask);
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800174
Jamie Iles9589bf52011-05-06 15:28:56 +0100175 if (irq_status & INTR_STATUS__TIME_OUT)
Jamie Iles84457942011-05-06 15:28:55 +0100176 dev_err(denali->dev, "reset bank failed.\n");
Jason Robertsce082592010-05-13 15:57:33 +0100177}
178
179/* Reset the flash controller */
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800180static uint16_t denali_nand_reset(struct denali_nand_info *denali)
Jason Robertsce082592010-05-13 15:57:33 +0100181{
Masahiro Yamada93e3c8a2014-09-09 11:01:54 +0900182 int i;
Jason Robertsce082592010-05-13 15:57:33 +0100183
Jamie Iles84457942011-05-06 15:28:55 +0100184 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
Masahiro Yamada81254502014-09-16 20:04:25 +0900185 __FILE__, __LINE__, __func__);
Jason Robertsce082592010-05-13 15:57:33 +0100186
Masahiro Yamada81254502014-09-16 20:04:25 +0900187 for (i = 0; i < denali->max_banks; i++)
Jamie Iles9589bf52011-05-06 15:28:56 +0100188 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
189 denali->flash_reg + INTR_STATUS(i));
Jason Robertsce082592010-05-13 15:57:33 +0100190
Masahiro Yamada81254502014-09-16 20:04:25 +0900191 for (i = 0; i < denali->max_banks; i++) {
Jamie Iles9589bf52011-05-06 15:28:56 +0100192 iowrite32(1 << i, denali->flash_reg + DEVICE_RESET);
Masahiro Yamada81254502014-09-16 20:04:25 +0900193 while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) &
Jamie Iles9589bf52011-05-06 15:28:56 +0100194 (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
Chuanxiao Dong628bfd412010-08-11 17:53:29 +0800195 cpu_relax();
Jamie Iles9589bf52011-05-06 15:28:56 +0100196 if (ioread32(denali->flash_reg + INTR_STATUS(i)) &
197 INTR_STATUS__TIME_OUT)
Jamie Iles84457942011-05-06 15:28:55 +0100198 dev_dbg(denali->dev,
Jason Robertsce082592010-05-13 15:57:33 +0100199 "NAND Reset operation timed out on bank %d\n", i);
200 }
201
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100202 for (i = 0; i < denali->max_banks; i++)
Jamie Iles9589bf52011-05-06 15:28:56 +0100203 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
Masahiro Yamada81254502014-09-16 20:04:25 +0900204 denali->flash_reg + INTR_STATUS(i));
Jason Robertsce082592010-05-13 15:57:33 +0100205
206 return PASS;
207}
208
Masahiro Yamada43914a22014-09-09 11:01:51 +0900209/*
210 * this routine calculates the ONFI timing values for a given mode and
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800211 * programs the clocking register accordingly. The mode is determined by
212 * the get_onfi_nand_para routine.
Jason Robertsce082592010-05-13 15:57:33 +0100213 */
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800214static void nand_onfi_timing_set(struct denali_nand_info *denali,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800215 uint16_t mode)
Jason Robertsce082592010-05-13 15:57:33 +0100216{
217 uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
218 uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
219 uint16_t Treh[6] = {30, 15, 15, 10, 10, 7};
220 uint16_t Trc[6] = {100, 50, 35, 30, 25, 20};
221 uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15};
222 uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5};
223 uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25};
224 uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70};
225 uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100};
226 uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100};
227 uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60};
228 uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15};
229
Jason Robertsce082592010-05-13 15:57:33 +0100230 uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
231 uint16_t dv_window = 0;
232 uint16_t en_lo, en_hi;
233 uint16_t acc_clks;
234 uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
235
Jamie Iles84457942011-05-06 15:28:55 +0100236 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
Masahiro Yamada81254502014-09-16 20:04:25 +0900237 __FILE__, __LINE__, __func__);
Jason Robertsce082592010-05-13 15:57:33 +0100238
239 en_lo = CEIL_DIV(Trp[mode], CLK_X);
240 en_hi = CEIL_DIV(Treh[mode], CLK_X);
241#if ONFI_BLOOM_TIME
242 if ((en_hi * CLK_X) < (Treh[mode] + 2))
243 en_hi++;
244#endif
245
246 if ((en_lo + en_hi) * CLK_X < Trc[mode])
247 en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X);
248
249 if ((en_lo + en_hi) < CLK_MULTI)
250 en_lo += CLK_MULTI - en_lo - en_hi;
251
252 while (dv_window < 8) {
253 data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode];
254
255 data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode];
256
Masahiro Yamada81254502014-09-16 20:04:25 +0900257 data_invalid = data_invalid_rhoh < data_invalid_rloh ?
258 data_invalid_rhoh : data_invalid_rloh;
Jason Robertsce082592010-05-13 15:57:33 +0100259
260 dv_window = data_invalid - Trea[mode];
261
262 if (dv_window < 8)
263 en_lo++;
264 }
265
266 acc_clks = CEIL_DIV(Trea[mode], CLK_X);
267
Masahiro Yamada7d14ecd2014-09-16 20:04:24 +0900268 while (acc_clks * CLK_X - Trea[mode] < 3)
Jason Robertsce082592010-05-13 15:57:33 +0100269 acc_clks++;
270
Masahiro Yamada7d14ecd2014-09-16 20:04:24 +0900271 if (data_invalid - acc_clks * CLK_X < 2)
Jamie Iles84457942011-05-06 15:28:55 +0100272 dev_warn(denali->dev, "%s, Line %d: Warning!\n",
Masahiro Yamada81254502014-09-16 20:04:25 +0900273 __FILE__, __LINE__);
Jason Robertsce082592010-05-13 15:57:33 +0100274
275 addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
276 re_2_we = CEIL_DIV(Trhw[mode], CLK_X);
277 re_2_re = CEIL_DIV(Trhz[mode], CLK_X);
278 we_2_re = CEIL_DIV(Twhr[mode], CLK_X);
279 cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X);
Jason Robertsce082592010-05-13 15:57:33 +0100280 if (cs_cnt == 0)
281 cs_cnt = 1;
282
283 if (Tcea[mode]) {
Masahiro Yamada7d14ecd2014-09-16 20:04:24 +0900284 while (cs_cnt * CLK_X + Trea[mode] < Tcea[mode])
Jason Robertsce082592010-05-13 15:57:33 +0100285 cs_cnt++;
286 }
287
288#if MODE5_WORKAROUND
289 if (mode == 5)
290 acc_clks = 5;
291#endif
292
293 /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
Masahiro Yamada7d14ecd2014-09-16 20:04:24 +0900294 if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 &&
295 ioread32(denali->flash_reg + DEVICE_ID) == 0x88)
Jason Robertsce082592010-05-13 15:57:33 +0100296 acc_clks = 6;
297
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800298 iowrite32(acc_clks, denali->flash_reg + ACC_CLKS);
299 iowrite32(re_2_we, denali->flash_reg + RE_2_WE);
300 iowrite32(re_2_re, denali->flash_reg + RE_2_RE);
301 iowrite32(we_2_re, denali->flash_reg + WE_2_RE);
302 iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
303 iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
304 iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
305 iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
Jason Robertsce082592010-05-13 15:57:33 +0100306}
307
Jason Robertsce082592010-05-13 15:57:33 +0100308/* queries the NAND device to see what ONFI modes it supports. */
309static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
310{
311 int i;
Masahiro Yamada43914a22014-09-09 11:01:51 +0900312
313 /*
314 * we needn't to do a reset here because driver has already
Chuanxiao Dong4c03bbd2010-08-06 15:45:19 +0800315 * reset all the banks before
Masahiro Yamada43914a22014-09-09 11:01:51 +0900316 */
Jason Robertsce082592010-05-13 15:57:33 +0100317 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
318 ONFI_TIMING_MODE__VALUE))
319 return FAIL;
320
321 for (i = 5; i > 0; i--) {
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800322 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
323 (0x01 << i))
Jason Robertsce082592010-05-13 15:57:33 +0100324 break;
325 }
326
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800327 nand_onfi_timing_set(denali, i);
Jason Robertsce082592010-05-13 15:57:33 +0100328
Masahiro Yamada43914a22014-09-09 11:01:51 +0900329 /*
330 * By now, all the ONFI devices we know support the page cache
331 * rw feature. So here we enable the pipeline_rw_ahead feature
332 */
Jason Robertsce082592010-05-13 15:57:33 +0100333 /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
334 /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */
335
336 return PASS;
337}
338
Chuanxiao Dong4c03bbd2010-08-06 15:45:19 +0800339static void get_samsung_nand_para(struct denali_nand_info *denali,
340 uint8_t device_id)
Jason Robertsce082592010-05-13 15:57:33 +0100341{
Chuanxiao Dong4c03bbd2010-08-06 15:45:19 +0800342 if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
Jason Robertsce082592010-05-13 15:57:33 +0100343 /* Set timing register values according to datasheet */
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800344 iowrite32(5, denali->flash_reg + ACC_CLKS);
345 iowrite32(20, denali->flash_reg + RE_2_WE);
346 iowrite32(12, denali->flash_reg + WE_2_RE);
347 iowrite32(14, denali->flash_reg + ADDR_2_DATA);
348 iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT);
349 iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT);
350 iowrite32(2, denali->flash_reg + CS_SETUP_CNT);
Jason Robertsce082592010-05-13 15:57:33 +0100351 }
Jason Robertsce082592010-05-13 15:57:33 +0100352}
353
354static void get_toshiba_nand_para(struct denali_nand_info *denali)
355{
Jason Robertsce082592010-05-13 15:57:33 +0100356 uint32_t tmp;
357
Masahiro Yamada43914a22014-09-09 11:01:51 +0900358 /*
359 * Workaround to fix a controller bug which reports a wrong
360 * spare area size for some kind of Toshiba NAND device
361 */
Jason Robertsce082592010-05-13 15:57:33 +0100362 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
363 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800364 iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
Jason Robertsce082592010-05-13 15:57:33 +0100365 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
366 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800367 iowrite32(tmp,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800368 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
Jason Robertsce082592010-05-13 15:57:33 +0100369#if SUPPORT_15BITECC
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800370 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +0100371#elif SUPPORT_8BITECC
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800372 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +0100373#endif
374 }
Jason Robertsce082592010-05-13 15:57:33 +0100375}
376
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800377static void get_hynix_nand_para(struct denali_nand_info *denali,
378 uint8_t device_id)
Jason Robertsce082592010-05-13 15:57:33 +0100379{
Jason Robertsce082592010-05-13 15:57:33 +0100380 uint32_t main_size, spare_size;
381
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800382 switch (device_id) {
Jason Robertsce082592010-05-13 15:57:33 +0100383 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
384 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800385 iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK);
386 iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
387 iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800388 main_size = 4096 *
389 ioread32(denali->flash_reg + DEVICES_CONNECTED);
390 spare_size = 224 *
391 ioread32(denali->flash_reg + DEVICES_CONNECTED);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800392 iowrite32(main_size,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800393 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800394 iowrite32(spare_size,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800395 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800396 iowrite32(0, denali->flash_reg + DEVICE_WIDTH);
Jason Robertsce082592010-05-13 15:57:33 +0100397#if SUPPORT_15BITECC
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800398 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +0100399#elif SUPPORT_8BITECC
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800400 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +0100401#endif
Jason Robertsce082592010-05-13 15:57:33 +0100402 break;
403 default:
Jamie Iles84457942011-05-06 15:28:55 +0100404 dev_warn(denali->dev,
Masahiro Yamada789ccf12016-11-09 13:35:24 +0900405 "Unknown Hynix NAND (Device ID: 0x%x).\n"
Masahiro Yamada81254502014-09-16 20:04:25 +0900406 "Will use default parameter values instead.\n",
407 device_id);
Jason Robertsce082592010-05-13 15:57:33 +0100408 }
409}
410
Masahiro Yamada43914a22014-09-09 11:01:51 +0900411/*
412 * determines how many NAND chips are connected to the controller. Note for
Chuanxiao Dongb292c342010-08-11 17:46:00 +0800413 * Intel CE4100 devices we don't support more than one device.
Jason Robertsce082592010-05-13 15:57:33 +0100414 */
415static void find_valid_banks(struct denali_nand_info *denali)
416{
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100417 uint32_t id[denali->max_banks];
Jason Robertsce082592010-05-13 15:57:33 +0100418 int i;
419
420 denali->total_used_banks = 1;
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100421 for (i = 0; i < denali->max_banks; i++) {
Masahiro Yamada3157d1e2014-09-09 11:01:53 +0900422 index_addr(denali, MODE_11 | (i << 24) | 0, 0x90);
423 index_addr(denali, MODE_11 | (i << 24) | 1, 0);
Masahiro Yamada81254502014-09-16 20:04:25 +0900424 index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]);
Jason Robertsce082592010-05-13 15:57:33 +0100425
Jamie Iles84457942011-05-06 15:28:55 +0100426 dev_dbg(denali->dev,
Jason Robertsce082592010-05-13 15:57:33 +0100427 "Return 1st ID for bank[%d]: %x\n", i, id[i]);
428
429 if (i == 0) {
430 if (!(id[i] & 0x0ff))
431 break; /* WTF? */
432 } else {
433 if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
434 denali->total_used_banks++;
435 else
436 break;
437 }
438 }
439
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800440 if (denali->platform == INTEL_CE4100) {
Masahiro Yamada43914a22014-09-09 11:01:51 +0900441 /*
442 * Platform limitations of the CE4100 device limit
Jason Robertsce082592010-05-13 15:57:33 +0100443 * users to a single chip solution for NAND.
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800444 * Multichip support is not enabled.
445 */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800446 if (denali->total_used_banks != 1) {
Jamie Iles84457942011-05-06 15:28:55 +0100447 dev_err(denali->dev,
Masahiro Yamada81254502014-09-16 20:04:25 +0900448 "Sorry, Intel CE4100 only supports a single NAND device.\n");
Jason Robertsce082592010-05-13 15:57:33 +0100449 BUG();
450 }
451 }
Jamie Iles84457942011-05-06 15:28:55 +0100452 dev_dbg(denali->dev,
Jason Robertsce082592010-05-13 15:57:33 +0100453 "denali->total_used_banks: %d\n", denali->total_used_banks);
454}
455
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100456/*
457 * Use the configuration feature register to determine the maximum number of
458 * banks that the hardware supports.
459 */
460static void detect_max_banks(struct denali_nand_info *denali)
461{
462 uint32_t features = ioread32(denali->flash_reg + FEATURES);
Graham Moore271707b2015-07-21 09:39:31 -0500463 /*
464 * Read the revision register, so we can calculate the max_banks
465 * properly: the encoding changed from rev 5.0 to 5.1
466 */
467 u32 revision = MAKE_COMPARABLE_REVISION(
468 ioread32(denali->flash_reg + REVISION));
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100469
Graham Moore271707b2015-07-21 09:39:31 -0500470 if (revision < REVISION_5_1)
471 denali->max_banks = 2 << (features & FEATURES__N_BANKS);
472 else
473 denali->max_banks = 1 << (features & FEATURES__N_BANKS);
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100474}
475
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800476static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
Jason Robertsce082592010-05-13 15:57:33 +0100477{
478 uint16_t status = PASS;
grmoore@altera.comd68a5c32014-06-23 14:21:10 -0500479 uint32_t id_bytes[8], addr;
Masahiro Yamada93e3c8a2014-09-09 11:01:54 +0900480 uint8_t maf_id, device_id;
481 int i;
Jason Robertsce082592010-05-13 15:57:33 +0100482
Masahiro Yamada81254502014-09-16 20:04:25 +0900483 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800484 __FILE__, __LINE__, __func__);
Jason Robertsce082592010-05-13 15:57:33 +0100485
Masahiro Yamada43914a22014-09-09 11:01:51 +0900486 /*
487 * Use read id method to get device ID and other params.
488 * For some NAND chips, controller can't report the correct
489 * device ID by reading from DEVICE_ID register
490 */
Masahiro Yamada3157d1e2014-09-09 11:01:53 +0900491 addr = MODE_11 | BANK(denali->flash_bank);
492 index_addr(denali, addr | 0, 0x90);
493 index_addr(denali, addr | 1, 0);
grmoore@altera.comd68a5c32014-06-23 14:21:10 -0500494 for (i = 0; i < 8; i++)
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800495 index_addr_read_data(denali, addr | 2, &id_bytes[i]);
496 maf_id = id_bytes[0];
497 device_id = id_bytes[1];
Jason Robertsce082592010-05-13 15:57:33 +0100498
499 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
500 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
501 if (FAIL == get_onfi_nand_para(denali))
502 return FAIL;
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800503 } else if (maf_id == 0xEC) { /* Samsung NAND */
Chuanxiao Dong4c03bbd2010-08-06 15:45:19 +0800504 get_samsung_nand_para(denali, device_id);
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800505 } else if (maf_id == 0x98) { /* Toshiba NAND */
Jason Robertsce082592010-05-13 15:57:33 +0100506 get_toshiba_nand_para(denali);
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800507 } else if (maf_id == 0xAD) { /* Hynix NAND */
508 get_hynix_nand_para(denali, device_id);
Jason Robertsce082592010-05-13 15:57:33 +0100509 }
510
Jamie Iles84457942011-05-06 15:28:55 +0100511 dev_info(denali->dev,
Masahiro Yamada81254502014-09-16 20:04:25 +0900512 "Dump timing register values:\n"
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800513 "acc_clks: %d, re_2_we: %d, re_2_re: %d\n"
514 "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n"
Jason Robertsce082592010-05-13 15:57:33 +0100515 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
516 ioread32(denali->flash_reg + ACC_CLKS),
517 ioread32(denali->flash_reg + RE_2_WE),
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800518 ioread32(denali->flash_reg + RE_2_RE),
Jason Robertsce082592010-05-13 15:57:33 +0100519 ioread32(denali->flash_reg + WE_2_RE),
520 ioread32(denali->flash_reg + ADDR_2_DATA),
521 ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
522 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
523 ioread32(denali->flash_reg + CS_SETUP_CNT));
524
Jason Robertsce082592010-05-13 15:57:33 +0100525 find_valid_banks(denali);
526
Masahiro Yamada43914a22014-09-09 11:01:51 +0900527 /*
528 * If the user specified to override the default timings
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800529 * with a specific ONFI mode, we apply those changes here.
Jason Robertsce082592010-05-13 15:57:33 +0100530 */
531 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800532 nand_onfi_timing_set(denali, onfi_timing_mode);
Jason Robertsce082592010-05-13 15:57:33 +0100533
534 return status;
535}
536
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800537static void denali_set_intr_modes(struct denali_nand_info *denali,
Jason Robertsce082592010-05-13 15:57:33 +0100538 uint16_t INT_ENABLE)
539{
Jamie Iles84457942011-05-06 15:28:55 +0100540 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
Masahiro Yamada81254502014-09-16 20:04:25 +0900541 __FILE__, __LINE__, __func__);
Jason Robertsce082592010-05-13 15:57:33 +0100542
543 if (INT_ENABLE)
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800544 iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
Jason Robertsce082592010-05-13 15:57:33 +0100545 else
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800546 iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
Jason Robertsce082592010-05-13 15:57:33 +0100547}
548
Masahiro Yamada43914a22014-09-09 11:01:51 +0900549/*
550 * validation function to verify that the controlling software is making
Chuanxiao Dongb292c342010-08-11 17:46:00 +0800551 * a valid request
Jason Robertsce082592010-05-13 15:57:33 +0100552 */
553static inline bool is_flash_bank_valid(int flash_bank)
554{
Masahiro Yamada7d14ecd2014-09-16 20:04:24 +0900555 return flash_bank >= 0 && flash_bank < 4;
Jason Robertsce082592010-05-13 15:57:33 +0100556}
557
558static void denali_irq_init(struct denali_nand_info *denali)
559{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900560 uint32_t int_mask;
Jamie Iles9589bf52011-05-06 15:28:56 +0100561 int i;
Jason Robertsce082592010-05-13 15:57:33 +0100562
563 /* Disable global interrupts */
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800564 denali_set_intr_modes(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +0100565
566 int_mask = DENALI_IRQ_ALL;
567
568 /* Clear all status bits */
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100569 for (i = 0; i < denali->max_banks; ++i)
Jamie Iles9589bf52011-05-06 15:28:56 +0100570 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i));
Jason Robertsce082592010-05-13 15:57:33 +0100571
572 denali_irq_enable(denali, int_mask);
573}
574
575static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
576{
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800577 denali_set_intr_modes(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +0100578}
579
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800580static void denali_irq_enable(struct denali_nand_info *denali,
581 uint32_t int_mask)
Jason Robertsce082592010-05-13 15:57:33 +0100582{
Jamie Iles9589bf52011-05-06 15:28:56 +0100583 int i;
584
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100585 for (i = 0; i < denali->max_banks; ++i)
Jamie Iles9589bf52011-05-06 15:28:56 +0100586 iowrite32(int_mask, denali->flash_reg + INTR_EN(i));
Jason Robertsce082592010-05-13 15:57:33 +0100587}
588
Masahiro Yamada43914a22014-09-09 11:01:51 +0900589/*
590 * This function only returns when an interrupt that this driver cares about
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800591 * occurs. This is to reduce the overhead of servicing interrupts
Jason Robertsce082592010-05-13 15:57:33 +0100592 */
593static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
594{
Chuanxiao Donga99d1792010-07-27 11:32:21 +0800595 return read_interrupt_status(denali) & DENALI_IRQ_ALL;
Jason Robertsce082592010-05-13 15:57:33 +0100596}
597
598/* Interrupts are cleared by writing a 1 to the appropriate status bit */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800599static inline void clear_interrupt(struct denali_nand_info *denali,
600 uint32_t irq_mask)
Jason Robertsce082592010-05-13 15:57:33 +0100601{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900602 uint32_t intr_status_reg;
Jason Robertsce082592010-05-13 15:57:33 +0100603
Jamie Iles9589bf52011-05-06 15:28:56 +0100604 intr_status_reg = INTR_STATUS(denali->flash_bank);
Jason Robertsce082592010-05-13 15:57:33 +0100605
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800606 iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
Jason Robertsce082592010-05-13 15:57:33 +0100607}
608
609static void clear_interrupts(struct denali_nand_info *denali)
610{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900611 uint32_t status;
612
Jason Robertsce082592010-05-13 15:57:33 +0100613 spin_lock_irq(&denali->irq_lock);
614
615 status = read_interrupt_status(denali);
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800616 clear_interrupt(denali, status);
Jason Robertsce082592010-05-13 15:57:33 +0100617
Jason Robertsce082592010-05-13 15:57:33 +0100618 denali->irq_status = 0x0;
619 spin_unlock_irq(&denali->irq_lock);
620}
621
622static uint32_t read_interrupt_status(struct denali_nand_info *denali)
623{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900624 uint32_t intr_status_reg;
Jason Robertsce082592010-05-13 15:57:33 +0100625
Jamie Iles9589bf52011-05-06 15:28:56 +0100626 intr_status_reg = INTR_STATUS(denali->flash_bank);
Jason Robertsce082592010-05-13 15:57:33 +0100627
628 return ioread32(denali->flash_reg + intr_status_reg);
629}
630
Masahiro Yamada43914a22014-09-09 11:01:51 +0900631/*
632 * This is the interrupt service routine. It handles all interrupts
633 * sent to this device. Note that on CE4100, this is a shared interrupt.
Jason Robertsce082592010-05-13 15:57:33 +0100634 */
635static irqreturn_t denali_isr(int irq, void *dev_id)
636{
637 struct denali_nand_info *denali = dev_id;
Masahiro Yamada5637b692014-09-09 11:01:52 +0900638 uint32_t irq_status;
Jason Robertsce082592010-05-13 15:57:33 +0100639 irqreturn_t result = IRQ_NONE;
640
641 spin_lock(&denali->irq_lock);
642
Masahiro Yamada43914a22014-09-09 11:01:51 +0900643 /* check to see if a valid NAND chip has been selected. */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800644 if (is_flash_bank_valid(denali->flash_bank)) {
Masahiro Yamada43914a22014-09-09 11:01:51 +0900645 /*
646 * check to see if controller generated the interrupt,
647 * since this is a shared interrupt
648 */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800649 irq_status = denali_irq_detected(denali);
650 if (irq_status != 0) {
Jason Robertsce082592010-05-13 15:57:33 +0100651 /* handle interrupt */
652 /* first acknowledge it */
653 clear_interrupt(denali, irq_status);
Masahiro Yamada43914a22014-09-09 11:01:51 +0900654 /*
655 * store the status in the device context for someone
656 * to read
657 */
Jason Robertsce082592010-05-13 15:57:33 +0100658 denali->irq_status |= irq_status;
659 /* notify anyone who cares that it happened */
660 complete(&denali->complete);
661 /* tell the OS that we've handled this */
662 result = IRQ_HANDLED;
663 }
664 }
665 spin_unlock(&denali->irq_lock);
666 return result;
667}
668#define BANK(x) ((x) << 24)
669
670static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
671{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900672 unsigned long comp_res;
673 uint32_t intr_status;
Jason Robertsce082592010-05-13 15:57:33 +0100674 unsigned long timeout = msecs_to_jiffies(1000);
675
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800676 do {
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800677 comp_res =
678 wait_for_completion_timeout(&denali->complete, timeout);
Jason Robertsce082592010-05-13 15:57:33 +0100679 spin_lock_irq(&denali->irq_lock);
680 intr_status = denali->irq_status;
681
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800682 if (intr_status & irq_mask) {
Jason Robertsce082592010-05-13 15:57:33 +0100683 denali->irq_status &= ~irq_mask;
684 spin_unlock_irq(&denali->irq_lock);
Jason Robertsce082592010-05-13 15:57:33 +0100685 /* our interrupt was detected */
686 break;
Jason Robertsce082592010-05-13 15:57:33 +0100687 }
Masahiro Yamada81254502014-09-16 20:04:25 +0900688
689 /*
690 * these are not the interrupts you are looking for -
691 * need to wait again
692 */
693 spin_unlock_irq(&denali->irq_lock);
Jason Robertsce082592010-05-13 15:57:33 +0100694 } while (comp_res != 0);
695
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800696 if (comp_res == 0) {
Jason Robertsce082592010-05-13 15:57:33 +0100697 /* timeout */
Dinh Nguyen2a0a2882012-09-27 10:58:05 -0600698 pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n",
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800699 intr_status, irq_mask);
Jason Robertsce082592010-05-13 15:57:33 +0100700
701 intr_status = 0;
702 }
703 return intr_status;
704}
705
Masahiro Yamada43914a22014-09-09 11:01:51 +0900706/*
707 * This helper function setups the registers for ECC and whether or not
708 * the spare area will be transferred.
709 */
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800710static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
Jason Robertsce082592010-05-13 15:57:33 +0100711 bool transfer_spare)
712{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900713 int ecc_en_flag, transfer_spare_flag;
Jason Robertsce082592010-05-13 15:57:33 +0100714
715 /* set ECC, transfer spare bits if needed */
716 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
717 transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
718
719 /* Enable spare area/ECC per user's request. */
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800720 iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
Masahiro Yamada81254502014-09-16 20:04:25 +0900721 iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);
Jason Robertsce082592010-05-13 15:57:33 +0100722}
723
Masahiro Yamada43914a22014-09-09 11:01:51 +0900724/*
725 * sends a pipeline command operation to the controller. See the Denali NAND
Chuanxiao Dongb292c342010-08-11 17:46:00 +0800726 * controller's user guide for more information (section 4.2.3.6).
Jason Robertsce082592010-05-13 15:57:33 +0100727 */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800728static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
Masahiro Yamada81254502014-09-16 20:04:25 +0900729 bool ecc_en, bool transfer_spare,
730 int access_type, int op)
Jason Robertsce082592010-05-13 15:57:33 +0100731{
732 int status = PASS;
Masahiro Yamada5637b692014-09-09 11:01:52 +0900733 uint32_t page_count = 1;
734 uint32_t addr, cmd, irq_status, irq_mask;
Jason Robertsce082592010-05-13 15:57:33 +0100735
Chuanxiao Donga99d1792010-07-27 11:32:21 +0800736 if (op == DENALI_READ)
Jamie Iles9589bf52011-05-06 15:28:56 +0100737 irq_mask = INTR_STATUS__LOAD_COMP;
Chuanxiao Donga99d1792010-07-27 11:32:21 +0800738 else if (op == DENALI_WRITE)
739 irq_mask = 0;
740 else
741 BUG();
Jason Robertsce082592010-05-13 15:57:33 +0100742
743 setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
744
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800745 clear_interrupts(denali);
Jason Robertsce082592010-05-13 15:57:33 +0100746
747 addr = BANK(denali->flash_bank) | denali->page;
748
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800749 if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800750 cmd = MODE_01 | addr;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800751 iowrite32(cmd, denali->flash_mem);
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800752 } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
Jason Robertsce082592010-05-13 15:57:33 +0100753 /* read spare area */
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800754 cmd = MODE_10 | addr;
Masahiro Yamada3157d1e2014-09-09 11:01:53 +0900755 index_addr(denali, cmd, access_type);
Jason Robertsce082592010-05-13 15:57:33 +0100756
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800757 cmd = MODE_01 | addr;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800758 iowrite32(cmd, denali->flash_mem);
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800759 } else if (op == DENALI_READ) {
Jason Robertsce082592010-05-13 15:57:33 +0100760 /* setup page read request for access type */
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800761 cmd = MODE_10 | addr;
Masahiro Yamada3157d1e2014-09-09 11:01:53 +0900762 index_addr(denali, cmd, access_type);
Jason Robertsce082592010-05-13 15:57:33 +0100763
Masahiro Yamada43914a22014-09-09 11:01:51 +0900764 /*
765 * page 33 of the NAND controller spec indicates we should not
766 * use the pipeline commands in Spare area only mode.
767 * So we don't.
Jason Robertsce082592010-05-13 15:57:33 +0100768 */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800769 if (access_type == SPARE_ACCESS) {
Jason Robertsce082592010-05-13 15:57:33 +0100770 cmd = MODE_01 | addr;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800771 iowrite32(cmd, denali->flash_mem);
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800772 } else {
Masahiro Yamada3157d1e2014-09-09 11:01:53 +0900773 index_addr(denali, cmd,
Masahiro Yamada29023302014-07-11 11:14:05 +0900774 PIPELINE_ACCESS | op | page_count);
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800775
Masahiro Yamada43914a22014-09-09 11:01:51 +0900776 /*
777 * wait for command to be accepted
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800778 * can always use status0 bit as the
Masahiro Yamada43914a22014-09-09 11:01:51 +0900779 * mask is identical for each bank.
780 */
Jason Robertsce082592010-05-13 15:57:33 +0100781 irq_status = wait_for_irq(denali, irq_mask);
782
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800783 if (irq_status == 0) {
Jamie Iles84457942011-05-06 15:28:55 +0100784 dev_err(denali->dev,
Masahiro Yamada81254502014-09-16 20:04:25 +0900785 "cmd, page, addr on timeout (0x%x, 0x%x, 0x%x)\n",
786 cmd, denali->page, addr);
Jason Robertsce082592010-05-13 15:57:33 +0100787 status = FAIL;
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800788 } else {
Jason Robertsce082592010-05-13 15:57:33 +0100789 cmd = MODE_01 | addr;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800790 iowrite32(cmd, denali->flash_mem);
Jason Robertsce082592010-05-13 15:57:33 +0100791 }
792 }
793 }
794 return status;
795}
796
797/* helper function that simply writes a buffer to the flash */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800798static int write_data_to_flash_mem(struct denali_nand_info *denali,
Masahiro Yamada81254502014-09-16 20:04:25 +0900799 const uint8_t *buf, int len)
Jason Robertsce082592010-05-13 15:57:33 +0100800{
Masahiro Yamada93e3c8a2014-09-09 11:01:54 +0900801 uint32_t *buf32;
802 int i;
Jason Robertsce082592010-05-13 15:57:33 +0100803
Masahiro Yamada43914a22014-09-09 11:01:51 +0900804 /*
805 * verify that the len is a multiple of 4.
806 * see comment in read_data_from_flash_mem()
807 */
Jason Robertsce082592010-05-13 15:57:33 +0100808 BUG_ON((len % 4) != 0);
809
810 /* write the data to the flash memory */
811 buf32 = (uint32_t *)buf;
812 for (i = 0; i < len / 4; i++)
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800813 iowrite32(*buf32++, denali->flash_mem + 0x10);
Masahiro Yamada81254502014-09-16 20:04:25 +0900814 return i * 4; /* intent is to return the number of bytes read */
Jason Robertsce082592010-05-13 15:57:33 +0100815}
816
817/* helper function that simply reads a buffer from the flash */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800818static int read_data_from_flash_mem(struct denali_nand_info *denali,
Masahiro Yamada81254502014-09-16 20:04:25 +0900819 uint8_t *buf, int len)
Jason Robertsce082592010-05-13 15:57:33 +0100820{
Masahiro Yamada93e3c8a2014-09-09 11:01:54 +0900821 uint32_t *buf32;
822 int i;
Jason Robertsce082592010-05-13 15:57:33 +0100823
Masahiro Yamada43914a22014-09-09 11:01:51 +0900824 /*
825 * we assume that len will be a multiple of 4, if not it would be nice
826 * to know about it ASAP rather than have random failures...
827 * This assumption is based on the fact that this function is designed
828 * to be used to read flash pages, which are typically multiples of 4.
Jason Robertsce082592010-05-13 15:57:33 +0100829 */
Jason Robertsce082592010-05-13 15:57:33 +0100830 BUG_ON((len % 4) != 0);
831
832 /* transfer the data from the flash */
833 buf32 = (uint32_t *)buf;
834 for (i = 0; i < len / 4; i++)
Jason Robertsce082592010-05-13 15:57:33 +0100835 *buf32++ = ioread32(denali->flash_mem + 0x10);
Masahiro Yamada81254502014-09-16 20:04:25 +0900836 return i * 4; /* intent is to return the number of bytes read */
Jason Robertsce082592010-05-13 15:57:33 +0100837}
838
839/* writes OOB data to the device */
840static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
841{
842 struct denali_nand_info *denali = mtd_to_denali(mtd);
Masahiro Yamada5637b692014-09-09 11:01:52 +0900843 uint32_t irq_status;
Jamie Iles9589bf52011-05-06 15:28:56 +0100844 uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
845 INTR_STATUS__PROGRAM_FAIL;
Jason Robertsce082592010-05-13 15:57:33 +0100846 int status = 0;
847
848 denali->page = page;
849
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800850 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800851 DENALI_WRITE) == PASS) {
Jason Robertsce082592010-05-13 15:57:33 +0100852 write_data_to_flash_mem(denali, buf, mtd->oobsize);
853
Jason Robertsce082592010-05-13 15:57:33 +0100854 /* wait for operation to complete */
855 irq_status = wait_for_irq(denali, irq_mask);
856
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800857 if (irq_status == 0) {
Jamie Iles84457942011-05-06 15:28:55 +0100858 dev_err(denali->dev, "OOB write failed\n");
Jason Robertsce082592010-05-13 15:57:33 +0100859 status = -EIO;
860 }
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800861 } else {
Jamie Iles84457942011-05-06 15:28:55 +0100862 dev_err(denali->dev, "unable to send pipeline command\n");
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800863 status = -EIO;
Jason Robertsce082592010-05-13 15:57:33 +0100864 }
865 return status;
866}
867
868/* reads OOB data from the device */
869static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
870{
871 struct denali_nand_info *denali = mtd_to_denali(mtd);
Masahiro Yamada5637b692014-09-09 11:01:52 +0900872 uint32_t irq_mask = INTR_STATUS__LOAD_COMP;
873 uint32_t irq_status, addr, cmd;
Jason Robertsce082592010-05-13 15:57:33 +0100874
875 denali->page = page;
876
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800877 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800878 DENALI_READ) == PASS) {
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800879 read_data_from_flash_mem(denali, buf, mtd->oobsize);
Jason Robertsce082592010-05-13 15:57:33 +0100880
Masahiro Yamada43914a22014-09-09 11:01:51 +0900881 /*
882 * wait for command to be accepted
883 * can always use status0 bit as the
884 * mask is identical for each bank.
885 */
Jason Robertsce082592010-05-13 15:57:33 +0100886 irq_status = wait_for_irq(denali, irq_mask);
887
888 if (irq_status == 0)
Jamie Iles84457942011-05-06 15:28:55 +0100889 dev_err(denali->dev, "page on OOB timeout %d\n",
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800890 denali->page);
Jason Robertsce082592010-05-13 15:57:33 +0100891
Masahiro Yamada43914a22014-09-09 11:01:51 +0900892 /*
893 * We set the device back to MAIN_ACCESS here as I observed
Jason Robertsce082592010-05-13 15:57:33 +0100894 * instability with the controller if you do a block erase
895 * and the last transaction was a SPARE_ACCESS. Block erase
896 * is reliable (according to the MTD test infrastructure)
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800897 * if you are in MAIN_ACCESS.
Jason Robertsce082592010-05-13 15:57:33 +0100898 */
899 addr = BANK(denali->flash_bank) | denali->page;
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800900 cmd = MODE_10 | addr;
Masahiro Yamada3157d1e2014-09-09 11:01:53 +0900901 index_addr(denali, cmd, MAIN_ACCESS);
Jason Robertsce082592010-05-13 15:57:33 +0100902 }
903}
904
Masahiro Yamada43914a22014-09-09 11:01:51 +0900905/*
906 * this function examines buffers to see if they contain data that
Jason Robertsce082592010-05-13 15:57:33 +0100907 * indicate that the buffer is part of an erased region of flash.
908 */
Rashika Kheria919193c2013-12-13 12:46:04 +0530909static bool is_erased(uint8_t *buf, int len)
Jason Robertsce082592010-05-13 15:57:33 +0100910{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900911 int i;
Masahiro Yamada81254502014-09-16 20:04:25 +0900912
Jason Robertsce082592010-05-13 15:57:33 +0100913 for (i = 0; i < len; i++)
Jason Robertsce082592010-05-13 15:57:33 +0100914 if (buf[i] != 0xFF)
Jason Robertsce082592010-05-13 15:57:33 +0100915 return false;
Jason Robertsce082592010-05-13 15:57:33 +0100916 return true;
917}
918#define ECC_SECTOR_SIZE 512
919
920#define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
921#define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET))
922#define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800923#define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE))
924#define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8)
Jason Robertsce082592010-05-13 15:57:33 +0100925#define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
926
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800927static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
Mike Dunn3f91e942012-04-25 12:06:09 -0700928 uint32_t irq_status, unsigned int *max_bitflips)
Jason Robertsce082592010-05-13 15:57:33 +0100929{
930 bool check_erased_page = false;
Mike Dunn3f91e942012-04-25 12:06:09 -0700931 unsigned int bitflips = 0;
Jason Robertsce082592010-05-13 15:57:33 +0100932
Jamie Iles9589bf52011-05-06 15:28:56 +0100933 if (irq_status & INTR_STATUS__ECC_ERR) {
Jason Robertsce082592010-05-13 15:57:33 +0100934 /* read the ECC errors. we'll ignore them for now */
Masahiro Yamada5637b692014-09-09 11:01:52 +0900935 uint32_t err_address, err_correction_info, err_byte,
936 err_sector, err_device, err_correction_value;
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800937 denali_set_intr_modes(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +0100938
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800939 do {
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800940 err_address = ioread32(denali->flash_reg +
Jason Robertsce082592010-05-13 15:57:33 +0100941 ECC_ERROR_ADDRESS);
942 err_sector = ECC_SECTOR(err_address);
943 err_byte = ECC_BYTE(err_address);
944
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800945 err_correction_info = ioread32(denali->flash_reg +
Jason Robertsce082592010-05-13 15:57:33 +0100946 ERR_CORRECTION_INFO);
Chuanxiao5bac3acf2010-08-05 23:06:04 +0800947 err_correction_value =
Jason Robertsce082592010-05-13 15:57:33 +0100948 ECC_CORRECTION_VALUE(err_correction_info);
949 err_device = ECC_ERR_DEVICE(err_correction_info);
950
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800951 if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
Masahiro Yamada43914a22014-09-09 11:01:51 +0900952 /*
953 * If err_byte is larger than ECC_SECTOR_SIZE,
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300954 * means error happened in OOB, so we ignore
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800955 * it. It's no need for us to correct it
956 * err_device is represented the NAND error
957 * bits are happened in if there are more
958 * than one NAND connected.
Masahiro Yamada43914a22014-09-09 11:01:51 +0900959 */
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800960 if (err_byte < ECC_SECTOR_SIZE) {
Boris BREZILLON442f201b2015-12-11 15:06:00 +0100961 struct mtd_info *mtd =
962 nand_to_mtd(&denali->nand);
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800963 int offset;
Masahiro Yamada81254502014-09-16 20:04:25 +0900964
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800965 offset = (err_sector *
966 ECC_SECTOR_SIZE +
967 err_byte) *
968 denali->devnum +
969 err_device;
Jason Robertsce082592010-05-13 15:57:33 +0100970 /* correct the ECC error */
971 buf[offset] ^= err_correction_value;
Boris BREZILLON442f201b2015-12-11 15:06:00 +0100972 mtd->ecc_stats.corrected++;
Mike Dunn3f91e942012-04-25 12:06:09 -0700973 bitflips++;
Jason Robertsce082592010-05-13 15:57:33 +0100974 }
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800975 } else {
Masahiro Yamada43914a22014-09-09 11:01:51 +0900976 /*
977 * if the error is not correctable, need to
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800978 * look at the page to see if it is an erased
979 * page. if so, then it's not a real ECC error
Masahiro Yamada43914a22014-09-09 11:01:51 +0900980 */
Jason Robertsce082592010-05-13 15:57:33 +0100981 check_erased_page = true;
982 }
Jason Robertsce082592010-05-13 15:57:33 +0100983 } while (!ECC_LAST_ERR(err_correction_info));
Masahiro Yamada43914a22014-09-09 11:01:51 +0900984 /*
985 * Once handle all ecc errors, controller will triger
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800986 * a ECC_TRANSACTION_DONE interrupt, so here just wait
987 * for a while for this interrupt
Masahiro Yamada43914a22014-09-09 11:01:51 +0900988 */
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800989 while (!(read_interrupt_status(denali) &
Jamie Iles9589bf52011-05-06 15:28:56 +0100990 INTR_STATUS__ECC_TRANSACTION_DONE))
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800991 cpu_relax();
992 clear_interrupts(denali);
993 denali_set_intr_modes(denali, true);
Jason Robertsce082592010-05-13 15:57:33 +0100994 }
Mike Dunn3f91e942012-04-25 12:06:09 -0700995 *max_bitflips = bitflips;
Jason Robertsce082592010-05-13 15:57:33 +0100996 return check_erased_page;
997}
998
999/* programs the controller to either enable/disable DMA transfers */
David Woodhouseaadff492010-05-13 16:12:43 +01001000static void denali_enable_dma(struct denali_nand_info *denali, bool en)
Jason Robertsce082592010-05-13 15:57:33 +01001001{
Masahiro Yamada5637b692014-09-09 11:01:52 +09001002 iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE);
Jason Robertsce082592010-05-13 15:57:33 +01001003 ioread32(denali->flash_reg + DMA_ENABLE);
1004}
1005
1006/* setups the HW to perform the data DMA */
David Woodhouseaadff492010-05-13 16:12:43 +01001007static void denali_setup_dma(struct denali_nand_info *denali, int op)
Jason Robertsce082592010-05-13 15:57:33 +01001008{
Masahiro Yamada5637b692014-09-09 11:01:52 +09001009 uint32_t mode;
Jason Robertsce082592010-05-13 15:57:33 +01001010 const int page_count = 1;
Masahiro Yamada3157d1e2014-09-09 11:01:53 +09001011 uint32_t addr = denali->buf.dma_buf;
Jason Robertsce082592010-05-13 15:57:33 +01001012
1013 mode = MODE_10 | BANK(denali->flash_bank);
1014
1015 /* DMA is a four step process */
1016
1017 /* 1. setup transfer type and # of pages */
1018 index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
1019
1020 /* 2. set memory high address bits 23:8 */
Masahiro Yamada3157d1e2014-09-09 11:01:53 +09001021 index_addr(denali, mode | ((addr >> 16) << 8), 0x2200);
Jason Robertsce082592010-05-13 15:57:33 +01001022
1023 /* 3. set memory low address bits 23:8 */
Graham Moore7c272ac2015-01-09 09:32:35 -06001024 index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300);
Jason Robertsce082592010-05-13 15:57:33 +01001025
Masahiro Yamada43914a22014-09-09 11:01:51 +09001026 /* 4. interrupt when complete, burst len = 64 bytes */
Jason Robertsce082592010-05-13 15:57:33 +01001027 index_addr(denali, mode | 0x14000, 0x2400);
1028}
1029
Masahiro Yamada43914a22014-09-09 11:01:51 +09001030/*
1031 * writes a page. user specifies type, and this function handles the
1032 * configuration details.
1033 */
Josh Wufdbad98d2012-06-25 18:07:45 +08001034static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
Jason Robertsce082592010-05-13 15:57:33 +01001035 const uint8_t *buf, bool raw_xfer)
1036{
1037 struct denali_nand_info *denali = mtd_to_denali(mtd);
Jason Robertsce082592010-05-13 15:57:33 +01001038 dma_addr_t addr = denali->buf.dma_buf;
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001039 size_t size = mtd->writesize + mtd->oobsize;
Masahiro Yamada5637b692014-09-09 11:01:52 +09001040 uint32_t irq_status;
Jamie Iles9589bf52011-05-06 15:28:56 +01001041 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP |
1042 INTR_STATUS__PROGRAM_FAIL;
Jason Robertsce082592010-05-13 15:57:33 +01001043
Masahiro Yamada43914a22014-09-09 11:01:51 +09001044 /*
1045 * if it is a raw xfer, we want to disable ecc and send the spare area.
Jason Robertsce082592010-05-13 15:57:33 +01001046 * !raw_xfer - enable ecc
1047 * raw_xfer - transfer spare
1048 */
1049 setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer);
1050
1051 /* copy buffer into DMA buffer */
1052 memcpy(denali->buf.buf, buf, mtd->writesize);
1053
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001054 if (raw_xfer) {
Jason Robertsce082592010-05-13 15:57:33 +01001055 /* transfer the data to the spare area */
Chuanxiao5bac3acf2010-08-05 23:06:04 +08001056 memcpy(denali->buf.buf + mtd->writesize,
1057 chip->oob_poi,
1058 mtd->oobsize);
Jason Robertsce082592010-05-13 15:57:33 +01001059 }
1060
Jamie Iles84457942011-05-06 15:28:55 +01001061 dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE);
Jason Robertsce082592010-05-13 15:57:33 +01001062
1063 clear_interrupts(denali);
Chuanxiao5bac3acf2010-08-05 23:06:04 +08001064 denali_enable_dma(denali, true);
Jason Robertsce082592010-05-13 15:57:33 +01001065
David Woodhouseaadff492010-05-13 16:12:43 +01001066 denali_setup_dma(denali, DENALI_WRITE);
Jason Robertsce082592010-05-13 15:57:33 +01001067
1068 /* wait for operation to complete */
1069 irq_status = wait_for_irq(denali, irq_mask);
1070
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001071 if (irq_status == 0) {
Masahiro Yamada81254502014-09-16 20:04:25 +09001072 dev_err(denali->dev, "timeout on write_page (type = %d)\n",
1073 raw_xfer);
Brian Norrisc115add2014-07-21 19:07:31 -07001074 denali->status = NAND_STATUS_FAIL;
Jason Robertsce082592010-05-13 15:57:33 +01001075 }
1076
Chuanxiao5bac3acf2010-08-05 23:06:04 +08001077 denali_enable_dma(denali, false);
Jamie Iles84457942011-05-06 15:28:55 +01001078 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE);
Josh Wufdbad98d2012-06-25 18:07:45 +08001079
1080 return 0;
Jason Robertsce082592010-05-13 15:57:33 +01001081}
1082
1083/* NAND core entry points */
1084
Masahiro Yamada43914a22014-09-09 11:01:51 +09001085/*
1086 * this is the callback that the NAND core calls to write a page. Since
Chuanxiao Dongb292c342010-08-11 17:46:00 +08001087 * writing a page with ECC or without is similar, all the work is done
1088 * by write_page above.
Masahiro Yamada43914a22014-09-09 11:01:51 +09001089 */
Josh Wufdbad98d2012-06-25 18:07:45 +08001090static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
Boris BREZILLON45aaeff2015-10-13 11:22:18 +02001091 const uint8_t *buf, int oob_required, int page)
Jason Robertsce082592010-05-13 15:57:33 +01001092{
Masahiro Yamada43914a22014-09-09 11:01:51 +09001093 /*
1094 * for regular page writes, we let HW handle all the ECC
1095 * data written to the device.
1096 */
Josh Wufdbad98d2012-06-25 18:07:45 +08001097 return write_page(mtd, chip, buf, false);
Jason Robertsce082592010-05-13 15:57:33 +01001098}
1099
Masahiro Yamada43914a22014-09-09 11:01:51 +09001100/*
1101 * This is the callback that the NAND core calls to write a page without ECC.
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001102 * raw access is similar to ECC page writes, so all the work is done in the
Chuanxiao Dongb292c342010-08-11 17:46:00 +08001103 * write_page() function above.
Jason Robertsce082592010-05-13 15:57:33 +01001104 */
Josh Wufdbad98d2012-06-25 18:07:45 +08001105static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
Boris BREZILLON45aaeff2015-10-13 11:22:18 +02001106 const uint8_t *buf, int oob_required,
1107 int page)
Jason Robertsce082592010-05-13 15:57:33 +01001108{
Masahiro Yamada43914a22014-09-09 11:01:51 +09001109 /*
1110 * for raw page writes, we want to disable ECC and simply write
1111 * whatever data is in the buffer.
1112 */
Josh Wufdbad98d2012-06-25 18:07:45 +08001113 return write_page(mtd, chip, buf, true);
Jason Robertsce082592010-05-13 15:57:33 +01001114}
1115
Chuanxiao5bac3acf2010-08-05 23:06:04 +08001116static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
Jason Robertsce082592010-05-13 15:57:33 +01001117 int page)
1118{
Chuanxiao5bac3acf2010-08-05 23:06:04 +08001119 return write_oob_data(mtd, chip->oob_poi, page);
Jason Robertsce082592010-05-13 15:57:33 +01001120}
1121
Chuanxiao5bac3acf2010-08-05 23:06:04 +08001122static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
Shmulik Ladkani5c2ffb12012-05-09 13:06:35 +03001123 int page)
Jason Robertsce082592010-05-13 15:57:33 +01001124{
1125 read_oob_data(mtd, chip->oob_poi, page);
1126
Shmulik Ladkani5c2ffb12012-05-09 13:06:35 +03001127 return 0;
Jason Robertsce082592010-05-13 15:57:33 +01001128}
1129
1130static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
Brian Norris1fbb9382012-05-02 10:14:55 -07001131 uint8_t *buf, int oob_required, int page)
Jason Robertsce082592010-05-13 15:57:33 +01001132{
Mike Dunn3f91e942012-04-25 12:06:09 -07001133 unsigned int max_bitflips;
Jason Robertsce082592010-05-13 15:57:33 +01001134 struct denali_nand_info *denali = mtd_to_denali(mtd);
Jason Robertsce082592010-05-13 15:57:33 +01001135
1136 dma_addr_t addr = denali->buf.dma_buf;
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001137 size_t size = mtd->writesize + mtd->oobsize;
Jason Robertsce082592010-05-13 15:57:33 +01001138
Masahiro Yamada5637b692014-09-09 11:01:52 +09001139 uint32_t irq_status;
Jamie Iles9589bf52011-05-06 15:28:56 +01001140 uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE |
1141 INTR_STATUS__ECC_ERR;
Jason Robertsce082592010-05-13 15:57:33 +01001142 bool check_erased_page = false;
1143
Chuanxiao Dong7d8a26f2010-08-11 18:19:23 +08001144 if (page != denali->page) {
Masahiro Yamada81254502014-09-16 20:04:25 +09001145 dev_err(denali->dev,
1146 "IN %s: page %d is not equal to denali->page %d",
1147 __func__, page, denali->page);
Chuanxiao Dong7d8a26f2010-08-11 18:19:23 +08001148 BUG();
1149 }
1150
Jason Robertsce082592010-05-13 15:57:33 +01001151 setup_ecc_for_xfer(denali, true, false);
1152
David Woodhouseaadff492010-05-13 16:12:43 +01001153 denali_enable_dma(denali, true);
Jamie Iles84457942011-05-06 15:28:55 +01001154 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
Jason Robertsce082592010-05-13 15:57:33 +01001155
1156 clear_interrupts(denali);
David Woodhouseaadff492010-05-13 16:12:43 +01001157 denali_setup_dma(denali, DENALI_READ);
Jason Robertsce082592010-05-13 15:57:33 +01001158
1159 /* wait for operation to complete */
1160 irq_status = wait_for_irq(denali, irq_mask);
1161
Jamie Iles84457942011-05-06 15:28:55 +01001162 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
Jason Robertsce082592010-05-13 15:57:33 +01001163
1164 memcpy(buf, denali->buf.buf, mtd->writesize);
Chuanxiao5bac3acf2010-08-05 23:06:04 +08001165
Mike Dunn3f91e942012-04-25 12:06:09 -07001166 check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips);
David Woodhouseaadff492010-05-13 16:12:43 +01001167 denali_enable_dma(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +01001168
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001169 if (check_erased_page) {
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001170 read_oob_data(mtd, chip->oob_poi, denali->page);
Jason Robertsce082592010-05-13 15:57:33 +01001171
1172 /* check ECC failures that may have occurred on erased pages */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001173 if (check_erased_page) {
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001174 if (!is_erased(buf, mtd->writesize))
1175 mtd->ecc_stats.failed++;
1176 if (!is_erased(buf, mtd->oobsize))
1177 mtd->ecc_stats.failed++;
Chuanxiao5bac3acf2010-08-05 23:06:04 +08001178 }
Jason Robertsce082592010-05-13 15:57:33 +01001179 }
Mike Dunn3f91e942012-04-25 12:06:09 -07001180 return max_bitflips;
Jason Robertsce082592010-05-13 15:57:33 +01001181}
1182
1183static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
Brian Norris1fbb9382012-05-02 10:14:55 -07001184 uint8_t *buf, int oob_required, int page)
Jason Robertsce082592010-05-13 15:57:33 +01001185{
1186 struct denali_nand_info *denali = mtd_to_denali(mtd);
Jason Robertsce082592010-05-13 15:57:33 +01001187 dma_addr_t addr = denali->buf.dma_buf;
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001188 size_t size = mtd->writesize + mtd->oobsize;
Jamie Iles9589bf52011-05-06 15:28:56 +01001189 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
Chuanxiao5bac3acf2010-08-05 23:06:04 +08001190
Chuanxiao Dong7d8a26f2010-08-11 18:19:23 +08001191 if (page != denali->page) {
Masahiro Yamada81254502014-09-16 20:04:25 +09001192 dev_err(denali->dev,
1193 "IN %s: page %d is not equal to denali->page %d",
1194 __func__, page, denali->page);
Chuanxiao Dong7d8a26f2010-08-11 18:19:23 +08001195 BUG();
1196 }
1197
Jason Robertsce082592010-05-13 15:57:33 +01001198 setup_ecc_for_xfer(denali, false, true);
David Woodhouseaadff492010-05-13 16:12:43 +01001199 denali_enable_dma(denali, true);
Jason Robertsce082592010-05-13 15:57:33 +01001200
Jamie Iles84457942011-05-06 15:28:55 +01001201 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
Jason Robertsce082592010-05-13 15:57:33 +01001202
1203 clear_interrupts(denali);
David Woodhouseaadff492010-05-13 16:12:43 +01001204 denali_setup_dma(denali, DENALI_READ);
Jason Robertsce082592010-05-13 15:57:33 +01001205
1206 /* wait for operation to complete */
Brian Norrisba5f2bc2014-09-19 09:37:19 -07001207 wait_for_irq(denali, irq_mask);
Jason Robertsce082592010-05-13 15:57:33 +01001208
Jamie Iles84457942011-05-06 15:28:55 +01001209 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
Jason Robertsce082592010-05-13 15:57:33 +01001210
David Woodhouseaadff492010-05-13 16:12:43 +01001211 denali_enable_dma(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +01001212
1213 memcpy(buf, denali->buf.buf, mtd->writesize);
1214 memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize);
1215
1216 return 0;
1217}
1218
1219static uint8_t denali_read_byte(struct mtd_info *mtd)
1220{
1221 struct denali_nand_info *denali = mtd_to_denali(mtd);
1222 uint8_t result = 0xff;
1223
1224 if (denali->buf.head < denali->buf.tail)
Jason Robertsce082592010-05-13 15:57:33 +01001225 result = denali->buf.buf[denali->buf.head++];
Jason Robertsce082592010-05-13 15:57:33 +01001226
Jason Robertsce082592010-05-13 15:57:33 +01001227 return result;
1228}
1229
1230static void denali_select_chip(struct mtd_info *mtd, int chip)
1231{
1232 struct denali_nand_info *denali = mtd_to_denali(mtd);
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +08001233
Jason Robertsce082592010-05-13 15:57:33 +01001234 spin_lock_irq(&denali->irq_lock);
1235 denali->flash_bank = chip;
1236 spin_unlock_irq(&denali->irq_lock);
1237}
1238
1239static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1240{
1241 struct denali_nand_info *denali = mtd_to_denali(mtd);
1242 int status = denali->status;
Masahiro Yamada81254502014-09-16 20:04:25 +09001243
Jason Robertsce082592010-05-13 15:57:33 +01001244 denali->status = 0;
1245
Jason Robertsce082592010-05-13 15:57:33 +01001246 return status;
1247}
1248
Brian Norris49c50b92014-05-06 16:02:19 -07001249static int denali_erase(struct mtd_info *mtd, int page)
Jason Robertsce082592010-05-13 15:57:33 +01001250{
1251 struct denali_nand_info *denali = mtd_to_denali(mtd);
1252
Masahiro Yamada5637b692014-09-09 11:01:52 +09001253 uint32_t cmd, irq_status;
Jason Robertsce082592010-05-13 15:57:33 +01001254
Chuanxiao5bac3acf2010-08-05 23:06:04 +08001255 clear_interrupts(denali);
Jason Robertsce082592010-05-13 15:57:33 +01001256
1257 /* setup page read request for access type */
1258 cmd = MODE_10 | BANK(denali->flash_bank) | page;
Masahiro Yamada3157d1e2014-09-09 11:01:53 +09001259 index_addr(denali, cmd, 0x1);
Jason Robertsce082592010-05-13 15:57:33 +01001260
1261 /* wait for erase to complete or failure to occur */
Jamie Iles9589bf52011-05-06 15:28:56 +01001262 irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
1263 INTR_STATUS__ERASE_FAIL);
Jason Robertsce082592010-05-13 15:57:33 +01001264
Masahiro Yamada7d14ecd2014-09-16 20:04:24 +09001265 return irq_status & INTR_STATUS__ERASE_FAIL ? NAND_STATUS_FAIL : PASS;
Jason Robertsce082592010-05-13 15:57:33 +01001266}
1267
Chuanxiao5bac3acf2010-08-05 23:06:04 +08001268static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
Jason Robertsce082592010-05-13 15:57:33 +01001269 int page)
1270{
1271 struct denali_nand_info *denali = mtd_to_denali(mtd);
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +08001272 uint32_t addr, id;
1273 int i;
Jason Robertsce082592010-05-13 15:57:33 +01001274
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001275 switch (cmd) {
Chuanxiao Donga99d1792010-07-27 11:32:21 +08001276 case NAND_CMD_PAGEPROG:
1277 break;
1278 case NAND_CMD_STATUS:
1279 read_status(denali);
1280 break;
1281 case NAND_CMD_READID:
Florian Fainelli42af8b52010-08-30 18:32:20 +02001282 case NAND_CMD_PARAM:
Chuanxiao Donga99d1792010-07-27 11:32:21 +08001283 reset_buf(denali);
Masahiro Yamada43914a22014-09-09 11:01:51 +09001284 /*
1285 * sometimes ManufactureId read from register is not right
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +08001286 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1287 * So here we send READID cmd to NAND insteand
Masahiro Yamada43914a22014-09-09 11:01:51 +09001288 */
Masahiro Yamada3157d1e2014-09-09 11:01:53 +09001289 addr = MODE_11 | BANK(denali->flash_bank);
1290 index_addr(denali, addr | 0, 0x90);
Enrico Jorns9c07d092015-09-18 10:02:41 +02001291 index_addr(denali, addr | 1, col);
grmoore@altera.comd68a5c32014-06-23 14:21:10 -05001292 for (i = 0; i < 8; i++) {
Masahiro Yamada81254502014-09-16 20:04:25 +09001293 index_addr_read_data(denali, addr | 2, &id);
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +08001294 write_byte_to_buf(denali, id);
Chuanxiao Donga99d1792010-07-27 11:32:21 +08001295 }
1296 break;
1297 case NAND_CMD_READ0:
1298 case NAND_CMD_SEQIN:
1299 denali->page = page;
1300 break;
1301 case NAND_CMD_RESET:
1302 reset_bank(denali);
1303 break;
1304 case NAND_CMD_READOOB:
1305 /* TODO: Read OOB data */
1306 break;
1307 default:
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001308 pr_err(": unsupported command received 0x%x\n", cmd);
Chuanxiao Donga99d1792010-07-27 11:32:21 +08001309 break;
Jason Robertsce082592010-05-13 15:57:33 +01001310 }
1311}
Jason Robertsce082592010-05-13 15:57:33 +01001312/* end NAND core entry points */
1313
1314/* Initialization code to bring the device up to a known good state */
1315static void denali_hw_init(struct denali_nand_info *denali)
1316{
Masahiro Yamada43914a22014-09-09 11:01:51 +09001317 /*
1318 * tell driver how many bit controller will skip before
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001319 * writing ECC code in OOB, this register may be already
1320 * set by firmware. So we read this value out.
1321 * if this value is 0, just let it be.
Masahiro Yamada43914a22014-09-09 11:01:51 +09001322 */
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001323 denali->bbtskipbytes = ioread32(denali->flash_reg +
1324 SPARE_AREA_SKIP_BYTES);
Jamie Ilesbc27ede2011-06-06 17:11:34 +01001325 detect_max_banks(denali);
Chuanxiao Dongeda936e2010-07-27 14:17:37 +08001326 denali_nand_reset(denali);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001327 iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1328 iowrite32(CHIP_EN_DONT_CARE__FLAG,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +08001329 denali->flash_reg + CHIP_ENABLE_DONT_CARE);
Jason Robertsce082592010-05-13 15:57:33 +01001330
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001331 iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
Jason Robertsce082592010-05-13 15:57:33 +01001332
1333 /* Should set value for these registers when init */
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001334 iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1335 iowrite32(1, denali->flash_reg + ECC_ENABLE);
Chuanxiao Dong5eab6aaa2010-08-12 10:07:18 +08001336 denali_nand_timing_set(denali);
1337 denali_irq_init(denali);
Jason Robertsce082592010-05-13 15:57:33 +01001338}
1339
Masahiro Yamada43914a22014-09-09 11:01:51 +09001340/*
1341 * Althogh controller spec said SLC ECC is forceb to be 4bit,
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001342 * but denali controller in MRST only support 15bit and 8bit ECC
1343 * correction
Masahiro Yamada43914a22014-09-09 11:01:51 +09001344 */
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001345#define ECC_8BITS 14
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001346#define ECC_15BITS 26
Boris Brezillon14fad622016-02-03 20:00:11 +01001347
1348static int denali_ooblayout_ecc(struct mtd_info *mtd, int section,
1349 struct mtd_oob_region *oobregion)
1350{
1351 struct denali_nand_info *denali = mtd_to_denali(mtd);
1352 struct nand_chip *chip = mtd_to_nand(mtd);
1353
1354 if (section)
1355 return -ERANGE;
1356
1357 oobregion->offset = denali->bbtskipbytes;
1358 oobregion->length = chip->ecc.total;
1359
1360 return 0;
1361}
1362
1363static int denali_ooblayout_free(struct mtd_info *mtd, int section,
1364 struct mtd_oob_region *oobregion)
1365{
1366 struct denali_nand_info *denali = mtd_to_denali(mtd);
1367 struct nand_chip *chip = mtd_to_nand(mtd);
1368
1369 if (section)
1370 return -ERANGE;
1371
1372 oobregion->offset = chip->ecc.total + denali->bbtskipbytes;
1373 oobregion->length = mtd->oobsize - oobregion->offset;
1374
1375 return 0;
1376}
1377
1378static const struct mtd_ooblayout_ops denali_ooblayout_ops = {
1379 .ecc = denali_ooblayout_ecc,
1380 .free = denali_ooblayout_free,
Jason Robertsce082592010-05-13 15:57:33 +01001381};
1382
1383static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
1384static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
1385
1386static struct nand_bbt_descr bbt_main_descr = {
1387 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1388 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1389 .offs = 8,
1390 .len = 4,
1391 .veroffs = 12,
1392 .maxblocks = 4,
1393 .pattern = bbt_pattern,
1394};
1395
1396static struct nand_bbt_descr bbt_mirror_descr = {
1397 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1398 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1399 .offs = 8,
1400 .len = 4,
1401 .veroffs = 12,
1402 .maxblocks = 4,
1403 .pattern = mirror_pattern,
1404};
1405
Uwe Kleine-König421f91d2010-06-11 12:17:00 +02001406/* initialize driver data structures */
Brian Norris8c519432013-08-10 22:57:30 -07001407static void denali_drv_init(struct denali_nand_info *denali)
Jason Robertsce082592010-05-13 15:57:33 +01001408{
Masahiro Yamada43914a22014-09-09 11:01:51 +09001409 /*
1410 * the completion object will be used to notify
1411 * the callee that the interrupt is done
1412 */
Jason Robertsce082592010-05-13 15:57:33 +01001413 init_completion(&denali->complete);
1414
Masahiro Yamada43914a22014-09-09 11:01:51 +09001415 /*
1416 * the spinlock will be used to synchronize the ISR with any
1417 * element that might be access shared data (interrupt status)
1418 */
Jason Robertsce082592010-05-13 15:57:33 +01001419 spin_lock_init(&denali->irq_lock);
1420
1421 /* indicate that MTD has not selected a valid bank yet */
1422 denali->flash_bank = CHIP_SELECT_INVALID;
1423
1424 /* initialize our irq_status variable to indicate no interrupts */
1425 denali->irq_status = 0;
1426}
1427
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001428int denali_init(struct denali_nand_info *denali)
Jason Robertsce082592010-05-13 15:57:33 +01001429{
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001430 struct mtd_info *mtd = nand_to_mtd(&denali->nand);
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001431 int ret;
Jason Robertsce082592010-05-13 15:57:33 +01001432
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001433 if (denali->platform == INTEL_CE4100) {
Masahiro Yamada43914a22014-09-09 11:01:51 +09001434 /*
1435 * Due to a silicon limitation, we can only support
Chuanxiao5bac3acf2010-08-05 23:06:04 +08001436 * ONFI timing mode 1 and below.
1437 */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001438 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001439 pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n");
1440 return -EINVAL;
Jason Robertsce082592010-05-13 15:57:33 +01001441 }
1442 }
1443
Huang Shijiee07caa32013-12-21 00:02:28 +08001444 /* allocate a temporary buffer for nand_scan_ident() */
1445 denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE,
1446 GFP_DMA | GFP_KERNEL);
1447 if (!denali->buf.buf)
1448 return -ENOMEM;
Jason Robertsce082592010-05-13 15:57:33 +01001449
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001450 mtd->dev.parent = denali->dev;
Jason Robertsce082592010-05-13 15:57:33 +01001451 denali_hw_init(denali);
1452 denali_drv_init(denali);
1453
Masahiro Yamada7ebb8d02016-11-09 13:35:27 +09001454 /* Request IRQ after all the hardware initialization is finished */
1455 ret = devm_request_irq(denali->dev, denali->irq, denali_isr,
1456 IRQF_SHARED, DENALI_NAND_NAME, denali);
1457 if (ret) {
Masahiro Yamada789ccf12016-11-09 13:35:24 +09001458 dev_err(denali->dev, "Unable to request IRQ\n");
Masahiro Yamada7ebb8d02016-11-09 13:35:27 +09001459 return ret;
Jason Robertsce082592010-05-13 15:57:33 +01001460 }
1461
1462 /* now that our ISR is registered, we can enable interrupts */
Chuanxiao Dongeda936e2010-07-27 14:17:37 +08001463 denali_set_intr_modes(denali, true);
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001464 mtd->name = "denali-nand";
Jason Robertsce082592010-05-13 15:57:33 +01001465
1466 /* register the driver with the NAND core subsystem */
1467 denali->nand.select_chip = denali_select_chip;
1468 denali->nand.cmdfunc = denali_cmdfunc;
1469 denali->nand.read_byte = denali_read_byte;
1470 denali->nand.waitfunc = denali_waitfunc;
1471
Masahiro Yamada43914a22014-09-09 11:01:51 +09001472 /*
1473 * scan for NAND devices attached to the controller
Jason Robertsce082592010-05-13 15:57:33 +01001474 * this is the first stage in a two step process to register
Masahiro Yamada43914a22014-09-09 11:01:51 +09001475 * with the nand subsystem
1476 */
Masahiro Yamadaa227d4e2016-11-09 13:35:28 +09001477 ret = nand_scan_ident(mtd, denali->max_banks, NULL);
1478 if (ret)
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001479 goto failed_req_irq;
Chuanxiao5bac3acf2010-08-05 23:06:04 +08001480
Huang Shijiee07caa32013-12-21 00:02:28 +08001481 /* allocate the right size buffer now */
1482 devm_kfree(denali->dev, denali->buf.buf);
1483 denali->buf.buf = devm_kzalloc(denali->dev,
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001484 mtd->writesize + mtd->oobsize,
Huang Shijiee07caa32013-12-21 00:02:28 +08001485 GFP_KERNEL);
1486 if (!denali->buf.buf) {
1487 ret = -ENOMEM;
1488 goto failed_req_irq;
1489 }
1490
1491 /* Is 32-bit DMA supported? */
1492 ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32));
1493 if (ret) {
Masahiro Yamada789ccf12016-11-09 13:35:24 +09001494 dev_err(denali->dev, "No usable DMA configuration\n");
Huang Shijiee07caa32013-12-21 00:02:28 +08001495 goto failed_req_irq;
1496 }
1497
1498 denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf,
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001499 mtd->writesize + mtd->oobsize,
Huang Shijiee07caa32013-12-21 00:02:28 +08001500 DMA_BIDIRECTIONAL);
1501 if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) {
Masahiro Yamada789ccf12016-11-09 13:35:24 +09001502 dev_err(denali->dev, "Failed to map DMA buffer\n");
Huang Shijiee07caa32013-12-21 00:02:28 +08001503 ret = -EIO;
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001504 goto failed_req_irq;
Chuanxiao.Dong664065242010-08-06 18:48:21 +08001505 }
1506
Masahiro Yamada43914a22014-09-09 11:01:51 +09001507 /*
1508 * support for multi nand
1509 * MTD known nothing about multi nand, so we should tell it
1510 * the real pagesize and anything necessery
Chuanxiao Dong08b9ab92010-08-06 18:19:09 +08001511 */
1512 denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
1513 denali->nand.chipsize <<= (denali->devnum - 1);
1514 denali->nand.page_shift += (denali->devnum - 1);
1515 denali->nand.pagemask = (denali->nand.chipsize >>
1516 denali->nand.page_shift) - 1;
1517 denali->nand.bbt_erase_shift += (denali->devnum - 1);
1518 denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
1519 denali->nand.chip_shift += (denali->devnum - 1);
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001520 mtd->writesize <<= (denali->devnum - 1);
1521 mtd->oobsize <<= (denali->devnum - 1);
1522 mtd->erasesize <<= (denali->devnum - 1);
1523 mtd->size = denali->nand.numchips * denali->nand.chipsize;
Chuanxiao Dong08b9ab92010-08-06 18:19:09 +08001524 denali->bbtskipbytes *= denali->devnum;
1525
Masahiro Yamada43914a22014-09-09 11:01:51 +09001526 /*
1527 * second stage of the NAND scan
Chuanxiao5bac3acf2010-08-05 23:06:04 +08001528 * this stage requires information regarding ECC and
Masahiro Yamada43914a22014-09-09 11:01:51 +09001529 * bad block management.
1530 */
Jason Robertsce082592010-05-13 15:57:33 +01001531
1532 /* Bad block management */
1533 denali->nand.bbt_td = &bbt_main_descr;
1534 denali->nand.bbt_md = &bbt_mirror_descr;
1535
1536 /* skip the scan for now until we have OOB read and write support */
Brian Norrisbb9ebd4e2011-05-31 16:31:23 -07001537 denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
Brian Norrisa40f7342011-05-31 16:31:22 -07001538 denali->nand.options |= NAND_SKIP_BBTSCAN;
Jason Robertsce082592010-05-13 15:57:33 +01001539 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
1540
Graham Moored99d7282015-01-14 09:38:50 -06001541 /* no subpage writes on denali */
1542 denali->nand.options |= NAND_NO_SUBPAGE_WRITE;
1543
Masahiro Yamada43914a22014-09-09 11:01:51 +09001544 /*
1545 * Denali Controller only support 15bit and 8bit ECC in MRST,
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001546 * so just let controller do 15bit ECC for MLC and 8bit ECC for
1547 * SLC if possible.
1548 * */
Huang Shijie1d0ed692013-09-25 14:58:10 +08001549 if (!nand_is_slc(&denali->nand) &&
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001550 (mtd->oobsize > (denali->bbtskipbytes +
1551 ECC_15BITS * (mtd->writesize /
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001552 ECC_SECTOR_SIZE)))) {
1553 /* if MLC OOB size is large enough, use 15bit ECC*/
Mike Dunn6a918ba2012-03-11 14:21:11 -07001554 denali->nand.ecc.strength = 15;
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001555 denali->nand.ecc.bytes = ECC_15BITS;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001556 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001557 } else if (mtd->oobsize < (denali->bbtskipbytes +
1558 ECC_8BITS * (mtd->writesize /
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001559 ECC_SECTOR_SIZE))) {
Masahiro Yamada81254502014-09-16 20:04:25 +09001560 pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes");
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001561 goto failed_req_irq;
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001562 } else {
Mike Dunn6a918ba2012-03-11 14:21:11 -07001563 denali->nand.ecc.strength = 8;
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001564 denali->nand.ecc.bytes = ECC_8BITS;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001565 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +01001566 }
1567
Boris Brezillon14fad622016-02-03 20:00:11 +01001568 mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
Chuanxiao Dong08b9ab92010-08-06 18:19:09 +08001569 denali->nand.ecc.bytes *= denali->devnum;
Mike Dunn6a918ba2012-03-11 14:21:11 -07001570 denali->nand.ecc.strength *= denali->devnum;
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001571
Jason Robertsce082592010-05-13 15:57:33 +01001572 /* override the default read operations */
Chuanxiao Dong08b9ab92010-08-06 18:19:09 +08001573 denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
Jason Robertsce082592010-05-13 15:57:33 +01001574 denali->nand.ecc.read_page = denali_read_page;
1575 denali->nand.ecc.read_page_raw = denali_read_page_raw;
1576 denali->nand.ecc.write_page = denali_write_page;
1577 denali->nand.ecc.write_page_raw = denali_write_page_raw;
1578 denali->nand.ecc.read_oob = denali_read_oob;
1579 denali->nand.ecc.write_oob = denali_write_oob;
Brian Norris49c50b92014-05-06 16:02:19 -07001580 denali->nand.erase = denali_erase;
Jason Robertsce082592010-05-13 15:57:33 +01001581
Masahiro Yamadaa227d4e2016-11-09 13:35:28 +09001582 ret = nand_scan_tail(mtd);
1583 if (ret)
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001584 goto failed_req_irq;
Jason Robertsce082592010-05-13 15:57:33 +01001585
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001586 ret = mtd_device_register(mtd, NULL, 0);
Jason Robertsce082592010-05-13 15:57:33 +01001587 if (ret) {
Masahiro Yamada789ccf12016-11-09 13:35:24 +09001588 dev_err(denali->dev, "Failed to register MTD: %d\n", ret);
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001589 goto failed_req_irq;
Jason Robertsce082592010-05-13 15:57:33 +01001590 }
1591 return 0;
1592
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001593failed_req_irq:
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001594 denali_irq_cleanup(denali->irq, denali);
1595
Jason Robertsce082592010-05-13 15:57:33 +01001596 return ret;
1597}
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001598EXPORT_SYMBOL(denali_init);
Jason Robertsce082592010-05-13 15:57:33 +01001599
1600/* driver exit point */
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001601void denali_remove(struct denali_nand_info *denali)
Jason Robertsce082592010-05-13 15:57:33 +01001602{
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001603 struct mtd_info *mtd = nand_to_mtd(&denali->nand);
Boris BREZILLON320092a2015-12-11 15:02:34 +01001604 /*
1605 * Pre-compute DMA buffer size to avoid any problems in case
1606 * nand_release() ever changes in a way that mtd->writesize and
1607 * mtd->oobsize are not reliable after this call.
1608 */
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001609 int bufsize = mtd->writesize + mtd->oobsize;
Boris BREZILLON320092a2015-12-11 15:02:34 +01001610
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001611 nand_release(mtd);
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001612 denali_irq_cleanup(denali->irq, denali);
Boris BREZILLON320092a2015-12-11 15:02:34 +01001613 dma_unmap_single(denali->dev, denali->buf.dma_buf, bufsize,
Masahiro Yamada81254502014-09-16 20:04:25 +09001614 DMA_BIDIRECTIONAL);
Jason Robertsce082592010-05-13 15:57:33 +01001615}
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001616EXPORT_SYMBOL(denali_remove);