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Archit Tanejac76b78d2016-02-03 14:29:50 +05301/*
2 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/clk.h>
15#include <linux/slab.h>
16#include <linux/bitops.h>
17#include <linux/dma-mapping.h>
18#include <linux/dmaengine.h>
19#include <linux/module.h>
20#include <linux/mtd/nand.h>
21#include <linux/mtd/partitions.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
Archit Tanejac76b78d2016-02-03 14:29:50 +053024#include <linux/delay.h>
25
26/* NANDc reg offsets */
27#define NAND_FLASH_CMD 0x00
28#define NAND_ADDR0 0x04
29#define NAND_ADDR1 0x08
30#define NAND_FLASH_CHIP_SELECT 0x0c
31#define NAND_EXEC_CMD 0x10
32#define NAND_FLASH_STATUS 0x14
33#define NAND_BUFFER_STATUS 0x18
34#define NAND_DEV0_CFG0 0x20
35#define NAND_DEV0_CFG1 0x24
36#define NAND_DEV0_ECC_CFG 0x28
37#define NAND_DEV1_ECC_CFG 0x2c
38#define NAND_DEV1_CFG0 0x30
39#define NAND_DEV1_CFG1 0x34
40#define NAND_READ_ID 0x40
41#define NAND_READ_STATUS 0x44
42#define NAND_DEV_CMD0 0xa0
43#define NAND_DEV_CMD1 0xa4
44#define NAND_DEV_CMD2 0xa8
45#define NAND_DEV_CMD_VLD 0xac
46#define SFLASHC_BURST_CFG 0xe0
47#define NAND_ERASED_CW_DETECT_CFG 0xe8
48#define NAND_ERASED_CW_DETECT_STATUS 0xec
49#define NAND_EBI2_ECC_BUF_CFG 0xf0
50#define FLASH_BUF_ACC 0x100
51
52#define NAND_CTRL 0xf00
53#define NAND_VERSION 0xf08
54#define NAND_READ_LOCATION_0 0xf20
55#define NAND_READ_LOCATION_1 0xf24
Abhishek Sahu91af95c2017-08-17 17:37:43 +053056#define NAND_READ_LOCATION_2 0xf28
57#define NAND_READ_LOCATION_3 0xf2c
Archit Tanejac76b78d2016-02-03 14:29:50 +053058
59/* dummy register offsets, used by write_reg_dma */
60#define NAND_DEV_CMD1_RESTORE 0xdead
61#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
62
63/* NAND_FLASH_CMD bits */
64#define PAGE_ACC BIT(4)
65#define LAST_PAGE BIT(5)
66
67/* NAND_FLASH_CHIP_SELECT bits */
68#define NAND_DEV_SEL 0
69#define DM_EN BIT(2)
70
71/* NAND_FLASH_STATUS bits */
72#define FS_OP_ERR BIT(4)
73#define FS_READY_BSY_N BIT(5)
74#define FS_MPU_ERR BIT(8)
75#define FS_DEVICE_STS_ERR BIT(16)
76#define FS_DEVICE_WP BIT(23)
77
78/* NAND_BUFFER_STATUS bits */
79#define BS_UNCORRECTABLE_BIT BIT(8)
80#define BS_CORRECTABLE_ERR_MSK 0x1f
81
82/* NAND_DEVn_CFG0 bits */
83#define DISABLE_STATUS_AFTER_WRITE 4
84#define CW_PER_PAGE 6
85#define UD_SIZE_BYTES 9
86#define ECC_PARITY_SIZE_BYTES_RS 19
87#define SPARE_SIZE_BYTES 23
88#define NUM_ADDR_CYCLES 27
89#define STATUS_BFR_READ 30
90#define SET_RD_MODE_AFTER_STATUS 31
91
92/* NAND_DEVn_CFG0 bits */
93#define DEV0_CFG1_ECC_DISABLE 0
94#define WIDE_FLASH 1
95#define NAND_RECOVERY_CYCLES 2
96#define CS_ACTIVE_BSY 5
97#define BAD_BLOCK_BYTE_NUM 6
98#define BAD_BLOCK_IN_SPARE_AREA 16
99#define WR_RD_BSY_GAP 17
100#define ENABLE_BCH_ECC 27
101
102/* NAND_DEV0_ECC_CFG bits */
103#define ECC_CFG_ECC_DISABLE 0
104#define ECC_SW_RESET 1
105#define ECC_MODE 4
106#define ECC_PARITY_SIZE_BYTES_BCH 8
107#define ECC_NUM_DATA_BYTES 16
108#define ECC_FORCE_CLK_OPEN 30
109
110/* NAND_DEV_CMD1 bits */
111#define READ_ADDR 0
112
113/* NAND_DEV_CMD_VLD bits */
Abhishek Sahud8a9b322017-08-11 17:09:16 +0530114#define READ_START_VLD BIT(0)
115#define READ_STOP_VLD BIT(1)
116#define WRITE_START_VLD BIT(2)
117#define ERASE_START_VLD BIT(3)
118#define SEQ_READ_START_VLD BIT(4)
Archit Tanejac76b78d2016-02-03 14:29:50 +0530119
120/* NAND_EBI2_ECC_BUF_CFG bits */
121#define NUM_STEPS 0
122
123/* NAND_ERASED_CW_DETECT_CFG bits */
124#define ERASED_CW_ECC_MASK 1
125#define AUTO_DETECT_RES 0
126#define MASK_ECC (1 << ERASED_CW_ECC_MASK)
127#define RESET_ERASED_DET (1 << AUTO_DETECT_RES)
128#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
129#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
130#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
131
132/* NAND_ERASED_CW_DETECT_STATUS bits */
133#define PAGE_ALL_ERASED BIT(7)
134#define CODEWORD_ALL_ERASED BIT(6)
135#define PAGE_ERASED BIT(5)
136#define CODEWORD_ERASED BIT(4)
137#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
138#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
139
Abhishek Sahu91af95c2017-08-17 17:37:43 +0530140/* NAND_READ_LOCATION_n bits */
141#define READ_LOCATION_OFFSET 0
142#define READ_LOCATION_SIZE 16
143#define READ_LOCATION_LAST 31
144
Archit Tanejac76b78d2016-02-03 14:29:50 +0530145/* Version Mask */
146#define NAND_VERSION_MAJOR_MASK 0xf0000000
147#define NAND_VERSION_MAJOR_SHIFT 28
148#define NAND_VERSION_MINOR_MASK 0x0fff0000
149#define NAND_VERSION_MINOR_SHIFT 16
150
151/* NAND OP_CMDs */
152#define PAGE_READ 0x2
153#define PAGE_READ_WITH_ECC 0x3
154#define PAGE_READ_WITH_ECC_SPARE 0x4
155#define PROGRAM_PAGE 0x6
156#define PAGE_PROGRAM_WITH_ECC 0x7
157#define PROGRAM_PAGE_SPARE 0x9
158#define BLOCK_ERASE 0xa
159#define FETCH_ID 0xb
160#define RESET_DEVICE 0xd
161
Abhishek Sahud8a9b322017-08-11 17:09:16 +0530162/* Default Value for NAND_DEV_CMD_VLD */
163#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \
164 ERASE_START_VLD | SEQ_READ_START_VLD)
165
Archit Tanejac76b78d2016-02-03 14:29:50 +0530166/*
167 * the NAND controller performs reads/writes with ECC in 516 byte chunks.
168 * the driver calls the chunks 'step' or 'codeword' interchangeably
169 */
170#define NANDC_STEP_SIZE 512
171
172/*
173 * the largest page size we support is 8K, this will have 16 steps/codewords
174 * of 512 bytes each
175 */
176#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
177
178/* we read at most 3 registers per codeword scan */
179#define MAX_REG_RD (3 * MAX_NUM_STEPS)
180
181/* ECC modes supported by the controller */
182#define ECC_NONE BIT(0)
183#define ECC_RS_4BIT BIT(1)
184#define ECC_BCH_4BIT BIT(2)
185#define ECC_BCH_8BIT BIT(3)
186
Abhishek Sahu91af95c2017-08-17 17:37:43 +0530187#define nandc_set_read_loc(nandc, reg, offset, size, is_last) \
188nandc_set_reg(nandc, NAND_READ_LOCATION_##reg, \
189 ((offset) << READ_LOCATION_OFFSET) | \
190 ((size) << READ_LOCATION_SIZE) | \
191 ((is_last) << READ_LOCATION_LAST))
192
Abhishek Sahucb80f112017-08-17 17:37:40 +0530193#define QPIC_PER_CW_CMD_SGL 32
194#define QPIC_PER_CW_DATA_SGL 8
195
196/*
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530197 * Flags used in DMA descriptor preparation helper functions
198 * (i.e. read_reg_dma/write_reg_dma/read_data_dma/write_data_dma)
199 */
200/* Don't set the EOT in current tx BAM sgl */
201#define NAND_BAM_NO_EOT BIT(0)
202/* Set the NWD flag in current BAM sgl */
203#define NAND_BAM_NWD BIT(1)
204/* Finish writing in the current BAM sgl and start writing in another BAM sgl */
205#define NAND_BAM_NEXT_SGL BIT(2)
Abhishek Sahua86b9c42017-08-17 17:37:44 +0530206/*
207 * Erased codeword status is being used two times in single transfer so this
208 * flag will determine the current value of erased codeword status register
209 */
210#define NAND_ERASED_CW_SET BIT(4)
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530211
212/*
Abhishek Sahucb80f112017-08-17 17:37:40 +0530213 * This data type corresponds to the BAM transaction which will be used for all
214 * NAND transfers.
215 * @cmd_sgl - sgl for NAND BAM command pipe
216 * @data_sgl - sgl for NAND BAM consumer/producer pipe
217 * @cmd_sgl_pos - current index in command sgl.
218 * @cmd_sgl_start - start index in command sgl.
219 * @tx_sgl_pos - current index in data sgl for tx.
220 * @tx_sgl_start - start index in data sgl for tx.
221 * @rx_sgl_pos - current index in data sgl for rx.
222 * @rx_sgl_start - start index in data sgl for rx.
223 */
224struct bam_transaction {
225 struct scatterlist *cmd_sgl;
226 struct scatterlist *data_sgl;
227 u32 cmd_sgl_pos;
228 u32 cmd_sgl_start;
229 u32 tx_sgl_pos;
230 u32 tx_sgl_start;
231 u32 rx_sgl_pos;
232 u32 rx_sgl_start;
233};
234
Abhishek Sahu381dd242017-08-17 17:37:41 +0530235/*
236 * This data type corresponds to the nand dma descriptor
237 * @list - list for desc_info
238 * @dir - DMA transfer direction
239 * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
240 * ADM
241 * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
242 * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
243 * @dma_desc - low level DMA engine descriptor
244 */
Archit Tanejac76b78d2016-02-03 14:29:50 +0530245struct desc_info {
246 struct list_head node;
247
248 enum dma_data_direction dir;
Abhishek Sahu381dd242017-08-17 17:37:41 +0530249 union {
250 struct scatterlist adm_sgl;
251 struct {
252 struct scatterlist *bam_sgl;
253 int sgl_cnt;
254 };
255 };
Archit Tanejac76b78d2016-02-03 14:29:50 +0530256 struct dma_async_tx_descriptor *dma_desc;
257};
258
259/*
260 * holds the current register values that we want to write. acts as a contiguous
261 * chunk of memory which we use to write the controller registers through DMA.
262 */
263struct nandc_regs {
264 __le32 cmd;
265 __le32 addr0;
266 __le32 addr1;
267 __le32 chip_sel;
268 __le32 exec;
269
270 __le32 cfg0;
271 __le32 cfg1;
272 __le32 ecc_bch_cfg;
273
274 __le32 clrflashstatus;
275 __le32 clrreadstatus;
276
277 __le32 cmd1;
278 __le32 vld;
279
280 __le32 orig_cmd1;
281 __le32 orig_vld;
282
283 __le32 ecc_buf_cfg;
Abhishek Sahu91af95c2017-08-17 17:37:43 +0530284 __le32 read_location0;
285 __le32 read_location1;
286 __le32 read_location2;
287 __le32 read_location3;
288
Abhishek Sahua86b9c42017-08-17 17:37:44 +0530289 __le32 erased_cw_detect_cfg_clr;
290 __le32 erased_cw_detect_cfg_set;
Archit Tanejac76b78d2016-02-03 14:29:50 +0530291};
292
293/*
294 * NAND controller data struct
295 *
296 * @controller: base controller structure
297 * @host_list: list containing all the chips attached to the
298 * controller
299 * @dev: parent device
300 * @base: MMIO base
301 * @base_dma: physical base address of controller registers
302 * @core_clk: controller clock
303 * @aon_clk: another controller clock
304 *
305 * @chan: dma channel
306 * @cmd_crci: ADM DMA CRCI for command flow control
307 * @data_crci: ADM DMA CRCI for data flow control
308 * @desc_list: DMA descriptor list (list of desc_infos)
309 *
310 * @data_buffer: our local DMA buffer for page read/writes,
311 * used when we can't use the buffer provided
312 * by upper layers directly
313 * @buf_size/count/start: markers for chip->read_buf/write_buf functions
314 * @reg_read_buf: local buffer for reading back registers via DMA
Abhishek Sahu6192ff72017-08-17 17:37:39 +0530315 * @reg_read_dma: contains dma address for register read buffer
Archit Tanejac76b78d2016-02-03 14:29:50 +0530316 * @reg_read_pos: marker for data read in reg_read_buf
317 *
318 * @regs: a contiguous chunk of memory for DMA register
319 * writes. contains the register values to be
320 * written to controller
321 * @cmd1/vld: some fixed controller register values
Abhishek Sahu58f1f222017-08-11 17:09:17 +0530322 * @props: properties of current NAND controller,
Archit Tanejac76b78d2016-02-03 14:29:50 +0530323 * initialized via DT match data
Abhishek Sahucb80f112017-08-17 17:37:40 +0530324 * @max_cwperpage: maximum QPIC codewords required. calculated
325 * from all connected NAND devices pagesize
Archit Tanejac76b78d2016-02-03 14:29:50 +0530326 */
327struct qcom_nand_controller {
328 struct nand_hw_control controller;
329 struct list_head host_list;
330
331 struct device *dev;
332
333 void __iomem *base;
334 dma_addr_t base_dma;
335
336 struct clk *core_clk;
337 struct clk *aon_clk;
338
Abhishek Sahu497d7d82017-08-11 17:09:19 +0530339 union {
340 /* will be used only by QPIC for BAM DMA */
341 struct {
342 struct dma_chan *tx_chan;
343 struct dma_chan *rx_chan;
344 struct dma_chan *cmd_chan;
345 };
346
347 /* will be used only by EBI2 for ADM DMA */
348 struct {
349 struct dma_chan *chan;
350 unsigned int cmd_crci;
351 unsigned int data_crci;
352 };
353 };
354
Archit Tanejac76b78d2016-02-03 14:29:50 +0530355 struct list_head desc_list;
Abhishek Sahucb80f112017-08-17 17:37:40 +0530356 struct bam_transaction *bam_txn;
Archit Tanejac76b78d2016-02-03 14:29:50 +0530357
358 u8 *data_buffer;
359 int buf_size;
360 int buf_count;
361 int buf_start;
Abhishek Sahucb80f112017-08-17 17:37:40 +0530362 unsigned int max_cwperpage;
Archit Tanejac76b78d2016-02-03 14:29:50 +0530363
364 __le32 *reg_read_buf;
Abhishek Sahu6192ff72017-08-17 17:37:39 +0530365 dma_addr_t reg_read_dma;
Archit Tanejac76b78d2016-02-03 14:29:50 +0530366 int reg_read_pos;
367
368 struct nandc_regs *regs;
369
370 u32 cmd1, vld;
Abhishek Sahu58f1f222017-08-11 17:09:17 +0530371 const struct qcom_nandc_props *props;
Archit Tanejac76b78d2016-02-03 14:29:50 +0530372};
373
374/*
375 * NAND chip structure
376 *
377 * @chip: base NAND chip structure
378 * @node: list node to add itself to host_list in
379 * qcom_nand_controller
380 *
381 * @cs: chip select value for this chip
382 * @cw_size: the number of bytes in a single step/codeword
383 * of a page, consisting of all data, ecc, spare
384 * and reserved bytes
385 * @cw_data: the number of bytes within a codeword protected
386 * by ECC
387 * @use_ecc: request the controller to use ECC for the
388 * upcoming read/write
389 * @bch_enabled: flag to tell whether BCH ECC mode is used
390 * @ecc_bytes_hw: ECC bytes used by controller hardware for this
391 * chip
392 * @status: value to be returned if NAND_CMD_STATUS command
393 * is executed
394 * @last_command: keeps track of last command on this chip. used
395 * for reading correct status
396 *
397 * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for
398 * ecc/non-ecc mode for the current nand flash
399 * device
400 */
401struct qcom_nand_host {
402 struct nand_chip chip;
403 struct list_head node;
404
405 int cs;
406 int cw_size;
407 int cw_data;
408 bool use_ecc;
409 bool bch_enabled;
410 int ecc_bytes_hw;
411 int spare_bytes;
412 int bbm_size;
413 u8 status;
414 int last_command;
415
416 u32 cfg0, cfg1;
417 u32 cfg0_raw, cfg1_raw;
418 u32 ecc_buf_cfg;
419 u32 ecc_bch_cfg;
420 u32 clrflashstatus;
421 u32 clrreadstatus;
422};
423
Abhishek Sahu58f1f222017-08-11 17:09:17 +0530424/*
425 * This data type corresponds to the NAND controller properties which varies
426 * among different NAND controllers.
427 * @ecc_modes - ecc mode for NAND
Abhishek Sahu8c5d5d62017-08-11 17:09:18 +0530428 * @is_bam - whether NAND controller is using BAM
Abhishek Sahu58f1f222017-08-11 17:09:17 +0530429 */
430struct qcom_nandc_props {
431 u32 ecc_modes;
Abhishek Sahu8c5d5d62017-08-11 17:09:18 +0530432 bool is_bam;
Abhishek Sahu58f1f222017-08-11 17:09:17 +0530433};
434
Abhishek Sahucb80f112017-08-17 17:37:40 +0530435/* Frees the BAM transaction memory */
436static void free_bam_transaction(struct qcom_nand_controller *nandc)
437{
438 struct bam_transaction *bam_txn = nandc->bam_txn;
439
440 devm_kfree(nandc->dev, bam_txn);
441}
442
443/* Allocates and Initializes the BAM transaction */
444static struct bam_transaction *
445alloc_bam_transaction(struct qcom_nand_controller *nandc)
446{
447 struct bam_transaction *bam_txn;
448 size_t bam_txn_size;
449 unsigned int num_cw = nandc->max_cwperpage;
450 void *bam_txn_buf;
451
452 bam_txn_size =
453 sizeof(*bam_txn) + num_cw *
454 ((sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
455 (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
456
457 bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
458 if (!bam_txn_buf)
459 return NULL;
460
461 bam_txn = bam_txn_buf;
462 bam_txn_buf += sizeof(*bam_txn);
463
464 bam_txn->cmd_sgl = bam_txn_buf;
465 bam_txn_buf +=
466 sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
467
468 bam_txn->data_sgl = bam_txn_buf;
469
470 return bam_txn;
471}
472
Archit Tanejac76b78d2016-02-03 14:29:50 +0530473static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
474{
475 return container_of(chip, struct qcom_nand_host, chip);
476}
477
478static inline struct qcom_nand_controller *
479get_qcom_nand_controller(struct nand_chip *chip)
480{
481 return container_of(chip->controller, struct qcom_nand_controller,
482 controller);
483}
484
485static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset)
486{
487 return ioread32(nandc->base + offset);
488}
489
490static inline void nandc_write(struct qcom_nand_controller *nandc, int offset,
491 u32 val)
492{
493 iowrite32(val, nandc->base + offset);
494}
495
Abhishek Sahu6192ff72017-08-17 17:37:39 +0530496static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,
497 bool is_cpu)
498{
499 if (!nandc->props->is_bam)
500 return;
501
502 if (is_cpu)
503 dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma,
504 MAX_REG_RD *
505 sizeof(*nandc->reg_read_buf),
506 DMA_FROM_DEVICE);
507 else
508 dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma,
509 MAX_REG_RD *
510 sizeof(*nandc->reg_read_buf),
511 DMA_FROM_DEVICE);
512}
513
Archit Tanejac76b78d2016-02-03 14:29:50 +0530514static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
515{
516 switch (offset) {
517 case NAND_FLASH_CMD:
518 return &regs->cmd;
519 case NAND_ADDR0:
520 return &regs->addr0;
521 case NAND_ADDR1:
522 return &regs->addr1;
523 case NAND_FLASH_CHIP_SELECT:
524 return &regs->chip_sel;
525 case NAND_EXEC_CMD:
526 return &regs->exec;
527 case NAND_FLASH_STATUS:
528 return &regs->clrflashstatus;
529 case NAND_DEV0_CFG0:
530 return &regs->cfg0;
531 case NAND_DEV0_CFG1:
532 return &regs->cfg1;
533 case NAND_DEV0_ECC_CFG:
534 return &regs->ecc_bch_cfg;
535 case NAND_READ_STATUS:
536 return &regs->clrreadstatus;
537 case NAND_DEV_CMD1:
538 return &regs->cmd1;
539 case NAND_DEV_CMD1_RESTORE:
540 return &regs->orig_cmd1;
541 case NAND_DEV_CMD_VLD:
542 return &regs->vld;
543 case NAND_DEV_CMD_VLD_RESTORE:
544 return &regs->orig_vld;
545 case NAND_EBI2_ECC_BUF_CFG:
546 return &regs->ecc_buf_cfg;
Abhishek Sahu91af95c2017-08-17 17:37:43 +0530547 case NAND_READ_LOCATION_0:
548 return &regs->read_location0;
549 case NAND_READ_LOCATION_1:
550 return &regs->read_location1;
551 case NAND_READ_LOCATION_2:
552 return &regs->read_location2;
553 case NAND_READ_LOCATION_3:
554 return &regs->read_location3;
Archit Tanejac76b78d2016-02-03 14:29:50 +0530555 default:
556 return NULL;
557 }
558}
559
560static void nandc_set_reg(struct qcom_nand_controller *nandc, int offset,
561 u32 val)
562{
563 struct nandc_regs *regs = nandc->regs;
564 __le32 *reg;
565
566 reg = offset_to_nandc_reg(regs, offset);
567
568 if (reg)
569 *reg = cpu_to_le32(val);
570}
571
572/* helper to configure address register values */
573static void set_address(struct qcom_nand_host *host, u16 column, int page)
574{
575 struct nand_chip *chip = &host->chip;
576 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
577
578 if (chip->options & NAND_BUSWIDTH_16)
579 column >>= 1;
580
581 nandc_set_reg(nandc, NAND_ADDR0, page << 16 | column);
582 nandc_set_reg(nandc, NAND_ADDR1, page >> 16 & 0xff);
583}
584
585/*
586 * update_rw_regs: set up read/write register values, these will be
587 * written to the NAND controller registers via DMA
588 *
589 * @num_cw: number of steps for the read/write operation
590 * @read: read or write operation
591 */
592static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
593{
594 struct nand_chip *chip = &host->chip;
595 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
596 u32 cmd, cfg0, cfg1, ecc_bch_cfg;
597
598 if (read) {
599 if (host->use_ecc)
600 cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
601 else
602 cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
603 } else {
604 cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
605 }
606
607 if (host->use_ecc) {
608 cfg0 = (host->cfg0 & ~(7U << CW_PER_PAGE)) |
609 (num_cw - 1) << CW_PER_PAGE;
610
611 cfg1 = host->cfg1;
612 ecc_bch_cfg = host->ecc_bch_cfg;
613 } else {
614 cfg0 = (host->cfg0_raw & ~(7U << CW_PER_PAGE)) |
615 (num_cw - 1) << CW_PER_PAGE;
616
617 cfg1 = host->cfg1_raw;
618 ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
619 }
620
621 nandc_set_reg(nandc, NAND_FLASH_CMD, cmd);
622 nandc_set_reg(nandc, NAND_DEV0_CFG0, cfg0);
623 nandc_set_reg(nandc, NAND_DEV0_CFG1, cfg1);
624 nandc_set_reg(nandc, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
625 nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
626 nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
627 nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
628 nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
Abhishek Sahu91af95c2017-08-17 17:37:43 +0530629
630 if (read)
631 nandc_set_read_loc(nandc, 0, 0, host->use_ecc ?
632 host->cw_data : host->cw_size, 1);
Archit Tanejac76b78d2016-02-03 14:29:50 +0530633}
634
Abhishek Sahu381dd242017-08-17 17:37:41 +0530635/*
636 * Maps the scatter gather list for DMA transfer and forms the DMA descriptor
637 * for BAM. This descriptor will be added in the NAND DMA descriptor queue
638 * which will be submitted to DMA engine.
639 */
640static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
641 struct dma_chan *chan,
642 unsigned long flags)
643{
644 struct desc_info *desc;
645 struct scatterlist *sgl;
646 unsigned int sgl_cnt;
647 int ret;
648 struct bam_transaction *bam_txn = nandc->bam_txn;
649 enum dma_transfer_direction dir_eng;
650 struct dma_async_tx_descriptor *dma_desc;
651
652 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
653 if (!desc)
654 return -ENOMEM;
655
656 if (chan == nandc->cmd_chan) {
657 sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
658 sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
659 bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
660 dir_eng = DMA_MEM_TO_DEV;
661 desc->dir = DMA_TO_DEVICE;
662 } else if (chan == nandc->tx_chan) {
663 sgl = &bam_txn->data_sgl[bam_txn->tx_sgl_start];
664 sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
665 bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
666 dir_eng = DMA_MEM_TO_DEV;
667 desc->dir = DMA_TO_DEVICE;
668 } else {
669 sgl = &bam_txn->data_sgl[bam_txn->rx_sgl_start];
670 sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
671 bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
672 dir_eng = DMA_DEV_TO_MEM;
673 desc->dir = DMA_FROM_DEVICE;
674 }
675
676 sg_mark_end(sgl + sgl_cnt - 1);
677 ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
678 if (ret == 0) {
679 dev_err(nandc->dev, "failure in mapping desc\n");
680 kfree(desc);
681 return -ENOMEM;
682 }
683
684 desc->sgl_cnt = sgl_cnt;
685 desc->bam_sgl = sgl;
686
687 dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
688 flags);
689
690 if (!dma_desc) {
691 dev_err(nandc->dev, "failure in prep desc\n");
692 dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
693 kfree(desc);
694 return -EINVAL;
695 }
696
697 desc->dma_desc = dma_desc;
698
699 list_add_tail(&desc->node, &nandc->desc_list);
700
701 return 0;
702}
703
704static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
705 int reg_off, const void *vaddr, int size,
706 bool flow_control)
Archit Tanejac76b78d2016-02-03 14:29:50 +0530707{
708 struct desc_info *desc;
709 struct dma_async_tx_descriptor *dma_desc;
710 struct scatterlist *sgl;
711 struct dma_slave_config slave_conf;
712 enum dma_transfer_direction dir_eng;
713 int ret;
714
715 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
716 if (!desc)
717 return -ENOMEM;
718
Abhishek Sahu381dd242017-08-17 17:37:41 +0530719 sgl = &desc->adm_sgl;
Archit Tanejac76b78d2016-02-03 14:29:50 +0530720
721 sg_init_one(sgl, vaddr, size);
722
723 if (read) {
724 dir_eng = DMA_DEV_TO_MEM;
725 desc->dir = DMA_FROM_DEVICE;
726 } else {
727 dir_eng = DMA_MEM_TO_DEV;
728 desc->dir = DMA_TO_DEVICE;
729 }
730
731 ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir);
732 if (ret == 0) {
733 ret = -ENOMEM;
734 goto err;
735 }
736
737 memset(&slave_conf, 0x00, sizeof(slave_conf));
738
739 slave_conf.device_fc = flow_control;
740 if (read) {
741 slave_conf.src_maxburst = 16;
742 slave_conf.src_addr = nandc->base_dma + reg_off;
743 slave_conf.slave_id = nandc->data_crci;
744 } else {
745 slave_conf.dst_maxburst = 16;
746 slave_conf.dst_addr = nandc->base_dma + reg_off;
747 slave_conf.slave_id = nandc->cmd_crci;
748 }
749
750 ret = dmaengine_slave_config(nandc->chan, &slave_conf);
751 if (ret) {
752 dev_err(nandc->dev, "failed to configure dma channel\n");
753 goto err;
754 }
755
756 dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0);
757 if (!dma_desc) {
758 dev_err(nandc->dev, "failed to prepare desc\n");
759 ret = -EINVAL;
760 goto err;
761 }
762
763 desc->dma_desc = dma_desc;
764
765 list_add_tail(&desc->node, &nandc->desc_list);
766
767 return 0;
768err:
769 kfree(desc);
770
771 return ret;
772}
773
774/*
775 * read_reg_dma: prepares a descriptor to read a given number of
776 * contiguous registers to the reg_read_buf pointer
777 *
778 * @first: offset of the first register in the contiguous block
779 * @num_regs: number of registers to read
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530780 * @flags: flags to control DMA descriptor preparation
Archit Tanejac76b78d2016-02-03 14:29:50 +0530781 */
782static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530783 int num_regs, unsigned int flags)
Archit Tanejac76b78d2016-02-03 14:29:50 +0530784{
785 bool flow_control = false;
786 void *vaddr;
787 int size;
788
789 if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
790 flow_control = true;
791
792 size = num_regs * sizeof(u32);
793 vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
794 nandc->reg_read_pos += num_regs;
795
Abhishek Sahu381dd242017-08-17 17:37:41 +0530796 return prep_adm_dma_desc(nandc, true, first, vaddr, size, flow_control);
Archit Tanejac76b78d2016-02-03 14:29:50 +0530797}
798
799/*
800 * write_reg_dma: prepares a descriptor to write a given number of
801 * contiguous registers
802 *
803 * @first: offset of the first register in the contiguous block
804 * @num_regs: number of registers to write
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530805 * @flags: flags to control DMA descriptor preparation
Archit Tanejac76b78d2016-02-03 14:29:50 +0530806 */
807static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530808 int num_regs, unsigned int flags)
Archit Tanejac76b78d2016-02-03 14:29:50 +0530809{
810 bool flow_control = false;
811 struct nandc_regs *regs = nandc->regs;
812 void *vaddr;
813 int size;
814
815 vaddr = offset_to_nandc_reg(regs, first);
816
817 if (first == NAND_FLASH_CMD)
818 flow_control = true;
819
Abhishek Sahua86b9c42017-08-17 17:37:44 +0530820 if (first == NAND_ERASED_CW_DETECT_CFG) {
821 if (flags & NAND_ERASED_CW_SET)
822 vaddr = &regs->erased_cw_detect_cfg_set;
823 else
824 vaddr = &regs->erased_cw_detect_cfg_clr;
825 }
826
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530827 if (first == NAND_EXEC_CMD)
828 flags |= NAND_BAM_NWD;
829
Archit Tanejac76b78d2016-02-03 14:29:50 +0530830 if (first == NAND_DEV_CMD1_RESTORE)
831 first = NAND_DEV_CMD1;
832
833 if (first == NAND_DEV_CMD_VLD_RESTORE)
834 first = NAND_DEV_CMD_VLD;
835
836 size = num_regs * sizeof(u32);
837
Abhishek Sahu381dd242017-08-17 17:37:41 +0530838 return prep_adm_dma_desc(nandc, false, first, vaddr, size,
839 flow_control);
Archit Tanejac76b78d2016-02-03 14:29:50 +0530840}
841
842/*
843 * read_data_dma: prepares a DMA descriptor to transfer data from the
844 * controller's internal buffer to the buffer 'vaddr'
845 *
846 * @reg_off: offset within the controller's data buffer
847 * @vaddr: virtual address of the buffer we want to write to
848 * @size: DMA transaction size in bytes
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530849 * @flags: flags to control DMA descriptor preparation
Archit Tanejac76b78d2016-02-03 14:29:50 +0530850 */
851static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530852 const u8 *vaddr, int size, unsigned int flags)
Archit Tanejac76b78d2016-02-03 14:29:50 +0530853{
Abhishek Sahu381dd242017-08-17 17:37:41 +0530854 return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
Archit Tanejac76b78d2016-02-03 14:29:50 +0530855}
856
857/*
858 * write_data_dma: prepares a DMA descriptor to transfer data from
859 * 'vaddr' to the controller's internal buffer
860 *
861 * @reg_off: offset within the controller's data buffer
862 * @vaddr: virtual address of the buffer we want to read from
863 * @size: DMA transaction size in bytes
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530864 * @flags: flags to control DMA descriptor preparation
Archit Tanejac76b78d2016-02-03 14:29:50 +0530865 */
866static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530867 const u8 *vaddr, int size, unsigned int flags)
Archit Tanejac76b78d2016-02-03 14:29:50 +0530868{
Abhishek Sahu381dd242017-08-17 17:37:41 +0530869 return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
Archit Tanejac76b78d2016-02-03 14:29:50 +0530870}
871
872/*
Abhishek Sahubde43302017-07-19 17:17:55 +0530873 * Helper to prepare DMA descriptors for configuring registers
874 * before reading a NAND page.
Archit Tanejac76b78d2016-02-03 14:29:50 +0530875 */
Abhishek Sahubde43302017-07-19 17:17:55 +0530876static void config_nand_page_read(struct qcom_nand_controller *nandc)
Archit Tanejac76b78d2016-02-03 14:29:50 +0530877{
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530878 write_reg_dma(nandc, NAND_ADDR0, 2, 0);
879 write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
880 write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
Abhishek Sahua86b9c42017-08-17 17:37:44 +0530881 write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
882 write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
883 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
Abhishek Sahubde43302017-07-19 17:17:55 +0530884}
Archit Tanejac76b78d2016-02-03 14:29:50 +0530885
Abhishek Sahubde43302017-07-19 17:17:55 +0530886/*
887 * Helper to prepare DMA descriptors for configuring registers
888 * before reading each codeword in NAND page.
889 */
890static void config_nand_cw_read(struct qcom_nand_controller *nandc)
891{
Abhishek Sahu91af95c2017-08-17 17:37:43 +0530892 if (nandc->props->is_bam)
893 write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
894 NAND_BAM_NEXT_SGL);
895
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530896 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
897 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
Archit Tanejac76b78d2016-02-03 14:29:50 +0530898
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530899 read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
900 read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
901 NAND_BAM_NEXT_SGL);
Archit Tanejac76b78d2016-02-03 14:29:50 +0530902}
903
904/*
Abhishek Sahubde43302017-07-19 17:17:55 +0530905 * Helper to prepare dma descriptors to configure registers needed for reading a
906 * single codeword in page
Archit Tanejac76b78d2016-02-03 14:29:50 +0530907 */
Abhishek Sahubde43302017-07-19 17:17:55 +0530908static void config_nand_single_cw_page_read(struct qcom_nand_controller *nandc)
909{
910 config_nand_page_read(nandc);
911 config_nand_cw_read(nandc);
912}
913
Abhishek Sahu77cc5362017-07-19 17:17:56 +0530914/*
915 * Helper to prepare DMA descriptors used to configure registers needed for
916 * before writing a NAND page.
917 */
918static void config_nand_page_write(struct qcom_nand_controller *nandc)
Archit Tanejac76b78d2016-02-03 14:29:50 +0530919{
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530920 write_reg_dma(nandc, NAND_ADDR0, 2, 0);
921 write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
922 write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
923 NAND_BAM_NEXT_SGL);
Archit Tanejac76b78d2016-02-03 14:29:50 +0530924}
925
Abhishek Sahu77cc5362017-07-19 17:17:56 +0530926/*
927 * Helper to prepare DMA descriptors for configuring registers
928 * before writing each codeword in NAND page.
929 */
930static void config_nand_cw_write(struct qcom_nand_controller *nandc)
Archit Tanejac76b78d2016-02-03 14:29:50 +0530931{
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530932 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
933 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
Archit Tanejac76b78d2016-02-03 14:29:50 +0530934
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530935 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
Archit Tanejac76b78d2016-02-03 14:29:50 +0530936
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530937 write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
938 write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
Archit Tanejac76b78d2016-02-03 14:29:50 +0530939}
940
941/*
942 * the following functions are used within chip->cmdfunc() to perform different
943 * NAND_CMD_* commands
944 */
945
946/* sets up descriptors for NAND_CMD_PARAM */
947static int nandc_param(struct qcom_nand_host *host)
948{
949 struct nand_chip *chip = &host->chip;
950 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
951
952 /*
953 * NAND_CMD_PARAM is called before we know much about the FLASH chip
954 * in use. we configure the controller to perform a raw read of 512
955 * bytes to read onfi params
956 */
957 nandc_set_reg(nandc, NAND_FLASH_CMD, PAGE_READ | PAGE_ACC | LAST_PAGE);
958 nandc_set_reg(nandc, NAND_ADDR0, 0);
959 nandc_set_reg(nandc, NAND_ADDR1, 0);
960 nandc_set_reg(nandc, NAND_DEV0_CFG0, 0 << CW_PER_PAGE
961 | 512 << UD_SIZE_BYTES
962 | 5 << NUM_ADDR_CYCLES
963 | 0 << SPARE_SIZE_BYTES);
964 nandc_set_reg(nandc, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES
965 | 0 << CS_ACTIVE_BSY
966 | 17 << BAD_BLOCK_BYTE_NUM
967 | 1 << BAD_BLOCK_IN_SPARE_AREA
968 | 2 << WR_RD_BSY_GAP
969 | 0 << WIDE_FLASH
970 | 1 << DEV0_CFG1_ECC_DISABLE);
971 nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
972
973 /* configure CMD1 and VLD for ONFI param probing */
974 nandc_set_reg(nandc, NAND_DEV_CMD_VLD,
Abhishek Sahud8a9b322017-08-11 17:09:16 +0530975 (nandc->vld & ~READ_START_VLD));
Archit Tanejac76b78d2016-02-03 14:29:50 +0530976 nandc_set_reg(nandc, NAND_DEV_CMD1,
977 (nandc->cmd1 & ~(0xFF << READ_ADDR))
978 | NAND_CMD_PARAM << READ_ADDR);
979
980 nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
981
982 nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
983 nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
Abhishek Sahu91af95c2017-08-17 17:37:43 +0530984 nandc_set_read_loc(nandc, 0, 0, 512, 1);
Archit Tanejac76b78d2016-02-03 14:29:50 +0530985
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530986 write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
987 write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
Archit Tanejac76b78d2016-02-03 14:29:50 +0530988
989 nandc->buf_count = 512;
990 memset(nandc->data_buffer, 0xff, nandc->buf_count);
991
Abhishek Sahubde43302017-07-19 17:17:55 +0530992 config_nand_single_cw_page_read(nandc);
Archit Tanejac76b78d2016-02-03 14:29:50 +0530993
994 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530995 nandc->buf_count, 0);
Archit Tanejac76b78d2016-02-03 14:29:50 +0530996
997 /* restore CMD1 and VLD regs */
Abhishek Sahu67e830a2017-08-17 17:37:42 +0530998 write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0);
999 write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301000
1001 return 0;
1002}
1003
1004/* sets up descriptors for NAND_CMD_ERASE1 */
1005static int erase_block(struct qcom_nand_host *host, int page_addr)
1006{
1007 struct nand_chip *chip = &host->chip;
1008 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1009
1010 nandc_set_reg(nandc, NAND_FLASH_CMD,
1011 BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
1012 nandc_set_reg(nandc, NAND_ADDR0, page_addr);
1013 nandc_set_reg(nandc, NAND_ADDR1, 0);
1014 nandc_set_reg(nandc, NAND_DEV0_CFG0,
1015 host->cfg0_raw & ~(7 << CW_PER_PAGE));
1016 nandc_set_reg(nandc, NAND_DEV0_CFG1, host->cfg1_raw);
1017 nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
1018 nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
1019 nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
1020
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301021 write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
1022 write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
1023 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301024
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301025 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301026
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301027 write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
1028 write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301029
1030 return 0;
1031}
1032
1033/* sets up descriptors for NAND_CMD_READID */
1034static int read_id(struct qcom_nand_host *host, int column)
1035{
1036 struct nand_chip *chip = &host->chip;
1037 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1038
1039 if (column == -1)
1040 return 0;
1041
1042 nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
1043 nandc_set_reg(nandc, NAND_ADDR0, column);
1044 nandc_set_reg(nandc, NAND_ADDR1, 0);
1045 nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
1046 nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
1047
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301048 write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
1049 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301050
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301051 read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301052
1053 return 0;
1054}
1055
1056/* sets up descriptors for NAND_CMD_RESET */
1057static int reset(struct qcom_nand_host *host)
1058{
1059 struct nand_chip *chip = &host->chip;
1060 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1061
1062 nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
1063 nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
1064
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301065 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
1066 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301067
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301068 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301069
1070 return 0;
1071}
1072
1073/* helpers to submit/free our list of dma descriptors */
1074static int submit_descs(struct qcom_nand_controller *nandc)
1075{
1076 struct desc_info *desc;
1077 dma_cookie_t cookie = 0;
Abhishek Sahu381dd242017-08-17 17:37:41 +05301078 struct bam_transaction *bam_txn = nandc->bam_txn;
1079 int r;
1080
1081 if (nandc->props->is_bam) {
1082 if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) {
1083 r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
1084 if (r)
1085 return r;
1086 }
1087
1088 if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) {
1089 r = prepare_bam_async_desc(nandc, nandc->tx_chan,
1090 DMA_PREP_INTERRUPT);
1091 if (r)
1092 return r;
1093 }
1094
1095 if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
1096 r = prepare_bam_async_desc(nandc, nandc->cmd_chan, 0);
1097 if (r)
1098 return r;
1099 }
1100 }
Archit Tanejac76b78d2016-02-03 14:29:50 +05301101
1102 list_for_each_entry(desc, &nandc->desc_list, node)
1103 cookie = dmaengine_submit(desc->dma_desc);
1104
Abhishek Sahu381dd242017-08-17 17:37:41 +05301105 if (nandc->props->is_bam) {
1106 dma_async_issue_pending(nandc->tx_chan);
1107 dma_async_issue_pending(nandc->rx_chan);
1108
1109 if (dma_sync_wait(nandc->cmd_chan, cookie) != DMA_COMPLETE)
1110 return -ETIMEDOUT;
1111 } else {
1112 if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
1113 return -ETIMEDOUT;
1114 }
Archit Tanejac76b78d2016-02-03 14:29:50 +05301115
1116 return 0;
1117}
1118
1119static void free_descs(struct qcom_nand_controller *nandc)
1120{
1121 struct desc_info *desc, *n;
1122
1123 list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
1124 list_del(&desc->node);
Abhishek Sahu381dd242017-08-17 17:37:41 +05301125
1126 if (nandc->props->is_bam)
1127 dma_unmap_sg(nandc->dev, desc->bam_sgl,
1128 desc->sgl_cnt, desc->dir);
1129 else
1130 dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1,
1131 desc->dir);
1132
Archit Tanejac76b78d2016-02-03 14:29:50 +05301133 kfree(desc);
1134 }
1135}
1136
1137/* reset the register read buffer for next NAND operation */
1138static void clear_read_regs(struct qcom_nand_controller *nandc)
1139{
1140 nandc->reg_read_pos = 0;
Abhishek Sahu6192ff72017-08-17 17:37:39 +05301141 nandc_read_buffer_sync(nandc, false);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301142}
1143
1144static void pre_command(struct qcom_nand_host *host, int command)
1145{
1146 struct nand_chip *chip = &host->chip;
1147 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1148
1149 nandc->buf_count = 0;
1150 nandc->buf_start = 0;
1151 host->use_ecc = false;
1152 host->last_command = command;
1153
1154 clear_read_regs(nandc);
1155}
1156
1157/*
1158 * this is called after NAND_CMD_PAGEPROG and NAND_CMD_ERASE1 to set our
1159 * privately maintained status byte, this status byte can be read after
1160 * NAND_CMD_STATUS is called
1161 */
1162static void parse_erase_write_errors(struct qcom_nand_host *host, int command)
1163{
1164 struct nand_chip *chip = &host->chip;
1165 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1166 struct nand_ecc_ctrl *ecc = &chip->ecc;
1167 int num_cw;
1168 int i;
1169
1170 num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;
Abhishek Sahu6192ff72017-08-17 17:37:39 +05301171 nandc_read_buffer_sync(nandc, true);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301172
1173 for (i = 0; i < num_cw; i++) {
1174 u32 flash_status = le32_to_cpu(nandc->reg_read_buf[i]);
1175
1176 if (flash_status & FS_MPU_ERR)
1177 host->status &= ~NAND_STATUS_WP;
1178
1179 if (flash_status & FS_OP_ERR || (i == (num_cw - 1) &&
1180 (flash_status &
1181 FS_DEVICE_STS_ERR)))
1182 host->status |= NAND_STATUS_FAIL;
1183 }
1184}
1185
1186static void post_command(struct qcom_nand_host *host, int command)
1187{
1188 struct nand_chip *chip = &host->chip;
1189 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1190
1191 switch (command) {
1192 case NAND_CMD_READID:
Abhishek Sahu6192ff72017-08-17 17:37:39 +05301193 nandc_read_buffer_sync(nandc, true);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301194 memcpy(nandc->data_buffer, nandc->reg_read_buf,
1195 nandc->buf_count);
1196 break;
1197 case NAND_CMD_PAGEPROG:
1198 case NAND_CMD_ERASE1:
1199 parse_erase_write_errors(host, command);
1200 break;
1201 default:
1202 break;
1203 }
1204}
1205
1206/*
1207 * Implements chip->cmdfunc. It's only used for a limited set of commands.
1208 * The rest of the commands wouldn't be called by upper layers. For example,
1209 * NAND_CMD_READOOB would never be called because we have our own versions
1210 * of read_oob ops for nand_ecc_ctrl.
1211 */
1212static void qcom_nandc_command(struct mtd_info *mtd, unsigned int command,
1213 int column, int page_addr)
1214{
1215 struct nand_chip *chip = mtd_to_nand(mtd);
1216 struct qcom_nand_host *host = to_qcom_nand_host(chip);
1217 struct nand_ecc_ctrl *ecc = &chip->ecc;
1218 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1219 bool wait = false;
1220 int ret = 0;
1221
1222 pre_command(host, command);
1223
1224 switch (command) {
1225 case NAND_CMD_RESET:
1226 ret = reset(host);
1227 wait = true;
1228 break;
1229
1230 case NAND_CMD_READID:
1231 nandc->buf_count = 4;
1232 ret = read_id(host, column);
1233 wait = true;
1234 break;
1235
1236 case NAND_CMD_PARAM:
1237 ret = nandc_param(host);
1238 wait = true;
1239 break;
1240
1241 case NAND_CMD_ERASE1:
1242 ret = erase_block(host, page_addr);
1243 wait = true;
1244 break;
1245
1246 case NAND_CMD_READ0:
1247 /* we read the entire page for now */
1248 WARN_ON(column != 0);
1249
1250 host->use_ecc = true;
1251 set_address(host, 0, page_addr);
1252 update_rw_regs(host, ecc->steps, true);
1253 break;
1254
1255 case NAND_CMD_SEQIN:
1256 WARN_ON(column != 0);
1257 set_address(host, 0, page_addr);
1258 break;
1259
1260 case NAND_CMD_PAGEPROG:
1261 case NAND_CMD_STATUS:
1262 case NAND_CMD_NONE:
1263 default:
1264 break;
1265 }
1266
1267 if (ret) {
1268 dev_err(nandc->dev, "failure executing command %d\n",
1269 command);
1270 free_descs(nandc);
1271 return;
1272 }
1273
1274 if (wait) {
1275 ret = submit_descs(nandc);
1276 if (ret)
1277 dev_err(nandc->dev,
1278 "failure submitting descs for command %d\n",
1279 command);
1280 }
1281
1282 free_descs(nandc);
1283
1284 post_command(host, command);
1285}
1286
1287/*
1288 * when using BCH ECC, the HW flags an error in NAND_FLASH_STATUS if it read
1289 * an erased CW, and reports an erased CW in NAND_ERASED_CW_DETECT_STATUS.
1290 *
1291 * when using RS ECC, the HW reports the same erros when reading an erased CW,
1292 * but it notifies that it is an erased CW by placing special characters at
1293 * certain offsets in the buffer.
1294 *
1295 * verify if the page is erased or not, and fix up the page for RS ECC by
1296 * replacing the special characters with 0xff.
1297 */
1298static bool erased_chunk_check_and_fixup(u8 *data_buf, int data_len)
1299{
1300 u8 empty1, empty2;
1301
1302 /*
1303 * an erased page flags an error in NAND_FLASH_STATUS, check if the page
1304 * is erased by looking for 0x54s at offsets 3 and 175 from the
1305 * beginning of each codeword
1306 */
1307
1308 empty1 = data_buf[3];
1309 empty2 = data_buf[175];
1310
1311 /*
1312 * if the erased codework markers, if they exist override them with
1313 * 0xffs
1314 */
1315 if ((empty1 == 0x54 && empty2 == 0xff) ||
1316 (empty1 == 0xff && empty2 == 0x54)) {
1317 data_buf[3] = 0xff;
1318 data_buf[175] = 0xff;
1319 }
1320
1321 /*
1322 * check if the entire chunk contains 0xffs or not. if it doesn't, then
1323 * restore the original values at the special offsets
1324 */
1325 if (memchr_inv(data_buf, 0xff, data_len)) {
1326 data_buf[3] = empty1;
1327 data_buf[175] = empty2;
1328
1329 return false;
1330 }
1331
1332 return true;
1333}
1334
1335struct read_stats {
1336 __le32 flash;
1337 __le32 buffer;
1338 __le32 erased_cw;
1339};
1340
1341/*
1342 * reads back status registers set by the controller to notify page read
1343 * errors. this is equivalent to what 'ecc->correct()' would do.
1344 */
1345static int parse_read_errors(struct qcom_nand_host *host, u8 *data_buf,
1346 u8 *oob_buf)
1347{
1348 struct nand_chip *chip = &host->chip;
1349 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1350 struct mtd_info *mtd = nand_to_mtd(chip);
1351 struct nand_ecc_ctrl *ecc = &chip->ecc;
1352 unsigned int max_bitflips = 0;
1353 struct read_stats *buf;
1354 int i;
1355
1356 buf = (struct read_stats *)nandc->reg_read_buf;
Abhishek Sahu6192ff72017-08-17 17:37:39 +05301357 nandc_read_buffer_sync(nandc, true);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301358
1359 for (i = 0; i < ecc->steps; i++, buf++) {
1360 u32 flash, buffer, erased_cw;
1361 int data_len, oob_len;
1362
1363 if (i == (ecc->steps - 1)) {
1364 data_len = ecc->size - ((ecc->steps - 1) << 2);
1365 oob_len = ecc->steps << 2;
1366 } else {
1367 data_len = host->cw_data;
1368 oob_len = 0;
1369 }
1370
1371 flash = le32_to_cpu(buf->flash);
1372 buffer = le32_to_cpu(buf->buffer);
1373 erased_cw = le32_to_cpu(buf->erased_cw);
1374
1375 if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
1376 bool erased;
1377
1378 /* ignore erased codeword errors */
1379 if (host->bch_enabled) {
1380 erased = (erased_cw & ERASED_CW) == ERASED_CW ?
1381 true : false;
1382 } else {
1383 erased = erased_chunk_check_and_fixup(data_buf,
1384 data_len);
1385 }
1386
1387 if (erased) {
1388 data_buf += data_len;
1389 if (oob_buf)
1390 oob_buf += oob_len + ecc->bytes;
1391 continue;
1392 }
1393
1394 if (buffer & BS_UNCORRECTABLE_BIT) {
1395 int ret, ecclen, extraooblen;
1396 void *eccbuf;
1397
1398 eccbuf = oob_buf ? oob_buf + oob_len : NULL;
1399 ecclen = oob_buf ? host->ecc_bytes_hw : 0;
1400 extraooblen = oob_buf ? oob_len : 0;
1401
1402 /*
1403 * make sure it isn't an erased page reported
1404 * as not-erased by HW because of a few bitflips
1405 */
1406 ret = nand_check_erased_ecc_chunk(data_buf,
1407 data_len, eccbuf, ecclen, oob_buf,
1408 extraooblen, ecc->strength);
1409 if (ret < 0) {
1410 mtd->ecc_stats.failed++;
1411 } else {
1412 mtd->ecc_stats.corrected += ret;
1413 max_bitflips =
1414 max_t(unsigned int, max_bitflips, ret);
1415 }
1416 }
1417 } else {
1418 unsigned int stat;
1419
1420 stat = buffer & BS_CORRECTABLE_ERR_MSK;
1421 mtd->ecc_stats.corrected += stat;
1422 max_bitflips = max(max_bitflips, stat);
1423 }
1424
1425 data_buf += data_len;
1426 if (oob_buf)
1427 oob_buf += oob_len + ecc->bytes;
1428 }
1429
1430 return max_bitflips;
1431}
1432
1433/*
1434 * helper to perform the actual page read operation, used by ecc->read_page(),
1435 * ecc->read_oob()
1436 */
1437static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
1438 u8 *oob_buf)
1439{
1440 struct nand_chip *chip = &host->chip;
1441 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1442 struct nand_ecc_ctrl *ecc = &chip->ecc;
1443 int i, ret;
1444
Abhishek Sahubde43302017-07-19 17:17:55 +05301445 config_nand_page_read(nandc);
1446
Archit Tanejac76b78d2016-02-03 14:29:50 +05301447 /* queue cmd descs for each codeword */
1448 for (i = 0; i < ecc->steps; i++) {
1449 int data_size, oob_size;
1450
1451 if (i == (ecc->steps - 1)) {
1452 data_size = ecc->size - ((ecc->steps - 1) << 2);
1453 oob_size = (ecc->steps << 2) + host->ecc_bytes_hw +
1454 host->spare_bytes;
1455 } else {
1456 data_size = host->cw_data;
1457 oob_size = host->ecc_bytes_hw + host->spare_bytes;
1458 }
1459
Abhishek Sahu91af95c2017-08-17 17:37:43 +05301460 if (nandc->props->is_bam) {
1461 if (data_buf && oob_buf) {
1462 nandc_set_read_loc(nandc, 0, 0, data_size, 0);
1463 nandc_set_read_loc(nandc, 1, data_size,
1464 oob_size, 1);
1465 } else if (data_buf) {
1466 nandc_set_read_loc(nandc, 0, 0, data_size, 1);
1467 } else {
1468 nandc_set_read_loc(nandc, 0, data_size,
1469 oob_size, 1);
1470 }
1471 }
1472
Abhishek Sahubde43302017-07-19 17:17:55 +05301473 config_nand_cw_read(nandc);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301474
1475 if (data_buf)
1476 read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301477 data_size, 0);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301478
1479 /*
1480 * when ecc is enabled, the controller doesn't read the real
1481 * or dummy bad block markers in each chunk. To maintain a
1482 * consistent layout across RAW and ECC reads, we just
1483 * leave the real/dummy BBM offsets empty (i.e, filled with
1484 * 0xffs)
1485 */
1486 if (oob_buf) {
1487 int j;
1488
1489 for (j = 0; j < host->bbm_size; j++)
1490 *oob_buf++ = 0xff;
1491
1492 read_data_dma(nandc, FLASH_BUF_ACC + data_size,
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301493 oob_buf, oob_size, 0);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301494 }
1495
1496 if (data_buf)
1497 data_buf += data_size;
1498 if (oob_buf)
1499 oob_buf += oob_size;
1500 }
1501
1502 ret = submit_descs(nandc);
1503 if (ret)
1504 dev_err(nandc->dev, "failure to read page/oob\n");
1505
1506 free_descs(nandc);
1507
1508 return ret;
1509}
1510
1511/*
1512 * a helper that copies the last step/codeword of a page (containing free oob)
1513 * into our local buffer
1514 */
1515static int copy_last_cw(struct qcom_nand_host *host, int page)
1516{
1517 struct nand_chip *chip = &host->chip;
1518 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1519 struct nand_ecc_ctrl *ecc = &chip->ecc;
1520 int size;
1521 int ret;
1522
1523 clear_read_regs(nandc);
1524
1525 size = host->use_ecc ? host->cw_data : host->cw_size;
1526
1527 /* prepare a clean read buffer */
1528 memset(nandc->data_buffer, 0xff, size);
1529
1530 set_address(host, host->cw_size * (ecc->steps - 1), page);
1531 update_rw_regs(host, 1, true);
1532
Abhishek Sahubde43302017-07-19 17:17:55 +05301533 config_nand_single_cw_page_read(nandc);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301534
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301535 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301536
1537 ret = submit_descs(nandc);
1538 if (ret)
1539 dev_err(nandc->dev, "failed to copy last codeword\n");
1540
1541 free_descs(nandc);
1542
1543 return ret;
1544}
1545
1546/* implements ecc->read_page() */
1547static int qcom_nandc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1548 uint8_t *buf, int oob_required, int page)
1549{
1550 struct qcom_nand_host *host = to_qcom_nand_host(chip);
1551 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1552 u8 *data_buf, *oob_buf = NULL;
1553 int ret;
1554
1555 data_buf = buf;
1556 oob_buf = oob_required ? chip->oob_poi : NULL;
1557
1558 ret = read_page_ecc(host, data_buf, oob_buf);
1559 if (ret) {
1560 dev_err(nandc->dev, "failure to read page\n");
1561 return ret;
1562 }
1563
1564 return parse_read_errors(host, data_buf, oob_buf);
1565}
1566
1567/* implements ecc->read_page_raw() */
1568static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
1569 struct nand_chip *chip, uint8_t *buf,
1570 int oob_required, int page)
1571{
1572 struct qcom_nand_host *host = to_qcom_nand_host(chip);
1573 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1574 u8 *data_buf, *oob_buf;
1575 struct nand_ecc_ctrl *ecc = &chip->ecc;
1576 int i, ret;
Abhishek Sahu91af95c2017-08-17 17:37:43 +05301577 int read_loc;
Archit Tanejac76b78d2016-02-03 14:29:50 +05301578
1579 data_buf = buf;
1580 oob_buf = chip->oob_poi;
1581
1582 host->use_ecc = false;
1583 update_rw_regs(host, ecc->steps, true);
Abhishek Sahubde43302017-07-19 17:17:55 +05301584 config_nand_page_read(nandc);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301585
1586 for (i = 0; i < ecc->steps; i++) {
1587 int data_size1, data_size2, oob_size1, oob_size2;
1588 int reg_off = FLASH_BUF_ACC;
1589
1590 data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
1591 oob_size1 = host->bbm_size;
1592
1593 if (i == (ecc->steps - 1)) {
1594 data_size2 = ecc->size - data_size1 -
1595 ((ecc->steps - 1) << 2);
1596 oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw +
1597 host->spare_bytes;
1598 } else {
1599 data_size2 = host->cw_data - data_size1;
1600 oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
1601 }
1602
Abhishek Sahu91af95c2017-08-17 17:37:43 +05301603 if (nandc->props->is_bam) {
1604 read_loc = 0;
1605 nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
1606 read_loc += data_size1;
1607
1608 nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
1609 read_loc += oob_size1;
1610
1611 nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
1612 read_loc += data_size2;
1613
1614 nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
1615 }
1616
Abhishek Sahubde43302017-07-19 17:17:55 +05301617 config_nand_cw_read(nandc);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301618
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301619 read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301620 reg_off += data_size1;
1621 data_buf += data_size1;
1622
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301623 read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301624 reg_off += oob_size1;
1625 oob_buf += oob_size1;
1626
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301627 read_data_dma(nandc, reg_off, data_buf, data_size2, 0);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301628 reg_off += data_size2;
1629 data_buf += data_size2;
1630
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301631 read_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301632 oob_buf += oob_size2;
1633 }
1634
1635 ret = submit_descs(nandc);
1636 if (ret)
1637 dev_err(nandc->dev, "failure to read raw page\n");
1638
1639 free_descs(nandc);
1640
1641 return 0;
1642}
1643
1644/* implements ecc->read_oob() */
1645static int qcom_nandc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1646 int page)
1647{
1648 struct qcom_nand_host *host = to_qcom_nand_host(chip);
1649 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1650 struct nand_ecc_ctrl *ecc = &chip->ecc;
1651 int ret;
1652
1653 clear_read_regs(nandc);
1654
1655 host->use_ecc = true;
1656 set_address(host, 0, page);
1657 update_rw_regs(host, ecc->steps, true);
1658
1659 ret = read_page_ecc(host, NULL, chip->oob_poi);
1660 if (ret)
1661 dev_err(nandc->dev, "failure to read oob\n");
1662
1663 return ret;
1664}
1665
1666/* implements ecc->write_page() */
1667static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1668 const uint8_t *buf, int oob_required, int page)
1669{
1670 struct qcom_nand_host *host = to_qcom_nand_host(chip);
1671 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1672 struct nand_ecc_ctrl *ecc = &chip->ecc;
1673 u8 *data_buf, *oob_buf;
1674 int i, ret;
1675
1676 clear_read_regs(nandc);
1677
1678 data_buf = (u8 *)buf;
1679 oob_buf = chip->oob_poi;
1680
1681 host->use_ecc = true;
1682 update_rw_regs(host, ecc->steps, false);
Abhishek Sahu77cc5362017-07-19 17:17:56 +05301683 config_nand_page_write(nandc);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301684
1685 for (i = 0; i < ecc->steps; i++) {
1686 int data_size, oob_size;
1687
1688 if (i == (ecc->steps - 1)) {
1689 data_size = ecc->size - ((ecc->steps - 1) << 2);
1690 oob_size = (ecc->steps << 2) + host->ecc_bytes_hw +
1691 host->spare_bytes;
1692 } else {
1693 data_size = host->cw_data;
1694 oob_size = ecc->bytes;
1695 }
1696
Archit Tanejac76b78d2016-02-03 14:29:50 +05301697
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301698 write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size,
1699 i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301700
1701 /*
1702 * when ECC is enabled, we don't really need to write anything
1703 * to oob for the first n - 1 codewords since these oob regions
1704 * just contain ECC bytes that's written by the controller
1705 * itself. For the last codeword, we skip the bbm positions and
1706 * write to the free oob area.
1707 */
1708 if (i == (ecc->steps - 1)) {
1709 oob_buf += host->bbm_size;
1710
1711 write_data_dma(nandc, FLASH_BUF_ACC + data_size,
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301712 oob_buf, oob_size, 0);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301713 }
1714
Abhishek Sahu77cc5362017-07-19 17:17:56 +05301715 config_nand_cw_write(nandc);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301716
1717 data_buf += data_size;
1718 oob_buf += oob_size;
1719 }
1720
1721 ret = submit_descs(nandc);
1722 if (ret)
1723 dev_err(nandc->dev, "failure to write page\n");
1724
1725 free_descs(nandc);
1726
1727 return ret;
1728}
1729
1730/* implements ecc->write_page_raw() */
1731static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
1732 struct nand_chip *chip, const uint8_t *buf,
1733 int oob_required, int page)
1734{
1735 struct qcom_nand_host *host = to_qcom_nand_host(chip);
1736 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1737 struct nand_ecc_ctrl *ecc = &chip->ecc;
1738 u8 *data_buf, *oob_buf;
1739 int i, ret;
1740
1741 clear_read_regs(nandc);
1742
1743 data_buf = (u8 *)buf;
1744 oob_buf = chip->oob_poi;
1745
1746 host->use_ecc = false;
1747 update_rw_regs(host, ecc->steps, false);
Abhishek Sahu77cc5362017-07-19 17:17:56 +05301748 config_nand_page_write(nandc);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301749
1750 for (i = 0; i < ecc->steps; i++) {
1751 int data_size1, data_size2, oob_size1, oob_size2;
1752 int reg_off = FLASH_BUF_ACC;
1753
1754 data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
1755 oob_size1 = host->bbm_size;
1756
1757 if (i == (ecc->steps - 1)) {
1758 data_size2 = ecc->size - data_size1 -
1759 ((ecc->steps - 1) << 2);
1760 oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw +
1761 host->spare_bytes;
1762 } else {
1763 data_size2 = host->cw_data - data_size1;
1764 oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
1765 }
1766
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301767 write_data_dma(nandc, reg_off, data_buf, data_size1,
1768 NAND_BAM_NO_EOT);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301769 reg_off += data_size1;
1770 data_buf += data_size1;
1771
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301772 write_data_dma(nandc, reg_off, oob_buf, oob_size1,
1773 NAND_BAM_NO_EOT);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301774 reg_off += oob_size1;
1775 oob_buf += oob_size1;
1776
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301777 write_data_dma(nandc, reg_off, data_buf, data_size2,
1778 NAND_BAM_NO_EOT);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301779 reg_off += data_size2;
1780 data_buf += data_size2;
1781
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301782 write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301783 oob_buf += oob_size2;
1784
Abhishek Sahu77cc5362017-07-19 17:17:56 +05301785 config_nand_cw_write(nandc);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301786 }
1787
1788 ret = submit_descs(nandc);
1789 if (ret)
1790 dev_err(nandc->dev, "failure to write raw page\n");
1791
1792 free_descs(nandc);
1793
1794 return ret;
1795}
1796
1797/*
1798 * implements ecc->write_oob()
1799 *
1800 * the NAND controller cannot write only data or only oob within a codeword,
1801 * since ecc is calculated for the combined codeword. we first copy the
1802 * entire contents for the last codeword(data + oob), replace the old oob
1803 * with the new one in chip->oob_poi, and then write the entire codeword.
1804 * this read-copy-write operation results in a slight performance loss.
1805 */
1806static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1807 int page)
1808{
1809 struct qcom_nand_host *host = to_qcom_nand_host(chip);
1810 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1811 struct nand_ecc_ctrl *ecc = &chip->ecc;
1812 u8 *oob = chip->oob_poi;
Archit Tanejac76b78d2016-02-03 14:29:50 +05301813 int data_size, oob_size;
1814 int ret, status = 0;
1815
1816 host->use_ecc = true;
1817
1818 ret = copy_last_cw(host, page);
1819 if (ret)
1820 return ret;
1821
1822 clear_read_regs(nandc);
1823
1824 /* calculate the data and oob size for the last codeword/step */
1825 data_size = ecc->size - ((ecc->steps - 1) << 2);
Boris Brezillonaa02fcf2016-03-18 17:53:31 +01001826 oob_size = mtd->oobavail;
Archit Tanejac76b78d2016-02-03 14:29:50 +05301827
1828 /* override new oob content to last codeword */
Boris Brezillonaa02fcf2016-03-18 17:53:31 +01001829 mtd_ooblayout_get_databytes(mtd, nandc->data_buffer + data_size, oob,
1830 0, mtd->oobavail);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301831
1832 set_address(host, host->cw_size * (ecc->steps - 1), page);
1833 update_rw_regs(host, 1, false);
1834
Abhishek Sahu77cc5362017-07-19 17:17:56 +05301835 config_nand_page_write(nandc);
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301836 write_data_dma(nandc, FLASH_BUF_ACC,
1837 nandc->data_buffer, data_size + oob_size, 0);
Abhishek Sahu77cc5362017-07-19 17:17:56 +05301838 config_nand_cw_write(nandc);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301839
1840 ret = submit_descs(nandc);
1841
1842 free_descs(nandc);
1843
1844 if (ret) {
1845 dev_err(nandc->dev, "failure to write oob\n");
1846 return -EIO;
1847 }
1848
1849 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1850
1851 status = chip->waitfunc(mtd, chip);
1852
1853 return status & NAND_STATUS_FAIL ? -EIO : 0;
1854}
1855
1856static int qcom_nandc_block_bad(struct mtd_info *mtd, loff_t ofs)
1857{
1858 struct nand_chip *chip = mtd_to_nand(mtd);
1859 struct qcom_nand_host *host = to_qcom_nand_host(chip);
1860 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1861 struct nand_ecc_ctrl *ecc = &chip->ecc;
1862 int page, ret, bbpos, bad = 0;
1863 u32 flash_status;
1864
1865 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
1866
1867 /*
1868 * configure registers for a raw sub page read, the address is set to
1869 * the beginning of the last codeword, we don't care about reading ecc
1870 * portion of oob. we just want the first few bytes from this codeword
1871 * that contains the BBM
1872 */
1873 host->use_ecc = false;
1874
1875 ret = copy_last_cw(host, page);
1876 if (ret)
1877 goto err;
1878
1879 flash_status = le32_to_cpu(nandc->reg_read_buf[0]);
1880
1881 if (flash_status & (FS_OP_ERR | FS_MPU_ERR)) {
1882 dev_warn(nandc->dev, "error when trying to read BBM\n");
1883 goto err;
1884 }
1885
1886 bbpos = mtd->writesize - host->cw_size * (ecc->steps - 1);
1887
1888 bad = nandc->data_buffer[bbpos] != 0xff;
1889
1890 if (chip->options & NAND_BUSWIDTH_16)
1891 bad = bad || (nandc->data_buffer[bbpos + 1] != 0xff);
1892err:
1893 return bad;
1894}
1895
1896static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
1897{
1898 struct nand_chip *chip = mtd_to_nand(mtd);
1899 struct qcom_nand_host *host = to_qcom_nand_host(chip);
1900 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1901 struct nand_ecc_ctrl *ecc = &chip->ecc;
1902 int page, ret, status = 0;
1903
1904 clear_read_regs(nandc);
1905
1906 /*
1907 * to mark the BBM as bad, we flash the entire last codeword with 0s.
1908 * we don't care about the rest of the content in the codeword since
1909 * we aren't going to use this block again
1910 */
1911 memset(nandc->data_buffer, 0x00, host->cw_size);
1912
1913 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
1914
1915 /* prepare write */
1916 host->use_ecc = false;
1917 set_address(host, host->cw_size * (ecc->steps - 1), page);
1918 update_rw_regs(host, 1, false);
1919
Abhishek Sahu77cc5362017-07-19 17:17:56 +05301920 config_nand_page_write(nandc);
Abhishek Sahu67e830a2017-08-17 17:37:42 +05301921 write_data_dma(nandc, FLASH_BUF_ACC,
1922 nandc->data_buffer, host->cw_size, 0);
Abhishek Sahu77cc5362017-07-19 17:17:56 +05301923 config_nand_cw_write(nandc);
Archit Tanejac76b78d2016-02-03 14:29:50 +05301924
1925 ret = submit_descs(nandc);
1926
1927 free_descs(nandc);
1928
1929 if (ret) {
1930 dev_err(nandc->dev, "failure to update BBM\n");
1931 return -EIO;
1932 }
1933
1934 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1935
1936 status = chip->waitfunc(mtd, chip);
1937
1938 return status & NAND_STATUS_FAIL ? -EIO : 0;
1939}
1940
1941/*
1942 * the three functions below implement chip->read_byte(), chip->read_buf()
1943 * and chip->write_buf() respectively. these aren't used for
1944 * reading/writing page data, they are used for smaller data like reading
1945 * id, status etc
1946 */
1947static uint8_t qcom_nandc_read_byte(struct mtd_info *mtd)
1948{
1949 struct nand_chip *chip = mtd_to_nand(mtd);
1950 struct qcom_nand_host *host = to_qcom_nand_host(chip);
1951 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1952 u8 *buf = nandc->data_buffer;
1953 u8 ret = 0x0;
1954
1955 if (host->last_command == NAND_CMD_STATUS) {
1956 ret = host->status;
1957
1958 host->status = NAND_STATUS_READY | NAND_STATUS_WP;
1959
1960 return ret;
1961 }
1962
1963 if (nandc->buf_start < nandc->buf_count)
1964 ret = buf[nandc->buf_start++];
1965
1966 return ret;
1967}
1968
1969static void qcom_nandc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1970{
1971 struct nand_chip *chip = mtd_to_nand(mtd);
1972 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1973 int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start);
1974
1975 memcpy(buf, nandc->data_buffer + nandc->buf_start, real_len);
1976 nandc->buf_start += real_len;
1977}
1978
1979static void qcom_nandc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
1980 int len)
1981{
1982 struct nand_chip *chip = mtd_to_nand(mtd);
1983 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1984 int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start);
1985
1986 memcpy(nandc->data_buffer + nandc->buf_start, buf, real_len);
1987
1988 nandc->buf_start += real_len;
1989}
1990
1991/* we support only one external chip for now */
1992static void qcom_nandc_select_chip(struct mtd_info *mtd, int chipnr)
1993{
1994 struct nand_chip *chip = mtd_to_nand(mtd);
1995 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1996
1997 if (chipnr <= 0)
1998 return;
1999
2000 dev_warn(nandc->dev, "invalid chip select\n");
2001}
2002
2003/*
2004 * NAND controller page layout info
2005 *
2006 * Layout with ECC enabled:
2007 *
2008 * |----------------------| |---------------------------------|
2009 * | xx.......yy| | *********xx.......yy|
2010 * | DATA xx..ECC..yy| | DATA **SPARE**xx..ECC..yy|
2011 * | (516) xx.......yy| | (516-n*4) **(n*4)**xx.......yy|
2012 * | xx.......yy| | *********xx.......yy|
2013 * |----------------------| |---------------------------------|
2014 * codeword 1,2..n-1 codeword n
2015 * <---(528/532 Bytes)--> <-------(528/532 Bytes)--------->
2016 *
2017 * n = Number of codewords in the page
2018 * . = ECC bytes
2019 * * = Spare/free bytes
2020 * x = Unused byte(s)
2021 * y = Reserved byte(s)
2022 *
2023 * 2K page: n = 4, spare = 16 bytes
2024 * 4K page: n = 8, spare = 32 bytes
2025 * 8K page: n = 16, spare = 64 bytes
2026 *
2027 * the qcom nand controller operates at a sub page/codeword level. each
2028 * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
2029 * the number of ECC bytes vary based on the ECC strength and the bus width.
2030 *
2031 * the first n - 1 codewords contains 516 bytes of user data, the remaining
2032 * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
2033 * both user data and spare(oobavail) bytes that sum up to 516 bytes.
2034 *
2035 * When we access a page with ECC enabled, the reserved bytes(s) are not
2036 * accessible at all. When reading, we fill up these unreadable positions
2037 * with 0xffs. When writing, the controller skips writing the inaccessible
2038 * bytes.
2039 *
2040 * Layout with ECC disabled:
2041 *
2042 * |------------------------------| |---------------------------------------|
2043 * | yy xx.......| | bb *********xx.......|
2044 * | DATA1 yy DATA2 xx..ECC..| | DATA1 bb DATA2 **SPARE**xx..ECC..|
2045 * | (size1) yy (size2) xx.......| | (size1) bb (size2) **(n*4)**xx.......|
2046 * | yy xx.......| | bb *********xx.......|
2047 * |------------------------------| |---------------------------------------|
2048 * codeword 1,2..n-1 codeword n
2049 * <-------(528/532 Bytes)------> <-----------(528/532 Bytes)----------->
2050 *
2051 * n = Number of codewords in the page
2052 * . = ECC bytes
2053 * * = Spare/free bytes
2054 * x = Unused byte(s)
2055 * y = Dummy Bad Bock byte(s)
2056 * b = Real Bad Block byte(s)
2057 * size1/size2 = function of codeword size and 'n'
2058 *
2059 * when the ECC block is disabled, one reserved byte (or two for 16 bit bus
2060 * width) is now accessible. For the first n - 1 codewords, these are dummy Bad
2061 * Block Markers. In the last codeword, this position contains the real BBM
2062 *
2063 * In order to have a consistent layout between RAW and ECC modes, we assume
2064 * the following OOB layout arrangement:
2065 *
2066 * |-----------| |--------------------|
2067 * |yyxx.......| |bb*********xx.......|
2068 * |yyxx..ECC..| |bb*FREEOOB*xx..ECC..|
2069 * |yyxx.......| |bb*********xx.......|
2070 * |yyxx.......| |bb*********xx.......|
2071 * |-----------| |--------------------|
2072 * first n - 1 nth OOB region
2073 * OOB regions
2074 *
2075 * n = Number of codewords in the page
2076 * . = ECC bytes
2077 * * = FREE OOB bytes
2078 * y = Dummy bad block byte(s) (inaccessible when ECC enabled)
2079 * x = Unused byte(s)
2080 * b = Real bad block byte(s) (inaccessible when ECC enabled)
2081 *
2082 * This layout is read as is when ECC is disabled. When ECC is enabled, the
2083 * inaccessible Bad Block byte(s) are ignored when we write to a page/oob,
2084 * and assumed as 0xffs when we read a page/oob. The ECC, unused and
Boris Brezillon421e81c2016-03-18 17:54:27 +01002085 * dummy/real bad block bytes are grouped as ecc bytes (i.e, ecc->bytes is
2086 * the sum of the three).
Archit Tanejac76b78d2016-02-03 14:29:50 +05302087 */
Boris Brezillon421e81c2016-03-18 17:54:27 +01002088static int qcom_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
2089 struct mtd_oob_region *oobregion)
Archit Tanejac76b78d2016-02-03 14:29:50 +05302090{
Boris Brezillon421e81c2016-03-18 17:54:27 +01002091 struct nand_chip *chip = mtd_to_nand(mtd);
2092 struct qcom_nand_host *host = to_qcom_nand_host(chip);
Archit Tanejac76b78d2016-02-03 14:29:50 +05302093 struct nand_ecc_ctrl *ecc = &chip->ecc;
Archit Tanejac76b78d2016-02-03 14:29:50 +05302094
Boris Brezillon421e81c2016-03-18 17:54:27 +01002095 if (section > 1)
2096 return -ERANGE;
Archit Tanejac76b78d2016-02-03 14:29:50 +05302097
Boris Brezillon421e81c2016-03-18 17:54:27 +01002098 if (!section) {
2099 oobregion->length = (ecc->bytes * (ecc->steps - 1)) +
2100 host->bbm_size;
2101 oobregion->offset = 0;
2102 } else {
2103 oobregion->length = host->ecc_bytes_hw + host->spare_bytes;
2104 oobregion->offset = mtd->oobsize - oobregion->length;
Archit Tanejac76b78d2016-02-03 14:29:50 +05302105 }
2106
Boris Brezillon421e81c2016-03-18 17:54:27 +01002107 return 0;
Archit Tanejac76b78d2016-02-03 14:29:50 +05302108}
2109
Boris Brezillon421e81c2016-03-18 17:54:27 +01002110static int qcom_nand_ooblayout_free(struct mtd_info *mtd, int section,
2111 struct mtd_oob_region *oobregion)
2112{
2113 struct nand_chip *chip = mtd_to_nand(mtd);
2114 struct qcom_nand_host *host = to_qcom_nand_host(chip);
2115 struct nand_ecc_ctrl *ecc = &chip->ecc;
2116
2117 if (section)
2118 return -ERANGE;
2119
2120 oobregion->length = ecc->steps * 4;
2121 oobregion->offset = ((ecc->steps - 1) * ecc->bytes) + host->bbm_size;
2122
2123 return 0;
2124}
2125
2126static const struct mtd_ooblayout_ops qcom_nand_ooblayout_ops = {
2127 .ecc = qcom_nand_ooblayout_ecc,
2128 .free = qcom_nand_ooblayout_free,
2129};
2130
Archit Tanejac76b78d2016-02-03 14:29:50 +05302131static int qcom_nand_host_setup(struct qcom_nand_host *host)
2132{
2133 struct nand_chip *chip = &host->chip;
2134 struct mtd_info *mtd = nand_to_mtd(chip);
2135 struct nand_ecc_ctrl *ecc = &chip->ecc;
2136 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2137 int cwperpage, bad_block_byte;
2138 bool wide_bus;
2139 int ecc_mode = 1;
2140
2141 /*
2142 * the controller requires each step consists of 512 bytes of data.
2143 * bail out if DT has populated a wrong step size.
2144 */
2145 if (ecc->size != NANDC_STEP_SIZE) {
2146 dev_err(nandc->dev, "invalid ecc size\n");
2147 return -EINVAL;
2148 }
2149
2150 wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
2151
2152 if (ecc->strength >= 8) {
2153 /* 8 bit ECC defaults to BCH ECC on all platforms */
2154 host->bch_enabled = true;
2155 ecc_mode = 1;
2156
2157 if (wide_bus) {
2158 host->ecc_bytes_hw = 14;
2159 host->spare_bytes = 0;
2160 host->bbm_size = 2;
2161 } else {
2162 host->ecc_bytes_hw = 13;
2163 host->spare_bytes = 2;
2164 host->bbm_size = 1;
2165 }
2166 } else {
2167 /*
2168 * if the controller supports BCH for 4 bit ECC, the controller
2169 * uses lesser bytes for ECC. If RS is used, the ECC bytes is
2170 * always 10 bytes
2171 */
Abhishek Sahu58f1f222017-08-11 17:09:17 +05302172 if (nandc->props->ecc_modes & ECC_BCH_4BIT) {
Archit Tanejac76b78d2016-02-03 14:29:50 +05302173 /* BCH */
2174 host->bch_enabled = true;
2175 ecc_mode = 0;
2176
2177 if (wide_bus) {
2178 host->ecc_bytes_hw = 8;
2179 host->spare_bytes = 2;
2180 host->bbm_size = 2;
2181 } else {
2182 host->ecc_bytes_hw = 7;
2183 host->spare_bytes = 4;
2184 host->bbm_size = 1;
2185 }
2186 } else {
2187 /* RS */
2188 host->ecc_bytes_hw = 10;
2189
2190 if (wide_bus) {
2191 host->spare_bytes = 0;
2192 host->bbm_size = 2;
2193 } else {
2194 host->spare_bytes = 1;
2195 host->bbm_size = 1;
2196 }
2197 }
2198 }
2199
2200 /*
2201 * we consider ecc->bytes as the sum of all the non-data content in a
2202 * step. It gives us a clean representation of the oob area (even if
2203 * all the bytes aren't used for ECC).It is always 16 bytes for 8 bit
2204 * ECC and 12 bytes for 4 bit ECC
2205 */
2206 ecc->bytes = host->ecc_bytes_hw + host->spare_bytes + host->bbm_size;
2207
2208 ecc->read_page = qcom_nandc_read_page;
2209 ecc->read_page_raw = qcom_nandc_read_page_raw;
2210 ecc->read_oob = qcom_nandc_read_oob;
2211 ecc->write_page = qcom_nandc_write_page;
2212 ecc->write_page_raw = qcom_nandc_write_page_raw;
2213 ecc->write_oob = qcom_nandc_write_oob;
2214
2215 ecc->mode = NAND_ECC_HW;
2216
Boris Brezillon421e81c2016-03-18 17:54:27 +01002217 mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
Archit Tanejac76b78d2016-02-03 14:29:50 +05302218
2219 cwperpage = mtd->writesize / ecc->size;
Abhishek Sahucb80f112017-08-17 17:37:40 +05302220 nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage,
2221 cwperpage);
Archit Tanejac76b78d2016-02-03 14:29:50 +05302222
2223 /*
2224 * DATA_UD_BYTES varies based on whether the read/write command protects
2225 * spare data with ECC too. We protect spare data by default, so we set
2226 * it to main + spare data, which are 512 and 4 bytes respectively.
2227 */
2228 host->cw_data = 516;
2229
2230 /*
2231 * total bytes in a step, either 528 bytes for 4 bit ECC, or 532 bytes
2232 * for 8 bit ECC
2233 */
2234 host->cw_size = host->cw_data + ecc->bytes;
2235
2236 if (ecc->bytes * (mtd->writesize / ecc->size) > mtd->oobsize) {
2237 dev_err(nandc->dev, "ecc data doesn't fit in OOB area\n");
2238 return -EINVAL;
2239 }
2240
2241 bad_block_byte = mtd->writesize - host->cw_size * (cwperpage - 1) + 1;
2242
2243 host->cfg0 = (cwperpage - 1) << CW_PER_PAGE
2244 | host->cw_data << UD_SIZE_BYTES
2245 | 0 << DISABLE_STATUS_AFTER_WRITE
2246 | 5 << NUM_ADDR_CYCLES
2247 | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_RS
2248 | 0 << STATUS_BFR_READ
2249 | 1 << SET_RD_MODE_AFTER_STATUS
2250 | host->spare_bytes << SPARE_SIZE_BYTES;
2251
2252 host->cfg1 = 7 << NAND_RECOVERY_CYCLES
2253 | 0 << CS_ACTIVE_BSY
2254 | bad_block_byte << BAD_BLOCK_BYTE_NUM
2255 | 0 << BAD_BLOCK_IN_SPARE_AREA
2256 | 2 << WR_RD_BSY_GAP
2257 | wide_bus << WIDE_FLASH
2258 | host->bch_enabled << ENABLE_BCH_ECC;
2259
2260 host->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE
2261 | host->cw_size << UD_SIZE_BYTES
2262 | 5 << NUM_ADDR_CYCLES
2263 | 0 << SPARE_SIZE_BYTES;
2264
2265 host->cfg1_raw = 7 << NAND_RECOVERY_CYCLES
2266 | 0 << CS_ACTIVE_BSY
2267 | 17 << BAD_BLOCK_BYTE_NUM
2268 | 1 << BAD_BLOCK_IN_SPARE_AREA
2269 | 2 << WR_RD_BSY_GAP
2270 | wide_bus << WIDE_FLASH
2271 | 1 << DEV0_CFG1_ECC_DISABLE;
2272
Abhishek Sahu10777de2017-08-03 17:56:39 +02002273 host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
Archit Tanejac76b78d2016-02-03 14:29:50 +05302274 | 0 << ECC_SW_RESET
2275 | host->cw_data << ECC_NUM_DATA_BYTES
2276 | 1 << ECC_FORCE_CLK_OPEN
2277 | ecc_mode << ECC_MODE
2278 | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
2279
2280 host->ecc_buf_cfg = 0x203 << NUM_STEPS;
2281
2282 host->clrflashstatus = FS_READY_BSY_N;
2283 host->clrreadstatus = 0xc0;
Abhishek Sahua86b9c42017-08-17 17:37:44 +05302284 nandc->regs->erased_cw_detect_cfg_clr =
2285 cpu_to_le32(CLR_ERASED_PAGE_DET);
2286 nandc->regs->erased_cw_detect_cfg_set =
2287 cpu_to_le32(SET_ERASED_PAGE_DET);
Archit Tanejac76b78d2016-02-03 14:29:50 +05302288
2289 dev_dbg(nandc->dev,
2290 "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
2291 host->cfg0, host->cfg1, host->ecc_buf_cfg, host->ecc_bch_cfg,
2292 host->cw_size, host->cw_data, ecc->strength, ecc->bytes,
2293 cwperpage);
2294
2295 return 0;
2296}
2297
2298static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
2299{
2300 int ret;
2301
2302 ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32));
2303 if (ret) {
2304 dev_err(nandc->dev, "failed to set DMA mask\n");
2305 return ret;
2306 }
2307
2308 /*
2309 * we use the internal buffer for reading ONFI params, reading small
2310 * data like ID and status, and preforming read-copy-write operations
2311 * when writing to a codeword partially. 532 is the maximum possible
2312 * size of a codeword for our nand controller
2313 */
2314 nandc->buf_size = 532;
2315
2316 nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size,
2317 GFP_KERNEL);
2318 if (!nandc->data_buffer)
2319 return -ENOMEM;
2320
2321 nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs),
2322 GFP_KERNEL);
2323 if (!nandc->regs)
2324 return -ENOMEM;
2325
2326 nandc->reg_read_buf = devm_kzalloc(nandc->dev,
2327 MAX_REG_RD * sizeof(*nandc->reg_read_buf),
2328 GFP_KERNEL);
2329 if (!nandc->reg_read_buf)
2330 return -ENOMEM;
2331
Abhishek Sahu497d7d82017-08-11 17:09:19 +05302332 if (nandc->props->is_bam) {
Abhishek Sahu6192ff72017-08-17 17:37:39 +05302333 nandc->reg_read_dma =
2334 dma_map_single(nandc->dev, nandc->reg_read_buf,
2335 MAX_REG_RD *
2336 sizeof(*nandc->reg_read_buf),
2337 DMA_FROM_DEVICE);
2338 if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) {
2339 dev_err(nandc->dev, "failed to DMA MAP reg buffer\n");
2340 return -EIO;
2341 }
2342
Abhishek Sahu497d7d82017-08-11 17:09:19 +05302343 nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
2344 if (!nandc->tx_chan) {
2345 dev_err(nandc->dev, "failed to request tx channel\n");
2346 return -ENODEV;
2347 }
2348
2349 nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
2350 if (!nandc->rx_chan) {
2351 dev_err(nandc->dev, "failed to request rx channel\n");
2352 return -ENODEV;
2353 }
2354
2355 nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
2356 if (!nandc->cmd_chan) {
2357 dev_err(nandc->dev, "failed to request cmd channel\n");
2358 return -ENODEV;
2359 }
Abhishek Sahucb80f112017-08-17 17:37:40 +05302360
2361 /*
2362 * Initially allocate BAM transaction to read ONFI param page.
2363 * After detecting all the devices, this BAM transaction will
2364 * be freed and the next BAM tranasction will be allocated with
2365 * maximum codeword size
2366 */
2367 nandc->max_cwperpage = 1;
2368 nandc->bam_txn = alloc_bam_transaction(nandc);
2369 if (!nandc->bam_txn) {
2370 dev_err(nandc->dev,
2371 "failed to allocate bam transaction\n");
2372 return -ENOMEM;
2373 }
Abhishek Sahu497d7d82017-08-11 17:09:19 +05302374 } else {
2375 nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
2376 if (!nandc->chan) {
2377 dev_err(nandc->dev,
2378 "failed to request slave channel\n");
2379 return -ENODEV;
2380 }
Archit Tanejac76b78d2016-02-03 14:29:50 +05302381 }
2382
2383 INIT_LIST_HEAD(&nandc->desc_list);
2384 INIT_LIST_HEAD(&nandc->host_list);
2385
Marc Gonzalezd45bc582016-07-27 11:23:52 +02002386 nand_hw_control_init(&nandc->controller);
Archit Tanejac76b78d2016-02-03 14:29:50 +05302387
2388 return 0;
2389}
2390
2391static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
2392{
Abhishek Sahu497d7d82017-08-11 17:09:19 +05302393 if (nandc->props->is_bam) {
Abhishek Sahu6192ff72017-08-17 17:37:39 +05302394 if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma))
2395 dma_unmap_single(nandc->dev, nandc->reg_read_dma,
2396 MAX_REG_RD *
2397 sizeof(*nandc->reg_read_buf),
2398 DMA_FROM_DEVICE);
2399
Abhishek Sahu497d7d82017-08-11 17:09:19 +05302400 if (nandc->tx_chan)
2401 dma_release_channel(nandc->tx_chan);
2402
2403 if (nandc->rx_chan)
2404 dma_release_channel(nandc->rx_chan);
2405
2406 if (nandc->cmd_chan)
2407 dma_release_channel(nandc->cmd_chan);
2408 } else {
2409 if (nandc->chan)
2410 dma_release_channel(nandc->chan);
2411 }
Archit Tanejac76b78d2016-02-03 14:29:50 +05302412}
2413
2414/* one time setup of a few nand controller registers */
2415static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
2416{
2417 /* kill onenand */
2418 nandc_write(nandc, SFLASHC_BURST_CFG, 0);
Abhishek Sahud8a9b322017-08-11 17:09:16 +05302419 nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
Archit Tanejac76b78d2016-02-03 14:29:50 +05302420
2421 /* enable ADM DMA */
2422 nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
2423
2424 /* save the original values of these registers */
2425 nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
Abhishek Sahud8a9b322017-08-11 17:09:16 +05302426 nandc->vld = NAND_DEV_CMD_VLD_VAL;
Archit Tanejac76b78d2016-02-03 14:29:50 +05302427
2428 return 0;
2429}
2430
2431static int qcom_nand_host_init(struct qcom_nand_controller *nandc,
2432 struct qcom_nand_host *host,
2433 struct device_node *dn)
2434{
2435 struct nand_chip *chip = &host->chip;
2436 struct mtd_info *mtd = nand_to_mtd(chip);
2437 struct device *dev = nandc->dev;
2438 int ret;
2439
2440 ret = of_property_read_u32(dn, "reg", &host->cs);
2441 if (ret) {
2442 dev_err(dev, "can't get chip-select\n");
2443 return -ENXIO;
2444 }
2445
2446 nand_set_flash_node(chip, dn);
2447 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "qcom_nand.%d", host->cs);
2448 mtd->owner = THIS_MODULE;
2449 mtd->dev.parent = dev;
2450
2451 chip->cmdfunc = qcom_nandc_command;
2452 chip->select_chip = qcom_nandc_select_chip;
2453 chip->read_byte = qcom_nandc_read_byte;
2454 chip->read_buf = qcom_nandc_read_buf;
2455 chip->write_buf = qcom_nandc_write_buf;
Boris Brezillon4a78cc62017-05-26 17:10:15 +02002456 chip->onfi_set_features = nand_onfi_get_set_features_notsupp;
2457 chip->onfi_get_features = nand_onfi_get_set_features_notsupp;
Archit Tanejac76b78d2016-02-03 14:29:50 +05302458
2459 /*
2460 * the bad block marker is readable only when we read the last codeword
2461 * of a page with ECC disabled. currently, the nand_base and nand_bbt
2462 * helpers don't allow us to read BB from a nand chip with ECC
2463 * disabled (MTD_OPS_PLACE_OOB is set by default). use the block_bad
2464 * and block_markbad helpers until we permanently switch to using
2465 * MTD_OPS_RAW for all drivers (with the help of badblockbits)
2466 */
2467 chip->block_bad = qcom_nandc_block_bad;
2468 chip->block_markbad = qcom_nandc_block_markbad;
2469
2470 chip->controller = &nandc->controller;
2471 chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER |
2472 NAND_SKIP_BBTSCAN;
2473
2474 /* set up initial status value */
2475 host->status = NAND_STATUS_READY | NAND_STATUS_WP;
2476
2477 ret = nand_scan_ident(mtd, 1, NULL);
2478 if (ret)
2479 return ret;
2480
2481 ret = qcom_nand_host_setup(host);
Abhishek Sahu89f51272017-07-19 17:17:58 +05302482
2483 return ret;
2484}
2485
2486static int qcom_nand_mtd_register(struct qcom_nand_controller *nandc,
2487 struct qcom_nand_host *host,
2488 struct device_node *dn)
2489{
2490 struct nand_chip *chip = &host->chip;
2491 struct mtd_info *mtd = nand_to_mtd(chip);
2492 int ret;
Archit Tanejac76b78d2016-02-03 14:29:50 +05302493
2494 ret = nand_scan_tail(mtd);
2495 if (ret)
2496 return ret;
2497
Abhishek Sahu89f51272017-07-19 17:17:58 +05302498 ret = mtd_device_register(mtd, NULL, 0);
2499 if (ret)
2500 nand_cleanup(mtd_to_nand(mtd));
2501
2502 return ret;
2503}
2504
2505static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc)
2506{
2507 struct device *dev = nandc->dev;
2508 struct device_node *dn = dev->of_node, *child;
2509 struct qcom_nand_host *host, *tmp;
2510 int ret;
2511
2512 for_each_available_child_of_node(dn, child) {
2513 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2514 if (!host) {
2515 of_node_put(child);
2516 return -ENOMEM;
2517 }
2518
2519 ret = qcom_nand_host_init(nandc, host, child);
2520 if (ret) {
2521 devm_kfree(dev, host);
2522 continue;
2523 }
2524
2525 list_add_tail(&host->node, &nandc->host_list);
2526 }
2527
2528 if (list_empty(&nandc->host_list))
2529 return -ENODEV;
2530
Abhishek Sahucb80f112017-08-17 17:37:40 +05302531 if (nandc->props->is_bam) {
2532 free_bam_transaction(nandc);
2533 nandc->bam_txn = alloc_bam_transaction(nandc);
2534 if (!nandc->bam_txn) {
2535 dev_err(nandc->dev,
2536 "failed to allocate bam transaction\n");
2537 return -ENOMEM;
2538 }
2539 }
2540
Abhishek Sahu89f51272017-07-19 17:17:58 +05302541 list_for_each_entry_safe(host, tmp, &nandc->host_list, node) {
2542 ret = qcom_nand_mtd_register(nandc, host, child);
2543 if (ret) {
2544 list_del(&host->node);
2545 devm_kfree(dev, host);
2546 }
2547 }
2548
2549 if (list_empty(&nandc->host_list))
2550 return -ENODEV;
2551
2552 return 0;
Archit Tanejac76b78d2016-02-03 14:29:50 +05302553}
2554
2555/* parse custom DT properties here */
2556static int qcom_nandc_parse_dt(struct platform_device *pdev)
2557{
2558 struct qcom_nand_controller *nandc = platform_get_drvdata(pdev);
2559 struct device_node *np = nandc->dev->of_node;
2560 int ret;
2561
Abhishek Sahu497d7d82017-08-11 17:09:19 +05302562 if (!nandc->props->is_bam) {
2563 ret = of_property_read_u32(np, "qcom,cmd-crci",
2564 &nandc->cmd_crci);
2565 if (ret) {
2566 dev_err(nandc->dev, "command CRCI unspecified\n");
2567 return ret;
2568 }
Archit Tanejac76b78d2016-02-03 14:29:50 +05302569
Abhishek Sahu497d7d82017-08-11 17:09:19 +05302570 ret = of_property_read_u32(np, "qcom,data-crci",
2571 &nandc->data_crci);
2572 if (ret) {
2573 dev_err(nandc->dev, "data CRCI unspecified\n");
2574 return ret;
2575 }
Archit Tanejac76b78d2016-02-03 14:29:50 +05302576 }
2577
2578 return 0;
2579}
2580
2581static int qcom_nandc_probe(struct platform_device *pdev)
2582{
2583 struct qcom_nand_controller *nandc;
Archit Tanejac76b78d2016-02-03 14:29:50 +05302584 const void *dev_data;
2585 struct device *dev = &pdev->dev;
Archit Tanejac76b78d2016-02-03 14:29:50 +05302586 struct resource *res;
2587 int ret;
2588
2589 nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
2590 if (!nandc)
2591 return -ENOMEM;
2592
2593 platform_set_drvdata(pdev, nandc);
2594 nandc->dev = dev;
2595
2596 dev_data = of_device_get_match_data(dev);
2597 if (!dev_data) {
2598 dev_err(&pdev->dev, "failed to get device data\n");
2599 return -ENODEV;
2600 }
2601
Abhishek Sahu58f1f222017-08-11 17:09:17 +05302602 nandc->props = dev_data;
Archit Tanejac76b78d2016-02-03 14:29:50 +05302603
2604 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2605 nandc->base = devm_ioremap_resource(dev, res);
2606 if (IS_ERR(nandc->base))
2607 return PTR_ERR(nandc->base);
2608
2609 nandc->base_dma = phys_to_dma(dev, (phys_addr_t)res->start);
2610
2611 nandc->core_clk = devm_clk_get(dev, "core");
2612 if (IS_ERR(nandc->core_clk))
2613 return PTR_ERR(nandc->core_clk);
2614
2615 nandc->aon_clk = devm_clk_get(dev, "aon");
2616 if (IS_ERR(nandc->aon_clk))
2617 return PTR_ERR(nandc->aon_clk);
2618
2619 ret = qcom_nandc_parse_dt(pdev);
2620 if (ret)
2621 return ret;
2622
2623 ret = qcom_nandc_alloc(nandc);
2624 if (ret)
Abhishek Sahu497d7d82017-08-11 17:09:19 +05302625 goto err_core_clk;
Archit Tanejac76b78d2016-02-03 14:29:50 +05302626
2627 ret = clk_prepare_enable(nandc->core_clk);
2628 if (ret)
2629 goto err_core_clk;
2630
2631 ret = clk_prepare_enable(nandc->aon_clk);
2632 if (ret)
2633 goto err_aon_clk;
2634
2635 ret = qcom_nandc_setup(nandc);
2636 if (ret)
2637 goto err_setup;
2638
Abhishek Sahu89f51272017-07-19 17:17:58 +05302639 ret = qcom_probe_nand_devices(nandc);
2640 if (ret)
2641 goto err_setup;
Archit Tanejac76b78d2016-02-03 14:29:50 +05302642
2643 return 0;
2644
Archit Tanejac76b78d2016-02-03 14:29:50 +05302645err_setup:
2646 clk_disable_unprepare(nandc->aon_clk);
2647err_aon_clk:
2648 clk_disable_unprepare(nandc->core_clk);
2649err_core_clk:
2650 qcom_nandc_unalloc(nandc);
2651
2652 return ret;
2653}
2654
2655static int qcom_nandc_remove(struct platform_device *pdev)
2656{
2657 struct qcom_nand_controller *nandc = platform_get_drvdata(pdev);
2658 struct qcom_nand_host *host;
2659
2660 list_for_each_entry(host, &nandc->host_list, node)
2661 nand_release(nand_to_mtd(&host->chip));
2662
2663 qcom_nandc_unalloc(nandc);
2664
2665 clk_disable_unprepare(nandc->aon_clk);
2666 clk_disable_unprepare(nandc->core_clk);
2667
2668 return 0;
2669}
2670
Abhishek Sahu58f1f222017-08-11 17:09:17 +05302671static const struct qcom_nandc_props ipq806x_nandc_props = {
2672 .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
Abhishek Sahu8c5d5d62017-08-11 17:09:18 +05302673 .is_bam = false,
Abhishek Sahu58f1f222017-08-11 17:09:17 +05302674};
Archit Tanejac76b78d2016-02-03 14:29:50 +05302675
2676/*
2677 * data will hold a struct pointer containing more differences once we support
2678 * more controller variants
2679 */
2680static const struct of_device_id qcom_nandc_of_match[] = {
Abhishek Sahu58f1f222017-08-11 17:09:17 +05302681 {
2682 .compatible = "qcom,ipq806x-nand",
2683 .data = &ipq806x_nandc_props,
Archit Tanejac76b78d2016-02-03 14:29:50 +05302684 },
2685 {}
2686};
2687MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
2688
2689static struct platform_driver qcom_nandc_driver = {
2690 .driver = {
2691 .name = "qcom-nandc",
2692 .of_match_table = qcom_nandc_of_match,
2693 },
2694 .probe = qcom_nandc_probe,
2695 .remove = qcom_nandc_remove,
2696};
2697module_platform_driver(qcom_nandc_driver);
2698
2699MODULE_AUTHOR("Archit Taneja <architt@codeaurora.org>");
2700MODULE_DESCRIPTION("Qualcomm NAND Controller driver");
2701MODULE_LICENSE("GPL v2");