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Bard Liao07cf7cba2014-06-20 14:41:13 +08001/*
2 * rt286.c -- RT286 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
Bard Liao6c67cde22014-11-06 09:59:59 +080020#include <linux/dmi.h>
Bard Liao07cf7cba2014-06-20 14:41:13 +080021#include <linux/acpi.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <sound/jack.h>
30#include <linux/workqueue.h>
31#include <sound/rt286.h>
32#include <sound/hda_verbs.h>
33
Oder Chioubc08f962015-06-12 17:06:29 +080034#include "rl6347a.h"
Bard Liao07cf7cba2014-06-20 14:41:13 +080035#include "rt286.h"
36
37#define RT286_VENDOR_ID 0x10ec0286
Bard Liao3ab888d2015-02-09 14:19:45 +080038#define RT288_VENDOR_ID 0x10ec0288
Bard Liao07cf7cba2014-06-20 14:41:13 +080039
40struct rt286_priv {
Oder Chioubc08f962015-06-12 17:06:29 +080041 struct reg_default *index_cache;
42 int index_cache_size;
Bard Liao07cf7cba2014-06-20 14:41:13 +080043 struct regmap *regmap;
Bard Liao6879db72014-10-31 14:52:16 +080044 struct snd_soc_codec *codec;
Bard Liao07cf7cba2014-06-20 14:41:13 +080045 struct rt286_platform_data pdata;
46 struct i2c_client *i2c;
47 struct snd_soc_jack *jack;
48 struct delayed_work jack_detect_work;
49 int sys_clk;
Bard Liao6879db72014-10-31 14:52:16 +080050 int clk_id;
Bard Liao07cf7cba2014-06-20 14:41:13 +080051};
52
53static struct reg_default rt286_index_def[] = {
54 { 0x01, 0xaaaa },
55 { 0x02, 0x8aaa },
56 { 0x03, 0x0002 },
57 { 0x04, 0xaf01 },
58 { 0x08, 0x000d },
59 { 0x09, 0xd810 },
Bard Liaob7a29762014-09-26 11:06:39 +080060 { 0x0a, 0x0120 },
Bard Liao07cf7cba2014-06-20 14:41:13 +080061 { 0x0b, 0x0000 },
Bard Liaobc6c4e42014-07-07 19:15:30 +080062 { 0x0d, 0x2800 },
Bard Liao07cf7cba2014-06-20 14:41:13 +080063 { 0x0f, 0x0000 },
64 { 0x19, 0x0a17 },
65 { 0x20, 0x0020 },
66 { 0x33, 0x0208 },
67 { 0x49, 0x0004 },
68 { 0x4f, 0x50e9 },
Bard Liaob7a29762014-09-26 11:06:39 +080069 { 0x50, 0x2000 },
Bard Liao07cf7cba2014-06-20 14:41:13 +080070 { 0x63, 0x2902 },
Bard Liaobc6c4e42014-07-07 19:15:30 +080071 { 0x67, 0x1111 },
72 { 0x68, 0x1016 },
73 { 0x69, 0x273f },
Bard Liao07cf7cba2014-06-20 14:41:13 +080074};
75#define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
76
77static const struct reg_default rt286_reg[] = {
78 { 0x00170500, 0x00000400 },
79 { 0x00220000, 0x00000031 },
80 { 0x00239000, 0x0000007f },
81 { 0x0023a000, 0x0000007f },
82 { 0x00270500, 0x00000400 },
83 { 0x00370500, 0x00000400 },
84 { 0x00870500, 0x00000400 },
85 { 0x00920000, 0x00000031 },
86 { 0x00935000, 0x000000c3 },
87 { 0x00936000, 0x000000c3 },
88 { 0x00970500, 0x00000400 },
89 { 0x00b37000, 0x00000097 },
90 { 0x00b37200, 0x00000097 },
91 { 0x00b37300, 0x00000097 },
92 { 0x00c37000, 0x00000000 },
93 { 0x00c37100, 0x00000080 },
94 { 0x01270500, 0x00000400 },
95 { 0x01370500, 0x00000400 },
96 { 0x01371f00, 0x411111f0 },
97 { 0x01439000, 0x00000080 },
98 { 0x0143a000, 0x00000080 },
99 { 0x01470700, 0x00000000 },
100 { 0x01470500, 0x00000400 },
101 { 0x01470c00, 0x00000000 },
102 { 0x01470100, 0x00000000 },
103 { 0x01837000, 0x00000000 },
104 { 0x01870500, 0x00000400 },
105 { 0x02050000, 0x00000000 },
106 { 0x02139000, 0x00000080 },
107 { 0x0213a000, 0x00000080 },
108 { 0x02170100, 0x00000000 },
109 { 0x02170500, 0x00000400 },
110 { 0x02170700, 0x00000000 },
111 { 0x02270100, 0x00000000 },
112 { 0x02370100, 0x00000000 },
Bard Liao07cf7cba2014-06-20 14:41:13 +0800113 { 0x01870700, 0x00000020 },
114 { 0x00830000, 0x000000c3 },
115 { 0x00930000, 0x000000c3 },
116 { 0x01270700, 0x00000000 },
117};
118
119static bool rt286_volatile_register(struct device *dev, unsigned int reg)
120{
121 switch (reg) {
122 case 0 ... 0xff:
123 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
124 case RT286_GET_HP_SENSE:
125 case RT286_GET_MIC1_SENSE:
126 case RT286_PROC_COEF:
127 return true;
128 default:
129 return false;
130 }
131
132
133}
134
135static bool rt286_readable_register(struct device *dev, unsigned int reg)
136{
137 switch (reg) {
138 case 0 ... 0xff:
139 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
140 case RT286_GET_HP_SENSE:
141 case RT286_GET_MIC1_SENSE:
142 case RT286_SET_AUDIO_POWER:
143 case RT286_SET_HPO_POWER:
144 case RT286_SET_SPK_POWER:
145 case RT286_SET_DMIC1_POWER:
146 case RT286_SPK_MUX:
147 case RT286_HPO_MUX:
148 case RT286_ADC0_MUX:
149 case RT286_ADC1_MUX:
150 case RT286_SET_MIC1:
151 case RT286_SET_PIN_HPO:
152 case RT286_SET_PIN_SPK:
153 case RT286_SET_PIN_DMIC1:
154 case RT286_SPK_EAPD:
155 case RT286_SET_AMP_GAIN_HPO:
156 case RT286_SET_DMIC2_DEFAULT:
157 case RT286_DACL_GAIN:
158 case RT286_DACR_GAIN:
159 case RT286_ADCL_GAIN:
160 case RT286_ADCR_GAIN:
161 case RT286_MIC_GAIN:
162 case RT286_SPOL_GAIN:
163 case RT286_SPOR_GAIN:
164 case RT286_HPOL_GAIN:
165 case RT286_HPOR_GAIN:
166 case RT286_F_DAC_SWITCH:
167 case RT286_F_RECMIX_SWITCH:
168 case RT286_REC_MIC_SWITCH:
169 case RT286_REC_I2S_SWITCH:
170 case RT286_REC_LINE_SWITCH:
171 case RT286_REC_BEEP_SWITCH:
172 case RT286_DAC_FORMAT:
173 case RT286_ADC_FORMAT:
174 case RT286_COEF_INDEX:
175 case RT286_PROC_COEF:
176 case RT286_SET_AMP_GAIN_ADC_IN1:
177 case RT286_SET_AMP_GAIN_ADC_IN2:
178 case RT286_SET_POWER(RT286_DAC_OUT1):
179 case RT286_SET_POWER(RT286_DAC_OUT2):
180 case RT286_SET_POWER(RT286_ADC_IN1):
181 case RT286_SET_POWER(RT286_ADC_IN2):
182 case RT286_SET_POWER(RT286_DMIC2):
183 case RT286_SET_POWER(RT286_MIC1):
184 return true;
185 default:
186 return false;
187 }
188}
189
Thierry Reding81f3dfe2014-10-02 09:27:03 +0200190#ifdef CONFIG_PM
Bard Liao07cf7cba2014-06-20 14:41:13 +0800191static void rt286_index_sync(struct snd_soc_codec *codec)
192{
193 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
194 int i;
195
196 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
197 snd_soc_write(codec, rt286->index_cache[i].reg,
198 rt286->index_cache[i].def);
199 }
200}
Thierry Reding81f3dfe2014-10-02 09:27:03 +0200201#endif
Bard Liao07cf7cba2014-06-20 14:41:13 +0800202
203static int rt286_support_power_controls[] = {
204 RT286_DAC_OUT1,
205 RT286_DAC_OUT2,
206 RT286_ADC_IN1,
207 RT286_ADC_IN2,
208 RT286_MIC1,
209 RT286_DMIC1,
210 RT286_DMIC2,
211 RT286_SPK_OUT,
212 RT286_HP_OUT,
213};
214#define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
215
Bard Liao90f601e2014-07-29 13:50:57 +0800216static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
Bard Liao07cf7cba2014-06-20 14:41:13 +0800217{
Bard Liao07cf7cba2014-06-20 14:41:13 +0800218 unsigned int val, buf;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800219
220 *hp = false;
221 *mic = false;
222
Bard Liao28d1ad02015-02-05 16:40:33 +0800223 if (!rt286->codec)
224 return -EINVAL;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800225 if (rt286->pdata.cbj_en) {
Bard Liao90f601e2014-07-29 13:50:57 +0800226 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800227 *hp = buf & 0x80000000;
228 if (*hp) {
229 /* power on HV,VERF */
Bard Liao90f601e2014-07-29 13:50:57 +0800230 regmap_update_bits(rt286->regmap,
Bard Liao6879db72014-10-31 14:52:16 +0800231 RT286_DC_GAIN, 0x200, 0x200);
232
233 snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
234 "HV");
235 snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
236 "VREF");
Bard Liao07cf7cba2014-06-20 14:41:13 +0800237 /* power LDO1 */
Bard Liao6879db72014-10-31 14:52:16 +0800238 snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
239 "LDO1");
240 snd_soc_dapm_sync(&rt286->codec->dapm);
241
Bard Liao90f601e2014-07-29 13:50:57 +0800242 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
Bard Liao6879db72014-10-31 14:52:16 +0800243 msleep(50);
244
245 regmap_update_bits(rt286->regmap,
246 RT286_CBJ_CTRL1, 0xfcc0, 0xd400);
247 msleep(300);
Bard Liao90f601e2014-07-29 13:50:57 +0800248 regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800249
Bard Liao6879db72014-10-31 14:52:16 +0800250 if (0x0070 == (val & 0x0070)) {
251 *mic = true;
252 } else {
253 regmap_update_bits(rt286->regmap,
254 RT286_CBJ_CTRL1, 0xfcc0, 0xe400);
255 msleep(300);
Bard Liao90f601e2014-07-29 13:50:57 +0800256 regmap_read(rt286->regmap,
257 RT286_CBJ_CTRL2, &val);
Bard Liao6879db72014-10-31 14:52:16 +0800258 if (0x0070 == (val & 0x0070))
259 *mic = true;
260 else
261 *mic = false;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800262 }
Bard Liao90f601e2014-07-29 13:50:57 +0800263 regmap_update_bits(rt286->regmap,
Bard Liao6879db72014-10-31 14:52:16 +0800264 RT286_DC_GAIN, 0x200, 0x0);
265
Bard Liao07cf7cba2014-06-20 14:41:13 +0800266 } else {
Bard Liao07cf7cba2014-06-20 14:41:13 +0800267 *mic = false;
Bard Liao6879db72014-10-31 14:52:16 +0800268 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800269 }
270 } else {
Bard Liao90f601e2014-07-29 13:50:57 +0800271 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800272 *hp = buf & 0x80000000;
Bard Liao90f601e2014-07-29 13:50:57 +0800273 regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800274 *mic = buf & 0x80000000;
275 }
276
Bard Liao6879db72014-10-31 14:52:16 +0800277 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "HV");
278 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "VREF");
279 if (!*hp)
280 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "LDO1");
281 snd_soc_dapm_sync(&rt286->codec->dapm);
282
Bard Liao07cf7cba2014-06-20 14:41:13 +0800283 return 0;
284}
285
286static void rt286_jack_detect_work(struct work_struct *work)
287{
288 struct rt286_priv *rt286 =
289 container_of(work, struct rt286_priv, jack_detect_work.work);
290 int status = 0;
291 bool hp = false;
292 bool mic = false;
293
Bard Liao90f601e2014-07-29 13:50:57 +0800294 rt286_jack_detect(rt286, &hp, &mic);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800295
296 if (hp == true)
297 status |= SND_JACK_HEADPHONE;
298
299 if (mic == true)
300 status |= SND_JACK_MICROPHONE;
301
302 snd_soc_jack_report(rt286->jack, status,
303 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
304}
305
306int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
307{
308 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
309
310 rt286->jack = jack;
311
Jie Yange2cef682015-02-10 17:01:56 +0800312 if (jack) {
313 /* enable IRQ */
Jie Yang5af76d52015-02-27 12:52:26 +0800314 if (rt286->jack->status & SND_JACK_HEADPHONE)
Jie Yange2cef682015-02-10 17:01:56 +0800315 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO1");
316 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x2);
317 /* Send an initial empty report */
318 snd_soc_jack_report(rt286->jack, rt286->jack->status,
319 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
320 } else {
321 /* disable IRQ */
322 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x0);
323 snd_soc_dapm_disable_pin(&codec->dapm, "LDO1");
324 }
325 snd_soc_dapm_sync(&codec->dapm);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800326
327 return 0;
328}
329EXPORT_SYMBOL_GPL(rt286_mic_detect);
330
Bard Liao6879db72014-10-31 14:52:16 +0800331static int is_mclk_mode(struct snd_soc_dapm_widget *source,
332 struct snd_soc_dapm_widget *sink)
333{
Lars-Peter Clausen76f17f12015-01-15 12:52:10 +0100334 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
335 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
Bard Liao6879db72014-10-31 14:52:16 +0800336
337 if (rt286->clk_id == RT286_SCLK_S_MCLK)
338 return 1;
339 else
340 return 0;
341}
342
Bard Liao07cf7cba2014-06-20 14:41:13 +0800343static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
344static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
345
346static const struct snd_kcontrol_new rt286_snd_controls[] = {
347 SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
348 RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
Bard Liao54d96a42015-01-23 14:51:09 +0800349 SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN,
350 RT286_ADCR_GAIN, 7, 1, 1),
Bard Liao07cf7cba2014-06-20 14:41:13 +0800351 SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
352 RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
353 SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
354 0, 0x3, 0, mic_vol_tlv),
355 SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
356 RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
357};
358
359/* Digital Mixer */
360static const struct snd_kcontrol_new rt286_front_mix[] = {
361 SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH,
362 RT286_MUTE_SFT, 1, 1),
363 SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
364 RT286_MUTE_SFT, 1, 1),
365};
366
367/* Analog Input Mixer */
368static const struct snd_kcontrol_new rt286_rec_mix[] = {
369 SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
370 RT286_MUTE_SFT, 1, 1),
371 SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
372 RT286_MUTE_SFT, 1, 1),
373 SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
374 RT286_MUTE_SFT, 1, 1),
375 SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
376 RT286_MUTE_SFT, 1, 1),
377};
378
379static const struct snd_kcontrol_new spo_enable_control =
380 SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
381 RT286_SET_PIN_SFT, 1, 0);
382
383static const struct snd_kcontrol_new hpol_enable_control =
384 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
385 RT286_MUTE_SFT, 1, 1);
386
387static const struct snd_kcontrol_new hpor_enable_control =
388 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
389 RT286_MUTE_SFT, 1, 1);
390
391/* ADC0 source */
392static const char * const rt286_adc_src[] = {
393 "Mic", "RECMIX", "Dmic"
394};
395
396static const int rt286_adc_values[] = {
397 0, 4, 5,
398};
399
400static SOC_VALUE_ENUM_SINGLE_DECL(
401 rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
402 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
403
404static const struct snd_kcontrol_new rt286_adc0_mux =
405 SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
406
407static SOC_VALUE_ENUM_SINGLE_DECL(
408 rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
409 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
410
411static const struct snd_kcontrol_new rt286_adc1_mux =
412 SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
413
414static const char * const rt286_dac_src[] = {
415 "Front", "Surround"
416};
417/* HP-OUT source */
418static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
419 0, rt286_dac_src);
420
421static const struct snd_kcontrol_new rt286_hpo_mux =
422SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
423
424/* SPK-OUT source */
425static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
426 0, rt286_dac_src);
427
428static const struct snd_kcontrol_new rt286_spo_mux =
429SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
430
431static int rt286_spk_event(struct snd_soc_dapm_widget *w,
432 struct snd_kcontrol *kcontrol, int event)
433{
Lars-Peter Clausen76f17f12015-01-15 12:52:10 +0100434 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800435
436 switch (event) {
437 case SND_SOC_DAPM_POST_PMU:
438 snd_soc_write(codec,
439 RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
440 break;
441 case SND_SOC_DAPM_PRE_PMD:
442 snd_soc_write(codec,
443 RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
444 break;
445
446 default:
447 return 0;
448 }
449
450 return 0;
451}
452
453static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
454 struct snd_kcontrol *kcontrol, int event)
455{
Lars-Peter Clausen76f17f12015-01-15 12:52:10 +0100456 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800457
458 switch (event) {
459 case SND_SOC_DAPM_POST_PMU:
460 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20);
461 break;
462 case SND_SOC_DAPM_PRE_PMD:
463 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0);
464 break;
465 default:
466 return 0;
467 }
468
469 return 0;
470}
471
Bard Liao6879db72014-10-31 14:52:16 +0800472static int rt286_vref_event(struct snd_soc_dapm_widget *w,
473 struct snd_kcontrol *kcontrol, int event)
474{
Lars-Peter Clausen76f17f12015-01-15 12:52:10 +0100475 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Bard Liao6879db72014-10-31 14:52:16 +0800476
477 switch (event) {
478 case SND_SOC_DAPM_PRE_PMU:
479 snd_soc_update_bits(codec,
480 RT286_CBJ_CTRL1, 0x0400, 0x0000);
481 mdelay(50);
482 break;
483 default:
484 return 0;
485 }
486
487 return 0;
488}
489
490static int rt286_ldo2_event(struct snd_soc_dapm_widget *w,
491 struct snd_kcontrol *kcontrol, int event)
492{
Lars-Peter Clausen76f17f12015-01-15 12:52:10 +0100493 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Bard Liao6879db72014-10-31 14:52:16 +0800494
495 switch (event) {
496 case SND_SOC_DAPM_POST_PMU:
497 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x08);
498 break;
499 case SND_SOC_DAPM_PRE_PMD:
500 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x30);
501 break;
502 default:
503 return 0;
504 }
505
506 return 0;
507}
508
509static int rt286_mic1_event(struct snd_soc_dapm_widget *w,
510 struct snd_kcontrol *kcontrol, int event)
511{
Lars-Peter Clausen76f17f12015-01-15 12:52:10 +0100512 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Bard Liao6879db72014-10-31 14:52:16 +0800513
514 switch (event) {
515 case SND_SOC_DAPM_PRE_PMU:
516 snd_soc_update_bits(codec,
517 RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
518 snd_soc_update_bits(codec,
519 RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
520 break;
521 case SND_SOC_DAPM_POST_PMD:
522 snd_soc_update_bits(codec,
523 RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
524 snd_soc_update_bits(codec,
525 RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
526 break;
527 default:
528 return 0;
529 }
530
531 return 0;
532}
533
Bard Liao07cf7cba2014-06-20 14:41:13 +0800534static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
Bard Liao6879db72014-10-31 14:52:16 +0800535 SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1,
536 12, 1, NULL, 0),
537 SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1,
538 0, 1, rt286_vref_event, SND_SOC_DAPM_PRE_PMU),
539 SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2,
540 2, 0, NULL, 0),
541 SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1,
542 13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD |
543 SND_SOC_DAPM_POST_PMU),
544 SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
545 5, 0, NULL, 0),
546 SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
547 0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU |
548 SND_SOC_DAPM_POST_PMD),
549
Bard Liao07cf7cba2014-06-20 14:41:13 +0800550 /* Input Lines */
551 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
552 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
553 SND_SOC_DAPM_INPUT("MIC1"),
554 SND_SOC_DAPM_INPUT("LINE1"),
555 SND_SOC_DAPM_INPUT("Beep"),
556
557 /* DMIC */
558 SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
559 NULL, 0, rt286_set_dmic1_event,
560 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
561 SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
562 NULL, 0),
563 SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
564 0, 0, NULL, 0),
565
566 /* REC Mixer */
567 SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
568 rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
569
570 /* ADCs */
571 SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
572 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
573
574 /* ADC Mux */
Bard Liao54d96a42015-01-23 14:51:09 +0800575 SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
576 &rt286_adc0_mux),
577 SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
578 &rt286_adc1_mux),
Bard Liao07cf7cba2014-06-20 14:41:13 +0800579
580 /* Audio Interface */
581 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
582 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
583 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
584 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
585
586 /* Output Side */
587 /* DACs */
588 SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
589 SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
590
591 /* Output Mux */
592 SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
593 SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
594
595 SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
596 RT286_SET_PIN_SFT, 0, NULL, 0),
597
598 /* Output Mixer */
599 SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
600 rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
601 SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
602 NULL, 0),
603
604 /* Output Pga */
605 SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
606 &spo_enable_control, rt286_spk_event,
607 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
608 SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
609 &hpol_enable_control),
610 SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
611 &hpor_enable_control),
612
613 /* Output Lines */
614 SND_SOC_DAPM_OUTPUT("SPOL"),
615 SND_SOC_DAPM_OUTPUT("SPOR"),
616 SND_SOC_DAPM_OUTPUT("HPO Pin"),
617 SND_SOC_DAPM_OUTPUT("SPDIF"),
618};
619
620static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
Bard Liao6879db72014-10-31 14:52:16 +0800621 {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
622 {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
623 {"Front", NULL, "MCLK MODE", is_mclk_mode},
624 {"Surround", NULL, "MCLK MODE", is_mclk_mode},
625
626 {"HP Power", NULL, "LDO1"},
627 {"HP Power", NULL, "LDO2"},
628
629 {"MIC1", NULL, "LDO1"},
630 {"MIC1", NULL, "LDO2"},
631 {"MIC1", NULL, "HV"},
632 {"MIC1", NULL, "VREF"},
633 {"MIC1", NULL, "MIC1 Input Buffer"},
634
635 {"SPO", NULL, "LDO1"},
636 {"SPO", NULL, "LDO2"},
637 {"SPO", NULL, "HV"},
638 {"SPO", NULL, "VREF"},
639
Bard Liao07cf7cba2014-06-20 14:41:13 +0800640 {"DMIC1", NULL, "DMIC1 Pin"},
641 {"DMIC2", NULL, "DMIC2 Pin"},
642 {"DMIC1", NULL, "DMIC Receiver"},
643 {"DMIC2", NULL, "DMIC Receiver"},
644
645 {"RECMIX", "Beep Switch", "Beep"},
646 {"RECMIX", "Line1 Switch", "LINE1"},
647 {"RECMIX", "Mic1 Switch", "MIC1"},
648
649 {"ADC 0 Mux", "Dmic", "DMIC1"},
650 {"ADC 0 Mux", "RECMIX", "RECMIX"},
651 {"ADC 0 Mux", "Mic", "MIC1"},
652 {"ADC 1 Mux", "Dmic", "DMIC2"},
653 {"ADC 1 Mux", "RECMIX", "RECMIX"},
654 {"ADC 1 Mux", "Mic", "MIC1"},
655
656 {"ADC 0", NULL, "ADC 0 Mux"},
657 {"ADC 1", NULL, "ADC 1 Mux"},
658
659 {"AIF1TX", NULL, "ADC 0"},
660 {"AIF2TX", NULL, "ADC 1"},
661
662 {"DAC 0", NULL, "AIF1RX"},
663 {"DAC 1", NULL, "AIF2RX"},
664
665 {"Front", "DAC Switch", "DAC 0"},
666 {"Front", "RECMIX Switch", "RECMIX"},
667
668 {"Surround", NULL, "DAC 1"},
669
670 {"SPK Mux", "Front", "Front"},
671 {"SPK Mux", "Surround", "Surround"},
672
673 {"HPO Mux", "Front", "Front"},
674 {"HPO Mux", "Surround", "Surround"},
675
676 {"SPO", "Switch", "SPK Mux"},
677 {"HPO L", "Switch", "HPO Mux"},
678 {"HPO R", "Switch", "HPO Mux"},
679 {"HPO L", NULL, "HP Power"},
680 {"HPO R", NULL, "HP Power"},
681
682 {"SPOL", NULL, "SPO"},
683 {"SPOR", NULL, "SPO"},
684 {"HPO Pin", NULL, "HPO L"},
685 {"HPO Pin", NULL, "HPO R"},
686};
687
688static int rt286_hw_params(struct snd_pcm_substream *substream,
689 struct snd_pcm_hw_params *params,
690 struct snd_soc_dai *dai)
691{
692 struct snd_soc_codec *codec = dai->codec;
693 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
694 unsigned int val = 0;
695 int d_len_code;
696
697 switch (params_rate(params)) {
698 /* bit 14 0:48K 1:44.1K */
699 case 44100:
700 val |= 0x4000;
701 break;
702 case 48000:
703 break;
704 default:
705 dev_err(codec->dev, "Unsupported sample rate %d\n",
706 params_rate(params));
707 return -EINVAL;
708 }
709 switch (rt286->sys_clk) {
710 case 12288000:
711 case 24576000:
712 if (params_rate(params) != 48000) {
713 dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
714 params_rate(params), rt286->sys_clk);
715 return -EINVAL;
716 }
717 break;
718 case 11289600:
719 case 22579200:
720 if (params_rate(params) != 44100) {
721 dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
722 params_rate(params), rt286->sys_clk);
723 return -EINVAL;
724 }
725 break;
726 }
727
728 if (params_channels(params) <= 16) {
729 /* bit 3:0 Number of Channel */
730 val |= (params_channels(params) - 1);
731 } else {
732 dev_err(codec->dev, "Unsupported channels %d\n",
733 params_channels(params));
734 return -EINVAL;
735 }
736
737 d_len_code = 0;
738 switch (params_width(params)) {
739 /* bit 6:4 Bits per Sample */
740 case 16:
741 d_len_code = 0;
742 val |= (0x1 << 4);
743 break;
744 case 32:
745 d_len_code = 2;
746 val |= (0x4 << 4);
747 break;
748 case 20:
749 d_len_code = 1;
750 val |= (0x2 << 4);
751 break;
752 case 24:
753 d_len_code = 2;
754 val |= (0x3 << 4);
755 break;
756 case 8:
757 d_len_code = 3;
758 break;
759 default:
760 return -EINVAL;
761 }
762
763 snd_soc_update_bits(codec,
764 RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
765 dev_dbg(codec->dev, "format val = 0x%x\n", val);
766
Bard Liao45437fa2015-01-15 10:49:25 +0800767 snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val);
768 snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800769
770 return 0;
771}
772
773static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
774{
775 struct snd_soc_codec *codec = dai->codec;
776
777 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
778 case SND_SOC_DAIFMT_CBM_CFM:
779 snd_soc_update_bits(codec,
780 RT286_I2S_CTRL1, 0x800, 0x800);
781 break;
782 case SND_SOC_DAIFMT_CBS_CFS:
783 snd_soc_update_bits(codec,
784 RT286_I2S_CTRL1, 0x800, 0x0);
785 break;
786 default:
787 return -EINVAL;
788 }
789
790 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
791 case SND_SOC_DAIFMT_I2S:
792 snd_soc_update_bits(codec,
793 RT286_I2S_CTRL1, 0x300, 0x0);
794 break;
795 case SND_SOC_DAIFMT_LEFT_J:
796 snd_soc_update_bits(codec,
797 RT286_I2S_CTRL1, 0x300, 0x1 << 8);
798 break;
799 case SND_SOC_DAIFMT_DSP_A:
800 snd_soc_update_bits(codec,
801 RT286_I2S_CTRL1, 0x300, 0x2 << 8);
802 break;
803 case SND_SOC_DAIFMT_DSP_B:
804 snd_soc_update_bits(codec,
805 RT286_I2S_CTRL1, 0x300, 0x3 << 8);
806 break;
807 default:
808 return -EINVAL;
809 }
810 /* bit 15 Stream Type 0:PCM 1:Non-PCM */
811 snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0);
812 snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0);
813
814 return 0;
815}
816
817static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
818 int clk_id, unsigned int freq, int dir)
819{
820 struct snd_soc_codec *codec = dai->codec;
821 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
822
823 dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq);
824
825 if (RT286_SCLK_S_MCLK == clk_id) {
826 snd_soc_update_bits(codec,
827 RT286_I2S_CTRL2, 0x0100, 0x0);
828 snd_soc_update_bits(codec,
829 RT286_PLL_CTRL1, 0x20, 0x20);
830 } else {
831 snd_soc_update_bits(codec,
832 RT286_I2S_CTRL2, 0x0100, 0x0100);
833 snd_soc_update_bits(codec,
834 RT286_PLL_CTRL, 0x4, 0x4);
835 snd_soc_update_bits(codec,
836 RT286_PLL_CTRL1, 0x20, 0x0);
837 }
838
839 switch (freq) {
840 case 19200000:
841 if (RT286_SCLK_S_MCLK == clk_id) {
842 dev_err(codec->dev, "Should not use MCLK\n");
843 return -EINVAL;
844 }
845 snd_soc_update_bits(codec,
846 RT286_I2S_CTRL2, 0x40, 0x40);
847 break;
848 case 24000000:
849 if (RT286_SCLK_S_MCLK == clk_id) {
850 dev_err(codec->dev, "Should not use MCLK\n");
851 return -EINVAL;
852 }
853 snd_soc_update_bits(codec,
854 RT286_I2S_CTRL2, 0x40, 0x0);
855 break;
856 case 12288000:
857 case 11289600:
858 snd_soc_update_bits(codec,
859 RT286_I2S_CTRL2, 0x8, 0x0);
860 snd_soc_update_bits(codec,
861 RT286_CLK_DIV, 0xfc1e, 0x0004);
862 break;
863 case 24576000:
864 case 22579200:
865 snd_soc_update_bits(codec,
866 RT286_I2S_CTRL2, 0x8, 0x8);
867 snd_soc_update_bits(codec,
868 RT286_CLK_DIV, 0xfc1e, 0x5406);
869 break;
870 default:
871 dev_err(codec->dev, "Unsupported system clock\n");
872 return -EINVAL;
873 }
874
875 rt286->sys_clk = freq;
Bard Liao6879db72014-10-31 14:52:16 +0800876 rt286->clk_id = clk_id;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800877
878 return 0;
879}
880
881static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
882{
883 struct snd_soc_codec *codec = dai->codec;
884
885 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
886 if (50 == ratio)
887 snd_soc_update_bits(codec,
888 RT286_I2S_CTRL1, 0x1000, 0x1000);
889 else
890 snd_soc_update_bits(codec,
891 RT286_I2S_CTRL1, 0x1000, 0x0);
892
893
894 return 0;
895}
896
897static int rt286_set_bias_level(struct snd_soc_codec *codec,
898 enum snd_soc_bias_level level)
899{
900 switch (level) {
901 case SND_SOC_BIAS_PREPARE:
Bard Liaobc6c4e42014-07-07 19:15:30 +0800902 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
Bard Liao07cf7cba2014-06-20 14:41:13 +0800903 snd_soc_write(codec,
904 RT286_SET_AUDIO_POWER, AC_PWRST_D0);
Bard Liaobc6c4e42014-07-07 19:15:30 +0800905 snd_soc_update_bits(codec,
906 RT286_DC_GAIN, 0x200, 0x200);
907 }
908 break;
909
910 case SND_SOC_BIAS_ON:
911 mdelay(10);
Bard Liao6879db72014-10-31 14:52:16 +0800912 snd_soc_update_bits(codec,
913 RT286_CBJ_CTRL1, 0x0400, 0x0400);
914 snd_soc_update_bits(codec,
915 RT286_DC_GAIN, 0x200, 0x0);
916
Bard Liao07cf7cba2014-06-20 14:41:13 +0800917 break;
918
919 case SND_SOC_BIAS_STANDBY:
920 snd_soc_write(codec,
921 RT286_SET_AUDIO_POWER, AC_PWRST_D3);
Bard Liaobc6c4e42014-07-07 19:15:30 +0800922 snd_soc_update_bits(codec,
Bard Liao6879db72014-10-31 14:52:16 +0800923 RT286_CBJ_CTRL1, 0x0400, 0x0000);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800924 break;
925
926 default:
927 break;
928 }
929 codec->dapm.bias_level = level;
930
931 return 0;
932}
933
934static irqreturn_t rt286_irq(int irq, void *data)
935{
936 struct rt286_priv *rt286 = data;
937 bool hp = false;
938 bool mic = false;
939 int status = 0;
940
Bard Liao90f601e2014-07-29 13:50:57 +0800941 rt286_jack_detect(rt286, &hp, &mic);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800942
943 /* Clear IRQ */
Bard Liao90f601e2014-07-29 13:50:57 +0800944 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800945
946 if (hp == true)
947 status |= SND_JACK_HEADPHONE;
948
949 if (mic == true)
950 status |= SND_JACK_MICROPHONE;
951
952 snd_soc_jack_report(rt286->jack, status,
953 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
954
955 pm_wakeup_event(&rt286->i2c->dev, 300);
956
957 return IRQ_HANDLED;
958}
959
960static int rt286_probe(struct snd_soc_codec *codec)
961{
962 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800963
Bard Liao6879db72014-10-31 14:52:16 +0800964 rt286->codec = codec;
Bard Liao90f601e2014-07-29 13:50:57 +0800965
966 if (rt286->i2c->irq) {
967 regmap_update_bits(rt286->regmap,
968 RT286_IRQ_CTRL, 0x2, 0x2);
969
970 INIT_DELAYED_WORK(&rt286->jack_detect_work,
971 rt286_jack_detect_work);
972 schedule_delayed_work(&rt286->jack_detect_work,
973 msecs_to_jiffies(1250));
974 }
Bard Liao07cf7cba2014-06-20 14:41:13 +0800975
Bard Liao07cf7cba2014-06-20 14:41:13 +0800976 return 0;
977}
978
979static int rt286_remove(struct snd_soc_codec *codec)
980{
981 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
982
983 cancel_delayed_work_sync(&rt286->jack_detect_work);
984
985 return 0;
986}
987
988#ifdef CONFIG_PM
989static int rt286_suspend(struct snd_soc_codec *codec)
990{
991 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
992
993 regcache_cache_only(rt286->regmap, true);
994 regcache_mark_dirty(rt286->regmap);
995
996 return 0;
997}
998
999static int rt286_resume(struct snd_soc_codec *codec)
1000{
1001 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1002
1003 regcache_cache_only(rt286->regmap, false);
1004 rt286_index_sync(codec);
1005 regcache_sync(rt286->regmap);
1006
1007 return 0;
1008}
1009#else
1010#define rt286_suspend NULL
1011#define rt286_resume NULL
1012#endif
1013
1014#define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1015#define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1016 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1017
1018static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
1019 .hw_params = rt286_hw_params,
1020 .set_fmt = rt286_set_dai_fmt,
1021 .set_sysclk = rt286_set_dai_sysclk,
1022 .set_bclk_ratio = rt286_set_bclk_ratio,
1023};
1024
1025static struct snd_soc_dai_driver rt286_dai[] = {
1026 {
1027 .name = "rt286-aif1",
1028 .id = RT286_AIF1,
1029 .playback = {
1030 .stream_name = "AIF1 Playback",
1031 .channels_min = 1,
1032 .channels_max = 2,
1033 .rates = RT286_STEREO_RATES,
1034 .formats = RT286_FORMATS,
1035 },
1036 .capture = {
1037 .stream_name = "AIF1 Capture",
1038 .channels_min = 1,
1039 .channels_max = 2,
1040 .rates = RT286_STEREO_RATES,
1041 .formats = RT286_FORMATS,
1042 },
1043 .ops = &rt286_aif_dai_ops,
1044 .symmetric_rates = 1,
1045 },
1046 {
1047 .name = "rt286-aif2",
1048 .id = RT286_AIF2,
1049 .playback = {
1050 .stream_name = "AIF2 Playback",
1051 .channels_min = 1,
1052 .channels_max = 2,
1053 .rates = RT286_STEREO_RATES,
1054 .formats = RT286_FORMATS,
1055 },
1056 .capture = {
1057 .stream_name = "AIF2 Capture",
1058 .channels_min = 1,
1059 .channels_max = 2,
1060 .rates = RT286_STEREO_RATES,
1061 .formats = RT286_FORMATS,
1062 },
1063 .ops = &rt286_aif_dai_ops,
1064 .symmetric_rates = 1,
1065 },
1066
1067};
1068
1069static struct snd_soc_codec_driver soc_codec_dev_rt286 = {
1070 .probe = rt286_probe,
1071 .remove = rt286_remove,
1072 .suspend = rt286_suspend,
1073 .resume = rt286_resume,
1074 .set_bias_level = rt286_set_bias_level,
1075 .idle_bias_off = true,
1076 .controls = rt286_snd_controls,
1077 .num_controls = ARRAY_SIZE(rt286_snd_controls),
1078 .dapm_widgets = rt286_dapm_widgets,
1079 .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets),
1080 .dapm_routes = rt286_dapm_routes,
1081 .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes),
1082};
1083
1084static const struct regmap_config rt286_regmap = {
1085 .reg_bits = 32,
1086 .val_bits = 32,
1087 .max_register = 0x02370100,
1088 .volatile_reg = rt286_volatile_register,
1089 .readable_reg = rt286_readable_register,
Oder Chioubc08f962015-06-12 17:06:29 +08001090 .reg_write = rl6347a_hw_write,
1091 .reg_read = rl6347a_hw_read,
Bard Liao07cf7cba2014-06-20 14:41:13 +08001092 .cache_type = REGCACHE_RBTREE,
1093 .reg_defaults = rt286_reg,
1094 .num_reg_defaults = ARRAY_SIZE(rt286_reg),
1095};
1096
1097static const struct i2c_device_id rt286_i2c_id[] = {
1098 {"rt286", 0},
Bard Liao3ab888d2015-02-09 14:19:45 +08001099 {"rt288", 0},
Bard Liao07cf7cba2014-06-20 14:41:13 +08001100 {}
1101};
1102MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
1103
1104static const struct acpi_device_id rt286_acpi_match[] = {
1105 { "INT343A", 0 },
1106 {},
1107};
1108MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
1109
Sudip Mukherjeea5a267c2014-11-18 17:42:54 +05301110static struct dmi_system_id force_combo_jack_table[] = {
Bard Liao6c67cde22014-11-06 09:59:59 +08001111 {
1112 .ident = "Intel Wilson Beach",
1113 .matches = {
1114 DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
1115 }
1116 },
1117 { }
1118};
1119
Bard Liao2cc3f232015-02-05 16:40:34 +08001120static struct dmi_system_id dmi_dell_dino[] = {
1121 {
1122 .ident = "Dell Dino",
1123 .matches = {
1124 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
Bard Liaoa4ee5562015-03-06 10:12:58 +08001125 DMI_MATCH(DMI_PRODUCT_NAME, "XPS 13 9343")
Bard Liao2cc3f232015-02-05 16:40:34 +08001126 }
1127 },
1128 { }
1129};
1130
Bard Liao07cf7cba2014-06-20 14:41:13 +08001131static int rt286_i2c_probe(struct i2c_client *i2c,
1132 const struct i2c_device_id *id)
1133{
1134 struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
1135 struct rt286_priv *rt286;
Bard Liao143526e2015-03-24 09:51:12 +08001136 int i, ret, val;
Bard Liao07cf7cba2014-06-20 14:41:13 +08001137
1138 rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
1139 GFP_KERNEL);
1140 if (NULL == rt286)
1141 return -ENOMEM;
1142
1143 rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
1144 if (IS_ERR(rt286->regmap)) {
1145 ret = PTR_ERR(rt286->regmap);
1146 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1147 ret);
1148 return ret;
1149 }
1150
Bard Liao143526e2015-03-24 09:51:12 +08001151 ret = regmap_read(rt286->regmap,
1152 RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &val);
1153 if (ret != 0) {
1154 dev_err(&i2c->dev, "I2C error %d\n", ret);
1155 return ret;
1156 }
1157 if (val != RT286_VENDOR_ID && val != RT288_VENDOR_ID) {
Bard Liao4b217682014-07-07 16:48:37 +08001158 dev_err(&i2c->dev,
Bard Liao143526e2015-03-24 09:51:12 +08001159 "Device with ID register %x is not rt286\n", val);
Bard Liao4b217682014-07-07 16:48:37 +08001160 return -ENODEV;
1161 }
1162
Bard Liao07cf7cba2014-06-20 14:41:13 +08001163 rt286->index_cache = rt286_index_def;
Oder Chioubc08f962015-06-12 17:06:29 +08001164 rt286->index_cache_size = INDEX_CACHE_SIZE;
Bard Liao07cf7cba2014-06-20 14:41:13 +08001165 rt286->i2c = i2c;
1166 i2c_set_clientdata(i2c, rt286);
1167
Bard Liaod53d59e2015-04-09 11:20:32 +08001168 /* restore codec default */
1169 for (i = 0; i < INDEX_CACHE_SIZE; i++)
1170 regmap_write(rt286->regmap, rt286->index_cache[i].reg,
1171 rt286->index_cache[i].def);
1172 for (i = 0; i < ARRAY_SIZE(rt286_reg); i++)
1173 regmap_write(rt286->regmap, rt286_reg[i].reg,
1174 rt286_reg[i].def);
1175
Bard Liao07cf7cba2014-06-20 14:41:13 +08001176 if (pdata)
1177 rt286->pdata = *pdata;
1178
Bard Liao2cc3f232015-02-05 16:40:34 +08001179 if (dmi_check_system(force_combo_jack_table) ||
1180 dmi_check_system(dmi_dell_dino))
Bard Liao6c67cde22014-11-06 09:59:59 +08001181 rt286->pdata.cbj_en = true;
1182
Bard Liao61a414c2014-07-07 16:48:38 +08001183 regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
1184
1185 for (i = 0; i < RT286_POWER_REG_LEN; i++)
1186 regmap_write(rt286->regmap,
1187 RT286_SET_POWER(rt286_support_power_controls[i]),
1188 AC_PWRST_D1);
1189
1190 if (!rt286->pdata.cbj_en) {
1191 regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
1192 regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
Bard Liao61a414c2014-07-07 16:48:38 +08001193 regmap_update_bits(rt286->regmap,
1194 RT286_CBJ_CTRL1, 0xf000, 0xb000);
1195 } else {
1196 regmap_update_bits(rt286->regmap,
1197 RT286_CBJ_CTRL1, 0xf000, 0x5000);
1198 }
1199
1200 mdelay(10);
1201
1202 if (!rt286->pdata.gpio2_en)
1203 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000);
1204 else
1205 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
1206
1207 mdelay(10);
1208
Bard Liao6879db72014-10-31 14:52:16 +08001209 regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
Bard Liaof8c101b2014-11-06 10:00:00 +08001210 /* Power down LDO, VREF */
Bard Liao6879db72014-10-31 14:52:16 +08001211 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0);
1212 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001);
Bard Liao61a414c2014-07-07 16:48:38 +08001213
Bard Liaof8c101b2014-11-06 10:00:00 +08001214 /* Set depop parameter */
Bard Liaobc6c4e42014-07-07 19:15:30 +08001215 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
1216 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
1217 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
1218
Bard Liao2cc3f232015-02-05 16:40:34 +08001219 if (dmi_check_system(dmi_dell_dino)) {
1220 regmap_update_bits(rt286->regmap,
1221 RT286_SET_GPIO_MASK, 0x40, 0x40);
1222 regmap_update_bits(rt286->regmap,
1223 RT286_SET_GPIO_DIRECTION, 0x40, 0x40);
1224 regmap_update_bits(rt286->regmap,
1225 RT286_SET_GPIO_DATA, 0x40, 0x40);
1226 regmap_update_bits(rt286->regmap,
1227 RT286_GPIO_CTRL, 0xc, 0x8);
1228 }
1229
Bard Liao61a414c2014-07-07 16:48:38 +08001230 if (rt286->i2c->irq) {
Bard Liao61a414c2014-07-07 16:48:38 +08001231 ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
1232 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
1233 if (ret != 0) {
1234 dev_err(&i2c->dev,
1235 "Failed to reguest IRQ: %d\n", ret);
1236 return ret;
1237 }
1238 }
1239
Bard Liao07cf7cba2014-06-20 14:41:13 +08001240 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286,
1241 rt286_dai, ARRAY_SIZE(rt286_dai));
1242
1243 return ret;
1244}
1245
1246static int rt286_i2c_remove(struct i2c_client *i2c)
1247{
1248 struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
1249
1250 if (i2c->irq)
1251 free_irq(i2c->irq, rt286);
1252 snd_soc_unregister_codec(&i2c->dev);
1253
1254 return 0;
1255}
1256
1257
Bard Liao23c4fd52014-07-14 10:18:04 +08001258static struct i2c_driver rt286_i2c_driver = {
Bard Liao07cf7cba2014-06-20 14:41:13 +08001259 .driver = {
1260 .name = "rt286",
1261 .owner = THIS_MODULE,
1262 .acpi_match_table = ACPI_PTR(rt286_acpi_match),
1263 },
1264 .probe = rt286_i2c_probe,
1265 .remove = rt286_i2c_remove,
1266 .id_table = rt286_i2c_id,
1267};
1268
1269module_i2c_driver(rt286_i2c_driver);
1270
1271MODULE_DESCRIPTION("ASoC RT286 driver");
1272MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1273MODULE_LICENSE("GPL");