blob: 90cf7e775f153d63cb9429b2bf7bbc0420c4f884 [file] [log] [blame]
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001/*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
Charulatha V1a5d8192011-02-02 17:52:14 +05306 * Juha Yrj�l� <juha.yrjola@nokia.com>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070017 */
18
19#include <linux/kernel.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070020#include <linux/interrupt.h>
21#include <linux/module.h>
22#include <linux/device.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
Russell King53741ed2012-04-23 13:51:48 +010025#include <linux/dmaengine.h>
26#include <linux/omap-dma.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070027#include <linux/platform_device.h>
28#include <linux/err.h>
29#include <linux/clk.h>
30#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Govindraj.R1f1a4382011-02-02 17:52:15 +053032#include <linux/pm_runtime.h>
Benoit Coussond5a80032012-02-15 18:37:34 +010033#include <linux/of.h>
34#include <linux/of_device.h>
Illia Smyrnovd33f4732013-06-17 16:31:06 +030035#include <linux/gcd.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070036
37#include <linux/spi/spi.h>
Michael Wellingbc7f9bb2015-05-08 13:31:01 -050038#include <linux/gpio.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070039
Arnd Bergmann22037472012-08-24 15:21:06 +020040#include <linux/platform_data/spi-omap2-mcspi.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070041
42#define OMAP2_MCSPI_MAX_FREQ 48000000
Stefan Sørensenfaee9b02014-02-02 16:24:25 +010043#define OMAP2_MCSPI_MAX_DIVIDER 4096
Illia Smyrnovd33f4732013-06-17 16:31:06 +030044#define OMAP2_MCSPI_MAX_FIFODEPTH 64
45#define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
Shubhrajyoti D27b52842012-03-26 17:04:22 +053046#define SPI_AUTOSUSPEND_TIMEOUT 2000
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070047
48#define OMAP2_MCSPI_REVISION 0x00
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070049#define OMAP2_MCSPI_SYSSTATUS 0x14
50#define OMAP2_MCSPI_IRQSTATUS 0x18
51#define OMAP2_MCSPI_IRQENABLE 0x1c
52#define OMAP2_MCSPI_WAKEUPENABLE 0x20
53#define OMAP2_MCSPI_SYST 0x24
54#define OMAP2_MCSPI_MODULCTRL 0x28
Illia Smyrnovd33f4732013-06-17 16:31:06 +030055#define OMAP2_MCSPI_XFERLEVEL 0x7c
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070056
57/* per-channel banks, 0x14 bytes each, first is: */
58#define OMAP2_MCSPI_CHCONF0 0x2c
59#define OMAP2_MCSPI_CHSTAT0 0x30
60#define OMAP2_MCSPI_CHCTRL0 0x34
61#define OMAP2_MCSPI_TX0 0x38
62#define OMAP2_MCSPI_RX0 0x3c
63
64/* per-register bitmasks: */
Illia Smyrnovd33f4732013-06-17 16:31:06 +030065#define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070066
Jouni Hogander7a8fa722009-09-22 16:45:58 -070067#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
68#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
69#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070070
Jouni Hogander7a8fa722009-09-22 16:45:58 -070071#define OMAP2_MCSPI_CHCONF_PHA BIT(0)
72#define OMAP2_MCSPI_CHCONF_POL BIT(1)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070073#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
Jouni Hogander7a8fa722009-09-22 16:45:58 -070074#define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070075#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
Jouni Hogander7a8fa722009-09-22 16:45:58 -070076#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
77#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070078#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
Jouni Hogander7a8fa722009-09-22 16:45:58 -070079#define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
80#define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
81#define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
82#define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
83#define OMAP2_MCSPI_CHCONF_IS BIT(18)
84#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
85#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
Illia Smyrnovd33f4732013-06-17 16:31:06 +030086#define OMAP2_MCSPI_CHCONF_FFET BIT(27)
87#define OMAP2_MCSPI_CHCONF_FFER BIT(28)
Stefan Sørensenfaee9b02014-02-02 16:24:25 +010088#define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070089
Jouni Hogander7a8fa722009-09-22 16:45:58 -070090#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
91#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
92#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
Illia Smyrnovd33f4732013-06-17 16:31:06 +030093#define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070094
Jouni Hogander7a8fa722009-09-22 16:45:58 -070095#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
Stefan Sørensenfaee9b02014-02-02 16:24:25 +010096#define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070097
Jouni Hogander7a8fa722009-09-22 16:45:58 -070098#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070099
100/* We have 2 DMA channels per CS, one for RX and one for TX */
101struct omap2_mcspi_dma {
Russell King53741ed2012-04-23 13:51:48 +0100102 struct dma_chan *dma_tx;
103 struct dma_chan *dma_rx;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700104
105 int dma_tx_sync_dev;
106 int dma_rx_sync_dev;
107
108 struct completion dma_tx_completion;
109 struct completion dma_rx_completion;
Matt Porter74f3aaa2013-06-22 23:07:38 +0530110
111 char dma_rx_ch_name[14];
112 char dma_tx_ch_name[14];
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700113};
114
115/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
116 * cache operations; better heuristics consider wordsize and bitrate.
117 */
Roman Tereshonkov8b66c132010-04-12 09:07:54 +0000118#define DMA_MIN_BYTES 160
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700119
120
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530121/*
122 * Used for context save and restore, structure members to be updated whenever
123 * corresponding registers are modified.
124 */
125struct omap2_mcspi_regs {
126 u32 modulctrl;
127 u32 wakeupenable;
128 struct list_head cs;
129};
130
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700131struct omap2_mcspi {
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700132 struct spi_master *master;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700133 /* Virtual base address of the controller */
134 void __iomem *base;
Russell Kinge5480b732008-09-01 21:51:50 +0100135 unsigned long phys;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700136 /* SPI1 has 4 channels, while SPI2 has 2 */
137 struct omap2_mcspi_dma *dma_channels;
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530138 struct device *dev;
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530139 struct omap2_mcspi_regs ctx;
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300140 int fifo_depth;
Daniel Mack0384e902012-10-07 18:19:44 +0200141 unsigned int pin_dir:1;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700142};
143
144struct omap2_mcspi_cs {
145 void __iomem *base;
Russell Kinge5480b732008-09-01 21:51:50 +0100146 unsigned long phys;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700147 int word_len;
Mark A. Greer97ca0d62014-07-01 20:28:32 -0700148 u16 mode;
Tero Kristo89c05372009-09-22 16:46:17 -0700149 struct list_head node;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700150 /* Context save and restore shadow register */
Stefan Sørensenfaee9b02014-02-02 16:24:25 +0100151 u32 chconf0, chctrl0;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700152};
153
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700154static inline void mcspi_write_reg(struct spi_master *master,
155 int idx, u32 val)
156{
157 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
158
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200159 writel_relaxed(val, mcspi->base + idx);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700160}
161
162static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
163{
164 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
165
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200166 return readl_relaxed(mcspi->base + idx);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700167}
168
169static inline void mcspi_write_cs_reg(const struct spi_device *spi,
170 int idx, u32 val)
171{
172 struct omap2_mcspi_cs *cs = spi->controller_state;
173
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200174 writel_relaxed(val, cs->base + idx);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700175}
176
177static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
178{
179 struct omap2_mcspi_cs *cs = spi->controller_state;
180
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200181 return readl_relaxed(cs->base + idx);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700182}
183
Hemanth Va41ae1a2009-09-22 16:46:16 -0700184static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
185{
186 struct omap2_mcspi_cs *cs = spi->controller_state;
187
188 return cs->chconf0;
189}
190
191static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
192{
193 struct omap2_mcspi_cs *cs = spi->controller_state;
194
195 cs->chconf0 = val;
196 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
Roman Tereshonkova330ce22010-03-15 09:06:28 +0000197 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700198}
199
Illia Smyrnov56cd5c12013-06-14 19:12:07 +0300200static inline int mcspi_bytes_per_word(int word_len)
201{
202 if (word_len <= 8)
203 return 1;
204 else if (word_len <= 16)
205 return 2;
206 else /* word_len <= 32 */
207 return 4;
208}
209
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700210static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
211 int is_read, int enable)
212{
213 u32 l, rw;
214
Hemanth Va41ae1a2009-09-22 16:46:16 -0700215 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700216
217 if (is_read) /* 1 is read, 0 write */
218 rw = OMAP2_MCSPI_CHCONF_DMAR;
219 else
220 rw = OMAP2_MCSPI_CHCONF_DMAW;
221
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +0530222 if (enable)
223 l |= rw;
224 else
225 l &= ~rw;
226
Hemanth Va41ae1a2009-09-22 16:46:16 -0700227 mcspi_write_chconf0(spi, l);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700228}
229
230static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
231{
Stefan Sørensenfaee9b02014-02-02 16:24:25 +0100232 struct omap2_mcspi_cs *cs = spi->controller_state;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700233 u32 l;
234
Stefan Sørensenfaee9b02014-02-02 16:24:25 +0100235 l = cs->chctrl0;
236 if (enable)
237 l |= OMAP2_MCSPI_CHCTRL_EN;
238 else
239 l &= ~OMAP2_MCSPI_CHCTRL_EN;
240 cs->chctrl0 = l;
241 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000242 /* Flash post-writes */
243 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700244}
245
246static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
247{
248 u32 l;
249
Hemanth Va41ae1a2009-09-22 16:46:16 -0700250 l = mcspi_cached_chconf0(spi);
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +0530251 if (cs_active)
252 l |= OMAP2_MCSPI_CHCONF_FORCE;
253 else
254 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
255
Hemanth Va41ae1a2009-09-22 16:46:16 -0700256 mcspi_write_chconf0(spi, l);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700257}
258
259static void omap2_mcspi_set_master_mode(struct spi_master *master)
260{
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530261 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
262 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700263 u32 l;
264
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530265 /*
266 * Setup when switching from (reset default) slave mode
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700267 * to single-channel master mode
268 */
269 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +0530270 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
271 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700272 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700273
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530274 ctx->modulctrl = l;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700275}
276
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300277static void omap2_mcspi_set_fifo(const struct spi_device *spi,
278 struct spi_transfer *t, int enable)
279{
280 struct spi_master *master = spi->master;
281 struct omap2_mcspi_cs *cs = spi->controller_state;
282 struct omap2_mcspi *mcspi;
283 unsigned int wcnt;
Illia Smyrnov5db542e2013-10-09 15:05:08 +0300284 int max_fifo_depth, fifo_depth, bytes_per_word;
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300285 u32 chconf, xferlevel;
286
287 mcspi = spi_master_get_devdata(master);
288
289 chconf = mcspi_cached_chconf0(spi);
290 if (enable) {
291 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
292 if (t->len % bytes_per_word != 0)
293 goto disable_fifo;
294
Illia Smyrnov5db542e2013-10-09 15:05:08 +0300295 if (t->rx_buf != NULL && t->tx_buf != NULL)
296 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
297 else
298 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
299
300 fifo_depth = gcd(t->len, max_fifo_depth);
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300301 if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0)
302 goto disable_fifo;
303
304 wcnt = t->len / bytes_per_word;
305 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
306 goto disable_fifo;
307
308 xferlevel = wcnt << 16;
309 if (t->rx_buf != NULL) {
310 chconf |= OMAP2_MCSPI_CHCONF_FFER;
311 xferlevel |= (fifo_depth - 1) << 8;
Illia Smyrnov5db542e2013-10-09 15:05:08 +0300312 }
313 if (t->tx_buf != NULL) {
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300314 chconf |= OMAP2_MCSPI_CHCONF_FFET;
315 xferlevel |= fifo_depth - 1;
316 }
317
318 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
319 mcspi_write_chconf0(spi, chconf);
320 mcspi->fifo_depth = fifo_depth;
321
322 return;
323 }
324
325disable_fifo:
326 if (t->rx_buf != NULL)
327 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
Jorge A. Ventura3d0763c2014-08-09 16:06:58 -0500328
329 if (t->tx_buf != NULL)
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300330 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
331
332 mcspi_write_chconf0(spi, chconf);
333 mcspi->fifo_depth = 0;
334}
335
Hemanth Va41ae1a2009-09-22 16:46:16 -0700336static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
337{
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530338 struct spi_master *spi_cntrl = mcspi->master;
339 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
340 struct omap2_mcspi_cs *cs;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700341
342 /* McSPI: context restore */
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530343 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
344 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700345
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530346 list_for_each_entry(cs, &ctx->cs, node)
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200347 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700348}
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700349
Ilkka Koskinen2764c502010-10-19 17:07:31 +0300350static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
351{
352 unsigned long timeout;
353
354 timeout = jiffies + msecs_to_jiffies(1000);
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200355 while (!(readl_relaxed(reg) & bit)) {
Sebastian Andrzej Siewiorff23fa32013-03-21 13:22:48 +0100356 if (time_after(jiffies, timeout)) {
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200357 if (!(readl_relaxed(reg) & bit))
Sebastian Andrzej Siewiorff23fa32013-03-21 13:22:48 +0100358 return -ETIMEDOUT;
359 else
360 return 0;
361 }
Ilkka Koskinen2764c502010-10-19 17:07:31 +0300362 cpu_relax();
363 }
364 return 0;
365}
366
Russell King53741ed2012-04-23 13:51:48 +0100367static void omap2_mcspi_rx_callback(void *data)
368{
369 struct spi_device *spi = data;
370 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
371 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
372
Russell King53741ed2012-04-23 13:51:48 +0100373 /* We must disable the DMA RX request */
374 omap2_mcspi_set_dma_req(spi, 1, 0);
Felipe Balbi830379e2012-12-12 10:45:59 +0200375
376 complete(&mcspi_dma->dma_rx_completion);
Russell King53741ed2012-04-23 13:51:48 +0100377}
378
379static void omap2_mcspi_tx_callback(void *data)
380{
381 struct spi_device *spi = data;
382 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
383 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
384
Russell King53741ed2012-04-23 13:51:48 +0100385 /* We must disable the DMA TX request */
386 omap2_mcspi_set_dma_req(spi, 0, 0);
Felipe Balbi830379e2012-12-12 10:45:59 +0200387
388 complete(&mcspi_dma->dma_tx_completion);
Russell King53741ed2012-04-23 13:51:48 +0100389}
390
Shubhrajyoti Dd7b4394e2012-09-11 12:13:20 +0530391static void omap2_mcspi_tx_dma(struct spi_device *spi,
392 struct spi_transfer *xfer,
393 struct dma_slave_config cfg)
394{
395 struct omap2_mcspi *mcspi;
396 struct omap2_mcspi_dma *mcspi_dma;
397 unsigned int count;
Shubhrajyoti Dd7b4394e2012-09-11 12:13:20 +0530398
399 mcspi = spi_master_get_devdata(spi->master);
400 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
401 count = xfer->len;
402
Shubhrajyoti Dd7b4394e2012-09-11 12:13:20 +0530403 if (mcspi_dma->dma_tx) {
404 struct dma_async_tx_descriptor *tx;
405 struct scatterlist sg;
406
407 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
408
409 sg_init_table(&sg, 1);
410 sg_dma_address(&sg) = xfer->tx_dma;
411 sg_dma_len(&sg) = xfer->len;
412
413 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
414 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
415 if (tx) {
416 tx->callback = omap2_mcspi_tx_callback;
417 tx->callback_param = spi;
418 dmaengine_submit(tx);
419 } else {
420 /* FIXME: fall back to PIO? */
421 }
422 }
423 dma_async_issue_pending(mcspi_dma->dma_tx);
424 omap2_mcspi_set_dma_req(spi, 0, 1);
425
Shubhrajyoti Dd7b4394e2012-09-11 12:13:20 +0530426}
427
428static unsigned
429omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
430 struct dma_slave_config cfg,
431 unsigned es)
432{
433 struct omap2_mcspi *mcspi;
434 struct omap2_mcspi_dma *mcspi_dma;
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300435 unsigned int count, dma_count;
Shubhrajyoti Dd7b4394e2012-09-11 12:13:20 +0530436 u32 l;
437 int elements = 0;
438 int word_len, element_count;
439 struct omap2_mcspi_cs *cs = spi->controller_state;
440 mcspi = spi_master_get_devdata(spi->master);
441 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
442 count = xfer->len;
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300443 dma_count = xfer->len;
444
445 if (mcspi->fifo_depth == 0)
446 dma_count -= es;
447
Shubhrajyoti Dd7b4394e2012-09-11 12:13:20 +0530448 word_len = cs->word_len;
449 l = mcspi_cached_chconf0(spi);
450
451 if (word_len <= 8)
452 element_count = count;
453 else if (word_len <= 16)
454 element_count = count >> 1;
455 else /* word_len <= 32 */
456 element_count = count >> 2;
457
458 if (mcspi_dma->dma_rx) {
459 struct dma_async_tx_descriptor *tx;
460 struct scatterlist sg;
Shubhrajyoti Dd7b4394e2012-09-11 12:13:20 +0530461
462 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
463
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300464 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
465 dma_count -= es;
Shubhrajyoti Dd7b4394e2012-09-11 12:13:20 +0530466
467 sg_init_table(&sg, 1);
468 sg_dma_address(&sg) = xfer->rx_dma;
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300469 sg_dma_len(&sg) = dma_count;
Shubhrajyoti Dd7b4394e2012-09-11 12:13:20 +0530470
471 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
472 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
473 DMA_CTRL_ACK);
474 if (tx) {
475 tx->callback = omap2_mcspi_rx_callback;
476 tx->callback_param = spi;
477 dmaengine_submit(tx);
478 } else {
479 /* FIXME: fall back to PIO? */
480 }
481 }
482
483 dma_async_issue_pending(mcspi_dma->dma_rx);
484 omap2_mcspi_set_dma_req(spi, 1, 1);
485
486 wait_for_completion(&mcspi_dma->dma_rx_completion);
487 dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
488 DMA_FROM_DEVICE);
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300489
490 if (mcspi->fifo_depth > 0)
491 return count;
492
Shubhrajyoti Dd7b4394e2012-09-11 12:13:20 +0530493 omap2_mcspi_set_enable(spi, 0);
494
495 elements = element_count - 1;
496
497 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
498 elements--;
499
500 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
501 & OMAP2_MCSPI_CHSTAT_RXS)) {
502 u32 w;
503
504 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
505 if (word_len <= 8)
506 ((u8 *)xfer->rx_buf)[elements++] = w;
507 else if (word_len <= 16)
508 ((u16 *)xfer->rx_buf)[elements++] = w;
509 else /* word_len <= 32 */
510 ((u32 *)xfer->rx_buf)[elements++] = w;
511 } else {
Illia Smyrnov56cd5c12013-06-14 19:12:07 +0300512 int bytes_per_word = mcspi_bytes_per_word(word_len);
Jarkko Nikulaa1829d22013-10-11 13:53:59 +0300513 dev_err(&spi->dev, "DMA RX penultimate word empty\n");
Illia Smyrnov56cd5c12013-06-14 19:12:07 +0300514 count -= (bytes_per_word << 1);
Shubhrajyoti Dd7b4394e2012-09-11 12:13:20 +0530515 omap2_mcspi_set_enable(spi, 1);
516 return count;
517 }
518 }
519 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
520 & OMAP2_MCSPI_CHSTAT_RXS)) {
521 u32 w;
522
523 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
524 if (word_len <= 8)
525 ((u8 *)xfer->rx_buf)[elements] = w;
526 else if (word_len <= 16)
527 ((u16 *)xfer->rx_buf)[elements] = w;
528 else /* word_len <= 32 */
529 ((u32 *)xfer->rx_buf)[elements] = w;
530 } else {
Jarkko Nikulaa1829d22013-10-11 13:53:59 +0300531 dev_err(&spi->dev, "DMA RX last word empty\n");
Illia Smyrnov56cd5c12013-06-14 19:12:07 +0300532 count -= mcspi_bytes_per_word(word_len);
Shubhrajyoti Dd7b4394e2012-09-11 12:13:20 +0530533 }
534 omap2_mcspi_set_enable(spi, 1);
535 return count;
536}
537
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700538static unsigned
539omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
540{
541 struct omap2_mcspi *mcspi;
542 struct omap2_mcspi_cs *cs = spi->controller_state;
543 struct omap2_mcspi_dma *mcspi_dma;
Russell King8c7494a2012-04-23 13:56:25 +0100544 unsigned int count;
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000545 u32 l;
Shubhrajyoti Dd7b4394e2012-09-11 12:13:20 +0530546 u8 *rx;
547 const u8 *tx;
Russell King53741ed2012-04-23 13:51:48 +0100548 struct dma_slave_config cfg;
549 enum dma_slave_buswidth width;
550 unsigned es;
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300551 u32 burst;
Shubhrajyoti De47a6822012-11-06 14:30:19 +0530552 void __iomem *chstat_reg;
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300553 void __iomem *irqstat_reg;
554 int wait_res;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700555
556 mcspi = spi_master_get_devdata(spi->master);
557 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000558 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700559
Ilkka Koskinen2764c502010-10-19 17:07:31 +0300560
Russell King53741ed2012-04-23 13:51:48 +0100561 if (cs->word_len <= 8) {
562 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
563 es = 1;
564 } else if (cs->word_len <= 16) {
565 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
566 es = 2;
567 } else {
568 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
569 es = 4;
570 }
571
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300572 count = xfer->len;
573 burst = 1;
574
575 if (mcspi->fifo_depth > 0) {
576 if (count > mcspi->fifo_depth)
577 burst = mcspi->fifo_depth / es;
578 else
579 burst = count / es;
580 }
581
Russell King53741ed2012-04-23 13:51:48 +0100582 memset(&cfg, 0, sizeof(cfg));
583 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
584 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
585 cfg.src_addr_width = width;
586 cfg.dst_addr_width = width;
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300587 cfg.src_maxburst = burst;
588 cfg.dst_maxburst = burst;
Russell King53741ed2012-04-23 13:51:48 +0100589
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700590 rx = xfer->rx_buf;
591 tx = xfer->tx_buf;
592
Shubhrajyoti Dd7b4394e2012-09-11 12:13:20 +0530593 if (tx != NULL)
594 omap2_mcspi_tx_dma(spi, xfer, cfg);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700595
Shubhrajyoti Dd7b4394e2012-09-11 12:13:20 +0530596 if (rx != NULL)
Shubhrajyoti De47a6822012-11-06 14:30:19 +0530597 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700598
Shubhrajyoti De47a6822012-11-06 14:30:19 +0530599 if (tx != NULL) {
Shubhrajyoti De47a6822012-11-06 14:30:19 +0530600 wait_for_completion(&mcspi_dma->dma_tx_completion);
601 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
602 DMA_TO_DEVICE);
603
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300604 if (mcspi->fifo_depth > 0) {
605 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
606
607 if (mcspi_wait_for_reg_bit(irqstat_reg,
608 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
609 dev_err(&spi->dev, "EOW timed out\n");
610
611 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
612 OMAP2_MCSPI_IRQSTATUS_EOW);
613 }
614
Shubhrajyoti De47a6822012-11-06 14:30:19 +0530615 /* for TX_ONLY mode, be sure all words have shifted out */
616 if (rx == NULL) {
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300617 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
618 if (mcspi->fifo_depth > 0) {
619 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
620 OMAP2_MCSPI_CHSTAT_TXFFE);
621 if (wait_res < 0)
622 dev_err(&spi->dev, "TXFFE timed out\n");
623 } else {
624 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
625 OMAP2_MCSPI_CHSTAT_TXS);
626 if (wait_res < 0)
627 dev_err(&spi->dev, "TXS timed out\n");
628 }
629 if (wait_res >= 0 &&
630 (mcspi_wait_for_reg_bit(chstat_reg,
631 OMAP2_MCSPI_CHSTAT_EOT) < 0))
Shubhrajyoti De47a6822012-11-06 14:30:19 +0530632 dev_err(&spi->dev, "EOT timed out\n");
633 }
634 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700635 return count;
636}
637
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700638static unsigned
639omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
640{
641 struct omap2_mcspi *mcspi;
642 struct omap2_mcspi_cs *cs = spi->controller_state;
643 unsigned int count, c;
644 u32 l;
645 void __iomem *base = cs->base;
646 void __iomem *tx_reg;
647 void __iomem *rx_reg;
648 void __iomem *chstat_reg;
649 int word_len;
650
651 mcspi = spi_master_get_devdata(spi->master);
652 count = xfer->len;
653 c = count;
654 word_len = cs->word_len;
655
Hemanth Va41ae1a2009-09-22 16:46:16 -0700656 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700657
658 /* We store the pre-calculated register addresses on stack to speed
659 * up the transfer loop. */
660 tx_reg = base + OMAP2_MCSPI_TX0;
661 rx_reg = base + OMAP2_MCSPI_RX0;
662 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
663
Michael Jonesadef6582011-02-25 16:55:11 +0100664 if (c < (word_len>>3))
665 return 0;
666
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700667 if (word_len <= 8) {
668 u8 *rx;
669 const u8 *tx;
670
671 rx = xfer->rx_buf;
672 tx = xfer->tx_buf;
673
674 do {
Kalle Valofeed9ba2008-01-24 14:00:40 -0800675 c -= 1;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700676 if (tx != NULL) {
677 if (mcspi_wait_for_reg_bit(chstat_reg,
678 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
679 dev_err(&spi->dev, "TXS timed out\n");
680 goto out;
681 }
Felipe Balbi079a1762010-09-29 17:31:29 +0900682 dev_vdbg(&spi->dev, "write-%d %02x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700683 word_len, *tx);
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200684 writel_relaxed(*tx++, tx_reg);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700685 }
686 if (rx != NULL) {
687 if (mcspi_wait_for_reg_bit(chstat_reg,
688 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
689 dev_err(&spi->dev, "RXS timed out\n");
690 goto out;
691 }
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000692
693 if (c == 1 && tx == NULL &&
694 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
695 omap2_mcspi_set_enable(spi, 0);
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200696 *rx++ = readl_relaxed(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900697 dev_vdbg(&spi->dev, "read-%d %02x\n",
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000698 word_len, *(rx - 1));
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000699 if (mcspi_wait_for_reg_bit(chstat_reg,
700 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
701 dev_err(&spi->dev,
702 "RXS timed out\n");
703 goto out;
704 }
705 c = 0;
706 } else if (c == 0 && tx == NULL) {
707 omap2_mcspi_set_enable(spi, 0);
708 }
709
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200710 *rx++ = readl_relaxed(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900711 dev_vdbg(&spi->dev, "read-%d %02x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700712 word_len, *(rx - 1));
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700713 }
Jarkko Nikula95c5c3a2011-03-21 16:27:30 +0200714 } while (c);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700715 } else if (word_len <= 16) {
716 u16 *rx;
717 const u16 *tx;
718
719 rx = xfer->rx_buf;
720 tx = xfer->tx_buf;
721 do {
Kalle Valofeed9ba2008-01-24 14:00:40 -0800722 c -= 2;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700723 if (tx != NULL) {
724 if (mcspi_wait_for_reg_bit(chstat_reg,
725 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
726 dev_err(&spi->dev, "TXS timed out\n");
727 goto out;
728 }
Felipe Balbi079a1762010-09-29 17:31:29 +0900729 dev_vdbg(&spi->dev, "write-%d %04x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700730 word_len, *tx);
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200731 writel_relaxed(*tx++, tx_reg);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700732 }
733 if (rx != NULL) {
734 if (mcspi_wait_for_reg_bit(chstat_reg,
735 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
736 dev_err(&spi->dev, "RXS timed out\n");
737 goto out;
738 }
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000739
740 if (c == 2 && tx == NULL &&
741 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
742 omap2_mcspi_set_enable(spi, 0);
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200743 *rx++ = readl_relaxed(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900744 dev_vdbg(&spi->dev, "read-%d %04x\n",
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000745 word_len, *(rx - 1));
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000746 if (mcspi_wait_for_reg_bit(chstat_reg,
747 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
748 dev_err(&spi->dev,
749 "RXS timed out\n");
750 goto out;
751 }
752 c = 0;
753 } else if (c == 0 && tx == NULL) {
754 omap2_mcspi_set_enable(spi, 0);
755 }
756
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200757 *rx++ = readl_relaxed(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900758 dev_vdbg(&spi->dev, "read-%d %04x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700759 word_len, *(rx - 1));
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700760 }
Jarkko Nikula95c5c3a2011-03-21 16:27:30 +0200761 } while (c >= 2);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700762 } else if (word_len <= 32) {
763 u32 *rx;
764 const u32 *tx;
765
766 rx = xfer->rx_buf;
767 tx = xfer->tx_buf;
768 do {
Kalle Valofeed9ba2008-01-24 14:00:40 -0800769 c -= 4;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700770 if (tx != NULL) {
771 if (mcspi_wait_for_reg_bit(chstat_reg,
772 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
773 dev_err(&spi->dev, "TXS timed out\n");
774 goto out;
775 }
Felipe Balbi079a1762010-09-29 17:31:29 +0900776 dev_vdbg(&spi->dev, "write-%d %08x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700777 word_len, *tx);
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200778 writel_relaxed(*tx++, tx_reg);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700779 }
780 if (rx != NULL) {
781 if (mcspi_wait_for_reg_bit(chstat_reg,
782 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
783 dev_err(&spi->dev, "RXS timed out\n");
784 goto out;
785 }
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000786
787 if (c == 4 && tx == NULL &&
788 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
789 omap2_mcspi_set_enable(spi, 0);
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200790 *rx++ = readl_relaxed(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900791 dev_vdbg(&spi->dev, "read-%d %08x\n",
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000792 word_len, *(rx - 1));
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000793 if (mcspi_wait_for_reg_bit(chstat_reg,
794 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
795 dev_err(&spi->dev,
796 "RXS timed out\n");
797 goto out;
798 }
799 c = 0;
800 } else if (c == 0 && tx == NULL) {
801 omap2_mcspi_set_enable(spi, 0);
802 }
803
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200804 *rx++ = readl_relaxed(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900805 dev_vdbg(&spi->dev, "read-%d %08x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700806 word_len, *(rx - 1));
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700807 }
Jarkko Nikula95c5c3a2011-03-21 16:27:30 +0200808 } while (c >= 4);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700809 }
810
811 /* for TX_ONLY mode, be sure all words have shifted out */
812 if (xfer->rx_buf == NULL) {
813 if (mcspi_wait_for_reg_bit(chstat_reg,
814 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
815 dev_err(&spi->dev, "TXS timed out\n");
816 } else if (mcspi_wait_for_reg_bit(chstat_reg,
817 OMAP2_MCSPI_CHSTAT_EOT) < 0)
818 dev_err(&spi->dev, "EOT timed out\n");
Jason Wange1993ed2010-10-19 18:03:27 +0800819
820 /* disable chan to purge rx datas received in TX_ONLY transfer,
821 * otherwise these rx datas will affect the direct following
822 * RX_ONLY transfer.
823 */
824 omap2_mcspi_set_enable(spi, 0);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700825 }
826out:
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000827 omap2_mcspi_set_enable(spi, 1);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700828 return count - c;
829}
830
Hannu Heikkinen57d9c102011-02-24 21:31:33 +0200831static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
832{
833 u32 div;
834
835 for (div = 0; div < 15; div++)
836 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
837 return div;
838
839 return 15;
840}
841
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700842/* called only when no transfer is active to this device */
843static int omap2_mcspi_setup_transfer(struct spi_device *spi,
844 struct spi_transfer *t)
845{
846 struct omap2_mcspi_cs *cs = spi->controller_state;
847 struct omap2_mcspi *mcspi;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700848 struct spi_master *spi_cntrl;
Stefan Sørensenfaee9b02014-02-02 16:24:25 +0100849 u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700850 u8 word_len = spi->bits_per_word;
Scott Ellis9bd45172010-03-10 14:23:13 -0700851 u32 speed_hz = spi->max_speed_hz;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700852
853 mcspi = spi_master_get_devdata(spi->master);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700854 spi_cntrl = mcspi->master;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700855
856 if (t != NULL && t->bits_per_word)
857 word_len = t->bits_per_word;
858
859 cs->word_len = word_len;
860
Scott Ellis9bd45172010-03-10 14:23:13 -0700861 if (t && t->speed_hz)
862 speed_hz = t->speed_hz;
863
Hannu Heikkinen57d9c102011-02-24 21:31:33 +0200864 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
Stefan Sørensenfaee9b02014-02-02 16:24:25 +0100865 if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
866 clkd = omap2_mcspi_calc_divisor(speed_hz);
867 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
868 clkg = 0;
869 } else {
870 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
871 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
872 clkd = (div - 1) & 0xf;
873 extclk = (div - 1) >> 4;
874 clkg = OMAP2_MCSPI_CHCONF_CLKG;
875 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700876
Hemanth Va41ae1a2009-09-22 16:46:16 -0700877 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700878
879 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
880 * REVISIT: this controller could support SPI_3WIRE mode.
881 */
Daniel Mack2cd45172012-11-14 11:14:26 +0800882 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
Daniel Mack0384e902012-10-07 18:19:44 +0200883 l &= ~OMAP2_MCSPI_CHCONF_IS;
884 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
885 l |= OMAP2_MCSPI_CHCONF_DPE0;
886 } else {
887 l |= OMAP2_MCSPI_CHCONF_IS;
888 l |= OMAP2_MCSPI_CHCONF_DPE1;
889 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
890 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700891
892 /* wordlength */
893 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
894 l |= (word_len - 1) << 7;
895
896 /* set chipselect polarity; manage with FORCE */
897 if (!(spi->mode & SPI_CS_HIGH))
898 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
899 else
900 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
901
902 /* set clock divisor */
903 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
Stefan Sørensenfaee9b02014-02-02 16:24:25 +0100904 l |= clkd << 2;
905
906 /* set clock granularity */
907 l &= ~OMAP2_MCSPI_CHCONF_CLKG;
908 l |= clkg;
909 if (clkg) {
910 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
911 cs->chctrl0 |= extclk << 8;
912 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
913 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700914
915 /* set SPI mode 0..3 */
916 if (spi->mode & SPI_CPOL)
917 l |= OMAP2_MCSPI_CHCONF_POL;
918 else
919 l &= ~OMAP2_MCSPI_CHCONF_POL;
920 if (spi->mode & SPI_CPHA)
921 l |= OMAP2_MCSPI_CHCONF_PHA;
922 else
923 l &= ~OMAP2_MCSPI_CHCONF_PHA;
924
Hemanth Va41ae1a2009-09-22 16:46:16 -0700925 mcspi_write_chconf0(spi, l);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700926
Mark A. Greer97ca0d62014-07-01 20:28:32 -0700927 cs->mode = spi->mode;
928
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700929 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
Stefan Sørensenfaee9b02014-02-02 16:24:25 +0100930 speed_hz,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700931 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
932 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
933
934 return 0;
935}
936
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -0700937/*
938 * Note that we currently allow DMA only if we get a channel
939 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
940 */
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700941static int omap2_mcspi_request_dma(struct spi_device *spi)
942{
943 struct spi_master *master = spi->master;
944 struct omap2_mcspi *mcspi;
945 struct omap2_mcspi_dma *mcspi_dma;
Russell King53741ed2012-04-23 13:51:48 +0100946 dma_cap_mask_t mask;
947 unsigned sig;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700948
949 mcspi = spi_master_get_devdata(master);
950 mcspi_dma = mcspi->dma_channels + spi->chip_select;
951
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700952 init_completion(&mcspi_dma->dma_rx_completion);
953 init_completion(&mcspi_dma->dma_tx_completion);
954
Russell King53741ed2012-04-23 13:51:48 +0100955 dma_cap_zero(mask);
956 dma_cap_set(DMA_SLAVE, mask);
Russell King53741ed2012-04-23 13:51:48 +0100957 sig = mcspi_dma->dma_rx_sync_dev;
Matt Porter74f3aaa2013-06-22 23:07:38 +0530958
959 mcspi_dma->dma_rx =
960 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
961 &sig, &master->dev,
962 mcspi_dma->dma_rx_ch_name);
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -0700963 if (!mcspi_dma->dma_rx)
964 goto no_dma;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700965
Russell King53741ed2012-04-23 13:51:48 +0100966 sig = mcspi_dma->dma_tx_sync_dev;
Matt Porter74f3aaa2013-06-22 23:07:38 +0530967 mcspi_dma->dma_tx =
968 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
969 &sig, &master->dev,
970 mcspi_dma->dma_tx_ch_name);
971
Russell King53741ed2012-04-23 13:51:48 +0100972 if (!mcspi_dma->dma_tx) {
Russell King53741ed2012-04-23 13:51:48 +0100973 dma_release_channel(mcspi_dma->dma_rx);
974 mcspi_dma->dma_rx = NULL;
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -0700975 goto no_dma;
Russell King53741ed2012-04-23 13:51:48 +0100976 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700977
978 return 0;
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -0700979
980no_dma:
981 dev_warn(&spi->dev, "not using DMA for McSPI\n");
982 return -EAGAIN;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700983}
984
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700985static int omap2_mcspi_setup(struct spi_device *spi)
986{
987 int ret;
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530988 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
989 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700990 struct omap2_mcspi_dma *mcspi_dma;
991 struct omap2_mcspi_cs *cs = spi->controller_state;
992
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700993 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
994
995 if (!cs) {
Russell King10aa5a32012-06-18 11:27:04 +0100996 cs = kzalloc(sizeof *cs, GFP_KERNEL);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700997 if (!cs)
998 return -ENOMEM;
999 cs->base = mcspi->base + spi->chip_select * 0x14;
Russell Kinge5480b732008-09-01 21:51:50 +01001000 cs->phys = mcspi->phys + spi->chip_select * 0x14;
Mark A. Greer97ca0d62014-07-01 20:28:32 -07001001 cs->mode = 0;
Hemanth Va41ae1a2009-09-22 16:46:16 -07001002 cs->chconf0 = 0;
Stefan Sørensenfaee9b02014-02-02 16:24:25 +01001003 cs->chctrl0 = 0;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001004 spi->controller_state = cs;
Tero Kristo89c05372009-09-22 16:46:17 -07001005 /* Link this to context save list */
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301006 list_add_tail(&cs->node, &ctx->cs);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001007 }
1008
Russell King8c7494a2012-04-23 13:56:25 +01001009 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001010 ret = omap2_mcspi_request_dma(spi);
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -07001011 if (ret < 0 && ret != -EAGAIN)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001012 return ret;
1013 }
1014
Michael Wellingbc7f9bb2015-05-08 13:31:01 -05001015 if (gpio_is_valid(spi->cs_gpio)) {
1016 if (gpio_request(spi->cs_gpio, dev_name(&spi->dev)) == 0)
1017 gpio_direction_output(spi->cs_gpio,
1018 !(spi->mode & SPI_CS_HIGH));
1019 }
1020
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301021 ret = pm_runtime_get_sync(mcspi->dev);
Govindraj.R1f1a4382011-02-02 17:52:15 +05301022 if (ret < 0)
1023 return ret;
Hemanth Va41ae1a2009-09-22 16:46:16 -07001024
Kyungmin Park86eeb6f2007-10-16 01:27:45 -07001025 ret = omap2_mcspi_setup_transfer(spi, NULL);
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301026 pm_runtime_mark_last_busy(mcspi->dev);
1027 pm_runtime_put_autosuspend(mcspi->dev);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001028
1029 return ret;
1030}
1031
1032static void omap2_mcspi_cleanup(struct spi_device *spi)
1033{
1034 struct omap2_mcspi *mcspi;
1035 struct omap2_mcspi_dma *mcspi_dma;
Tero Kristo89c05372009-09-22 16:46:17 -07001036 struct omap2_mcspi_cs *cs;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001037
1038 mcspi = spi_master_get_devdata(spi->master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001039
Scott Ellis5e774942010-03-10 14:22:45 -07001040 if (spi->controller_state) {
1041 /* Unlink controller state from context save list */
1042 cs = spi->controller_state;
1043 list_del(&cs->node);
Tero Kristo89c05372009-09-22 16:46:17 -07001044
Russell King10aa5a32012-06-18 11:27:04 +01001045 kfree(cs);
Scott Ellis5e774942010-03-10 14:22:45 -07001046 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001047
Scott Ellis99f1a432010-05-24 14:20:27 +00001048 if (spi->chip_select < spi->master->num_chipselect) {
1049 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1050
Russell King53741ed2012-04-23 13:51:48 +01001051 if (mcspi_dma->dma_rx) {
1052 dma_release_channel(mcspi_dma->dma_rx);
1053 mcspi_dma->dma_rx = NULL;
Scott Ellis99f1a432010-05-24 14:20:27 +00001054 }
Russell King53741ed2012-04-23 13:51:48 +01001055 if (mcspi_dma->dma_tx) {
1056 dma_release_channel(mcspi_dma->dma_tx);
1057 mcspi_dma->dma_tx = NULL;
Scott Ellis99f1a432010-05-24 14:20:27 +00001058 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001059 }
Michael Wellingbc7f9bb2015-05-08 13:31:01 -05001060
1061 if (gpio_is_valid(spi->cs_gpio))
1062 gpio_free(spi->cs_gpio);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001063}
1064
Michael Wellingb28cb942015-05-07 18:36:53 -05001065static int omap2_mcspi_work_one(struct omap2_mcspi *mcspi,
1066 struct spi_device *spi, struct spi_transfer *t)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001067{
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001068
1069 /* We only enable one channel at a time -- the one whose message is
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301070 * -- although this controller would gladly
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001071 * arbitrate among multiple channels. This corresponds to "single
1072 * channel" master mode. As a side effect, we need to manage the
1073 * chipselect with the FORCE bit ... CS != channel enable.
1074 */
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001075
Matthias Brugger5cbc7ca2013-01-24 13:40:41 +01001076 struct spi_master *master;
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -07001077 struct omap2_mcspi_dma *mcspi_dma;
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301078 int cs_active = 0;
1079 struct omap2_mcspi_cs *cs;
1080 struct omap2_mcspi_device_config *cd;
1081 int par_override = 0;
1082 int status = 0;
1083 u32 chconf;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001084
Matthias Brugger5cbc7ca2013-01-24 13:40:41 +01001085 master = spi->master;
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -07001086 mcspi_dma = mcspi->dma_channels + spi->chip_select;
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301087 cs = spi->controller_state;
1088 cd = spi->controller_data;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001089
Mark A. Greer97ca0d62014-07-01 20:28:32 -07001090 /*
1091 * The slave driver could have changed spi->mode in which case
1092 * it will be different from cs->mode (the current hardware setup).
1093 * If so, set par_override (even though its not a parity issue) so
1094 * omap2_mcspi_setup_transfer will be called to configure the hardware
1095 * with the correct mode on the first iteration of the loop below.
1096 */
1097 if (spi->mode != cs->mode)
1098 par_override = 1;
1099
Illia Smyrnovd33f4732013-06-17 16:31:06 +03001100 omap2_mcspi_set_enable(spi, 0);
Matthias Brugger5cbc7ca2013-01-24 13:40:41 +01001101
Michael Wellingb28cb942015-05-07 18:36:53 -05001102 if (par_override ||
1103 (t->speed_hz != spi->max_speed_hz) ||
1104 (t->bits_per_word != spi->bits_per_word)) {
1105 par_override = 1;
1106 status = omap2_mcspi_setup_transfer(spi, t);
1107 if (status < 0)
1108 goto out;
1109 if (t->speed_hz == spi->max_speed_hz &&
1110 t->bits_per_word == spi->bits_per_word)
1111 par_override = 0;
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301112 }
Michael Wellingb28cb942015-05-07 18:36:53 -05001113 if (cd && cd->cs_per_word) {
1114 chconf = mcspi->ctx.modulctrl;
1115 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1116 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1117 mcspi->ctx.modulctrl =
1118 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1119 }
1120
1121 if (!cs_active) {
1122 omap2_mcspi_force_cs(spi, 1);
1123 cs_active = 1;
1124 }
1125
1126 chconf = mcspi_cached_chconf0(spi);
1127 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1128 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1129
1130 if (t->tx_buf == NULL)
1131 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1132 else if (t->rx_buf == NULL)
1133 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1134
1135 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1136 /* Turbo mode is for more than one word */
1137 if (t->len > ((cs->word_len + 7) >> 3))
1138 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1139 }
1140
1141 mcspi_write_chconf0(spi, chconf);
1142
1143 if (t->len) {
1144 unsigned count;
1145
1146 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1147 (t->len >= DMA_MIN_BYTES))
1148 omap2_mcspi_set_fifo(spi, t, 1);
1149
1150 omap2_mcspi_set_enable(spi, 1);
1151
1152 /* RX_ONLY mode needs dummy data in TX reg */
1153 if (t->tx_buf == NULL)
1154 writel_relaxed(0, cs->base
1155 + OMAP2_MCSPI_TX0);
1156
1157 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1158 (t->len >= DMA_MIN_BYTES))
1159 count = omap2_mcspi_txrx_dma(spi, t);
1160 else
1161 count = omap2_mcspi_txrx_pio(spi, t);
1162
1163 if (count != t->len) {
1164 status = -EIO;
1165 goto out;
1166 }
1167 }
1168
1169 if (t->delay_usecs)
1170 udelay(t->delay_usecs);
1171
1172 /* ignore the "leave it on after last xfer" hint */
1173 if (t->cs_change) {
1174 omap2_mcspi_force_cs(spi, 0);
1175 cs_active = 0;
1176 }
1177
1178 omap2_mcspi_set_enable(spi, 0);
1179
1180 if (mcspi->fifo_depth > 0)
1181 omap2_mcspi_set_fifo(spi, t, 0);
1182
1183out:
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301184 /* Restore defaults if they were overriden */
1185 if (par_override) {
1186 par_override = 0;
1187 status = omap2_mcspi_setup_transfer(spi, NULL);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001188 }
1189
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301190 if (cs_active)
1191 omap2_mcspi_force_cs(spi, 0);
Govindraj.R1f1a4382011-02-02 17:52:15 +05301192
Matthias Brugger5cbc7ca2013-01-24 13:40:41 +01001193 if (cd && cd->cs_per_word) {
1194 chconf = mcspi->ctx.modulctrl;
1195 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1196 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1197 mcspi->ctx.modulctrl =
1198 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1199 }
1200
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301201 omap2_mcspi_set_enable(spi, 0);
1202
Illia Smyrnovd33f4732013-06-17 16:31:06 +03001203 if (mcspi->fifo_depth > 0 && t)
1204 omap2_mcspi_set_fifo(spi, t, 0);
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301205
Michael Wellingb28cb942015-05-07 18:36:53 -05001206 return status;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001207}
1208
Michael Wellingb28cb942015-05-07 18:36:53 -05001209static int omap2_mcspi_transfer_one(struct spi_master *master,
1210 struct spi_device *spi, struct spi_transfer *t)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001211{
1212 struct omap2_mcspi *mcspi;
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -07001213 struct omap2_mcspi_dma *mcspi_dma;
Michael Wellingb28cb942015-05-07 18:36:53 -05001214 const void *tx_buf = t->tx_buf;
1215 void *rx_buf = t->rx_buf;
1216 unsigned len = t->len;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001217
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301218 mcspi = spi_master_get_devdata(master);
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -07001219 mcspi_dma = mcspi->dma_channels + spi->chip_select;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001220
Michael Wellingb28cb942015-05-07 18:36:53 -05001221 if ((len && !(rx_buf || tx_buf))) {
1222 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1223 t->speed_hz,
1224 len,
1225 tx_buf ? "tx" : "",
1226 rx_buf ? "rx" : "",
1227 t->bits_per_word);
1228 return -EINVAL;
1229 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001230
Michael Wellingb28cb942015-05-07 18:36:53 -05001231 if (len < DMA_MIN_BYTES)
1232 goto skip_dma_map;
1233
1234 if (mcspi_dma->dma_tx && tx_buf != NULL) {
1235 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1236 len, DMA_TO_DEVICE);
1237 if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1238 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1239 'T', len);
1240 return -EINVAL;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001241 }
Michael Wellingb28cb942015-05-07 18:36:53 -05001242 }
1243 if (mcspi_dma->dma_rx && rx_buf != NULL) {
1244 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1245 DMA_FROM_DEVICE);
1246 if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1247 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1248 'R', len);
1249 if (tx_buf != NULL)
1250 dma_unmap_single(mcspi->dev, t->tx_dma,
1251 len, DMA_TO_DEVICE);
1252 return -EINVAL;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001253 }
1254 }
1255
Michael Wellingb28cb942015-05-07 18:36:53 -05001256skip_dma_map:
1257 return omap2_mcspi_work_one(mcspi, spi, t);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001258}
1259
Grant Likelyfd4a3192012-12-07 16:57:14 +00001260static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001261{
1262 struct spi_master *master = mcspi->master;
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301263 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301264 int ret = 0;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001265
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301266 ret = pm_runtime_get_sync(mcspi->dev);
Govindraj.R1f1a4382011-02-02 17:52:15 +05301267 if (ret < 0)
1268 return ret;
Jouni Hoganderddb22192009-07-29 15:02:11 -07001269
Shubhrajyoti D39f80522012-03-29 22:11:07 +05301270 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
Matthias Brugger18dd6192013-01-24 13:28:58 +01001271 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
Shubhrajyoti D39f80522012-03-29 22:11:07 +05301272 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001273
1274 omap2_mcspi_set_master_mode(master);
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301275 pm_runtime_mark_last_busy(mcspi->dev);
1276 pm_runtime_put_autosuspend(mcspi->dev);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001277 return 0;
1278}
1279
Govindraj.R1f1a4382011-02-02 17:52:15 +05301280static int omap_mcspi_runtime_resume(struct device *dev)
1281{
1282 struct omap2_mcspi *mcspi;
1283 struct spi_master *master;
1284
1285 master = dev_get_drvdata(dev);
1286 mcspi = spi_master_get_devdata(master);
1287 omap2_mcspi_restore_ctx(mcspi);
1288
1289 return 0;
1290}
1291
Benoit Coussond5a80032012-02-15 18:37:34 +01001292static struct omap2_mcspi_platform_config omap2_pdata = {
1293 .regs_offset = 0,
1294};
1295
1296static struct omap2_mcspi_platform_config omap4_pdata = {
1297 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1298};
1299
1300static const struct of_device_id omap_mcspi_of_match[] = {
1301 {
1302 .compatible = "ti,omap2-mcspi",
1303 .data = &omap2_pdata,
1304 },
1305 {
1306 .compatible = "ti,omap4-mcspi",
1307 .data = &omap4_pdata,
1308 },
1309 { },
1310};
1311MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
Girishccc7bae2008-02-06 01:38:16 -08001312
Grant Likelyfd4a3192012-12-07 16:57:14 +00001313static int omap2_mcspi_probe(struct platform_device *pdev)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001314{
1315 struct spi_master *master;
Uwe Kleine-König83a01e72012-05-21 21:57:39 +02001316 const struct omap2_mcspi_platform_config *pdata;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001317 struct omap2_mcspi *mcspi;
1318 struct resource *r;
1319 int status = 0, i;
Benoit Coussond5a80032012-02-15 18:37:34 +01001320 u32 regs_offset = 0;
1321 static int bus_num = 1;
1322 struct device_node *node = pdev->dev.of_node;
1323 const struct of_device_id *match;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001324
1325 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1326 if (master == NULL) {
1327 dev_dbg(&pdev->dev, "master allocation failed\n");
1328 return -ENOMEM;
1329 }
1330
David Brownelle7db06b2009-06-17 16:26:04 -07001331 /* the spi->mode bits understood by this driver: */
1332 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
Stephen Warren24778be2013-05-21 20:36:35 -06001333 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001334 master->setup = omap2_mcspi_setup;
Mark Brownf0278a12013-07-28 15:34:37 +01001335 master->auto_runtime_pm = true;
Michael Wellingb28cb942015-05-07 18:36:53 -05001336 master->transfer_one = omap2_mcspi_transfer_one;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001337 master->cleanup = omap2_mcspi_cleanup;
Benoit Coussond5a80032012-02-15 18:37:34 +01001338 master->dev.of_node = node;
Axel Linaca09242014-02-18 22:02:47 +08001339 master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1340 master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
Benoit Coussond5a80032012-02-15 18:37:34 +01001341
Jingoo Han24b5a822013-05-23 19:20:40 +09001342 platform_set_drvdata(pdev, master);
Daniel Mack0384e902012-10-07 18:19:44 +02001343
1344 mcspi = spi_master_get_devdata(master);
1345 mcspi->master = master;
1346
Benoit Coussond5a80032012-02-15 18:37:34 +01001347 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1348 if (match) {
1349 u32 num_cs = 1; /* default number of chipselect */
1350 pdata = match->data;
1351
1352 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1353 master->num_chipselect = num_cs;
1354 master->bus_num = bus_num++;
Daniel Mack2cd45172012-11-14 11:14:26 +08001355 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1356 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
Benoit Coussond5a80032012-02-15 18:37:34 +01001357 } else {
Jingoo Han8074cf02013-07-30 16:58:59 +09001358 pdata = dev_get_platdata(&pdev->dev);
Benoit Coussond5a80032012-02-15 18:37:34 +01001359 master->num_chipselect = pdata->num_cs;
1360 if (pdev->id != -1)
1361 master->bus_num = pdev->id;
Daniel Mack0384e902012-10-07 18:19:44 +02001362 mcspi->pin_dir = pdata->pin_dir;
Benoit Coussond5a80032012-02-15 18:37:34 +01001363 }
1364 regs_offset = pdata->regs_offset;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001365
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001366 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1367 if (r == NULL) {
1368 status = -ENODEV;
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301369 goto free_master;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001370 }
Shubhrajyoti D1458d162011-10-24 15:54:24 +05301371
Benoit Coussond5a80032012-02-15 18:37:34 +01001372 r->start += regs_offset;
1373 r->end += regs_offset;
Shubhrajyoti D1458d162011-10-24 15:54:24 +05301374 mcspi->phys = r->start;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001375
Thierry Redingb0ee5602013-01-21 11:09:18 +01001376 mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1377 if (IS_ERR(mcspi->base)) {
1378 status = PTR_ERR(mcspi->base);
Shubhrajyoti D1a77b122012-03-17 12:44:01 +05301379 goto free_master;
Russell King55c381e2008-09-04 14:07:22 +01001380 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001381
Govindraj.R1f1a4382011-02-02 17:52:15 +05301382 mcspi->dev = &pdev->dev;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001383
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301384 INIT_LIST_HEAD(&mcspi->ctx.cs);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001385
Axel Lina6f936d2014-03-29 21:37:44 +08001386 mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1387 sizeof(struct omap2_mcspi_dma),
1388 GFP_KERNEL);
1389 if (mcspi->dma_channels == NULL) {
1390 status = -ENOMEM;
Shubhrajyoti D1a77b122012-03-17 12:44:01 +05301391 goto free_master;
Axel Lina6f936d2014-03-29 21:37:44 +08001392 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001393
Charulatha V1a5d8192011-02-02 17:52:14 +05301394 for (i = 0; i < master->num_chipselect; i++) {
Matt Porter74f3aaa2013-06-22 23:07:38 +05301395 char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name;
1396 char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name;
Charulatha V1a5d8192011-02-02 17:52:14 +05301397 struct resource *dma_res;
1398
Matt Porter74f3aaa2013-06-22 23:07:38 +05301399 sprintf(dma_rx_ch_name, "rx%d", i);
1400 if (!pdev->dev.of_node) {
1401 dma_res =
1402 platform_get_resource_byname(pdev,
1403 IORESOURCE_DMA,
1404 dma_rx_ch_name);
1405 if (!dma_res) {
1406 dev_dbg(&pdev->dev,
1407 "cannot get DMA RX channel\n");
1408 status = -ENODEV;
1409 break;
1410 }
Charulatha V1a5d8192011-02-02 17:52:14 +05301411
Matt Porter74f3aaa2013-06-22 23:07:38 +05301412 mcspi->dma_channels[i].dma_rx_sync_dev =
1413 dma_res->start;
Charulatha V1a5d8192011-02-02 17:52:14 +05301414 }
Matt Porter74f3aaa2013-06-22 23:07:38 +05301415 sprintf(dma_tx_ch_name, "tx%d", i);
1416 if (!pdev->dev.of_node) {
1417 dma_res =
1418 platform_get_resource_byname(pdev,
1419 IORESOURCE_DMA,
1420 dma_tx_ch_name);
1421 if (!dma_res) {
1422 dev_dbg(&pdev->dev,
1423 "cannot get DMA TX channel\n");
1424 status = -ENODEV;
1425 break;
1426 }
Charulatha V1a5d8192011-02-02 17:52:14 +05301427
Matt Porter74f3aaa2013-06-22 23:07:38 +05301428 mcspi->dma_channels[i].dma_tx_sync_dev =
1429 dma_res->start;
1430 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001431 }
1432
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301433 if (status < 0)
Axel Lina6f936d2014-03-29 21:37:44 +08001434 goto free_master;
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301435
Shubhrajyoti D27b52842012-03-26 17:04:22 +05301436 pm_runtime_use_autosuspend(&pdev->dev);
1437 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
Govindraj.R1f1a4382011-02-02 17:52:15 +05301438 pm_runtime_enable(&pdev->dev);
1439
Wei Yongjun142e07b2013-04-18 11:14:59 +08001440 status = omap2_mcspi_master_setup(mcspi);
1441 if (status < 0)
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301442 goto disable_pm;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001443
Jingoo Hanb95e02b2013-09-24 13:40:29 +09001444 status = devm_spi_register_master(&pdev->dev, master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001445 if (status < 0)
Shubhrajyoti D37a2d842012-08-02 16:41:25 +05301446 goto disable_pm;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001447
1448 return status;
1449
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301450disable_pm:
Shubhrajyoti D751c9252011-10-28 17:14:18 +05301451 pm_runtime_disable(&pdev->dev);
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301452free_master:
Shubhrajyoti D37a2d842012-08-02 16:41:25 +05301453 spi_master_put(master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001454 return status;
1455}
1456
Grant Likelyfd4a3192012-12-07 16:57:14 +00001457static int omap2_mcspi_remove(struct platform_device *pdev)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001458{
Axel Lina6f936d2014-03-29 21:37:44 +08001459 struct spi_master *master = platform_get_drvdata(pdev);
1460 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001461
Shubhrajyoti Da93a2022012-08-22 11:35:14 +05301462 pm_runtime_put_sync(mcspi->dev);
Shubhrajyoti D751c9252011-10-28 17:14:18 +05301463 pm_runtime_disable(&pdev->dev);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001464
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001465 return 0;
1466}
1467
Kay Sievers7e38c3c2008-04-10 21:29:20 -07001468/* work with hotplug and coldplug */
1469MODULE_ALIAS("platform:omap2_mcspi");
1470
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001471#ifdef CONFIG_SUSPEND
1472/*
1473 * When SPI wake up from off-mode, CS is in activate state. If it was in
1474 * unactive state when driver was suspend, then force it to unactive state at
1475 * wake up.
1476 */
1477static int omap2_mcspi_resume(struct device *dev)
1478{
1479 struct spi_master *master = dev_get_drvdata(dev);
1480 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301481 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1482 struct omap2_mcspi_cs *cs;
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001483
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301484 pm_runtime_get_sync(mcspi->dev);
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301485 list_for_each_entry(cs, &ctx->cs, node) {
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001486 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001487 /*
1488 * We need to toggle CS state for OMAP take this
1489 * change in account.
1490 */
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +05301491 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
Victor Kamensky21b2ce52013-11-16 02:01:16 +02001492 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +05301493 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
Victor Kamensky21b2ce52013-11-16 02:01:16 +02001494 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001495 }
1496 }
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301497 pm_runtime_mark_last_busy(mcspi->dev);
1498 pm_runtime_put_autosuspend(mcspi->dev);
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001499 return 0;
1500}
1501#else
1502#define omap2_mcspi_resume NULL
1503#endif
1504
1505static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1506 .resume = omap2_mcspi_resume,
Govindraj.R1f1a4382011-02-02 17:52:15 +05301507 .runtime_resume = omap_mcspi_runtime_resume,
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001508};
1509
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001510static struct platform_driver omap2_mcspi_driver = {
1511 .driver = {
1512 .name = "omap2_mcspi",
Benoit Coussond5a80032012-02-15 18:37:34 +01001513 .pm = &omap2_mcspi_pm_ops,
1514 .of_match_table = omap_mcspi_of_match,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001515 },
Felipe Balbi7d6b6d82012-03-14 11:18:30 +02001516 .probe = omap2_mcspi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +00001517 .remove = omap2_mcspi_remove,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001518};
1519
Felipe Balbi9fdca9d2012-03-14 11:18:31 +02001520module_platform_driver(omap2_mcspi_driver);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001521MODULE_LICENSE("GPL");