| Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | /* |
| Russell King | 4baa992 | 2008-08-02 10:55:55 +0100 | [diff] [blame] | 3 | * arch/arm/include/asm/cache.h |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | */ |
| 5 | #ifndef __ASMARM_CACHE_H |
| 6 | #define __ASMARM_CACHE_H |
| 7 | |
| Kirill A. Shutemov | 910a17e | 2009-09-15 10:23:53 +0100 | [diff] [blame] | 8 | #define L1_CACHE_SHIFT CONFIG_ARM_L1_CACHE_SHIFT |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) |
| 10 | |
| Martin Fuzzey | eb5f4ca | 2009-06-01 09:19:37 +0100 | [diff] [blame] | 11 | /* |
| 12 | * Memory returned by kmalloc() may be used for DMA, so we must make |
| 13 | * sure that all such allocations are cache aligned. Otherwise, |
| 14 | * unrelated code may cause parts of the buffer to be read into the |
| 15 | * cache before the transfer is done, causing old data to be seen by |
| 16 | * the CPU. |
| 17 | */ |
| FUJITA Tomonori | a6eb9fe | 2010-08-10 18:03:22 -0700 | [diff] [blame] | 18 | #define ARCH_DMA_MINALIGN L1_CACHE_BYTES |
| Martin Fuzzey | eb5f4ca | 2009-06-01 09:19:37 +0100 | [diff] [blame] | 19 | |
| 20 | /* |
| 21 | * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. |
| 22 | */ |
| 23 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) |
| 24 | #define ARCH_SLAB_MINALIGN 8 |
| 25 | #endif |
| 26 | |
| Russell King | daf8741 | 2010-12-04 17:08:32 +0000 | [diff] [blame] | 27 | #define __read_mostly __attribute__((__section__(".data..read_mostly"))) |
| 28 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | #endif |