Thomas Gleixner | 1621633 | 2019-05-19 15:51:31 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
Yoichi Yuasa | 1097c6a | 2007-10-22 19:43:15 +0900 | [diff] [blame] | 2 | /* |
| 3 | * Cobalt time initialization. |
| 4 | * |
Yoichi Yuasa | ada8e95 | 2009-07-03 00:39:38 +0900 | [diff] [blame] | 5 | * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org> |
Yoichi Yuasa | 1097c6a | 2007-10-22 19:43:15 +0900 | [diff] [blame] | 6 | */ |
Ralf Baechle | 334955e | 2011-06-01 19:04:57 +0100 | [diff] [blame] | 7 | #include <linux/i8253.h> |
Yoichi Yuasa | 1097c6a | 2007-10-22 19:43:15 +0900 | [diff] [blame] | 8 | #include <linux/init.h> |
| 9 | |
| 10 | #include <asm/gt64120.h> |
Yoichi Yuasa | 1097c6a | 2007-10-22 19:43:15 +0900 | [diff] [blame] | 11 | #include <asm/time.h> |
| 12 | |
| 13 | #define GT641XX_BASE_CLOCK 50000000 /* 50MHz */ |
| 14 | |
| 15 | void __init plat_time_init(void) |
| 16 | { |
Yoichi Yuasa | 18ca38d | 2007-12-09 21:22:04 +0900 | [diff] [blame] | 17 | u32 start, end; |
| 18 | int i = HZ / 10; |
| 19 | |
Yoichi Yuasa | 1097c6a | 2007-10-22 19:43:15 +0900 | [diff] [blame] | 20 | setup_pit_timer(); |
| 21 | |
| 22 | gt641xx_set_base_clock(GT641XX_BASE_CLOCK); |
| 23 | |
Yoichi Yuasa | 18ca38d | 2007-12-09 21:22:04 +0900 | [diff] [blame] | 24 | /* |
| 25 | * MIPS counter frequency is measured during a 100msec interval |
| 26 | * using GT64111 timer0. |
| 27 | */ |
| 28 | while (!gt641xx_timer0_state()) |
| 29 | ; |
| 30 | |
| 31 | start = read_c0_count(); |
| 32 | |
| 33 | while (i--) |
| 34 | while (!gt641xx_timer0_state()) |
| 35 | ; |
| 36 | |
| 37 | end = read_c0_count(); |
| 38 | |
| 39 | mips_hpt_frequency = (end - start) * 10; |
| 40 | printk(KERN_INFO "MIPS counter frequency %dHz\n", mips_hpt_frequency); |
Yoichi Yuasa | 1097c6a | 2007-10-22 19:43:15 +0900 | [diff] [blame] | 41 | } |