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git.odroid.com / yocto / kernel / common / c942fddf8793b2013be8c901b47d0a8dc02bf99f / . / arch / x86 / include / asm / tsc.h
blob: 8a0c25c6bf099cf9858568d67e382f940e493a47 [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]2/*
Thomas Gleixner2f0798a2007-10-12 23:04:23 +0200[diff] [blame]3 * x86 TSC related functions
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]4 */
H. Peter Anvin1965aae2008-10-22 22:26:29 -0700[diff] [blame]5#ifndef _ASM_X86_TSC_H
6#define _ASM_X86_TSC_H
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]7
8#include <asm/processor.h>
9
Thomas Gleixner2f0798a2007-10-12 23:04:23 +0200[diff] [blame]10#define NS_SCALE 10 /* 2^10, carefully chosen */
11#define US_SCALE 32 /* 2^32, arbitralrily chosen */
12
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]13/*
14 * Standard way to access the cycle counter.
15 */
16typedef unsigned long long cycles_t;
17
18extern unsigned int cpu_khz;
19extern unsigned int tsc_khz;
Glauber de Oliveira Costa73018a62008-01-30 13:31:26 +0100[diff] [blame]20
21extern void disable_TSC(void);
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]22
23static inline cycles_t get_cycles(void)
24{
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]25#ifndef CONFIG_X86_TSC
Borislav Petkov59e21e32016-04-04 22:24:59 +0200[diff] [blame]26 if (!boot_cpu_has(X86_FEATURE_TSC))
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]27 return 0;
28#endif
Ingo Molnar75f2ce02008-01-30 13:33:24 +0100[diff] [blame]29
Andy Lutomirski4ea16362015-06-25 18:44:07 +0200[diff] [blame]30 return rdtsc();
Andi Kleen6d63de82008-01-30 13:32:39 +0100[diff] [blame]31}
Glauber de Oliveira Costa4e871732008-01-30 13:31:03 +0100[diff] [blame]32
Thomas Gleixnera5a1d1c2016-12-21 20:32:01 +0100[diff] [blame]33extern struct system_counterval_t convert_art_to_tsc(u64 art);
Rajvi Jingarfc804f62018-03-08 09:28:36 -0800[diff] [blame]34extern struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns);
Christopher S. Hallf9677e02016-02-29 06:33:47 -0800[diff] [blame]35
Pavel Tatashincf7a63e2018-07-19 16:55:38 -0400[diff] [blame]36extern void tsc_early_init(void);
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]37extern void tsc_init(void);
Yi Wang89f579c2018-11-22 10:04:09 +0800[diff] [blame]38extern unsigned long calibrate_delay_is_known(void);
john stultz5a90cf22007-05-02 19:27:08 +0200[diff] [blame]39extern void mark_tsc_unstable(char *reason);
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]40extern int unsynchronized_tsc(void);
Thomas Gleixner2d826402009-08-20 17:06:25 +0200[diff] [blame]41extern int check_tsc_unstable(void);
mike.travis@hpe.com341102c2017-10-12 11:32:02 -0500[diff] [blame]42extern void mark_tsc_async_resets(char *reason);
Pavel Tatashin03821f42018-07-19 16:55:44 -0400[diff] [blame]43extern unsigned long native_calibrate_cpu_early(void);
Thomas Gleixner2d826402009-08-20 17:06:25 +0200[diff] [blame]44extern unsigned long native_calibrate_tsc(void);
Andi Kleena94cab22015-05-10 12:22:39 -0700[diff] [blame]45extern unsigned long long native_sched_clock_from_tsc(u64 tsc);
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]46
Suresh Siddha28a00182011-11-04 15:42:17 -0700[diff] [blame]47extern int tsc_clocksource_reliable;
Thomas Gleixnerc0fc9b12017-10-17 08:49:37 +0200[diff] [blame]48#ifdef CONFIG_X86_TSC
mike.travis@hpe.com341102c2017-10-12 11:32:02 -0500[diff] [blame]49extern bool tsc_async_resets;
Thomas Gleixnerc0fc9b12017-10-17 08:49:37 +0200[diff] [blame]50#else
51# define tsc_async_resets false
52#endif
Suresh Siddha28a00182011-11-04 15:42:17 -0700[diff] [blame]53
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]54/*
55 * Boot-time check whether the TSCs are synchronized across
56 * all CPUs/cores:
57 */
Thomas Gleixner8b223bc2016-11-19 13:47:36 +0000[diff] [blame]58#ifdef CONFIG_X86_TSC
Thomas Gleixner5bae1562016-12-13 13:14:17 +0000[diff] [blame]59extern bool tsc_store_and_check_tsc_adjust(bool bootcpu);
Thomas Gleixner6a369582016-12-13 13:14:17 +0000[diff] [blame]60extern void tsc_verify_tsc_adjust(bool resume);
Thomas Gleixnerb8365542016-11-29 20:28:31 +0100[diff] [blame]61extern void check_tsc_sync_source(int cpu);
62extern void check_tsc_sync_target(void);
Thomas Gleixner8b223bc2016-11-19 13:47:36 +0000[diff] [blame]63#else
Thomas Gleixner5bae1562016-12-13 13:14:17 +0000[diff] [blame]64static inline bool tsc_store_and_check_tsc_adjust(bool bootcpu) { return false; }
Thomas Gleixner6a369582016-12-13 13:14:17 +0000[diff] [blame]65static inline void tsc_verify_tsc_adjust(bool resume) { }
Thomas Gleixnerb8365542016-11-29 20:28:31 +0100[diff] [blame]66static inline void check_tsc_sync_source(int cpu) { }
67static inline void check_tsc_sync_target(void) { }
Thomas Gleixner8b223bc2016-11-19 13:47:36 +0000[diff] [blame]68#endif
69
Thomas Gleixner80ca9c92008-01-30 13:30:18 +0100[diff] [blame]70extern int notsc_setup(char *);
Marcelo Tosattib74f05d62012-02-13 11:07:27 -0200[diff] [blame]71extern void tsc_save_sched_clock_state(void);
72extern void tsc_restore_sched_clock_state(void);
Thomas Gleixnerd3716982007-10-12 23:04:06 +0200[diff] [blame]73
Len Brown02c0cd22016-06-17 01:22:50 -0400[diff] [blame]74unsigned long cpu_khz_from_msr(void);
Bin Gao7da7c152013-10-21 09:16:33 -0700[diff] [blame]75
H. Peter Anvin1965aae2008-10-22 22:26:29 -0700[diff] [blame]76#endif /* _ASM_X86_TSC_H */