Daniel Scheller | 3dae3c9 | 2018-06-19 14:51:18 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 2 | /* |
Daniel Scheller | 2dc3e05 | 2018-03-17 10:55:32 -0400 | [diff] [blame] | 3 | * cxd2099.c: Driver for the Sony CXD2099AR Common Interface Controller |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 4 | * |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 5 | * Copyright (C) 2010-2013 Digital Devices GmbH |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 6 | * |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License |
| 9 | * version 2 only, as published by the Free Software Foundation. |
| 10 | * |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 15 | */ |
| 16 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 17 | #include <linux/slab.h> |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/module.h> |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 20 | #include <linux/i2c.h> |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 21 | #include <linux/regmap.h> |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 22 | #include <linux/wait.h> |
| 23 | #include <linux/delay.h> |
| 24 | #include <linux/mutex.h> |
| 25 | #include <linux/io.h> |
| 26 | |
| 27 | #include "cxd2099.h" |
| 28 | |
Daniel Scheller | 2b64e4d | 2017-08-23 12:10:01 -0400 | [diff] [blame] | 29 | static int buffermode; |
| 30 | module_param(buffermode, int, 0444); |
Daniel Scheller | 6c84bbf | 2017-12-12 13:46:57 -0500 | [diff] [blame] | 31 | MODULE_PARM_DESC(buffermode, "Enable CXD2099AR buffer mode (default: disabled)"); |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 32 | |
| 33 | static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 34 | |
| 35 | struct cxd { |
| 36 | struct dvb_ca_en50221 en; |
| 37 | |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 38 | struct cxd2099_cfg cfg; |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 39 | struct i2c_client *client; |
| 40 | struct regmap *regmap; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 41 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 42 | u8 regs[0x23]; |
| 43 | u8 lastaddress; |
| 44 | u8 clk_reg_f; |
| 45 | u8 clk_reg_b; |
| 46 | int mode; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 47 | int ready; |
| 48 | int dr; |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 49 | int write_busy; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 50 | int slot_stat; |
| 51 | |
| 52 | u8 amem[1024]; |
| 53 | int amem_read; |
| 54 | |
| 55 | int cammode; |
Daniel Scheller | 65ac8c8 | 2017-12-12 13:46:55 -0500 | [diff] [blame] | 56 | struct mutex lock; /* device access lock */ |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 57 | |
| 58 | u8 rbuf[1028]; |
| 59 | u8 wbuf[1028]; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 60 | }; |
| 61 | |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 62 | static int read_block(struct cxd *ci, u8 adr, u8 *data, u16 n) |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 63 | { |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 64 | int status = 0; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 65 | |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 66 | if (ci->lastaddress != adr) |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 67 | status = regmap_write(ci->regmap, 0, adr); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 68 | if (!status) { |
| 69 | ci->lastaddress = adr; |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 70 | |
| 71 | while (n) { |
| 72 | int len = n; |
| 73 | |
Daniel Scheller | 65ac8c8 | 2017-12-12 13:46:55 -0500 | [diff] [blame] | 74 | if (ci->cfg.max_i2c && len > ci->cfg.max_i2c) |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 75 | len = ci->cfg.max_i2c; |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 76 | status = regmap_raw_read(ci->regmap, 1, data, len); |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 77 | if (status) |
| 78 | return status; |
| 79 | data += len; |
| 80 | n -= len; |
| 81 | } |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 82 | } |
| 83 | return status; |
| 84 | } |
| 85 | |
| 86 | static int read_reg(struct cxd *ci, u8 reg, u8 *val) |
| 87 | { |
| 88 | return read_block(ci, reg, val, 1); |
| 89 | } |
| 90 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 91 | static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n) |
| 92 | { |
| 93 | int status; |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 94 | u8 addr[2] = {address & 0xff, address >> 8}; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 95 | |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 96 | status = regmap_raw_write(ci->regmap, 2, addr, 2); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 97 | if (!status) |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 98 | status = regmap_raw_read(ci->regmap, 3, data, n); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 99 | return status; |
| 100 | } |
| 101 | |
| 102 | static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n) |
| 103 | { |
| 104 | int status; |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 105 | u8 addr[2] = {address & 0xff, address >> 8}; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 106 | |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 107 | status = regmap_raw_write(ci->regmap, 2, addr, 2); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 108 | if (!status) { |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 109 | u8 buf[256]; |
Aybuke Ozdemir | fcf1b73 | 2014-09-18 00:54:04 +0300 | [diff] [blame] | 110 | |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 111 | memcpy(buf, data, n); |
| 112 | status = regmap_raw_write(ci->regmap, 3, buf, n); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 113 | } |
| 114 | return status; |
| 115 | } |
| 116 | |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 117 | static int read_io(struct cxd *ci, u16 address, unsigned int *val) |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 118 | { |
| 119 | int status; |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 120 | u8 addr[2] = {address & 0xff, address >> 8}; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 121 | |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 122 | status = regmap_raw_write(ci->regmap, 2, addr, 2); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 123 | if (!status) |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 124 | status = regmap_read(ci->regmap, 3, val); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 125 | return status; |
| 126 | } |
| 127 | |
| 128 | static int write_io(struct cxd *ci, u16 address, u8 val) |
| 129 | { |
| 130 | int status; |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 131 | u8 addr[2] = {address & 0xff, address >> 8}; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 132 | |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 133 | status = regmap_raw_write(ci->regmap, 2, addr, 2); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 134 | if (!status) |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 135 | status = regmap_write(ci->regmap, 3, val); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 136 | return status; |
| 137 | } |
| 138 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 139 | static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask) |
| 140 | { |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 141 | int status = 0; |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 142 | unsigned int regval; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 143 | |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 144 | if (ci->lastaddress != reg) |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 145 | status = regmap_write(ci->regmap, 0, reg); |
| 146 | if (!status && reg >= 6 && reg <= 8 && mask != 0xff) { |
| 147 | status = regmap_read(ci->regmap, 1, ®val); |
| 148 | ci->regs[reg] = regval; |
| 149 | } |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 150 | ci->lastaddress = reg; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 151 | ci->regs[reg] = (ci->regs[reg] & (~mask)) | val; |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 152 | if (!status) |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 153 | status = regmap_write(ci->regmap, 1, ci->regs[reg]); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 154 | if (reg == 0x20) |
| 155 | ci->regs[reg] &= 0x7f; |
| 156 | return status; |
| 157 | } |
| 158 | |
| 159 | static int write_reg(struct cxd *ci, u8 reg, u8 val) |
| 160 | { |
| 161 | return write_regm(ci, reg, val, 0xff); |
| 162 | } |
| 163 | |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 164 | static int write_block(struct cxd *ci, u8 adr, u8 *data, u16 n) |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 165 | { |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 166 | int status = 0; |
| 167 | u8 *buf = ci->wbuf; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 168 | |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 169 | if (ci->lastaddress != adr) |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 170 | status = regmap_write(ci->regmap, 0, adr); |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 171 | if (status) |
| 172 | return status; |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 173 | |
| 174 | ci->lastaddress = adr; |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 175 | while (n) { |
| 176 | int len = n; |
| 177 | |
| 178 | if (ci->cfg.max_i2c && (len + 1 > ci->cfg.max_i2c)) |
| 179 | len = ci->cfg.max_i2c - 1; |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 180 | memcpy(buf, data, len); |
| 181 | status = regmap_raw_write(ci->regmap, 1, buf, len); |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 182 | if (status) |
| 183 | return status; |
| 184 | n -= len; |
| 185 | data += len; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 186 | } |
| 187 | return status; |
| 188 | } |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 189 | |
| 190 | static void set_mode(struct cxd *ci, int mode) |
| 191 | { |
| 192 | if (mode == ci->mode) |
| 193 | return; |
| 194 | |
| 195 | switch (mode) { |
| 196 | case 0x00: /* IO mem */ |
| 197 | write_regm(ci, 0x06, 0x00, 0x07); |
| 198 | break; |
| 199 | case 0x01: /* ATT mem */ |
| 200 | write_regm(ci, 0x06, 0x02, 0x07); |
| 201 | break; |
| 202 | default: |
| 203 | break; |
| 204 | } |
| 205 | ci->mode = mode; |
| 206 | } |
| 207 | |
| 208 | static void cam_mode(struct cxd *ci, int mode) |
| 209 | { |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 210 | u8 dummy; |
| 211 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 212 | if (mode == ci->cammode) |
| 213 | return; |
| 214 | |
| 215 | switch (mode) { |
| 216 | case 0x00: |
| 217 | write_regm(ci, 0x20, 0x80, 0x80); |
| 218 | break; |
| 219 | case 0x01: |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 220 | if (!ci->en.read_data) |
| 221 | return; |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 222 | ci->write_busy = 0; |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 223 | dev_info(&ci->client->dev, "enable cam buffer mode\n"); |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 224 | write_reg(ci, 0x0d, 0x00); |
| 225 | write_reg(ci, 0x0e, 0x01); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 226 | write_regm(ci, 0x08, 0x40, 0x40); |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 227 | read_reg(ci, 0x12, &dummy); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 228 | write_regm(ci, 0x08, 0x80, 0x80); |
| 229 | break; |
| 230 | default: |
| 231 | break; |
| 232 | } |
| 233 | ci->cammode = mode; |
| 234 | } |
| 235 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 236 | static int init(struct cxd *ci) |
| 237 | { |
| 238 | int status; |
| 239 | |
| 240 | mutex_lock(&ci->lock); |
| 241 | ci->mode = -1; |
| 242 | do { |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 243 | status = write_reg(ci, 0x00, 0x00); |
| 244 | if (status < 0) |
| 245 | break; |
| 246 | status = write_reg(ci, 0x01, 0x00); |
| 247 | if (status < 0) |
| 248 | break; |
| 249 | status = write_reg(ci, 0x02, 0x10); |
| 250 | if (status < 0) |
| 251 | break; |
| 252 | status = write_reg(ci, 0x03, 0x00); |
| 253 | if (status < 0) |
| 254 | break; |
| 255 | status = write_reg(ci, 0x05, 0xFF); |
| 256 | if (status < 0) |
| 257 | break; |
| 258 | status = write_reg(ci, 0x06, 0x1F); |
| 259 | if (status < 0) |
| 260 | break; |
| 261 | status = write_reg(ci, 0x07, 0x1F); |
| 262 | if (status < 0) |
| 263 | break; |
| 264 | status = write_reg(ci, 0x08, 0x28); |
| 265 | if (status < 0) |
| 266 | break; |
| 267 | status = write_reg(ci, 0x14, 0x20); |
| 268 | if (status < 0) |
| 269 | break; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 270 | |
Monam Agarwal | 4fe130f | 2014-03-02 04:10:04 +0530 | [diff] [blame] | 271 | /* TOSTRT = 8, Mode B (gated clock), falling Edge, |
Elise Lennion | 0907bb2 | 2016-10-09 23:24:33 -0300 | [diff] [blame] | 272 | * Serial, POL=HIGH, MSB |
| 273 | */ |
Monam Agarwal | 4fe130f | 2014-03-02 04:10:04 +0530 | [diff] [blame] | 274 | status = write_reg(ci, 0x0A, 0xA7); |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 275 | if (status < 0) |
| 276 | break; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 277 | |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 278 | status = write_reg(ci, 0x0B, 0x33); |
| 279 | if (status < 0) |
| 280 | break; |
| 281 | status = write_reg(ci, 0x0C, 0x33); |
| 282 | if (status < 0) |
| 283 | break; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 284 | |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 285 | status = write_regm(ci, 0x14, 0x00, 0x0F); |
| 286 | if (status < 0) |
| 287 | break; |
| 288 | status = write_reg(ci, 0x15, ci->clk_reg_b); |
| 289 | if (status < 0) |
| 290 | break; |
| 291 | status = write_regm(ci, 0x16, 0x00, 0x0F); |
| 292 | if (status < 0) |
| 293 | break; |
| 294 | status = write_reg(ci, 0x17, ci->clk_reg_f); |
| 295 | if (status < 0) |
| 296 | break; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 297 | |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 298 | if (ci->cfg.clock_mode == 2) { |
| 299 | /* bitrate*2^13/ 72000 */ |
| 300 | u32 reg = ((ci->cfg.bitrate << 13) + 71999) / 72000; |
| 301 | |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 302 | if (ci->cfg.polarity) { |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 303 | status = write_reg(ci, 0x09, 0x6f); |
| 304 | if (status < 0) |
| 305 | break; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 306 | } else { |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 307 | status = write_reg(ci, 0x09, 0x6d); |
| 308 | if (status < 0) |
| 309 | break; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 310 | } |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 311 | status = write_reg(ci, 0x20, 0x08); |
| 312 | if (status < 0) |
| 313 | break; |
| 314 | status = write_reg(ci, 0x21, (reg >> 8) & 0xff); |
| 315 | if (status < 0) |
| 316 | break; |
| 317 | status = write_reg(ci, 0x22, reg & 0xff); |
| 318 | if (status < 0) |
| 319 | break; |
| 320 | } else if (ci->cfg.clock_mode == 1) { |
| 321 | if (ci->cfg.polarity) { |
| 322 | status = write_reg(ci, 0x09, 0x6f); /* D */ |
| 323 | if (status < 0) |
| 324 | break; |
| 325 | } else { |
| 326 | status = write_reg(ci, 0x09, 0x6d); |
| 327 | if (status < 0) |
| 328 | break; |
| 329 | } |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 330 | status = write_reg(ci, 0x20, 0x68); |
| 331 | if (status < 0) |
| 332 | break; |
| 333 | status = write_reg(ci, 0x21, 0x00); |
| 334 | if (status < 0) |
| 335 | break; |
| 336 | status = write_reg(ci, 0x22, 0x02); |
| 337 | if (status < 0) |
| 338 | break; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 339 | } else { |
| 340 | if (ci->cfg.polarity) { |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 341 | status = write_reg(ci, 0x09, 0x4f); /* C */ |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 342 | if (status < 0) |
| 343 | break; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 344 | } else { |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 345 | status = write_reg(ci, 0x09, 0x4d); |
| 346 | if (status < 0) |
| 347 | break; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 348 | } |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 349 | status = write_reg(ci, 0x20, 0x28); |
| 350 | if (status < 0) |
| 351 | break; |
| 352 | status = write_reg(ci, 0x21, 0x00); |
| 353 | if (status < 0) |
| 354 | break; |
| 355 | status = write_reg(ci, 0x22, 0x07); |
| 356 | if (status < 0) |
| 357 | break; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 358 | } |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 359 | |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 360 | status = write_regm(ci, 0x20, 0x80, 0x80); |
| 361 | if (status < 0) |
| 362 | break; |
| 363 | status = write_regm(ci, 0x03, 0x02, 0x02); |
| 364 | if (status < 0) |
| 365 | break; |
| 366 | status = write_reg(ci, 0x01, 0x04); |
| 367 | if (status < 0) |
| 368 | break; |
| 369 | status = write_reg(ci, 0x00, 0x31); |
| 370 | if (status < 0) |
| 371 | break; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 372 | |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 373 | /* Put TS in bypass */ |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 374 | status = write_regm(ci, 0x09, 0x08, 0x08); |
| 375 | if (status < 0) |
| 376 | break; |
Oliver Endriss | 9daf9bc | 2011-07-03 14:02:24 -0300 | [diff] [blame] | 377 | ci->cammode = -1; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 378 | cam_mode(ci, 0); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 379 | } while (0); |
| 380 | mutex_unlock(&ci->lock); |
| 381 | |
| 382 | return 0; |
| 383 | } |
| 384 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 385 | static int read_attribute_mem(struct dvb_ca_en50221 *ca, |
| 386 | int slot, int address) |
| 387 | { |
| 388 | struct cxd *ci = ca->data; |
| 389 | u8 val; |
Aybuke Ozdemir | fcf1b73 | 2014-09-18 00:54:04 +0300 | [diff] [blame] | 390 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 391 | mutex_lock(&ci->lock); |
| 392 | set_mode(ci, 1); |
| 393 | read_pccard(ci, address, &val, 1); |
| 394 | mutex_unlock(&ci->lock); |
| 395 | return val; |
| 396 | } |
| 397 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 398 | static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot, |
| 399 | int address, u8 value) |
| 400 | { |
| 401 | struct cxd *ci = ca->data; |
| 402 | |
| 403 | mutex_lock(&ci->lock); |
| 404 | set_mode(ci, 1); |
| 405 | write_pccard(ci, address, &value, 1); |
| 406 | mutex_unlock(&ci->lock); |
| 407 | return 0; |
| 408 | } |
| 409 | |
| 410 | static int read_cam_control(struct dvb_ca_en50221 *ca, |
| 411 | int slot, u8 address) |
| 412 | { |
| 413 | struct cxd *ci = ca->data; |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 414 | unsigned int val; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 415 | |
| 416 | mutex_lock(&ci->lock); |
| 417 | set_mode(ci, 0); |
| 418 | read_io(ci, address, &val); |
| 419 | mutex_unlock(&ci->lock); |
| 420 | return val; |
| 421 | } |
| 422 | |
| 423 | static int write_cam_control(struct dvb_ca_en50221 *ca, int slot, |
| 424 | u8 address, u8 value) |
| 425 | { |
| 426 | struct cxd *ci = ca->data; |
| 427 | |
| 428 | mutex_lock(&ci->lock); |
| 429 | set_mode(ci, 0); |
| 430 | write_io(ci, address, value); |
| 431 | mutex_unlock(&ci->lock); |
| 432 | return 0; |
| 433 | } |
| 434 | |
| 435 | static int slot_reset(struct dvb_ca_en50221 *ca, int slot) |
| 436 | { |
| 437 | struct cxd *ci = ca->data; |
| 438 | |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 439 | if (ci->cammode) |
| 440 | read_data(ca, slot, ci->rbuf, 0); |
| 441 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 442 | mutex_lock(&ci->lock); |
| 443 | cam_mode(ci, 0); |
| 444 | write_reg(ci, 0x00, 0x21); |
| 445 | write_reg(ci, 0x06, 0x1F); |
| 446 | write_reg(ci, 0x00, 0x31); |
| 447 | write_regm(ci, 0x20, 0x80, 0x80); |
| 448 | write_reg(ci, 0x03, 0x02); |
| 449 | ci->ready = 0; |
| 450 | ci->mode = -1; |
| 451 | { |
| 452 | int i; |
Tamara Diaconita | 1f9f72f | 2017-03-02 20:43:10 +0200 | [diff] [blame] | 453 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 454 | for (i = 0; i < 100; i++) { |
Tapasweni Pathak | c3cefd3 | 2014-10-08 11:17:28 +0530 | [diff] [blame] | 455 | usleep_range(10000, 11000); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 456 | if (ci->ready) |
| 457 | break; |
| 458 | } |
| 459 | } |
| 460 | mutex_unlock(&ci->lock); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 461 | return 0; |
| 462 | } |
| 463 | |
| 464 | static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot) |
| 465 | { |
| 466 | struct cxd *ci = ca->data; |
| 467 | |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 468 | dev_dbg(&ci->client->dev, "%s\n", __func__); |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 469 | if (ci->cammode) |
| 470 | read_data(ca, slot, ci->rbuf, 0); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 471 | mutex_lock(&ci->lock); |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 472 | write_reg(ci, 0x00, 0x21); |
| 473 | write_reg(ci, 0x06, 0x1F); |
| 474 | msleep(300); |
| 475 | |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 476 | write_regm(ci, 0x09, 0x08, 0x08); |
| 477 | write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */ |
| 478 | write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */ |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 479 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 480 | ci->mode = -1; |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 481 | ci->write_busy = 0; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 482 | mutex_unlock(&ci->lock); |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 483 | return 0; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 484 | } |
| 485 | |
| 486 | static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot) |
| 487 | { |
| 488 | struct cxd *ci = ca->data; |
| 489 | |
| 490 | mutex_lock(&ci->lock); |
| 491 | write_regm(ci, 0x09, 0x00, 0x08); |
| 492 | set_mode(ci, 0); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 493 | cam_mode(ci, 1); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 494 | mutex_unlock(&ci->lock); |
| 495 | return 0; |
| 496 | } |
| 497 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 498 | static int campoll(struct cxd *ci) |
| 499 | { |
| 500 | u8 istat; |
| 501 | |
| 502 | read_reg(ci, 0x04, &istat); |
| 503 | if (!istat) |
| 504 | return 0; |
| 505 | write_reg(ci, 0x05, istat); |
| 506 | |
Ralph Metzler | 64754837 | 2017-06-25 18:37:09 -0300 | [diff] [blame] | 507 | if (istat & 0x40) |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 508 | ci->dr = 1; |
Ralph Metzler | 64754837 | 2017-06-25 18:37:09 -0300 | [diff] [blame] | 509 | if (istat & 0x20) |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 510 | ci->write_busy = 0; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 511 | |
Tamara Diaconita | 03173b4 | 2017-03-02 20:41:26 +0200 | [diff] [blame] | 512 | if (istat & 2) { |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 513 | u8 slotstat; |
| 514 | |
| 515 | read_reg(ci, 0x01, &slotstat); |
Tamara Diaconita | 03173b4 | 2017-03-02 20:41:26 +0200 | [diff] [blame] | 516 | if (!(2 & slotstat)) { |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 517 | if (!ci->slot_stat) { |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 518 | ci->slot_stat |= |
| 519 | DVB_CA_EN50221_POLL_CAM_PRESENT; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 520 | write_regm(ci, 0x03, 0x08, 0x08); |
| 521 | } |
| 522 | |
| 523 | } else { |
| 524 | if (ci->slot_stat) { |
| 525 | ci->slot_stat = 0; |
| 526 | write_regm(ci, 0x03, 0x00, 0x08); |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 527 | dev_info(&ci->client->dev, "NO CAM\n"); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 528 | ci->ready = 0; |
| 529 | } |
| 530 | } |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 531 | if ((istat & 8) && |
Daniel Scheller | 65ac8c8 | 2017-12-12 13:46:55 -0500 | [diff] [blame] | 532 | ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT) { |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 533 | ci->ready = 1; |
| 534 | ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_READY; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 535 | } |
| 536 | } |
| 537 | return 0; |
| 538 | } |
| 539 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 540 | static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open) |
| 541 | { |
| 542 | struct cxd *ci = ca->data; |
| 543 | u8 slotstat; |
| 544 | |
| 545 | mutex_lock(&ci->lock); |
| 546 | campoll(ci); |
| 547 | read_reg(ci, 0x01, &slotstat); |
| 548 | mutex_unlock(&ci->lock); |
| 549 | |
| 550 | return ci->slot_stat; |
| 551 | } |
| 552 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 553 | static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount) |
| 554 | { |
| 555 | struct cxd *ci = ca->data; |
| 556 | u8 msb, lsb; |
| 557 | u16 len; |
| 558 | |
| 559 | mutex_lock(&ci->lock); |
| 560 | campoll(ci); |
| 561 | mutex_unlock(&ci->lock); |
| 562 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 563 | if (!ci->dr) |
| 564 | return 0; |
| 565 | |
| 566 | mutex_lock(&ci->lock); |
| 567 | read_reg(ci, 0x0f, &msb); |
| 568 | read_reg(ci, 0x10, &lsb); |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 569 | len = ((u16)msb << 8) | lsb; |
| 570 | if (len > ecount || len < 2) { |
| 571 | /* read it anyway or cxd may hang */ |
| 572 | read_block(ci, 0x12, ci->rbuf, len); |
| 573 | mutex_unlock(&ci->lock); |
| 574 | return -EIO; |
| 575 | } |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 576 | read_block(ci, 0x12, ebuf, len); |
| 577 | ci->dr = 0; |
| 578 | mutex_unlock(&ci->lock); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 579 | return len; |
| 580 | } |
| 581 | |
| 582 | static int write_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount) |
| 583 | { |
| 584 | struct cxd *ci = ca->data; |
| 585 | |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 586 | if (ci->write_busy) |
| 587 | return -EAGAIN; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 588 | mutex_lock(&ci->lock); |
Tamara Diaconita | 03173b4 | 2017-03-02 20:41:26 +0200 | [diff] [blame] | 589 | write_reg(ci, 0x0d, ecount >> 8); |
| 590 | write_reg(ci, 0x0e, ecount & 0xff); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 591 | write_block(ci, 0x11, ebuf, ecount); |
Ralph Metzler | dd3c5d0 | 2017-06-25 18:37:08 -0300 | [diff] [blame] | 592 | ci->write_busy = 1; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 593 | mutex_unlock(&ci->lock); |
| 594 | return ecount; |
| 595 | } |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 596 | |
| 597 | static struct dvb_ca_en50221 en_templ = { |
| 598 | .read_attribute_mem = read_attribute_mem, |
| 599 | .write_attribute_mem = write_attribute_mem, |
| 600 | .read_cam_control = read_cam_control, |
| 601 | .write_cam_control = write_cam_control, |
| 602 | .slot_reset = slot_reset, |
| 603 | .slot_shutdown = slot_shutdown, |
| 604 | .slot_ts_enable = slot_ts_enable, |
| 605 | .poll_slot_status = poll_slot_status, |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 606 | .read_data = read_data, |
| 607 | .write_data = write_data, |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 608 | }; |
| 609 | |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 610 | static int cxd2099_probe(struct i2c_client *client, |
| 611 | const struct i2c_device_id *id) |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 612 | { |
Devendra Naga | 4aff355 | 2012-08-04 14:12:03 -0300 | [diff] [blame] | 613 | struct cxd *ci; |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 614 | struct cxd2099_cfg *cfg = client->dev.platform_data; |
| 615 | static const struct regmap_config rm_cfg = { |
| 616 | .reg_bits = 8, |
| 617 | .val_bits = 8, |
| 618 | }; |
| 619 | unsigned int val; |
| 620 | int ret; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 621 | |
Tamara Diaconita | 783dd92 | 2017-03-02 20:42:52 +0200 | [diff] [blame] | 622 | ci = kzalloc(sizeof(*ci), GFP_KERNEL); |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 623 | if (!ci) { |
| 624 | ret = -ENOMEM; |
| 625 | goto err; |
| 626 | } |
| 627 | |
| 628 | ci->client = client; |
| 629 | memcpy(&ci->cfg, cfg, sizeof(ci->cfg)); |
| 630 | |
| 631 | ci->regmap = regmap_init_i2c(client, &rm_cfg); |
| 632 | if (IS_ERR(ci->regmap)) { |
| 633 | ret = PTR_ERR(ci->regmap); |
| 634 | goto err_kfree; |
| 635 | } |
| 636 | |
| 637 | ret = regmap_read(ci->regmap, 0x00, &val); |
| 638 | if (ret < 0) { |
| 639 | dev_info(&client->dev, "No CXD2099AR detected at 0x%02x\n", |
| 640 | client->addr); |
| 641 | goto err_rmexit; |
| 642 | } |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 643 | |
| 644 | mutex_init(&ci->lock); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 645 | ci->lastaddress = 0xff; |
| 646 | ci->clk_reg_b = 0x4a; |
| 647 | ci->clk_reg_f = 0x1b; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 648 | |
Devendra Naga | 8d9b258 | 2012-08-05 16:40:02 -0300 | [diff] [blame] | 649 | ci->en = en_templ; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 650 | ci->en.data = ci; |
| 651 | init(ci); |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 652 | dev_info(&client->dev, "Attached CXD2099AR at 0x%02x\n", client->addr); |
| 653 | |
| 654 | *cfg->en = &ci->en; |
Daniel Scheller | 2b64e4d | 2017-08-23 12:10:01 -0400 | [diff] [blame] | 655 | |
| 656 | if (!buffermode) { |
| 657 | ci->en.read_data = NULL; |
| 658 | ci->en.write_data = NULL; |
| 659 | } else { |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 660 | dev_info(&client->dev, "Using CXD2099AR buffer mode"); |
Daniel Scheller | 2b64e4d | 2017-08-23 12:10:01 -0400 | [diff] [blame] | 661 | } |
| 662 | |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 663 | i2c_set_clientdata(client, ci); |
| 664 | |
| 665 | return 0; |
| 666 | |
| 667 | err_rmexit: |
| 668 | regmap_exit(ci->regmap); |
| 669 | err_kfree: |
| 670 | kfree(ci); |
| 671 | err: |
| 672 | |
| 673 | return ret; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 674 | } |
Daniel Scheller | 81a7059 | 2018-02-17 10:03:23 -0500 | [diff] [blame] | 675 | |
| 676 | static int cxd2099_remove(struct i2c_client *client) |
| 677 | { |
| 678 | struct cxd *ci = i2c_get_clientdata(client); |
| 679 | |
| 680 | regmap_exit(ci->regmap); |
| 681 | kfree(ci); |
| 682 | |
| 683 | return 0; |
| 684 | } |
| 685 | |
| 686 | static const struct i2c_device_id cxd2099_id[] = { |
| 687 | {"cxd2099", 0}, |
| 688 | {} |
| 689 | }; |
| 690 | MODULE_DEVICE_TABLE(i2c, cxd2099_id); |
| 691 | |
| 692 | static struct i2c_driver cxd2099_driver = { |
| 693 | .driver = { |
| 694 | .name = "cxd2099", |
| 695 | }, |
| 696 | .probe = cxd2099_probe, |
| 697 | .remove = cxd2099_remove, |
| 698 | .id_table = cxd2099_id, |
| 699 | }; |
| 700 | |
| 701 | module_i2c_driver(cxd2099_driver); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 702 | |
Daniel Scheller | 2dc3e05 | 2018-03-17 10:55:32 -0400 | [diff] [blame] | 703 | MODULE_DESCRIPTION("Sony CXD2099AR Common Interface controller driver"); |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 704 | MODULE_AUTHOR("Ralph Metzler"); |
Daniel Scheller | 579856f | 2018-06-19 14:51:17 -0400 | [diff] [blame] | 705 | MODULE_LICENSE("GPL v2"); |