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git.odroid.com / yocto / kernel / common / c942fddf8793b2013be8c901b47d0a8dc02bf99f / . / drivers / media / dvb-frontends / drxd_firm.h
blob: 7d9f9fa7ab3ce2151cd20fc6a795df2c425c8dad [file] [log] [blame]
Ralph Metzler126f1e62011-03-12 23:44:33 -0500[diff] [blame]1/*
2 * drxd_firm.h
3 *
4 * Copyright (C) 2006-2007 Micronas
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
Sakari Ailusbcb63312016-10-28 09:31:20 -0200[diff] [blame]16 * To obtain the license, point your browser to
17 * http://www.gnu.org/copyleft/gpl.html
Ralph Metzler126f1e62011-03-12 23:44:33 -0500[diff] [blame]18 */
19
20#ifndef _DRXD_FIRM_H_
21#define _DRXD_FIRM_H_
22
Mauro Carvalho Chehabbccd2d82011-03-25 10:46:32 -0300[diff] [blame]23#include <linux/types.h>
Ralph Metzler126f1e62011-03-12 23:44:33 -0500[diff] [blame]24#include "drxd_map_firm.h"
25
Ralph Metzler126f1e62011-03-12 23:44:33 -0500[diff] [blame]26#define VERSION_MAJOR 1
27#define VERSION_MINOR 4
28#define VERSION_PATCH 23
29
30#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
31
32#define DRXD_MAX_RETRIES (1000)
33#define HI_I2C_DELAY 84
34#define HI_I2C_BRIDGE_DELAY 750
35
Devin Heitmueller6cacdd42011-03-24 13:44:01 -0300[diff] [blame]36#define EQ_TD_TPS_PWR_UNKNOWN 0x00C0 /* Unknown configurations */
Ralph Metzler126f1e62011-03-12 23:44:33 -0500[diff] [blame]37#define EQ_TD_TPS_PWR_QPSK 0x016a
38#define EQ_TD_TPS_PWR_QAM16_ALPHAN 0x0195
39#define EQ_TD_TPS_PWR_QAM16_ALPHA1 0x0195
40#define EQ_TD_TPS_PWR_QAM16_ALPHA2 0x011E
41#define EQ_TD_TPS_PWR_QAM16_ALPHA4 0x01CE
42#define EQ_TD_TPS_PWR_QAM64_ALPHAN 0x019F
43#define EQ_TD_TPS_PWR_QAM64_ALPHA1 0x019F
44#define EQ_TD_TPS_PWR_QAM64_ALPHA2 0x00F8
45#define EQ_TD_TPS_PWR_QAM64_ALPHA4 0x014D
46
47#define DRXD_DEF_AG_PWD_CONSUMER 0x000E
48#define DRXD_DEF_AG_PWD_PRO 0x0000
49#define DRXD_DEF_AG_AGC_SIO 0x0000
50
51#define DRXD_FE_CTRL_MAX 1023
52
53#define DRXD_OSCDEV_DO_SCAN (16)
54
55#define DRXD_OSCDEV_DONT_SCAN (0)
56
57#define DRXD_OSCDEV_STEP (275)
58
59#define DRXD_SCAN_TIMEOUT (650)
60
Ralph Metzler126f1e62011-03-12 23:44:33 -0500[diff] [blame]61#define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
62#define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
63#define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
64
65#define IRLEN_COARSE_8K (10)
66#define IRLEN_FINE_8K (10)
67#define IRLEN_COARSE_2K (7)
68#define IRLEN_FINE_2K (9)
69#define DIFF_INVALID (511)
70#define DIFF_TARGET (4)
71#define DIFF_MARGIN (1)
72
Mauro Carvalho Chehabbccd2d82011-03-25 10:46:32 -0300[diff] [blame]73extern u8 DRXD_InitAtomicRead[];
74extern u8 DRXD_HiI2cPatch_1[];
75extern u8 DRXD_HiI2cPatch_3[];
Ralph Metzler126f1e62011-03-12 23:44:33 -0500[diff] [blame]76
Mauro Carvalho Chehabbccd2d82011-03-25 10:46:32 -0300[diff] [blame]77extern u8 DRXD_InitSC[];
Ralph Metzler126f1e62011-03-12 23:44:33 -0500[diff] [blame]78
Mauro Carvalho Chehabbccd2d82011-03-25 10:46:32 -0300[diff] [blame]79extern u8 DRXD_ResetCEFR[];
80extern u8 DRXD_InitFEA2_1[];
81extern u8 DRXD_InitFEA2_2[];
82extern u8 DRXD_InitCPA2[];
83extern u8 DRXD_InitCEA2[];
84extern u8 DRXD_InitEQA2[];
85extern u8 DRXD_InitECA2[];
86extern u8 DRXD_ResetECA2[];
87extern u8 DRXD_ResetECRAM[];
Ralph Metzler126f1e62011-03-12 23:44:33 -0500[diff] [blame]88
Mauro Carvalho Chehabbccd2d82011-03-25 10:46:32 -0300[diff] [blame]89extern u8 DRXD_A2_microcode[];
90extern u32 DRXD_A2_microcode_length;
Ralph Metzler126f1e62011-03-12 23:44:33 -0500[diff] [blame]91
Mauro Carvalho Chehabbccd2d82011-03-25 10:46:32 -0300[diff] [blame]92extern u8 DRXD_InitFEB1_1[];
93extern u8 DRXD_InitFEB1_2[];
94extern u8 DRXD_InitCPB1[];
95extern u8 DRXD_InitCEB1[];
96extern u8 DRXD_InitEQB1[];
97extern u8 DRXD_InitECB1[];
Ralph Metzler126f1e62011-03-12 23:44:33 -0500[diff] [blame]98
Mauro Carvalho Chehabbccd2d82011-03-25 10:46:32 -0300[diff] [blame]99extern u8 DRXD_InitDiversityFront[];
100extern u8 DRXD_InitDiversityEnd[];
101extern u8 DRXD_DisableDiversity[];
102extern u8 DRXD_StartDiversityFront[];
103extern u8 DRXD_StartDiversityEnd[];
Ralph Metzler126f1e62011-03-12 23:44:33 -0500[diff] [blame]104
Mauro Carvalho Chehabbccd2d82011-03-25 10:46:32 -0300[diff] [blame]105extern u8 DRXD_DiversityDelay8MHZ[];
106extern u8 DRXD_DiversityDelay6MHZ[];
Ralph Metzler126f1e62011-03-12 23:44:33 -0500[diff] [blame]107
Mauro Carvalho Chehabbccd2d82011-03-25 10:46:32 -0300[diff] [blame]108extern u8 DRXD_B1_microcode[];
109extern u32 DRXD_B1_microcode_length;
Ralph Metzler126f1e62011-03-12 23:44:33 -0500[diff] [blame]110
111#endif