blob: 967ae29390997cf21d8f255e9625df62bcfbfb34 [file] [log] [blame]
Thomas Gleixnerc942fdd2019-05-27 08:55:06 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Hans Verkuil1c1e45d2008-04-28 20:24:33 -03002/*
3 * cx18 mailbox functions
4 *
5 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
Andy Walls6afdeaf2010-05-23 18:53:35 -03006 * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net>
Hans Verkuil1c1e45d2008-04-28 20:24:33 -03007 */
8
9#include <stdarg.h>
10
11#include "cx18-driver.h"
Andy Wallsb1526422008-08-30 16:03:44 -030012#include "cx18-io.h"
Hans Verkuil1c1e45d2008-04-28 20:24:33 -030013#include "cx18-scb.h"
14#include "cx18-irq.h"
15#include "cx18-mailbox.h"
Andy Wallsee2d64f2008-11-16 01:38:19 -030016#include "cx18-queue.h"
17#include "cx18-streams.h"
Devin Heitmueller9972de92010-01-18 21:29:51 -030018#include "cx18-alsa-pcm.h" /* FIXME make configurable */
Andy Wallsee2d64f2008-11-16 01:38:19 -030019
20static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" };
Hans Verkuil1c1e45d2008-04-28 20:24:33 -030021
22#define API_FAST (1 << 2) /* Short timeout */
23#define API_SLOW (1 << 3) /* Additional 300ms timeout */
24
Hans Verkuil1c1e45d2008-04-28 20:24:33 -030025struct cx18_api_info {
26 u32 cmd;
27 u8 flags; /* Flags, see above */
28 u8 rpu; /* Processing unit */
Mauro Carvalho Chehab6e6a8b52018-01-04 13:08:56 -050029 const char *name; /* The name of the command */
Hans Verkuil1c1e45d2008-04-28 20:24:33 -030030};
31
32#define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x }
33
34static const struct cx18_api_info api_info[] = {
35 /* MPEG encoder API */
36 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
Mauro Carvalho Chehab6e6a8b52018-01-04 13:08:56 -050037 API_ENTRY(CPU, CX18_EPU_DEBUG, 0),
38 API_ENTRY(CPU, CX18_CREATE_TASK, 0),
39 API_ENTRY(CPU, CX18_DESTROY_TASK, 0),
Hans Verkuil1c1e45d2008-04-28 20:24:33 -030040 API_ENTRY(CPU, CX18_CPU_CAPTURE_START, API_SLOW),
41 API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP, API_SLOW),
42 API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE, 0),
43 API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME, 0),
44 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
45 API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 0),
46 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_IN, 0),
47 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RATE, 0),
48 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RESOLUTION, 0),
49 API_ENTRY(CPU, CX18_CPU_SET_FILTER_PARAM, 0),
50 API_ENTRY(CPU, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 0),
51 API_ENTRY(CPU, CX18_CPU_SET_MEDIAN_CORING, 0),
52 API_ENTRY(CPU, CX18_CPU_SET_INDEXTABLE, 0),
53 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PARAMETERS, 0),
54 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_MUTE, 0),
55 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_MUTE, 0),
56 API_ENTRY(CPU, CX18_CPU_SET_MISC_PARAMETERS, 0),
57 API_ENTRY(CPU, CX18_CPU_SET_RAW_VBI_PARAM, API_SLOW),
58 API_ENTRY(CPU, CX18_CPU_SET_CAPTURE_LINE_NO, 0),
59 API_ENTRY(CPU, CX18_CPU_SET_COPYRIGHT, 0),
60 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PID, 0),
61 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_PID, 0),
62 API_ENTRY(CPU, CX18_CPU_SET_VER_CROP_LINE, 0),
63 API_ENTRY(CPU, CX18_CPU_SET_GOP_STRUCTURE, 0),
64 API_ENTRY(CPU, CX18_CPU_SET_SCENE_CHANGE_DETECTION, 0),
65 API_ENTRY(CPU, CX18_CPU_SET_ASPECT_RATIO, 0),
66 API_ENTRY(CPU, CX18_CPU_SET_SKIP_INPUT_FRAME, 0),
67 API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM, 0),
68 API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER, 0),
69 API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS, 0),
Steven Tothb7101de2011-04-06 08:32:56 -030070 API_ENTRY(CPU, CX18_CPU_SET_VFC_PARAM, 0),
Hans Verkuil1c1e45d2008-04-28 20:24:33 -030071 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0),
72 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST),
Andy Walls4e6b6102008-11-01 01:07:36 -030073 API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, API_SLOW),
Andy Walls350145a2009-01-04 21:51:17 -030074 API_ENTRY(APU, CX18_APU_START, 0),
75 API_ENTRY(APU, CX18_APU_STOP, 0),
Andy Wallsfd6b9c92008-12-14 21:26:25 -030076 API_ENTRY(APU, CX18_APU_RESETAI, 0),
77 API_ENTRY(CPU, CX18_CPU_DEBUG_PEEK32, 0),
Hans Verkuil1c1e45d2008-04-28 20:24:33 -030078 API_ENTRY(0, 0, 0),
79};
80
81static const struct cx18_api_info *find_api_info(u32 cmd)
82{
83 int i;
84
85 for (i = 0; api_info[i].cmd; i++)
86 if (api_info[i].cmd == cmd)
87 return &api_info[i];
88 return NULL;
89}
90
Andy Walls50299992009-01-01 12:35:06 -030091/* Call with buf of n*11+1 bytes */
92static char *u32arr2hex(u32 data[], int n, char *buf)
93{
94 char *p;
95 int i;
96
97 for (i = 0, p = buf; i < n; i++, p += 11) {
98 /* kernel snprintf() appends '\0' always */
99 snprintf(p, 12, " %#010x", data[i]);
100 }
101 *p = '\0';
102 return buf;
103}
104
Andy Wallsee2d64f2008-11-16 01:38:19 -0300105static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name)
106{
107 char argstr[MAX_MB_ARGUMENTS*11+1];
Andy Wallsee2d64f2008-11-16 01:38:19 -0300108
109 if (!(cx18_debug & CX18_DBGFLG_API))
110 return;
111
Mauro Carvalho Chehab6beb1382016-10-18 17:44:03 -0200112 CX18_DEBUG_API("%s: req %#010x ack %#010x cmd %#010x err %#010x args%s\n",
113 name, mb->request, mb->ack, mb->cmd, mb->error,
Andy Walls50299992009-01-01 12:35:06 -0300114 u32arr2hex(mb->args, MAX_MB_ARGUMENTS, argstr));
Andy Wallsee2d64f2008-11-16 01:38:19 -0300115}
116
117
118/*
119 * Functions that run in a work_queue work handling context
120 */
121
Andy Walls52fcb3e2009-11-08 23:45:24 -0300122static void cx18_mdl_send_to_dvb(struct cx18_stream *s, struct cx18_mdl *mdl)
123{
124 struct cx18_buffer *buf;
125
Andy Walls754f9962010-12-11 20:38:20 -0300126 if (s->dvb == NULL || !s->dvb->enabled || mdl->bytesused == 0)
Andy Walls52fcb3e2009-11-08 23:45:24 -0300127 return;
128
129 /* We ignore mdl and buf readpos accounting here - it doesn't matter */
130
131 /* The likely case */
132 if (list_is_singular(&mdl->buf_list)) {
133 buf = list_first_entry(&mdl->buf_list, struct cx18_buffer,
134 list);
135 if (buf->bytesused)
Andy Walls754f9962010-12-11 20:38:20 -0300136 dvb_dmx_swfilter(&s->dvb->demux,
Andy Walls52fcb3e2009-11-08 23:45:24 -0300137 buf->buf, buf->bytesused);
138 return;
139 }
140
141 list_for_each_entry(buf, &mdl->buf_list, list) {
142 if (buf->bytesused == 0)
143 break;
Andy Walls754f9962010-12-11 20:38:20 -0300144 dvb_dmx_swfilter(&s->dvb->demux, buf->buf, buf->bytesused);
Andy Walls52fcb3e2009-11-08 23:45:24 -0300145 }
146}
147
Steven Tothb7101de2011-04-06 08:32:56 -0300148static void cx18_mdl_send_to_videobuf(struct cx18_stream *s,
149 struct cx18_mdl *mdl)
150{
151 struct cx18_videobuf_buffer *vb_buf;
152 struct cx18_buffer *buf;
Simon Farnsworthbea3c542011-05-05 09:42:36 -0300153 u8 *p;
Steven Tothb7101de2011-04-06 08:32:56 -0300154 u32 offset = 0;
155 int dispatch = 0;
Steven Tothb7101de2011-04-06 08:32:56 -0300156
157 if (mdl->bytesused == 0)
158 return;
159
160 /* Acquire a videobuf buffer, clone to and and release it */
161 spin_lock(&s->vb_lock);
162 if (list_empty(&s->vb_capture))
163 goto out;
164
Simon Farnsworth1bf58422011-05-03 08:57:40 -0300165 vb_buf = list_first_entry(&s->vb_capture, struct cx18_videobuf_buffer,
Steven Tothb7101de2011-04-06 08:32:56 -0300166 vb.queue);
167
168 p = videobuf_to_vmalloc(&vb_buf->vb);
169 if (!p)
170 goto out;
171
172 offset = vb_buf->bytes_used;
173 list_for_each_entry(buf, &mdl->buf_list, list) {
174 if (buf->bytesused == 0)
175 break;
176
177 if ((offset + buf->bytesused) <= vb_buf->vb.bsize) {
178 memcpy(p + offset, buf->buf, buf->bytesused);
179 offset += buf->bytesused;
180 vb_buf->bytes_used += buf->bytesused;
181 }
182 }
183
184 /* If we've filled the buffer as per the callers res then dispatch it */
Simon Farnsworth09fc9802011-09-05 12:23:12 -0300185 if (vb_buf->bytes_used >= s->vb_bytes_per_frame) {
Steven Tothb7101de2011-04-06 08:32:56 -0300186 dispatch = 1;
187 vb_buf->bytes_used = 0;
188 }
189
Steven Tothb7101de2011-04-06 08:32:56 -0300190 if (dispatch) {
Hans Verkuil15a40b22019-01-21 08:32:23 -0500191 vb_buf->vb.ts = ktime_get_ns();
Steven Tothb7101de2011-04-06 08:32:56 -0300192 list_del(&vb_buf->vb.queue);
193 vb_buf->vb.state = VIDEOBUF_DONE;
194 wake_up(&vb_buf->vb.done);
195 }
196
Simon Farnsworth1bf58422011-05-03 08:57:40 -0300197 mod_timer(&s->vb_timeout, msecs_to_jiffies(2000) + jiffies);
Steven Tothb7101de2011-04-06 08:32:56 -0300198
199out:
200 spin_unlock(&s->vb_lock);
201}
Devin Heitmueller9972de92010-01-18 21:29:51 -0300202
203static void cx18_mdl_send_to_alsa(struct cx18 *cx, struct cx18_stream *s,
204 struct cx18_mdl *mdl)
205{
206 struct cx18_buffer *buf;
207
208 if (mdl->bytesused == 0)
209 return;
210
211 /* We ignore mdl and buf readpos accounting here - it doesn't matter */
212
213 /* The likely case */
214 if (list_is_singular(&mdl->buf_list)) {
215 buf = list_first_entry(&mdl->buf_list, struct cx18_buffer,
216 list);
217 if (buf->bytesused)
218 cx->pcm_announce_callback(cx->alsa, buf->buf,
219 buf->bytesused);
220 return;
221 }
222
223 list_for_each_entry(buf, &mdl->buf_list, list) {
224 if (buf->bytesused == 0)
225 break;
226 cx->pcm_announce_callback(cx->alsa, buf->buf, buf->bytesused);
227 }
228}
229
Andy Wallsdeed75e2009-04-13 22:22:40 -0300230static void epu_dma_done(struct cx18 *cx, struct cx18_in_work_order *order)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300231{
Andy Wallsbca11a52008-11-19 01:24:33 -0300232 u32 handle, mdl_ack_count, id;
Andy Wallsee2d64f2008-11-16 01:38:19 -0300233 struct cx18_mailbox *mb;
234 struct cx18_mdl_ack *mdl_ack;
235 struct cx18_stream *s;
Andy Walls52fcb3e2009-11-08 23:45:24 -0300236 struct cx18_mdl *mdl;
Andy Wallsee2d64f2008-11-16 01:38:19 -0300237 int i;
238
239 mb = &order->mb;
240 handle = mb->args[0];
241 s = cx18_handle_to_stream(cx, handle);
242
243 if (s == NULL) {
Mauro Carvalho Chehab6beb1382016-10-18 17:44:03 -0200244 CX18_WARN("Got DMA done notification for unknown/inactive handle %d, %s mailbox seq no %d\n",
245 handle,
Andy Wallsbca11a52008-11-19 01:24:33 -0300246 (order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) ?
247 "stale" : "good", mb->request);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300248 return;
249 }
250
251 mdl_ack_count = mb->args[2];
252 mdl_ack = order->mdl_ack;
253 for (i = 0; i < mdl_ack_count; i++, mdl_ack++) {
Andy Wallsbca11a52008-11-19 01:24:33 -0300254 id = mdl_ack->id;
255 /*
256 * Simple integrity check for processing a stale (and possibly
Andy Walls52fcb3e2009-11-08 23:45:24 -0300257 * inconsistent mailbox): make sure the MDL id is in the
Andy Wallsbca11a52008-11-19 01:24:33 -0300258 * valid range for the stream.
259 *
260 * We go through the trouble of dealing with stale mailboxes
261 * because most of the time, the mailbox data is still valid and
262 * unchanged (and in practice the firmware ping-pongs the
263 * two mdl_ack buffers so mdl_acks are not stale).
264 *
265 * There are occasions when we get a half changed mailbox,
266 * which this check catches for a handle & id mismatch. If the
267 * handle and id do correspond, the worst case is that we
Andy Walls52fcb3e2009-11-08 23:45:24 -0300268 * completely lost the old MDL, but pick up the new MDL
Andy Wallsbca11a52008-11-19 01:24:33 -0300269 * early (but the new mdl_ack is guaranteed to be good in this
270 * case as the firmware wouldn't point us to a new mdl_ack until
271 * it's filled in).
272 *
Andy Walls52fcb3e2009-11-08 23:45:24 -0300273 * cx18_queue_get_mdl() will detect the lost MDLs
Andy Wallsabb096d2008-12-12 15:50:27 -0300274 * and send them back to q_free for fw rotation eventually.
Andy Wallsbca11a52008-11-19 01:24:33 -0300275 */
276 if ((order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) &&
Andy Wallsfa655dd2009-11-05 21:51:24 -0300277 !(id >= s->mdl_base_idx &&
278 id < (s->mdl_base_idx + s->buffers))) {
Mauro Carvalho Chehab6beb1382016-10-18 17:44:03 -0200279 CX18_WARN("Fell behind! Ignoring stale mailbox with inconsistent data. Lost MDL for mailbox seq no %d\n",
280 mb->request);
Andy Wallsbca11a52008-11-19 01:24:33 -0300281 break;
282 }
Andy Walls52fcb3e2009-11-08 23:45:24 -0300283 mdl = cx18_queue_get_mdl(s, id, mdl_ack->data_used);
Andy Wallsabb096d2008-12-12 15:50:27 -0300284
Andy Walls52fcb3e2009-11-08 23:45:24 -0300285 CX18_DEBUG_HI_DMA("DMA DONE for %s (MDL %d)\n", s->name, id);
286 if (mdl == NULL) {
287 CX18_WARN("Could not find MDL %d for stream %s\n",
Andy Wallsbca11a52008-11-19 01:24:33 -0300288 id, s->name);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300289 continue;
290 }
291
Andy Walls40c55202009-04-13 23:08:00 -0300292 CX18_DEBUG_HI_DMA("%s recv bytesused = %d\n",
Andy Walls52fcb3e2009-11-08 23:45:24 -0300293 s->name, mdl->bytesused);
Andy Walls40c55202009-04-13 23:08:00 -0300294
Devin Heitmueller9972de92010-01-18 21:29:51 -0300295 if (s->type == CX18_ENC_STREAM_TYPE_TS) {
296 cx18_mdl_send_to_dvb(s, mdl);
297 cx18_enqueue(s, mdl, &s->q_free);
298 } else if (s->type == CX18_ENC_STREAM_TYPE_PCM) {
299 /* Pass the data to cx18-alsa */
300 if (cx->pcm_announce_callback != NULL) {
301 cx18_mdl_send_to_alsa(cx, s, mdl);
302 cx18_enqueue(s, mdl, &s->q_free);
303 } else {
304 cx18_enqueue(s, mdl, &s->q_full);
305 }
Steven Tothb7101de2011-04-06 08:32:56 -0300306 } else if (s->type == CX18_ENC_STREAM_TYPE_YUV) {
307 cx18_mdl_send_to_videobuf(s, mdl);
308 cx18_enqueue(s, mdl, &s->q_free);
Devin Heitmueller9972de92010-01-18 21:29:51 -0300309 } else {
Andy Walls52fcb3e2009-11-08 23:45:24 -0300310 cx18_enqueue(s, mdl, &s->q_full);
Andy Wallsef9917972009-12-31 18:27:13 -0300311 if (s->type == CX18_ENC_STREAM_TYPE_IDX)
312 cx18_stream_rotate_idx_mdls(cx);
313 }
Andy Wallsee2d64f2008-11-16 01:38:19 -0300314 }
Andy Walls52fcb3e2009-11-08 23:45:24 -0300315 /* Put as many MDLs as possible back into fw use */
Andy Walls40c55202009-04-13 23:08:00 -0300316 cx18_stream_load_fw_queue(s);
317
Andy Wallsee2d64f2008-11-16 01:38:19 -0300318 wake_up(&cx->dma_waitq);
319 if (s->id != -1)
320 wake_up(&s->waitq);
321}
322
Andy Wallsdeed75e2009-04-13 22:22:40 -0300323static void epu_debug(struct cx18 *cx, struct cx18_in_work_order *order)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300324{
325 char *p;
326 char *str = order->str;
327
328 CX18_DEBUG_INFO("%x %s\n", order->mb.args[0], str);
329 p = strchr(str, '.');
330 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str)
331 CX18_INFO("FW version: %s\n", p - 1);
332}
333
Andy Wallsdeed75e2009-04-13 22:22:40 -0300334static void epu_cmd(struct cx18 *cx, struct cx18_in_work_order *order)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300335{
336 switch (order->rpu) {
337 case CPU:
338 {
339 switch (order->mb.cmd) {
340 case CX18_EPU_DMA_DONE:
341 epu_dma_done(cx, order);
342 break;
343 case CX18_EPU_DEBUG:
344 epu_debug(cx, order);
345 break;
346 default:
347 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
348 order->mb.cmd);
349 break;
350 }
351 break;
352 }
353 case APU:
354 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
355 order->mb.cmd);
356 break;
357 default:
358 break;
359 }
360}
361
362static
Andy Wallsdeed75e2009-04-13 22:22:40 -0300363void free_in_work_order(struct cx18 *cx, struct cx18_in_work_order *order)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300364{
365 atomic_set(&order->pending, 0);
366}
367
Andy Wallsdeed75e2009-04-13 22:22:40 -0300368void cx18_in_work_handler(struct work_struct *work)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300369{
Andy Wallsdeed75e2009-04-13 22:22:40 -0300370 struct cx18_in_work_order *order =
371 container_of(work, struct cx18_in_work_order, work);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300372 struct cx18 *cx = order->cx;
373 epu_cmd(cx, order);
Andy Wallsdeed75e2009-04-13 22:22:40 -0300374 free_in_work_order(cx, order);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300375}
376
377
378/*
379 * Functions that run in an interrupt handling context
380 */
381
Andy Wallsdeed75e2009-04-13 22:22:40 -0300382static void mb_ack_irq(struct cx18 *cx, struct cx18_in_work_order *order)
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300383{
Al Viro990c81c2008-05-21 00:32:01 -0300384 struct cx18_mailbox __iomem *ack_mb;
Andy Wallsee2d64f2008-11-16 01:38:19 -0300385 u32 ack_irq, req;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300386
Andy Wallsee2d64f2008-11-16 01:38:19 -0300387 switch (order->rpu) {
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300388 case APU:
389 ack_irq = IRQ_EPU_TO_APU_ACK;
390 ack_mb = &cx->scb->apu2epu_mb;
391 break;
392 case CPU:
393 ack_irq = IRQ_EPU_TO_CPU_ACK;
394 ack_mb = &cx->scb->cpu2epu_mb;
395 break;
396 default:
Andy Walls72c2d6d2008-11-06 01:15:41 -0300397 CX18_WARN("Unhandled RPU (%d) for command %x ack\n",
Andy Wallsee2d64f2008-11-16 01:38:19 -0300398 order->rpu, order->mb.cmd);
399 return;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300400 }
401
Andy Wallsee2d64f2008-11-16 01:38:19 -0300402 req = order->mb.request;
403 /* Don't ack if the RPU has gotten impatient and timed us out */
404 if (req != cx18_readl(cx, &ack_mb->request) ||
Andy Walls72a4f802008-11-16 21:18:00 -0300405 req == cx18_readl(cx, &ack_mb->ack)) {
Mauro Carvalho Chehab6beb1382016-10-18 17:44:03 -0200406 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our incoming %s to EPU mailbox (sequence no. %u) while processing\n",
Andy Wallsbca11a52008-11-19 01:24:33 -0300407 rpu_str[order->rpu], rpu_str[order->rpu], req);
Andy Walls72a4f802008-11-16 21:18:00 -0300408 order->flags |= CX18_F_EWO_MB_STALE_WHILE_PROC;
Andy Wallsee2d64f2008-11-16 01:38:19 -0300409 return;
Andy Walls72a4f802008-11-16 21:18:00 -0300410 }
Andy Wallsee2d64f2008-11-16 01:38:19 -0300411 cx18_writel(cx, req, &ack_mb->ack);
Andy Wallsf056d292008-10-31 20:49:12 -0300412 cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300413 return;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300414}
415
Andy Wallsdeed75e2009-04-13 22:22:40 -0300416static int epu_dma_done_irq(struct cx18 *cx, struct cx18_in_work_order *order)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300417{
418 u32 handle, mdl_ack_offset, mdl_ack_count;
419 struct cx18_mailbox *mb;
Hans Verkuil42d0c3a2012-05-26 08:07:03 -0300420 int i;
Andy Wallsee2d64f2008-11-16 01:38:19 -0300421
422 mb = &order->mb;
423 handle = mb->args[0];
424 mdl_ack_offset = mb->args[1];
425 mdl_ack_count = mb->args[2];
426
427 if (handle == CX18_INVALID_TASK_HANDLE ||
428 mdl_ack_count == 0 || mdl_ack_count > CX18_MAX_MDL_ACKS) {
Andy Walls72a4f802008-11-16 21:18:00 -0300429 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300430 mb_ack_irq(cx, order);
431 return -1;
432 }
433
Hans Verkuil42d0c3a2012-05-26 08:07:03 -0300434 for (i = 0; i < sizeof(struct cx18_mdl_ack) * mdl_ack_count; i += sizeof(u32))
435 ((u32 *)order->mdl_ack)[i / sizeof(u32)] =
436 cx18_readl(cx, cx->enc_mem + mdl_ack_offset + i);
Andy Walls72a4f802008-11-16 21:18:00 -0300437
438 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300439 mb_ack_irq(cx, order);
440 return 1;
441}
442
443static
Andy Wallsdeed75e2009-04-13 22:22:40 -0300444int epu_debug_irq(struct cx18 *cx, struct cx18_in_work_order *order)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300445{
446 u32 str_offset;
447 char *str = order->str;
448
449 str[0] = '\0';
450 str_offset = order->mb.args[1];
451 if (str_offset) {
452 cx18_setup_page(cx, str_offset);
453 cx18_memcpy_fromio(cx, str, cx->enc_mem + str_offset, 252);
454 str[252] = '\0';
455 cx18_setup_page(cx, SCB_OFFSET);
456 }
457
Andy Walls72a4f802008-11-16 21:18:00 -0300458 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300459 mb_ack_irq(cx, order);
460
461 return str_offset ? 1 : 0;
462}
463
464static inline
Andy Wallsdeed75e2009-04-13 22:22:40 -0300465int epu_cmd_irq(struct cx18 *cx, struct cx18_in_work_order *order)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300466{
467 int ret = -1;
468
469 switch (order->rpu) {
470 case CPU:
471 {
472 switch (order->mb.cmd) {
473 case CX18_EPU_DMA_DONE:
Andy Walls72a4f802008-11-16 21:18:00 -0300474 ret = epu_dma_done_irq(cx, order);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300475 break;
476 case CX18_EPU_DEBUG:
Andy Walls72a4f802008-11-16 21:18:00 -0300477 ret = epu_debug_irq(cx, order);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300478 break;
479 default:
480 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
481 order->mb.cmd);
482 break;
483 }
484 break;
485 }
486 case APU:
487 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
488 order->mb.cmd);
489 break;
490 default:
491 break;
492 }
493 return ret;
494}
495
496static inline
Andy Wallsdeed75e2009-04-13 22:22:40 -0300497struct cx18_in_work_order *alloc_in_work_order_irq(struct cx18 *cx)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300498{
499 int i;
Andy Wallsdeed75e2009-04-13 22:22:40 -0300500 struct cx18_in_work_order *order = NULL;
Andy Wallsee2d64f2008-11-16 01:38:19 -0300501
Andy Wallsdeed75e2009-04-13 22:22:40 -0300502 for (i = 0; i < CX18_MAX_IN_WORK_ORDERS; i++) {
Andy Wallsee2d64f2008-11-16 01:38:19 -0300503 /*
504 * We only need "pending" atomic to inspect its contents,
505 * and need not do a check and set because:
506 * 1. Any work handler thread only clears "pending" and only
507 * on one, particular work order at a time, per handler thread.
508 * 2. "pending" is only set here, and we're serialized because
509 * we're called in an IRQ handler context.
510 */
Andy Wallsdeed75e2009-04-13 22:22:40 -0300511 if (atomic_read(&cx->in_work_order[i].pending) == 0) {
512 order = &cx->in_work_order[i];
Andy Wallsee2d64f2008-11-16 01:38:19 -0300513 atomic_set(&order->pending, 1);
514 break;
515 }
516 }
517 return order;
518}
519
520void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
521{
522 struct cx18_mailbox __iomem *mb;
523 struct cx18_mailbox *order_mb;
Andy Wallsdeed75e2009-04-13 22:22:40 -0300524 struct cx18_in_work_order *order;
Andy Wallsee2d64f2008-11-16 01:38:19 -0300525 int submit;
Hans Verkuil42d0c3a2012-05-26 08:07:03 -0300526 int i;
Andy Wallsee2d64f2008-11-16 01:38:19 -0300527
528 switch (rpu) {
529 case CPU:
530 mb = &cx->scb->cpu2epu_mb;
531 break;
532 case APU:
533 mb = &cx->scb->apu2epu_mb;
534 break;
535 default:
536 return;
537 }
538
Andy Wallsdeed75e2009-04-13 22:22:40 -0300539 order = alloc_in_work_order_irq(cx);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300540 if (order == NULL) {
Mauro Carvalho Chehab6beb1382016-10-18 17:44:03 -0200541 CX18_WARN("Unable to find blank work order form to schedule incoming mailbox command processing\n");
Andy Wallsee2d64f2008-11-16 01:38:19 -0300542 return;
543 }
544
Andy Walls72a4f802008-11-16 21:18:00 -0300545 order->flags = 0;
Andy Wallsee2d64f2008-11-16 01:38:19 -0300546 order->rpu = rpu;
547 order_mb = &order->mb;
Andy Wallsd6c7e5f2008-11-17 22:48:46 -0300548
549 /* mb->cmd and mb->args[0] through mb->args[2] */
Hans Verkuil42d0c3a2012-05-26 08:07:03 -0300550 for (i = 0; i < 4; i++)
551 (&order_mb->cmd)[i] = cx18_readl(cx, &mb->cmd + i);
552
Andy Wallsd6c7e5f2008-11-17 22:48:46 -0300553 /* mb->request and mb->ack. N.B. we want to read mb->ack last */
Hans Verkuil42d0c3a2012-05-26 08:07:03 -0300554 for (i = 0; i < 2; i++)
555 (&order_mb->request)[i] = cx18_readl(cx, &mb->request + i);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300556
557 if (order_mb->request == order_mb->ack) {
Mauro Carvalho Chehab6beb1382016-10-18 17:44:03 -0200558 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our incoming %s to EPU mailbox (sequence no. %u)\n",
Andy Wallsbca11a52008-11-19 01:24:33 -0300559 rpu_str[rpu], rpu_str[rpu], order_mb->request);
Andy Walls50299992009-01-01 12:35:06 -0300560 if (cx18_debug & CX18_DBGFLG_WARN)
561 dump_mb(cx, order_mb, "incoming");
Andy Walls72a4f802008-11-16 21:18:00 -0300562 order->flags = CX18_F_EWO_MB_STALE_UPON_RECEIPT;
Andy Wallsee2d64f2008-11-16 01:38:19 -0300563 }
564
565 /*
566 * Individual EPU command processing is responsible for ack-ing
567 * a non-stale mailbox as soon as possible
568 */
Andy Walls72a4f802008-11-16 21:18:00 -0300569 submit = epu_cmd_irq(cx, order);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300570 if (submit > 0) {
Andy Wallsdeed75e2009-04-13 22:22:40 -0300571 queue_work(cx->in_work_queue, &order->work);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300572 }
573}
574
575
576/*
577 * Functions called from a non-interrupt, non work_queue context
578 */
579
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300580static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
581{
582 const struct cx18_api_info *info = find_api_info(cmd);
Hans Verkuil932205a2012-04-23 08:25:20 -0300583 u32 irq, req, ack, err;
Al Viro990c81c2008-05-21 00:32:01 -0300584 struct cx18_mailbox __iomem *mb;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300585 wait_queue_head_t *waitq;
Andy Walls72c2d6d2008-11-06 01:15:41 -0300586 struct mutex *mb_lock;
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300587 unsigned long int t0, timeout, ret;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300588 int i;
Andy Walls50299992009-01-01 12:35:06 -0300589 char argstr[MAX_MB_ARGUMENTS*11+1];
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300590 DEFINE_WAIT(w);
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300591
592 if (info == NULL) {
593 CX18_WARN("unknown cmd %x\n", cmd);
594 return -EINVAL;
595 }
596
Andy Walls50299992009-01-01 12:35:06 -0300597 if (cx18_debug & CX18_DBGFLG_API) { /* only call u32arr2hex if needed */
598 if (cmd == CX18_CPU_DE_SET_MDL) {
599 if (cx18_debug & CX18_DBGFLG_HIGHVOL)
600 CX18_DEBUG_HI_API("%s\tcmd %#010x args%s\n",
601 info->name, cmd,
602 u32arr2hex(data, args, argstr));
603 } else
604 CX18_DEBUG_API("%s\tcmd %#010x args%s\n",
605 info->name, cmd,
606 u32arr2hex(data, args, argstr));
607 }
Andy Walls72c2d6d2008-11-06 01:15:41 -0300608
609 switch (info->rpu) {
610 case APU:
611 waitq = &cx->mb_apu_waitq;
612 mb_lock = &cx->epu2apu_mb_lock;
Andy Wallsac504412008-11-07 23:57:46 -0300613 irq = IRQ_EPU_TO_APU;
614 mb = &cx->scb->epu2apu_mb;
Andy Walls72c2d6d2008-11-06 01:15:41 -0300615 break;
616 case CPU:
617 waitq = &cx->mb_cpu_waitq;
618 mb_lock = &cx->epu2cpu_mb_lock;
Andy Wallsac504412008-11-07 23:57:46 -0300619 irq = IRQ_EPU_TO_CPU;
620 mb = &cx->scb->epu2cpu_mb;
Andy Walls72c2d6d2008-11-06 01:15:41 -0300621 break;
622 default:
623 CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu);
624 return -EINVAL;
625 }
626
627 mutex_lock(mb_lock);
Andy Wallsac504412008-11-07 23:57:46 -0300628 /*
629 * Wait for an in-use mailbox to complete
630 *
631 * If the XPU is responding with Ack's, the mailbox shouldn't be in
632 * a busy state, since we serialize access to it on our end.
633 *
634 * If the wait for ack after sending a previous command was interrupted
635 * by a signal, we may get here and find a busy mailbox. After waiting,
636 * mark it "not busy" from our end, if the XPU hasn't ack'ed it still.
637 */
Andy Wallsac504412008-11-07 23:57:46 -0300638 req = cx18_readl(cx, &mb->request);
Andy Walls2bb49f12008-11-22 01:23:22 -0300639 timeout = msecs_to_jiffies(10);
Andy Wallsac504412008-11-07 23:57:46 -0300640 ret = wait_event_timeout(*waitq,
641 (ack = cx18_readl(cx, &mb->ack)) == req,
Andy Walls330c6ec2008-11-08 14:19:37 -0300642 timeout);
Andy Wallsac504412008-11-07 23:57:46 -0300643 if (req != ack) {
644 /* waited long enough, make the mbox "not busy" from our end */
645 cx18_writel(cx, req, &mb->ack);
Mauro Carvalho Chehab6beb1382016-10-18 17:44:03 -0200646 CX18_ERR("mbox was found stuck busy when setting up for %s; clearing busy and trying to proceed\n",
647 info->name);
Andy Walls330c6ec2008-11-08 14:19:37 -0300648 } else if (ret != timeout)
Andy Walls2bb49f12008-11-22 01:23:22 -0300649 CX18_DEBUG_API("waited %u msecs for busy mbox to be acked\n",
650 jiffies_to_msecs(timeout-ret));
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300651
Andy Wallsac504412008-11-07 23:57:46 -0300652 /* Build the outgoing mailbox */
653 req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1;
654
Andy Wallsb1526422008-08-30 16:03:44 -0300655 cx18_writel(cx, cmd, &mb->cmd);
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300656 for (i = 0; i < args; i++)
Andy Wallsb1526422008-08-30 16:03:44 -0300657 cx18_writel(cx, data[i], &mb->args[i]);
658 cx18_writel(cx, 0, &mb->error);
659 cx18_writel(cx, req, &mb->request);
Andy Wallsac504412008-11-07 23:57:46 -0300660 cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300661
Andy Walls330c6ec2008-11-08 14:19:37 -0300662 /*
663 * Notify the XPU and wait for it to send an Ack back
Andy Walls330c6ec2008-11-08 14:19:37 -0300664 */
Andy Walls2bb49f12008-11-22 01:23:22 -0300665 timeout = msecs_to_jiffies((info->flags & API_FAST) ? 10 : 20);
Andy Wallsac504412008-11-07 23:57:46 -0300666
667 CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n",
668 irq, info->name);
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300669
670 /* So we don't miss the wakeup, prepare to wait before notifying fw */
671 prepare_to_wait(waitq, &w, TASK_UNINTERRUPTIBLE);
Andy Wallsf056d292008-10-31 20:49:12 -0300672 cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300673
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300674 t0 = jiffies;
675 ack = cx18_readl(cx, &mb->ack);
676 if (ack != req) {
677 schedule_timeout(timeout);
678 ret = jiffies - t0;
679 ack = cx18_readl(cx, &mb->ack);
680 } else {
681 ret = jiffies - t0;
682 }
Andy Walls2bb49f12008-11-22 01:23:22 -0300683
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300684 finish_wait(waitq, &w);
685
686 if (req != ack) {
Andy Walls72c2d6d2008-11-06 01:15:41 -0300687 mutex_unlock(mb_lock);
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300688 if (ret >= timeout) {
689 /* Timed out */
Mauro Carvalho Chehab6beb1382016-10-18 17:44:03 -0200690 CX18_DEBUG_WARN("sending %s timed out waiting %d msecs for RPU acknowledgment\n",
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300691 info->name, jiffies_to_msecs(ret));
692 } else {
Mauro Carvalho Chehab6beb1382016-10-18 17:44:03 -0200693 CX18_DEBUG_WARN("woken up before mailbox ack was ready after submitting %s to RPU. only waited %d msecs on req %u but awakened with unmatched ack %u\n",
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300694 info->name,
695 jiffies_to_msecs(ret),
696 req, ack);
697 }
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300698 return -EINVAL;
Andy Walls330c6ec2008-11-08 14:19:37 -0300699 }
700
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300701 if (ret >= timeout)
Mauro Carvalho Chehab6beb1382016-10-18 17:44:03 -0200702 CX18_DEBUG_WARN("failed to be awakened upon RPU acknowledgment sending %s; timed out waiting %d msecs\n",
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300703 info->name, jiffies_to_msecs(ret));
704 else
Andy Walls330c6ec2008-11-08 14:19:37 -0300705 CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n",
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300706 jiffies_to_msecs(ret), info->name);
Andy Walls72c2d6d2008-11-06 01:15:41 -0300707
Andy Wallsac504412008-11-07 23:57:46 -0300708 /* Collect data returned by the XPU */
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300709 for (i = 0; i < MAX_MB_ARGUMENTS; i++)
Andy Wallsb1526422008-08-30 16:03:44 -0300710 data[i] = cx18_readl(cx, &mb->args[i]);
711 err = cx18_readl(cx, &mb->error);
Andy Walls72c2d6d2008-11-06 01:15:41 -0300712 mutex_unlock(mb_lock);
Andy Wallsac504412008-11-07 23:57:46 -0300713
714 /*
715 * Wait for XPU to perform extra actions for the caller in some cases.
Andy Walls52fcb3e2009-11-08 23:45:24 -0300716 * e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all MDLs
Andy Wallsac504412008-11-07 23:57:46 -0300717 * back in a burst shortly thereafter
718 */
Andy Walls72c2d6d2008-11-06 01:15:41 -0300719 if (info->flags & API_SLOW)
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300720 cx18_msleep_timeout(300, 0);
Andy Wallsac504412008-11-07 23:57:46 -0300721
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300722 if (err)
723 CX18_DEBUG_API("mailbox error %08x for command %s\n", err,
724 info->name);
725 return err ? -EIO : 0;
726}
727
728int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[])
729{
Andy Wallsac504412008-11-07 23:57:46 -0300730 return cx18_api_call(cx, cmd, args, data);
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300731}
732
733static int cx18_set_filter_param(struct cx18_stream *s)
734{
735 struct cx18 *cx = s->cx;
736 u32 mode;
737 int ret;
738
739 mode = (cx->filter_mode & 1) ? 2 : (cx->spatial_strength ? 1 : 0);
740 ret = cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
741 s->handle, 1, mode, cx->spatial_strength);
742 mode = (cx->filter_mode & 2) ? 2 : (cx->temporal_strength ? 1 : 0);
743 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
744 s->handle, 0, mode, cx->temporal_strength);
745 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
746 s->handle, 2, cx->filter_mode >> 2, 0);
747 return ret;
748}
749
750int cx18_api_func(void *priv, u32 cmd, int in, int out,
751 u32 data[CX2341X_MBOX_MAX_DATA])
752{
Hans Verkuila75b9be2010-12-31 10:22:52 -0300753 struct cx18_stream *s = priv;
754 struct cx18 *cx = s->cx;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300755
756 switch (cmd) {
757 case CX2341X_ENC_SET_OUTPUT_PORT:
758 return 0;
759 case CX2341X_ENC_SET_FRAME_RATE:
760 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_IN, 6,
761 s->handle, 0, 0, 0, 0, data[0]);
762 case CX2341X_ENC_SET_FRAME_SIZE:
763 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RESOLUTION, 3,
764 s->handle, data[1], data[0]);
765 case CX2341X_ENC_SET_STREAM_TYPE:
766 return cx18_vapi(cx, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 2,
767 s->handle, data[0]);
768 case CX2341X_ENC_SET_ASPECT_RATIO:
769 return cx18_vapi(cx, CX18_CPU_SET_ASPECT_RATIO, 2,
770 s->handle, data[0]);
771
772 case CX2341X_ENC_SET_GOP_PROPERTIES:
773 return cx18_vapi(cx, CX18_CPU_SET_GOP_STRUCTURE, 3,
774 s->handle, data[0], data[1]);
775 case CX2341X_ENC_SET_GOP_CLOSURE:
776 return 0;
777 case CX2341X_ENC_SET_AUDIO_PROPERTIES:
778 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_PARAMETERS, 2,
779 s->handle, data[0]);
780 case CX2341X_ENC_MUTE_AUDIO:
781 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2,
782 s->handle, data[0]);
783 case CX2341X_ENC_SET_BIT_RATE:
784 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RATE, 5,
785 s->handle, data[0], data[1], data[2], data[3]);
786 case CX2341X_ENC_MUTE_VIDEO:
787 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2,
788 s->handle, data[0]);
789 case CX2341X_ENC_SET_FRAME_DROP_RATE:
790 return cx18_vapi(cx, CX18_CPU_SET_SKIP_INPUT_FRAME, 2,
791 s->handle, data[0]);
792 case CX2341X_ENC_MISC:
793 return cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 4,
794 s->handle, data[0], data[1], data[2]);
795 case CX2341X_ENC_SET_DNR_FILTER_MODE:
796 cx->filter_mode = (data[0] & 3) | (data[1] << 2);
797 return cx18_set_filter_param(s);
798 case CX2341X_ENC_SET_DNR_FILTER_PROPS:
799 cx->spatial_strength = data[0];
800 cx->temporal_strength = data[1];
801 return cx18_set_filter_param(s);
802 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
803 return cx18_vapi(cx, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 3,
804 s->handle, data[0], data[1]);
805 case CX2341X_ENC_SET_CORING_LEVELS:
806 return cx18_vapi(cx, CX18_CPU_SET_MEDIAN_CORING, 5,
807 s->handle, data[0], data[1], data[2], data[3]);
808 }
809 CX18_WARN("Unknown cmd %x\n", cmd);
810 return 0;
811}
812
813int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS],
814 u32 cmd, int args, ...)
815{
816 va_list ap;
817 int i;
818
819 va_start(ap, args);
820 for (i = 0; i < args; i++)
821 data[i] = va_arg(ap, u32);
822 va_end(ap);
823 return cx18_api(cx, cmd, args, data);
824}
825
826int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...)
827{
828 u32 data[MAX_MB_ARGUMENTS];
829 va_list ap;
830 int i;
831
832 if (cx == NULL) {
833 CX18_ERR("cx == NULL (cmd=%x)\n", cmd);
834 return 0;
835 }
836 if (args > MAX_MB_ARGUMENTS) {
837 CX18_ERR("args too big (cmd=%x)\n", cmd);
838 args = MAX_MB_ARGUMENTS;
839 }
840 va_start(ap, args);
841 for (i = 0; i < args; i++)
842 data[i] = va_arg(ap, u32);
843 va_end(ap);
844 return cx18_api(cx, cmd, args, data);
845}